CN115469933A - Automatic data extraction system for memory chip - Google Patents

Automatic data extraction system for memory chip Download PDF

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Publication number
CN115469933A
CN115469933A CN202210953697.9A CN202210953697A CN115469933A CN 115469933 A CN115469933 A CN 115469933A CN 202210953697 A CN202210953697 A CN 202210953697A CN 115469933 A CN115469933 A CN 115469933A
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CN
China
Prior art keywords
memory chip
communication interface
data
clock
microprocessor
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Pending
Application number
CN202210953697.9A
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Chinese (zh)
Inventor
张兴斌
沈长达
刘亚鑫
黄庆发
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Xiamen Meiya Pico Information Co Ltd
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Xiamen Meiya Pico Information Co Ltd
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Priority to CN202210953697.9A priority Critical patent/CN115469933A/en
Publication of CN115469933A publication Critical patent/CN115469933A/en
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/4401—Bootstrapping
    • G06F9/4403—Processor initialisation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Security & Cryptography (AREA)
  • Communication Control (AREA)

Abstract

The invention relates to a system for automatically extracting data of a memory chip, which comprises: the communication interface is in communication connection with the microprocessor; the process of the system for automatically extracting the data of the memory chip comprises the following steps: initializing a system clock and a power supply voltage of a storage chip; configuring pins; initializing functions of each communication interface; the microprocessor identifies the accessed memory chip through the communication interface, judges whether the ID of the memory chip can be identified, judges the type of the accessed memory chip according to the ID if the ID can be identified, and reads data in the memory chip by adopting a set corresponding communication interface function according to different types; otherwise, after the power supply voltage of the memory chip and/or the communication clock of the memory chip are changed, the identification is carried out again. The invention integrates a plurality of data communication modes, and can automatically identify and read different types of memory chips in a non-disassembly mode.

Description

Automatic data extraction system for memory chip
Technical Field
The invention relates to the field of data extraction of memory chips, in particular to an automatic data extraction system of a memory chip.
Background
EEPROM, FLASH and eMMC are used as mainstream storage chips of consumer electronic products, and with the arrival of the era of Internet of things, data storage units of the electronic products are more and more abundant. In the electronic data field of collecting evidence, at present to the data acquisition mode of thing antithetical couplet memory chip, mainly still through dismantling the back to thing antithetical couplet memory chip and read the card equipment with the help of memory chip and read the instrument and carry out data acquisition, this kind of mode causes the damage to memory chip easily when dismantling the chip, and the while unsolder memory chip operation is complicated, unsatisfied the embedded demand of collecting evidence security domain development of thing networking. And the card reading equipment can only read the memory chips supported by the card reading equipment, and the corresponding data of the memory chips can be read only by selecting the types of the memory chips supported by the card reading equipment through a matched upper computer, so that the different types of memory chips cannot be automatically identified.
Disclosure of Invention
In order to solve the above problems, the present invention provides an automatic data extraction system for a memory chip.
The specific scheme is as follows:
an automatic data extraction system for a memory chip, comprising: the communication interface is in communication connection with the microprocessor; the process of the system for automatically extracting the data of the memory chip comprises the following steps:
s1: initializing and setting a system clock of a microprocessor;
s2: setting the connection relation between each pin in the microprocessor and the corresponding pin of each communication interface;
s3: initializing and setting the power supply voltage of a storage chip corresponding to the microprocessor;
s4: initializing and setting the functions of each communication interface;
s5: a user adopts the adapter plate of the corresponding type to connect the storage chip and the communication interface of the corresponding type according to the communication interface model of the storage chip;
s6: the microprocessor identifies the accessed memory chip through the communication interface, judges whether the ID of the memory chip can be identified or not, and if so, enters S7; otherwise, entering S8;
s7: judging the type of the accessed memory chip according to the ID of the memory chip, reading the data in the memory chip by adopting the set corresponding communication interface function according to the difference of the types, and ending;
s8: and returning to S6 for re-identification after the power supply voltage of the memory chip and/or the communication clock of the memory chip are changed.
Further, the setting of the clock includes a clock frequency, a clock polarity, and a clock phase.
Further, the setting range of the power supply voltage of the memory chip includes 1.8V and 3.3V.
Further, the communication interface includes any several of an SPI communication interface, an I2C communication interface, and an eMMC communication interface.
The invention adopts the technical scheme, integrates a plurality of data communication modes, and can automatically identify and read different types of memory chips in a non-disassembly mode.
Drawings
Fig. 1 is a schematic structural diagram of a system according to an embodiment of the present invention.
Fig. 2 is a flowchart illustrating a system for automatically extracting data from a memory chip according to an embodiment of the present invention.
Detailed Description
To further illustrate the various embodiments, the invention provides the accompanying drawings. The accompanying drawings, which are incorporated in and constitute a part of this disclosure, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the embodiments. With these references, one of ordinary skill in the art will appreciate other possible embodiments and advantages of the present invention.
The invention will now be further described with reference to the drawings and the detailed description.
The first embodiment is as follows:
the embodiment of the invention provides an automatic data extraction system for a memory chip, which comprises: the communication interface is connected with the microprocessor in a communication way.
The microprocessor may be a single chip, an ARM, an FPGA, or other processing chips, which is not limited herein.
The communication interface is an existing communication interface, and the communication interface is set in this embodiment to include three types, which are respectively: an SPI communication interface, an I2C communication interface, and an eMMC communication interface. Each type of communication interface protocol is described below
(1) I2C communication protocol
The I2C bus is a bidirectional two-wire synchronous serial bus developed by Philips for connecting a microcontroller and its peripheral devices, and is a serial bus formed by a data line SDA and a clock SCL, which can transmit and receive data. The high speed I2C bus typically reaches 400Kbps for bi-directional transfer between the microprocessor and the controlled IC. The I2C bus shares three types of signals in the process of transmitting data, which are a start signal, an end signal, and a response signal.
Start signal: when SCL is high, SDA transitions from high to low to begin transmitting data.
An end signal: when SCL is high level, SDA jumps from low level to high level to finish transmitting data.
Response signal: after receiving 8-bit data, the IC receiving the data sends a specific low-level pulse to the IC transmitting the data, indicating that the data has been received. After the microprocessor sends a signal to the controlled unit, waiting for the controlled unit to send a response signal, and after receiving the response signal, the microprocessor judges whether to continuously transmit the signal according to the actual condition. If the answer signal is not received, the controlled unit is judged to be in fault.
EEPROM memory chips typically employ I2C bus communication protocols for data transfer.
(2) SPI communication protocol
SPI is a full duplex synchronous serial bus developed by Motorola, a synchronous serial port for communication between a microprocessor control unit and peripheral devices. The SPI interface typically uses 4 wires for communication: MOSI master device data output and slave device data input. And the MISO master device data is input, and the slave device data is output. An SCLK clock signal, generated by the master device. And the CS slave device chip selection signal is controlled by the master device. The master and the slave have a serial shift register, the master initiates a transmission by writing a byte into its SPI serial register, the register transmits the byte to the slave through MOSI signal line, the slave also returns the content in its own shift register to the master through MISO signal line. Thus, the contents of the two shift registers are swapped.
According to the working requirements of different memory chips, the clock polarity and the clock phase are set differently, and when the Clock Polarity (CPOL) is set to be 0, the idle state of the serial synchronous clock is low level; if the Clock Polarity (CPOL) is set to 1, the idle state of the serial clock is high level; when the Clock Phase (CPHA) is set to 0, data is sampled at the first transition edge of the serial synchronous clock; if the Clock Phase (CPHA) is set to 1, the data is sampled on the second transition edge of the serial synchronous clock. The SPI master and the peripheral communicating with it should be phase and polarity identical.
The SPI interface is mainly applied to EEPROM and FLASH.
(2) eMMC communication protocol
The eMMC is short for embedded multimedia cards, is established by an mmc association, mainly aims at the standard specification of an embedded memory of products such as a mobile phone or a tablet personal computer, and integrates a controller in packaging to provide a standard interface and manage a memory.
The eMMC system has three modules, which are a host, an eMMC device, and an eMMC controller. The eMMC device also comprises a flash storage unit and a control unit thereof. The pins and internal structures of all devices in the process of manufacturing the chip based on the eMMC protocol are in accordance with the specification specified by the eMMC protocol. The protocol specifies that the pin has CLK, which is the input clock of the device, and the host provides signals, and the clock can send and receive commands and data.
CMD is a command line for bi-directional transmission for data communication between the host and the device. When the host sends a command, the device will reply to the host and can return to the host through the CMD line. The CMD has two modes, open drain and push pull, for responding to initialization and for responding to fast command transmission, respectively.
The RESET is a one-way RESET signal line and is sent by the host.
DAT0-DAT7 are the two-wire data bus of the eMMC for data communication between the host and the device. Which operates in a push-pull mode that handles fast command transmission. By default, when the user is powered on or reset, data is transmitted using only DAT0, one line. Meanwhile, the user can configure the number of DAT lines which are wanted to be used by himself, and 4 or 8 DAT lines can be selected.
Data Strobe is a latch line of Data, is mainly used for the HS400 mode proposed by emmc5.0, and equipment needs to latch an output signal.
VCC is the storage chip supply voltage, and some storage chips adopt 1.8V supply voltage, and some need use 3.3V supply voltage.
The structural schematic diagram of the automatic data extraction system of the memory chip in this embodiment is shown in fig. 1, and each communication interface is connected with the memory chip through a corresponding adapter plate, specifically, the SPI communication interface corresponds to the SPI fixture, the I2C communication interface corresponds to the I2C fixture, and the eMMC communication interface corresponds to the eMMC adapter plate. The storage chip can be accessed into the storage chip data automatic extraction system through the corresponding clamp, so that the data in the storage chip can be automatically identified. The problem that the memory chip can be read only by detaching the memory chip from the PCB can be solved by the adapter plate.
Three types of adapter plates are described below.
(1) SPI anchor clamps: one end can directly clamp the SOP8 packaging type memory chip, and the memory chip data automatic extraction system is directly connected with the memory chip through the SPI clamp.
(2) I2C clamp: similar to the SPI clamp, the automatic data extraction system of the memory chip can be connected with the I2C type memory chip.
(3) eMMC pinboard: one end of the adapter plate can be directly connected with each communication pin contact of the eMMC memory chip, and the other end of the adapter plate is connected with an eMMC communication interface of the memory chip data automatic extraction system.
As shown in fig. 2, the process of the system for automatically extracting the data of the memory chip includes the following steps:
s1: initializing and setting a system clock of a microprocessor;
s2: setting the connection relation between each pin in the microprocessor and the corresponding pin of each communication interface;
s3: initializing and setting the power supply voltage of a storage chip corresponding to the microprocessor;
s4: initializing and setting the functions of each communication interface;
s5: a user adopts a corresponding type of adapter plate to connect the storage chip and a corresponding type of communication interface according to the type of the communication interface of the storage chip;
s6: the microprocessor identifies the accessed memory chip through the communication interface, judges whether the ID of the memory chip can be identified or not, and if so, enters S7; otherwise, entering S8;
s7: judging the type of the accessed memory chip according to the ID of the memory chip, reading the data in the memory chip by adopting the set corresponding communication interface function according to the difference of the types, and ending;
s8: and after the power supply voltage of the memory chip and/or the communication clock of the memory chip are changed, returning to S6 for re-identification.
The setting of the clock in this embodiment includes a clock frequency, a clock polarity, and a clock phase. The setting range of the power supply voltage of the memory chip comprises 1.8V and 3.3V, and the initialization setting is 1.8V.
When the function of each communication interface is initialized, the function of the corresponding pin of each communication interface needs to be set according to the communication protocol of each communication interface, and meanwhile, the communication clock of the memory chip corresponding to each communication interface is set, wherein the communication clock comprises clock frequency, clock polarity and clock phase.
The embodiment of the invention integrates various data communication modes, and can automatically identify and read different types of memory chips in a non-disassembly mode. Because the voltage platforms, the clock frequency, the clock polarity and the clock phase used by the same type of memory chips are different, the embodiment of the invention can extract the identification data of the same type of memory chips by automatically switching the voltage platforms and adaptively configuring the clock polarity, the clock phase and the clock frequency.
While the invention has been particularly shown and described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (4)

1. An automatic data extraction system for a memory chip, comprising: the communication interface is in communication connection with the microprocessor; the process of the system for automatically extracting the data of the memory chip comprises the following steps:
s1: initializing and setting a system clock of a microprocessor;
s2: setting the connection relation between each pin in the microprocessor and the corresponding pin of each communication interface;
s3: initializing and setting the power supply voltage of a storage chip corresponding to the microprocessor;
s4: initializing and setting the functions of each communication interface;
s5: a user adopts a corresponding type of adapter plate to connect the storage chip and a corresponding type of communication interface according to the type of the communication interface of the storage chip;
s6: the microprocessor identifies the accessed memory chip through the communication interface, judges whether the ID of the memory chip can be identified or not, and if so, enters S7; otherwise, entering S8;
s7: judging the type of the accessed memory chip according to the ID of the memory chip, reading the data in the memory chip by adopting the set corresponding communication interface function according to the difference of the types, and ending;
s8: and returning to S6 for re-identification after the power supply voltage of the memory chip and/or the communication clock of the memory chip are changed.
2. The automatic extraction system of data of a memory chip according to claim 1, characterized in that: the setting of the clock includes the clock frequency, the clock polarity, and the clock phase.
3. The automatic extraction system of data of a memory chip according to claim 1, characterized in that: the set range of the power supply voltage of the memory chip comprises 1.8V and 3.3V.
4. The automatic extraction system of data of a memory chip according to claim 1, characterized in that: the communication interface comprises any one of an SPI communication interface, an I2C communication interface and an eMMC communication interface.
CN202210953697.9A 2022-08-10 2022-08-10 Automatic data extraction system for memory chip Pending CN115469933A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202210953697.9A CN115469933A (en) 2022-08-10 2022-08-10 Automatic data extraction system for memory chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210953697.9A CN115469933A (en) 2022-08-10 2022-08-10 Automatic data extraction system for memory chip

Publications (1)

Publication Number Publication Date
CN115469933A true CN115469933A (en) 2022-12-13

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Country Status (1)

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