CN115469490A - LCD mother board - Google Patents

LCD mother board Download PDF

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Publication number
CN115469490A
CN115469490A CN202210994449.9A CN202210994449A CN115469490A CN 115469490 A CN115469490 A CN 115469490A CN 202210994449 A CN202210994449 A CN 202210994449A CN 115469490 A CN115469490 A CN 115469490A
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CN
China
Prior art keywords
substrate
display panel
line
sub
liquid crystal
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Pending
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CN202210994449.9A
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Chinese (zh)
Inventor
翟宁宁
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Suzhou China Star Optoelectronics Technology Co Ltd
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Suzhou China Star Optoelectronics Technology Co Ltd
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Priority to CN202210994449.9A priority Critical patent/CN115469490A/en
Publication of CN115469490A publication Critical patent/CN115469490A/en
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Liquid Crystal (AREA)

Abstract

The application discloses liquid crystal display mother board, it includes two above sub display panel, through the connection of all realizing the signal in the face with two adjacent sub display panel's data line and DBS common electrode line, state data line and DBS common electrode line promptly and all be connected to first signal transmission portion can make radium-shine on the liquid crystal display mother board walk the line and only be equipped with an inflection point to can greatly practice thrift the takt time (Tact time) of radium-shine (Laser) board and the space of arranging of liquid crystal display mother board.

Description

LCD mother board
Technical Field
The application relates to the technical field of display, in particular to a liquid crystal display mother board.
Background
A Liquid Crystal Display (LCD) has the advantages of energy saving, light weight, and delicate picture, and is widely used in the field of Display technology. Liquid crystal display panels currently on the market can be classified into three types, namely, twisted Nematic (TN) or Super Twisted Nematic (STN) type, in-Plane Switching (IPS) type, and Vertical Alignment (VA) type. While the High Vertical Alignment (HVA) mode is an important branch of the VA mode, the HVA mode liquid crystal display panel operates by controlling the rotation of the liquid crystal molecules of the liquid crystal layer by the Vertical electric field formed by the array substrate side pixel electrodes and the CFcom.
As shown in fig. 1, a conventional Liquid Crystal display panel generally includes an array substrate 11, a Color Filter substrate 12 (CF), and a Liquid Crystal Layer (LCL) disposed between the array substrate 11 and the Color Filter substrate 12. The array substrate is provided with a signal transmission part (curing Pad), an array layer, a DBS electrode, a pixel electrode and an array substrate side common electrode (atom); CFcom and Acom are generally transparent conductive films. The color filter substrate is provided with a CF substrate side common electrode (CFcom) and a Color Filter (CF). CFcom and Acom are generally connected together by coating a sealant layer 15 (seal) with a conductive gold Ball (Au Ball) at a signal transmission portion (curing Pad) at the periphery of the display region, and the Acom is conducted with the CFcom through the signal transmission portion and the conductive gold Ball to transmit an HVA curing (curing) signal from the color film substrate 12 side to the array substrate 11 side through the conductive gold Ball.
As shown in fig. 2, the power supply method using LOC curing needs to partition and insulate signals of Acom, DBS electrode, pixel electrode, data line and scan line of the array layer, CFcom, etc. of the display panel by laser, i.e. laser routing is used to divide these signals into high voltage area and low voltage area. However, in the dividing process, since different display panels are powered on, the laser trace has a plurality of inflection points Q, and actually, too close inflection points of the laser trace will not only increase the Tact time (Tact time) of the machine, but also increase the cost. In addition, the design of the liquid crystal display mother board at the present stage tends to be extremely typeset, and the arrangement design of the liquid crystal display mother board is influenced by too many inflection points of laser routing considering that forbidden areas are reserved for laser.
Disclosure of Invention
The invention aims to provide a liquid crystal display mother board to solve the technical problem that the inflection point of laser routing of the liquid crystal display mother board at the present stage is too much to influence the extremely typesetting design of the liquid crystal display mother board.
In order to achieve the above object, the present invention provides a liquid crystal display mother panel, which includes more than two sub-display panels, each sub-display panel includes a first signal transmission portion and a second signal transmission portion, and the first signal transmission portion and the second signal transmission portion are located in a non-display region of each sub-display panel; each sub-display panel further includes: the first substrate comprises a data line and a DBS common electrode line positioned on the data line, and the data line and the DBS common electrode line are both connected to the first signal transmission part; a second substrate provided in a box-to-box relationship with the first substrate, the second substrate including a CF common electrode line connected to the second signal transmission part; the conducting component is arranged between the first substrate and the second substrate, is positioned in a non-display area of each sub-display panel and is used for conducting the first signal transmission part and the second signal transmission part; the display panel comprises a first sub display panel and a second sub display panel, wherein any two adjacent sub display panels are defined as the first sub display panel and the second sub display panel respectively, and a first signal transmission part of the first sub display panel is connected to a first signal transmission part of the second sub display panel through a transfer line.
Further, each sub-display panel includes a first voltage signal area and a second voltage signal area, the first signal transmission portion is disposed in the first voltage signal area, and the second signal transmission portion is disposed in the second voltage signal area.
Further, the second voltage signal area is manufactured by using LOC technology.
Further, the first substrate includes: a first substrate; the first metal layer is arranged on the first substrate and comprises a grid and more than two scanning lines; a first insulating layer covering the first metal layer and extending to a surface of the first substrate; a semiconductor layer which is arranged on the first insulating layer, and the projection of the semiconductor layer on the first substrate falls within the projection range of the grid electrode on the first substrate; the second metal layer is arranged on the semiconductor layer and extends to the surface of the first insulating layer from the semiconductor layer, and the second metal layer comprises a source electrode, a drain electrode and more than two data lines; the second insulating layer is arranged on the second metal layer, and is provided with a first through hole and a second through hole, the first through hole is used for exposing the source electrode, and the second through hole is used for exposing the data line; the patch cord comprises a first connecting line, and the first connecting line is arranged on the second insulating layer; one end of the first connecting line is connected to the source electrode of the first sub-display panel through the first through hole, and the other end of the first connecting line is connected to the data line of the second sub-display panel through the second through hole.
Further, the first substrate further includes: a third insulating layer disposed on the first connection line and extending to a surface of the second insulating layer; a third metal layer disposed on the third insulating layer, the third metal layer including the DBS common electrode line, the DBS common electrode line being opposite to the data line; a fourth insulating layer, disposed on the third metal layer, and provided with a third through hole, where the third through hole is used for exposing the DBS common electrode line; the patch cord further comprises a second connecting line, and the second connecting line is arranged on the fourth insulating layer; one end of the second connection line is connected to the DBS common electrode line of the first sub-display panel through the third through hole, and the other end of the second connection line is connected to the DBS common electrode line of the second sub-display panel through the third through hole.
Further, the third metal layer further includes a pixel electrode line, and the pixel electrode line and the DBS common electrode line are disposed on the same layer.
Further, the voltage of the first signal transmission section is different from the voltage of the second signal transmission section.
Further, the liquid crystal display mother board further includes: the frame adhesive layer is arranged between the first substrate and the second substrate and arranged in the non-display area of each sub-display panel; the conduction component is arranged in the frame glue layer.
Further, the first substrate is an array substrate, the second substrate is a color film substrate, and a liquid crystal layer is arranged between the array substrate and the color film substrate.
Further, the conductive material of the conducting part is a field effect transistor material or a semiconductor material.
The invention has the technical effect that the liquid crystal display mother board comprises more than two sub display panels, the data lines and the DBS common electrode lines of the two adjacent sub display panels are connected in the plane to realize signal connection, namely, the data lines and the DBS common electrode lines are connected to the first signal transmission part, so that Laser routing on the liquid crystal display mother board is only provided with one inflection point, and the Tact time of a Laser (Laser) machine and the arrangement space of the liquid crystal display mother board can be greatly saved.
Drawings
The technical solutions and other advantages of the present application will become apparent from the following detailed description of specific embodiments of the present application when taken in conjunction with the accompanying drawings.
Fig. 1 is a schematic diagram of a film structure of a conventional liquid crystal display panel.
Fig. 2 is a schematic diagram of a liquid crystal display mother board being insulated in a partitioned manner by LOC technology.
Fig. 3 is a schematic diagram of a liquid crystal display mother panel partitioned and insulated by LOC technology according to an embodiment of the present application.
Fig. 4 is a schematic view of a film structure of a sub-display panel according to an embodiment of the present disclosure.
Fig. 5 is a schematic view of a film structure of an array substrate according to an embodiment of the present disclosure.
The components of the drawings are identified as follows:
100. a liquid crystal display mother panel; 101a, a first sub-display panel; 101b, a second sub-display panel; AA. A display area; NA, non-display area; 1. a first signal transmission section; 2. a second signal transmission section; 3. a patch cord; 10. a first voltage signal region; 20. a second voltage signal region; 30. laser routing; q, an inflection point; 11. a first substrate; 12. a second substrate; 13. a liquid crystal layer; 14. a conducting member; 15. a frame glue layer; 111. a first substrate; 112. a first metal layer; 113. a first insulating layer; 114. a semiconductor layer; 115. a second metal layer; 116. a second insulating layer; 117. a first connecting line; 118. a third insulating layer; 119. a third metal layer; 120. a fourth insulating layer; 121. a second connecting line; 112a, a grid; 112b, scanning lines; 115a, a source electrode; 115b, a drain electrode; 115c, data lines; 119a, DBS common electrode lines; 119b, pixel electrode lines; t1, a first through hole; t2, a second through hole; t3, a third through hole; 121. a second substrate; 122. and a CF common electrode line.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It should be apparent that the described embodiments are only a few embodiments of the present application, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it is to be understood that the terms "first", "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; may be mechanically, electrically or may be in communication with each other; they may be directly connected or indirectly connected through intervening media, or may be connected through the use of two elements or the interaction of two elements. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.
As shown in fig. 3 to 5, the present embodiment provides a liquid crystal display mother panel 100, which includes more than two sub-display panels, each of which includes a display area AA and a non-display area NA surrounding the display area AA.
Each sub display panel includes a first signal transmission part 1 and a second signal transmission part 2, and the first signal transmission part 1 and the second signal transmission part 2 are located in a non-display area NA of each sub display panel.
Each sub-display panel further includes a first substrate 11, a second substrate 12, a liquid crystal layer 13, and a conducting member 14. The first substrate 11 is an array substrate, the second substrate 12 is a color film substrate, the liquid crystal layer 13 and the conducting component 14 are both disposed between the array substrate and the color film substrate, wherein the liquid crystal layer 13 is located in a display area AA of each sub-display panel, and the conducting component 14 is located in a non-display area NA of each sub-display panel.
The first substrate 11 includes a data line 115c and a DBS common electrode line 119a on the data line 115c, and the data line 115c and the DBS common electrode line 119a are both connected to the first signal transmission unit 1, so that the data line 115c and the DBS common electrode line 119a realize signal connection between two adjacent sub display panels by an in-plane design. Therefore, when the LOC technology is adopted to perform partition insulation on the liquid crystal display mother board 100, the Laser trace 30 on the liquid crystal display mother board 100 is only provided with one inflection point Q, so that the Tact time (Tact time) of a Laser (Laser) machine and the arrangement space of the liquid crystal display mother board 100 can be greatly saved.
Specifically, the first substrate 11 includes a first substrate 111, a first metal layer 112, a first insulating layer 113, a semiconductor layer 114, a second metal layer 115, a second insulating layer 116, a first connection line 117, a third insulating layer 118, a third metal layer 119, a fourth insulating layer 120, and a second connection line 121.
The first substrate 111 may be a flexible substrate or a rigid substrate, and is not particularly limited herein.
The first metal layer 112 is disposed on the first substrate 111, and the first metal layer 112 includes a gate 112a and two or more scan lines 112b, wherein the two or more scan lines 112b extend along a transverse direction.
A first insulating layer 113 covers the first metal layer 112 and extends to the surface of the first substrate 111. The first insulating layer 113 is a gate 112a insulating layer, and the material used is inorganic material such as silicon nitride and silicon oxide.
A semiconductor layer 114 is disposed on the first insulating layer 113, and a projection of the semiconductor layer 114 on the first substrate 111 falls within a projection range of the gate electrode 112a on the first substrate 111.
The second metal layer 115 is disposed on the semiconductor layer 114 and extends from the semiconductor layer 114 to the surface of the first insulating layer 113, and the second metal layer 115 includes a source electrode 115a, a drain electrode 115b, and two or more data lines 115c, wherein the two or more data lines 115c extend in a longitudinal direction.
The second insulating layer 116 is disposed on the second metal layer 115, and the second insulating layer 116 is provided with a first through hole T1 and a second through hole T2, where the first through hole T1 is used to expose the source electrode 115a, and the second through hole T2 is used to expose the data line 115c. The second insulating layer 116 may be a passivation layer made of an inorganic material such as silicon nitride or silicon oxide.
The first connection line 117 is disposed on the second insulating layer 116. One end of the first connection line 117 is connected to the source 115a of the first sub-display panel 101a through the first via T1, and the other end of the first connection line 117 is connected to the data line 115c of the second sub-display panel 101b through the second via T2. Wherein a connection point at which the first connection line 117 is connected to the source 115a of the first sub-display panel 101a and a connection point at which the first connection line 117 is connected to the data line 115c of the second sub-display panel 101b are first signal transmission parts 1.
A third insulating layer 118 is disposed on the first connection line 117 and extends to the surface of the second insulating layer 116. The third insulating layer 118 is made of inorganic materials such as silicon nitride and silicon oxide.
A third metal layer 119 is disposed on the third insulating layer 118, where the third metal layer 119 includes a pixel electrode line 119b and a DBS common electrode disposed on the same layer, and the DBS common electrode line 119a is opposite to the data line 115c.
The fourth insulating layer 120 is disposed on the third metal layer 119, and a third through hole T3 is disposed in the fourth insulating layer 120, where the third through hole T3 is used to expose the DBS common electrode line 119a. The fourth insulating layer 120 is made of inorganic materials such as silicon nitride and silicon oxide.
The second connection line 121 is disposed on the fourth insulating layer 120. One end of the second connection line 121 is connected to the DBS common electrode line 119a of the first sub-display panel 101a through the third through hole T3, and the other end of the second connection line 121 is connected to the DBS common electrode line 119a of the second sub-display panel 101b through the third through hole T3, so that the data line 115c of the two adjacent sub-display panels is connected to the signal in the plane, therefore, when the LOC technology is used for carrying out partition insulation on the liquid crystal display mother board 100, the Laser trace 30 on the liquid crystal display mother board 100 can be only provided with one inflection point Q, and thus, the takt time of a Laser (Laser) machine and the arrangement space of the liquid crystal display mother board 100 can be greatly saved.
Wherein, a connection point where the second connection line 121 is connected to the DBS common electrode line 119a of the first sub-display panel 101a and a connection point where the second connection line 121 is connected to the DBS common electrode line 119a of the second sub-display panel 101b are first signal transmission parts 1.
In this embodiment, the voltage of the first signal transmission part 1 connected to the source electrode 115a and the data line 115c is V1, and the voltage of the first signal transmission part 1 connected to the DBS common electrode line 119a is V2, where the voltage of V1 may be the same as or different from the voltage of V2, and is not particularly limited herein.
In this embodiment, the patch cord 3 includes the first connection line 117 and the second connection line 121, and in fig. 3, an orthographic projection of the first connection line 117 on the first substrate 111 and an orthographic projection of the second connection line 121 on the first substrate 111 coincide with each other.
The second substrate 12 is disposed opposite to the first substrate 11, and the second substrate 12 includes a second substrate 121 and a CF common electrode line 122.
The second substrate 121 is a color filter, the CF common electrode line 122 is disposed on a lower surface of the second substrate 121, and the CF common electrode line 122 is connected to the second signal transmitting part 2.
The conducting member 14 is disposed between the first substrate 11 and the second substrate 12, and located in the non-display area NA of each sub-display panel, and is used for conducting the first signal transmitting part 1 and the second signal transmitting part 2. In this embodiment, the conductive material of the conducting part 14 is a field effect transistor material or a semiconductor material.
The liquid crystal display mother panel 100 provided in this embodiment further includes a frame adhesive layer 15, the frame adhesive layer 15 is disposed between the first substrate 11 and the second substrate 12, and the frame adhesive layer 15 is disposed in the non-display area NA of each sub-display panel; the conducting component 14 is disposed in the frame adhesive layer 15.
In this embodiment, when each sub display panel operates, a vertical electric field is formed by the pixel electrode lines 119b on the array substrate side and the CF common electrode lines 122 on the color filter substrate side to control the rotation of liquid crystal molecules of the liquid crystal layer 13, and an HVA curing (curing) signal is introduced from the color filter substrate side to the array substrate side through the conduction unit 14, thereby realizing the display of each sub display panel.
Referring to fig. 3, two adjacent sub-display panels are defined as a first sub-display panel 101a and a second sub-display panel 101b, respectively. The first signal transmission part 1 of the first sub display panel 101a is connected to the first signal transmission part 1 of the second sub display panel 101b through a transfer line 3.
In this embodiment, the voltage of the first signal transmission unit 1 is different from the voltage of the second signal transmission unit 2. Each sub display panel includes a first voltage signal area 10 and a second voltage signal area 20, the first signal transmission part 1 is disposed in the first voltage signal area 10, and the second signal transmission part 2 is disposed in the second voltage signal area 20. The second voltage signal region 20 is formed by LOC technology.
Further, as shown in fig. 3 to fig. 5, the first signal transmission portion 1 located in the first voltage signal area 10 is a low voltage signal L, and the second signal transmission portion 2 located in the second voltage signal area 20 is a high voltage signal H. In the present embodiment, signal lines such as the CF common electrode line 122, the pixel electrode line 119b, the data line 115c, the DBS common electrode line 119a, and the scanning line 112b are signal-partitioned, where signals accessed by the data line 115c and the DBS common electrode line 119a are low-voltage signals L, and signals accessed by other signal lines are high-voltage signals H. So set up, when adopting LOC technique to carry out the subregion insulation to liquid crystal display mother board 100, can avoid radium-shine knee Q of walking line 30 too densely and increase the takt time of radium-shine (Laser) board, can also avoid the unable nimble redirecting scheduling problem of radium-shine syringe needle, this embodiment includes more than two sub display panel, through all realizing the connection of signal in the face with data line 115c and DBS public electrode line 119a of two adjacent sub display panel, state that data line 115c and DBS public electrode line 119a all are connected to first signal transmission portion 1 promptly, can make radium-shine walking line 30 on liquid crystal display mother board 100 only be equipped with a knee Q, thereby can greatly practice thrift the takt time (Tact time) of (Laser) board and the space of arranging of liquid crystal display mother board 100.
The liquid crystal display mother board provided by the embodiment of the present application is described in detail above, and specific examples are applied herein to explain the principle and the implementation of the present application, and the description of the above embodiment is only used to help understand the technical solution and the core idea of the present application; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure as defined by the appended claims.

Claims (10)

1. The liquid crystal display mother board is characterized by comprising more than two sub display panels, wherein each sub display panel comprises a first signal transmission part and a second signal transmission part, and the first signal transmission part and the second signal transmission part are positioned in a non-display area of each sub display panel;
each sub-display panel further includes:
the first substrate comprises a data line and a DBS common electrode line positioned on the data line, and the data line and the DBS common electrode line are both connected to the first signal transmission part;
a second substrate provided in a box-to-box relationship with the first substrate, the second substrate including a CF common electrode line connected to the second signal transmission part; and
a conducting member disposed between the first substrate and the second substrate, located in a non-display region of each sub-display panel, and configured to conduct the first signal transmission part and the second signal transmission part;
the display panel comprises a first sub display panel and a second sub display panel, wherein any two adjacent sub display panels are defined as the first sub display panel and the second sub display panel respectively, and a first signal transmission part of the first sub display panel is connected to a first signal transmission part of the second sub display panel through a transfer line.
2. The mother liquid crystal display panel according to claim 1, wherein each of the sub display panels includes a first voltage signal region and a second voltage signal region, the first signal transmitting portion is disposed in the first voltage signal region, and the second signal transmitting portion is disposed in the second voltage signal region.
3. The liquid crystal display mother panel according to claim 2,
the second voltage signal area is made by LOC technology.
4. The liquid crystal display mother panel according to claim 1, wherein the first substrate comprises:
a first substrate;
the first metal layer is arranged on the first substrate and comprises a grid electrode and more than two scanning lines;
a first insulating layer covering the first metal layer and extending to a surface of the first substrate;
the semiconductor layer is arranged on the first insulating layer, and the projection of the semiconductor layer on the first substrate falls into the projection range of the grid electrode on the first substrate;
the second metal layer is arranged on the semiconductor layer and extends to the surface of the first insulating layer from the semiconductor layer, and the second metal layer comprises a source electrode, a drain electrode and more than two data lines;
the second insulating layer is arranged on the second metal layer, and is provided with a first through hole and a second through hole, the first through hole is used for exposing the source electrode, and the second through hole is used for exposing the data line; and
the patch cord comprises a first connecting line, and the first connecting line is arranged on the second insulating layer;
one end of the first connecting line is connected to the source electrode of the first sub-display panel through the first through hole, and the other end of the first connecting line is connected to the data line of the second sub-display panel through the second through hole.
5. The liquid crystal display mother panel of claim 4, wherein the first substrate further comprises:
a third insulating layer disposed on the first connection line and extending to a surface of the second insulating layer;
a third metal layer disposed on the third insulating layer, the third metal layer including the DBS common electrode line, the DBS common electrode line being opposite to the data line;
a fourth insulating layer, disposed on the third metal layer, and provided with a third through hole, where the third through hole is used for exposing the DBS common electrode line; and
the patch cord further comprises a second connecting line, and the second connecting line is arranged on the fourth insulating layer;
one end of the second connection line is connected to the DBS common electrode line of the first sub-display panel through the third through hole, and the other end of the second connection line is connected to the DBS common electrode line of the second sub-display panel through the third through hole.
6. The lcd mother board of claim 1, wherein the third metal layer further comprises a pixel electrode line, and the pixel electrode line and the DBS common electrode line are disposed in the same layer.
7. The liquid crystal display mother panel according to claim 1,
the voltage of the first signal transmission part is different from the voltage of the second signal transmission part.
8. The mother panel for liquid crystal display according to claim 1, further comprising:
the frame adhesive layer is arranged between the first substrate and the second substrate and is arranged in the non-display area of each sub-display panel;
the conduction component is arranged in the frame glue layer.
9. The liquid crystal display mother panel according to claim 1,
the first substrate is an array substrate, the second substrate is a color film substrate, and a liquid crystal layer is arranged between the array substrate and the color film substrate.
10. The liquid crystal display mother panel according to claim 1,
the conducting material of the conducting part is a field effect transistor material or a semiconductor material.
CN202210994449.9A 2022-08-18 2022-08-18 LCD mother board Pending CN115469490A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202210994449.9A CN115469490A (en) 2022-08-18 2022-08-18 LCD mother board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210994449.9A CN115469490A (en) 2022-08-18 2022-08-18 LCD mother board

Publications (1)

Publication Number Publication Date
CN115469490A true CN115469490A (en) 2022-12-13

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN202210994449.9A Pending CN115469490A (en) 2022-08-18 2022-08-18 LCD mother board

Country Status (1)

Country Link
CN (1) CN115469490A (en)

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