CN115458270A - Magnetic flux regulation and control structure, test device and test method - Google Patents
Magnetic flux regulation and control structure, test device and test method Download PDFInfo
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- H01F5/00—Coils
- H01F5/003—Printed circuit coils
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- H05K1/00—Printed circuits
- H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
- H05K1/165—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed inductors
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Abstract
The application discloses a magnetic flux regulation and control structure, a testing device and a testing method, and belongs to the technical field of quantum computation. The application provides a magnetic flux regulation and control structure utilizes the coil that forms on the basement can form the magnetic field and apply to quantum chip to the magnetic flux of regulation and control SQUID has solved the problem that can't test quantum chip under the unusual condition of frequency regulation and control line of quantum chip. According to the testing method, the magnetic flux regulation and control structure and the quantum chip are placed face to face, current is introduced into the coil, then scattering parameters corresponding to the current are collected, then the testing result of the quantum chip is determined according to the scattering parameters, namely, the coil formed on the substrate can be utilized to form a magnetic field to be applied to the quantum chip to regulate and control the SQUID magnetic flux, and then the quantum chip is tested, so that the problem that the quantum chip cannot be tested under the condition that the frequency regulation and control line of the quantum chip is abnormal is solved.
Description
Technical Field
The application belongs to the field of quantum information, particularly relates to the technical field of quantum computing, and particularly relates to a magnetic flux regulation and control structure, a test device and a test method.
Background
The quantum bit on the quantum chip is a basic unit for executing quantum computation, and bit performance can be adjusted by changing the working frequency of the quantum bit, so that a series of bit operations are realized. Wherein the operating frequency can be controlled by applying a magnetic flux control signal to a frequency control line (Z-control line). The qualified quantum chip needs to be subjected to processes of layout drawing, process preparation, chip testing and the like, and needs to be repeatedly carried out to optimize relevant parameters. However, if the frequency control line (Z-control line) on the quantum chip is abnormal, the chip test may be affected.
Disclosure of the invention
Aiming at the defects in the prior art, the application provides a magnetic flux regulation and control structure, a testing device and a testing method so as to realize the test of a quantum chip.
An embodiment of the present application provides a magnetic flux regulating structure, including: a substrate; and a coil on the substrate, the coil having an I/O port.
In some embodiments, the substrate comprises an alumina substrate, a quartz glass substrate, a ceramic substrate, a sapphire substrate, as described above.
In some embodiments, as the above-mentioned magnetic flux modulating structure, the coil is a thin film circuit formed on the surface of the substrate.
In some embodiments, the thin film circuit comprises a superconducting transmission line, as described above for the flux modulating structure.
In some embodiments, as described above for the flux modulating structure, the superconducting transmission line is a tantalum nitride transmission line.
In some embodiments, as the magnetic flux regulating structure described above, the coil includes a first partial coil and a second partial coil which are connected in series and have opposite winding directions, and the whole of the second partial coil is located in the whole of the first partial coil.
Another embodiment of the present application provides a test apparatus, including: a quantum chip to be tested; the magnetic flux regulating structure is characterized in that the coil is opposite to the quantum chip; the packaging structure is provided with a first port and a second port, the packaging structure is used for packaging the quantum chip and the magnetic flux regulation structure, the first port is connected with the quantum chip in a bonding mode, and the second port is used for being connected with the I/O port; and a test instrument connected to the first port and the second port.
In some embodiments, the test device as described above, the second port comprises a cable lug, the substrate having formed therethrough an interconnect element electrically connecting the I/O port with the cable lug.
In some embodiments, the test apparatus as described above, the interconnect element comprises a superconducting layer formed within the via.
Yet another embodiment of the present application provides a testing method, including the steps of: the magnetic flux regulating structure is opposite to the quantum chip, and current is introduced into the coil; collecting scattering parameters corresponding to the current; and determining the test result of the quantum chip according to the scattering parameters.
The magnetic flux regulating structure provided by the application comprises a substrate; and the coil is positioned on the substrate and is provided with an I/O port, and a magnetic field can be formed by utilizing the coil formed on the substrate and applied to the quantum chip, so that the magnetic flux of the SQUID is regulated and controlled, and the problem that the quantum chip cannot be tested under the condition that a frequency regulating and controlling line of the quantum chip is abnormal is solved.
The application provides a testing arrangement includes: a quantum chip to be tested; the magnetic flux regulating structure is arranged, and the coil is opposite to the quantum chip; the packaging structure is provided with a first port and a second port, the packaging structure is used for packaging the quantum chip and the magnetic flux regulation structure, the first port is connected with the quantum chip in a bonding mode, and the second port is used for being connected with the I/O port; and a test instrument connected to the first port and the second port. The coil can generate an induction magnetic field by applying current through the second port by using a testing instrument, so that the magnetic flux of the SQUID structure in the corresponding quantum bit is regulated and controlled, and then the response of the quantum chip and the parameter information of the current are collected through the first port, so that the test for the quantum chip can be realized, and the problem that the quantum chip cannot be tested under the condition that the frequency regulation and control line of the quantum chip is abnormal is solved.
According to the testing method, the magnetic flux regulation and control structure and the quantum chip are placed face to face, current is introduced into the coil, then scattering parameters of the quantum chip are collected under the regulation and control effect of the current, the testing result of the quantum chip is determined according to the scattering parameters, namely, a magnetic field formed by the coil formed on the substrate can be applied to the quantum chip to regulate and control the magnetic flux of the SQUID structure in the corresponding quantum bit, and then the quantum chip is tested, so that the problem that the quantum chip cannot be tested under the condition that the frequency regulation and control line of the quantum chip is abnormal is solved.
Drawings
Fig. 1 is a schematic main structural diagram of a testing apparatus according to an embodiment of the present disclosure;
fig. 2 is a schematic main structural diagram of the second surface 12 of the substrate 1 according to the embodiment of the present application;
fig. 3 is a schematic flowchart of quantum chip testing provided in an embodiment of the present application.
Description of reference numerals: 1-substrate, 11-first surface, 12-second surface, 2-coil, 21-first partial coil, 22-second partial coil, 23-input port, 24-output port, 25-transfer point, 3-connector, 4-packaging structure, 41-first packaging part, 42-second packaging part, 5-second port, 51-I port, 52-O port, 6-first port, 61-input port, 62-output port, 7-first bonding pad, 8-second bonding pad.
Detailed Description
The embodiments described below with reference to the drawings are exemplary only for the purpose of explaining the present application and are not to be construed as limiting the present application.
The quantum chip is a processor for executing quantum computation in a quantum computer, the quantum chip comprises a quantum bit structure as a processing unit of the processor, the quantum bit comprises a capacitor and a SQUID structure connected with the capacitor in parallel, and the quantum bit is an energy level system constructed by the capacitor and the SQUID structure connected with the capacitor in parallel. The quantum chip is integrated with a plurality of quantum bits and reading resonant cavities which are in one-to-one correspondence and mutually coupled, one end of each reading resonant cavity, which is far away from the corresponding quantum bit, is connected to a reading signal transmission line which is integrated on the quantum chip, and the reading signal transmission line is used for receiving a reading input signal and transmitting a reading output signal responding to the reading input signal; each qubit is coupled with an XY signal transmission line and a Z signal transmission line (i.e., a frequency control line, Z-control line), a magnetic flux control signal on the Z signal transmission line adjusts the frequency of the qubit to a working frequency, and then a quantum state control signal is applied through the XY signal transmission line to perform quantum state control on the qubit in an initial state, a read resonant cavity is used to read the quantum state of the regulated qubit, specifically, an input carrier frequency pulse signal, for example, a microwave signal with a frequency of 4-8GHz, is applied through the read signal transmission line, and a response signal output by the read signal transmission line is analyzed to determine the quantum state in which the qubit is located.
For a quantum chip, basic parameters representing the performance of the quantum chip need to meet certain requirements to support quantum computation execution, and the basic parameters of a qubit include bit frequency, bit detuning, bit coherence time, reading cavity frequency, dispersion shift, and the like. Due to constraint limits of quantum chip hardware manufacturing technology, influence of working environment factors and the like, performance parameters of a quantum chip are easy to fluctuate, so that operation and reading of a quantum logic gate are influenced, for example, the fidelity of operation of the quantum logic gate is reduced, and the accuracy and efficiency of reading are also influenced. Therefore, the quantum chip prepared by the flow sheet process needs to be tested to know whether each basic parameter of the quantum chip is normal. Typically, a series of test characterizations are performed and characterization of the fundamental parameters of the qubit is achieved by reading the input signal on the signal line and processing the analysis of the output signal. In some test characterization experiments, the frequency of a qubit is changed by changing the magnetic flux obtained by a frequency control line (Z-control line), the frequency of a read cavity generates a discrete shift due to the dispersive coupling of the qubit and the read cavity, and then a fundamental parameter representing the performance of the quantum ratio is characterized by a scattering parameter S21 determined from an input signal and an output signal on a read signal line. The experimental procedure for testing the characterization requires that the frequency of the qubit be controllable, for example, in order to characterize some properties of the qubit and to adjust the single-qubit gate, the frequency of the qubit to be tested needs to be adjusted to the operating point according to the modulation profile of the Z-signaling line on the reading cavity. However, if the Z signal transmission line on the quantum chip is abnormal, the experiment of the test characterization described above cannot be performed for the quantum chip.
Fig. 1 is a schematic main structural diagram of a testing apparatus according to an embodiment of the present disclosure;
fig. 2 is a schematic main structural diagram of the second surface 12 of the substrate 1 according to an embodiment of the present disclosure.
Referring to fig. 1 and 2, an aspect of the present application provides a magnetic flux regulating structure including: a substrate 1; and a coil 2 on the substrate 1, the coil 2 having an I/O port. The I/O ports may comprise an input port 23 and an output port 24 of the coil 2. The SQUID structure can be equivalently regarded as a Josephson junction with critical current changing along with an external magnetic field, and the frequency of a quantum bit can be controlled by applying the external magnetic field.
In some embodiments, the substrate 1 comprises: alumina substrate, quartz glass substrate, ceramic substrate, sapphire substrate. Any suitable material may be selected for the substrate 1, wherein, for example, the substrate 1 may be an alumina substrate, a quartz glass substrate, a ceramic substrate, a sapphire substrate, or any combination thereof. The coil 2 formed on one surface of the substrate 1, the coil 2 may be formed in the form of a thin film circuit on one surface of the substrate 1, and the I/O port may take any suitable form, for example, in the form of a pad, wherein the thin film circuit may be formed by photolithography, plating, or the like, and patterned accordingly.
In some embodiments, the coil 2 is a thin film circuit formed on the surface of the substrate 1 and the thin film circuit is formed on the second surface 12 of the substrate 1, as will be understood by those skilled in the art, although in the present disclosure (including the drawings), the thin film circuit is depicted on the bottom surface of the substrate 1, the selection of top and bottom surfaces is relative and can be adjusted as desired.
In some embodiments, the thin film circuit comprises a superconducting transmission line. The superconducting transmission line may be formed of a superconductor material exhibiting superconducting characteristics at a temperature equal to or lower than a critical temperature, for example, at about 10-100 millikelvin (mK) or about 4K, such as aluminum, niobium, tantalum, titanium nitride, or the like, and the specific implementation is not limited thereto, and materials exhibiting superconducting characteristics at a temperature equal to or lower than a critical temperature may be used to form the superconducting transmission line. In some embodiments, the superconducting transmission line is a tantalum nitride transmission line.
The fabrication of thin film circuits may require the deposition of one or more materials, such as superconductors, dielectrics, and/or metals. Depending on the materials selected, these materials may be deposited using deposition processes such as chemical vapor deposition, physical vapor deposition (e.g., evaporation or sputtering), or epitaxial techniques, among others. The process of making the thin film circuits described in the embodiments of the present application may require the removal of one or more materials from the device during the manufacturing process. Depending on the material to be removed, the removal process may include, for example, a wet etching technique, a dry etching technique, or a lift-off (lift-off) process. The materials forming the circuit elements described herein may be patterned using known exposure (lithographical) techniques, such as photolithography or electron beam exposure.
In some embodiments, the coil 2 includes a first partial coil 21 and a second partial coil 22 connected in series and having opposite winding directions, and the whole of the second partial coil 22 is located in the whole of the first partial coil 21. It will be appreciated that the superconducting transmission line comprises two sections in series, one forming the first partial coil 21 and the other forming the second partial coil 22. In view of the fact that the central magnetic field is strong and the peripheral magnetic field is weak when the overall winding directions of the coils are kept consistent, and the magnetic field where the SQUID structure of each quantum bit on the quantum chip is located is easily uneven, in the embodiment of the present application, two partial coils with opposite winding directions are arranged in series and a form is adopted in which the whole of one partial coil is located inside the whole of the other partial coil, so that the central magnetic field can be relatively weakened, the peripheral annular magnetic field can be strengthened, and the uniformity of a certain degree can be favorably realized, or acceptable uniformity can be realized in a desired area. It is understood that, in the embodiment of the present application, the first partial coil 21 and the second partial coil 22 connected in series and having opposite winding directions may also be the above-mentioned thin film circuits, and the first partial coil 21 and the second partial coil 22 may be formed by photolithography, electroplating, or the like, which are prepared in synchronization with the above-mentioned processes. As shown in fig. 3, the superconducting transmission line formed on the second surface 12 of the substrate 1 includes an input port 23, an output port 24, and a transition point 25 located between the input port 23 and the output port 24, the transition point 25 divides the superconducting transmission line into two parts, a first part coil 21 is formed in the part between the input port 23 and the transition point 25, a second part coil 22 is formed in the part between the transition point 25 and the output port 24, the winding direction of the superconducting transmission line in the first part coil 21 is opposite to the winding direction of the superconducting transmission line in the second part coil 22, and the first part coil 21 and the second part coil 22 are connected in series at the transition point 25.
Referring to fig. 1 and 2, another aspect of the present application further provides a test apparatus including: the quantum chip to be tested is not shown in fig. 1 and fig. 2, and as described above, a plurality of quantum bits and read resonators that are in one-to-one correspondence and are coupled to each other are integrated on the quantum chip, one end of each read resonator, which is far away from the corresponding quantum bit, is connected to a read signal transmission line that is integrated on the quantum chip, and the read signal transmission line is configured to receive a read input signal and transmit a read output signal in response to the read input signal; each qubit is coupled with an XY signal transmission line and a Z signal transmission line (i.e., a frequency control line); the magnetic flux regulating structure is as described above, and the coil 2 is opposite to a surface having the SQUID structure on the quantum chip; an encapsulation structure 4 having a first port 6 and a second port 5, wherein the encapsulation structure 4 is used for encapsulating the quantum chip and the magnetic flux regulating structure, the first port 6 is connected with the quantum chip in a bonding manner, and the second port 5 is used for being connected with the I/O port; and a test instrument connected to the first port 6 and the second port 5.
The application provides a testing arrangement utilizes test instrument to exert current through second port 5 and can make coil 2 produce induction magnetic field, and then adjusts and control the magnetic flux of SQUID structure in corresponding quantum bit, rethread first port 6 gather quantum chip response with the parameter information of current, can realize the test to quantum chip to the problem that can't test quantum chip under the unusual circumstances of frequency regulation and control line of quantum chip has been solved. The package structure 4 may be a split structure including a first package 41 and a second package 42, the first package 41 and the second package 42 are assembled by a fixed connection element to form a space isolated from the external environment, and the opposing magnetic flux modulating structure and the quantum chip are disposed in the space, so that the magnetic flux modulating structure and the quantum chip are subjected to less interference or even no interference.
In some embodiments of the present application, the substrate 1 and the package structure 4 are fixedly connected by a connector 3. The connecting member 3 and the substrate 1 and the package structure 4 may be mounted in a threaded screw hole matching manner.
In some embodiments, the second port 5 includes an I port 51 and an O port 52, each of the I port 51 and the O port 52 is a cable connector, which may be an SMA connector or an SMP connector embedded in a sidewall of the package structure 4, and the substrate 2 has an interconnecting element formed therethrough, and the interconnecting element electrically connects the I/O port and the cable connector. The interconnection elements are formed in vias through the substrate 2 and are of a material and structure that enables electrical and physical connection, in one example the interconnection elements may be conductive pillars filled in the vias, the conductive pillars being connected to I/O ports of the second surface 12 and to top via pads of the first surface 12 through which electrical and physical connection with the cable tie is made, in another example the interconnection elements may be conductive layers plated to the inner walls of the vias, the conductive layers being connected to I/O ports of the second surface 12 and to top via pads of the first surface 11. In some embodiments, the interconnection element is a superconducting element, and the superconducting element may be formed of a superconductor material exhibiting superconducting properties at a temperature at or below a critical temperature, such as at about 10-100 millikelvin (mK) or about 4K, for example, aluminum, niobium, tantalum, titanium nitride, or the like, and is not limited in particular implementation, and materials exhibiting superconducting properties at a temperature at or below a critical temperature may be used to form the superconducting element. In some embodiments, the superconducting element comprises indium. In some embodiments, the interconnect element is in the form of a conductive layer plated to an inner wall of the via hole, and the conductive layer is a superconducting layer. The top via pad at the first surface 11 comprises a first pad 7 and a second pad 8, wherein the first pad 7 is conductively connected to the input port 23 and the second pad 8 is conductively connected to the output port 24 via the through-going interconnect element.
In some embodiments, the first port 6 includes an input port 61 and an output port 62, the input port 61 and the output port 62 are both cable connectors, the cable connectors may be SMA connectors or SMP connectors embedded on a side wall of the package structure 4, and are connected with the signal transmission lines on the quantum chip through the SMA connectors or SMP connectors, in a feasible form, the quantum chip is placed on the PCB and the transmission lines on the PCB board have one end bonded with the signal transmission lines on the quantum chip and the other end connected with the cable connectors, and the signal transmission lines on the quantum chip include, but are not limited to, read signal lines.
Fig. 3 is a schematic flowchart of quantum chip testing provided in an embodiment of the present application.
Referring to fig. 3 in conjunction with fig. 1-2, a further aspect of the present application provides a testing method comprising:
aiming at the quantum bit on the quantum chip, applying a magnetic flux regulation and control signal through a corresponding frequency regulation and control line and measuring the frequency of the quantum bit, so that the change condition of the frequency along with the magnetic flux regulation and control signal can be scanned;
judging whether the frequency comprises a target value, wherein the target value is a frequency value when the qualified quantum bit executes quantum computation work;
if not, executing the following steps S301 to S303, wherein:
step S301, enabling the magnetic flux regulation and control structure to be opposite to the quantum chip, and introducing current into the coil; in specific implementation, the quantum chip and the coil structure can be placed face to face for packaging, and then current is introduced into the coil;
step S302, collecting scattering parameters S21 of a quantum chip under the regulation and control action of the current, wherein quantum bits on the quantum chip are coupled with a read signal transmission line through a read resonant cavity, and the scattering parameters on the read signal transmission line can be collected, specifically, the scattering parameters S21 can be directly measured and obtained through a measuring instrument connected with an input port and an output port of the read signal transmission line, it needs to be noted that a plurality of quantum bits are usually arranged on the quantum chip, and different quantum bits can be coupled to different read signal transmission lines through the read resonant cavity, so that the read signal transmission line on the quantum chip, which needs to collect the scattering parameters 21, can be determined according to target bits regulated and controlled by the magnetic flux regulation and control structure;
and S303, determining a test result of the quantum chip according to the scattering parameters.
It should be noted that the step of determining whether the frequency includes the target value is mainly to determine whether a frequency modulation line prepared on the quantum chip is abnormal, and if the frequency does not include the target value, it indicates that the magnetic flux modulation signal applied through the frequency modulation line cannot make the frequency of the qubit reach the desired target value, which indicates that there may be an abnormality in the frequency modulation line, and it should be noted that the abnormality in the frequency modulation line has various forms and is not easy to be found, for example, a short circuit, an open circuit, or a quench at a certain current. Therefore, in specific implementation, the magnetic flux regulation and control structure can be directly opposite to the quantum chip, current is introduced into the coil, then scattering parameters S21 corresponding to the current are collected, and the test result of the quantum chip is determined according to the scattering parameters.
According to the testing method provided by the embodiment of the application, the magnetic flux regulation and control structure and the quantum chip are placed face to face, current is introduced into the coil, then scattering parameters corresponding to the current are collected, then the testing result of the quantum chip is determined according to the scattering parameters, namely, the coil formed on the substrate is utilized to form a magnetic field to be applied to the quantum chip so as to regulate and control the magnetic flux of the SQUID, then the quantum chip is tested, and therefore the problem that the quantum chip cannot be tested under the condition that the frequency regulation and control line of the quantum chip is abnormal is solved.
In some embodiments of the present application, the current applied to the coil is adjusted according to a target range to be achieved by the frequency of the qubit during mutual inductive coupling, for example, the current applied to the coil is ensured to enable a mutual inductance value between the coil and the SQUID structure corresponding to the qubit to reach 0.4pH to 0.6pH, and in specific implementations, the mutual inductance value may also be adjusted according to design parameters of the qubit.
The construction, features and functions of the present application have been described in detail and illustrated in the drawings, the present application is not limited to the embodiments, but rather the invention is intended to cover all modifications, equivalents and equivalents falling within the spirit and scope of the present application.
Claims (10)
1. A magnetic flux regulating structure, comprising:
a substrate; and
a coil on the substrate, the coil having an I/O port.
2. The magnetic flux regulating structure according to claim 1, wherein the substrate comprises: alumina substrate, quartz glass substrate, ceramic substrate, sapphire substrate.
3. The magnetic flux regulating structure according to claim 1, wherein the coil is a thin film circuit formed on the surface of the substrate.
4. The magnetic flux regulating structure according to claim 3, wherein said thin film circuit comprises a superconducting transmission line.
5. The magnetic flux regulating structure according to claim 4, wherein the superconducting transmission line is a tantalum nitride transmission line.
6. The magnetic flux regulating structure according to any one of claims 1 to 5, wherein the coil comprises a first partial coil and a second partial coil which are connected in series and have opposite winding directions, and the whole of the second partial coil is located in the whole of the first partial coil.
7. A test apparatus, comprising:
a quantum chip to be tested;
the magnetic flux modulating structure of any one of claims 1-6, with the coil opposing the quantum chip;
the packaging structure is provided with a first port and a second port, the packaging structure is used for packaging the quantum chip and the magnetic flux regulation structure, the first port is connected with the quantum chip in a bonding mode, and the second port is used for being connected with the I/O port; and
a test instrument connected with the first port and the second port.
8. The test device of claim 7, wherein the second port includes a cable lug, the substrate having an interconnect element formed therethrough, the interconnect element electrically connecting the I/O port with the cable lug.
9. The test device of claim 8, wherein the interconnect element comprises a superconducting layer formed within a via.
10. A method of testing, comprising:
the magnetic flux regulating structure as claimed in any one of claims 1 to 6 is arranged opposite to the quantum chip, and current is passed through the coil;
collecting scattering parameters of the quantum chip under the regulation and control action of the current;
and determining the test result of the quantum chip according to the scattering parameters.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117521594A (en) * | 2023-11-15 | 2024-02-06 | 北京百度网讯科技有限公司 | Superconducting quantum chip simulation verification method and device, electronic equipment and medium |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06230094A (en) * | 1993-02-03 | 1994-08-19 | Hitachi Ltd | Superconducting quantum interference element fluxmeter |
| CN105093093A (en) * | 2015-07-17 | 2015-11-25 | 中国科学院上海微系统与信息技术研究所 | SQUID chip and detection method thereof |
| US20170178018A1 (en) * | 2015-12-21 | 2017-06-22 | D-Wave Systems Inc. | Systems, methods and apparatus for use with superconducting based computing systems |
| CN107919433A (en) * | 2017-11-06 | 2018-04-17 | 中国科学院上海微系统与信息技术研究所 | A kind of manufacture device and method of the axial gradiometers of based superconductive connection |
| CN111554798A (en) * | 2020-04-30 | 2020-08-18 | 合肥本源量子计算科技有限责任公司 | Quantum chip test structure, preparation method and test method thereof |
| CN112444713A (en) * | 2019-08-28 | 2021-03-05 | 合肥本源量子计算科技有限责任公司 | Quantum chip detection method |
-
2022
- 2022-05-10 CN CN202210507332.3A patent/CN115458270B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06230094A (en) * | 1993-02-03 | 1994-08-19 | Hitachi Ltd | Superconducting quantum interference element fluxmeter |
| CN105093093A (en) * | 2015-07-17 | 2015-11-25 | 中国科学院上海微系统与信息技术研究所 | SQUID chip and detection method thereof |
| US20170178018A1 (en) * | 2015-12-21 | 2017-06-22 | D-Wave Systems Inc. | Systems, methods and apparatus for use with superconducting based computing systems |
| CN107919433A (en) * | 2017-11-06 | 2018-04-17 | 中国科学院上海微系统与信息技术研究所 | A kind of manufacture device and method of the axial gradiometers of based superconductive connection |
| CN112444713A (en) * | 2019-08-28 | 2021-03-05 | 合肥本源量子计算科技有限责任公司 | Quantum chip detection method |
| CN111554798A (en) * | 2020-04-30 | 2020-08-18 | 合肥本源量子计算科技有限责任公司 | Quantum chip test structure, preparation method and test method thereof |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117521594A (en) * | 2023-11-15 | 2024-02-06 | 北京百度网讯科技有限公司 | Superconducting quantum chip simulation verification method and device, electronic equipment and medium |
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