CN115454752A - Verification method, device, terminal and medium for detecting PCIe equipment speed reduction by BIOS - Google Patents

Verification method, device, terminal and medium for detecting PCIe equipment speed reduction by BIOS Download PDF

Info

Publication number
CN115454752A
CN115454752A CN202211201061.5A CN202211201061A CN115454752A CN 115454752 A CN115454752 A CN 115454752A CN 202211201061 A CN202211201061 A CN 202211201061A CN 115454752 A CN115454752 A CN 115454752A
Authority
CN
China
Prior art keywords
bios
pcie
detecting
speed reduction
breakpoint
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202211201061.5A
Other languages
Chinese (zh)
Inventor
席泽鹏
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Suzhou Inspur Intelligent Technology Co Ltd
Original Assignee
Suzhou Inspur Intelligent Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Suzhou Inspur Intelligent Technology Co Ltd filed Critical Suzhou Inspur Intelligent Technology Co Ltd
Priority to CN202211201061.5A priority Critical patent/CN115454752A/en
Publication of CN115454752A publication Critical patent/CN115454752A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/2221—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test input/output devices or peripheral units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/221—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test buses, lines or interfaces, e.g. stuck-at or open line faults
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2289—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing by configuration test

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)

Abstract

The invention relates to the field of BIOS function detection, and discloses a verification method, a device, a terminal and a medium for detecting the speed reduction of PCIe equipment by a BIOS, wherein a starting breakpoint program is configured in a BIOS code; restarting the machine, and before the breakpoint, detecting and recording the speed of the PCIe equipment by the BIOS; when the starting process reaches the breakpoint, the starting process is suspended, and the PCIe equipment is subjected to speed reduction configuration; after the starting process is restarted, the BIOS detects the speed of the PCIe equipment again and records the speed; after the boot is finished, detecting whether the BMC log contains a PCIe device deceleration log; if yes, the BIOS detects that the speed reduction function of the PCIe equipment is normal; otherwise, the BIOS detects a PCIe device speed reduction function exception. The invention sets the breakpoint in the starting process, and reduces the speed of the PCIe equipment so as to verify whether the BIOS can successfully detect the speed reduction of the PCIe equipment, and the fault PCIe equipment is not needed to be used, so that the test convenience and the test efficiency are improved.

Description

Verification method, device, terminal and medium for detecting PCIe equipment speed reduction by BIOS
Technical Field
The invention relates to the field of BIOS function detection, in particular to a verification method, a verification device, a verification terminal and a verification medium for detecting the speed reduction of PCIe equipment by a BIOS.
Background
The PCIe device is a common component in the server, and almost all peripheral hardware adopts the PCIe protocol, which is very important to ensure that the PCIe device can work normally. One problem common in practical applications is that a PCIe device is slowed down and once it happens, a worker needs to go to locate whether the reason is a hardware defect or not. Generally, in a boot process, i.e., an initialization stage, the BIOS detects a maximum rate and an actual rate supported by the PCIe device to determine whether a speed reduction occurs. In order to ensure that the BIOS can detect the PCIe device speed reduction, the function of detecting the PCIe device speed reduction by the BIOS needs to be tested in the server test stage, and the PCIe device with a failure is generally used to verify the BIOS to detect the PCIe device speed reduction currently, however, such PCIe devices are not well-found, which brings inconvenience to the test.
Disclosure of Invention
In order to solve the above problems, the present invention provides a verification method, apparatus, terminal and medium for detecting the speed reduction of the PCIe device by the BIOS, wherein a breakpoint is set during the boot process, and the speed reduction is performed on the PCIe device to verify whether the BIOS can successfully detect the speed reduction of the PCIe device, and the PCIe device does not need to be failed, thereby improving the test convenience and the test efficiency.
In a first aspect, a technical solution of the present invention provides a verification method for detecting a PCIe device speed reduction by a BIOS, including the following steps:
configuring a starting breakpoint program in the BIOS code;
restarting the machine, and before the breakpoint, detecting and recording the speed of the PCIe equipment by the BIOS;
when the starting process reaches the breakpoint, the starting process is suspended, and the PCIe equipment is subjected to speed reduction configuration;
after the starting process is restarted, the BIOS detects and records the speed of the PCIe equipment again;
after the boot is finished, detecting whether the BMC log contains a PCIe device deceleration log;
if yes, the BIOS detects that the speed reduction function of the PCIe equipment is normal; otherwise, the BIOS detects the PCIe device speed reduction function exception.
Further, before configuring the boot breakpoint program in the BIOS code, the method further includes the following steps:
view PCIe device rate;
detecting whether the PCIe device rate is consistent with the actually supported maximum rate;
if the BIOS codes are consistent, a startup breakpoint program is configured in the BIOS codes; and if the two are not consistent, an alarm is given.
Further, the boot breakpoint procedure is configured in the BIOS code by the csccripts tool.
Further, the PCIe device is down-configured by the csccripts utility.
In a second aspect, the present invention provides a verification apparatus for detecting the speed reduction of a PCIe device by a BIOS, including,
a breakpoint program configuration module: configuring a starting breakpoint program in the BIOS code;
a first rate detection module: restarting the machine, and before the breakpoint, detecting and recording the speed of the PCIe equipment by the BIOS;
a deceleration configuration module: when the starting process reaches the breakpoint, the starting process is suspended, and the PCIe equipment is subjected to speed reduction configuration;
a second rate detection module: after the starting process is restarted, the BIOS detects the speed of the PCIe equipment again and records the speed;
a log detection module: after the boot is finished, detecting whether the BMC log contains a PCIe device deceleration log;
a verification result analysis module: if yes, the BIOS detects that the speed reduction function of the PCIe equipment is normal; otherwise, the BIOS detects a PCIe device speed reduction function exception.
Further, the device also comprises a control device,
a rate viewing module: view PCIe device rate;
a rate judging module: detecting whether the PCIe device rate is consistent with the actually supported maximum rate; if the two codes are consistent, informing a breakpoint program configuration module to configure a startup breakpoint program in the BIOS code; and if the two are not consistent, an alarm is given.
Further, the breakpoint program configuration module configures the boot breakpoint program in the BIOS code through the csccripts tool.
Further, the slowdown configuration module performs slowdown configuration on the PCIe device through a CScripts tool.
In a third aspect, a technical solution of the present invention provides a terminal, including:
the memory is used for storing a verification program for detecting the speed reduction of the PCIe equipment by the BIOS;
and the processor is used for realizing the steps of the verification method for detecting the PCIe device speed reduction by the BIOS when executing the verification program for detecting the PCIe device speed reduction by the BIOS.
In a fourth aspect, the technical solution of the present invention provides a readable storage medium, where a verification program for detecting the PCIe device speed reduction by the BIOS is stored on the readable storage medium, and when executed by a processor, the verification program for detecting the PCIe device speed reduction by the BIOS implements the steps of the verification method for detecting the PCIe device speed reduction by the BIOS as described in any one of the above.
Compared with the prior art, the verification method, the device, the system, the terminal and the medium for detecting the speed reduction of the PCIe equipment by the BIOS have the following beneficial effects: and setting a breakpoint in the starting process, and slowing down the PCIe equipment to verify whether the BIOS can successfully detect the slowdown of the PCIe equipment or not, so that the fault PCIe equipment is not required to be used, and the test convenience and the test efficiency are improved.
Drawings
For a clearer explanation of the embodiments or technical solutions of the prior art of the present application, the drawings needed for the description of the embodiments or prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a schematic flowchart of a verification method for detecting a PCIe device speed reduction by a BIOS according to an embodiment of the present invention.
Fig. 2 is a flowchart illustrating a verification method for detecting a PCIe device speed reduction by the BIOS according to an embodiment of the present invention.
Fig. 3 is a block diagram illustrating a structure of an authentication apparatus for detecting a PCIe device speed reduction by a BIOS according to an embodiment of the present invention.
Fig. 4 is a schematic structural diagram of a terminal according to a fifth embodiment of the present invention.
Detailed Description
In order that those skilled in the art will better understand the disclosure, the following detailed description will be given with reference to the accompanying drawings. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Fig. 1 is a flowchart illustrating a verification method for detecting a PCIe device speed reduction by a BIOS according to an embodiment of the present invention, as shown in fig. 1, the method includes the following steps.
S1, configuring a power-on breakpoint program in a BIOS (basic input/output system) code.
The startup breakpoint program refers to normal startup after the machine is powered on, the startup is suspended when the startup program reaches the breakpoint, the task processing is performed by the staff, and the startup is driven to continue after the task processing is completed.
And S2, restarting the machine, and before the breakpoint, detecting and recording the speed of the PCIe equipment by the BIOS.
Before the breakpoint, the BIOS normally detects the rate of the PCIe device, records the rate, and compares the rate with the subsequent collected PCIe device rate.
And S3, when the starting process reaches the breakpoint, the starting process is suspended, and the PCIe equipment is subjected to speed reduction configuration.
It should be noted that, the PCIe devices may be configured to be slowed down manually by an operator, or may be automatically executed by a program, and the operator or the program may select one or some PCIe devices to slow down according to actual situations or requirements. Such as a PCIe device dropping from Gen4 to Gen3.
And S4, after the starting process is restarted, the BIOS detects the speed of the PCIe equipment again and records the speed.
After the PCIe equipment is processed and the speed is reduced, the machine is enabled to run continuously, the starting process is restarted, and the BIOS can continuously detect and record the PCIe equipment speed.
Because the rate of the PCIe device is changed before and after the breakpoint, the rate is reduced, under normal conditions, the BIOS can detect the reduction of the rate of the PCIe device according to the recorded data of the two stages, and at this time, the BMC log can be generated by triggering, and if the BIOS has abnormal functions, the rate reduction of the PCIe device can not be detected, and the BMC log cannot be generated.
And S5, after the boot is finished, detecting whether the BMC log contains a PCIe device deceleration log.
S6, if yes, the BIOS detects that the speed reduction function of the PCIe equipment is normal; otherwise, the BIOS detects a PCIe device speed reduction function exception.
After the boot is finished, whether the detection function of the BIOS is normal is judged by checking whether the BMC log contains the PCIe device deceleration log, if so, the BIOS detects that the PCIe device deceleration function is normal, and if not, the BIOS detects that the PCIe device deceleration function is abnormal.
The verification method for detecting the speed reduction of the PCIe equipment by the BIOS provided by the embodiment of the invention sets the breakpoint in the starting process, and reduces the speed of the PCIe equipment so as to verify whether the BIOS can successfully detect the speed reduction of the PCIe equipment, and the method does not need to use the fault PCIe equipment, thereby improving the test convenience and the test efficiency.
Fig. 2 is a flowchart illustrating a verification method for detecting a PCIe device speed reduction by the BIOS according to an embodiment of the present invention, as shown in fig. 2, the method includes the following steps.
S1, checking the PCIe device speed.
And S2, detecting whether the PCIe equipment speed is consistent with the actually supported maximum speed.
S3, if the two are consistent, executing the next step; and if the two are not consistent, an alarm is given.
Before the verification of the BIOS detection function is executed, the actual speed of the PCIe equipment is checked, and it can be understood that the PCIe equipment which executes the speed reduction subsequently is checked, and whether the actual speed of the PCIe equipment is consistent with the actually supported maximum speed or not is checked, so that the PCIe equipment which executes the speed reduction subsequently runs at the maximum speed, and the subsequent speed reduction and the detection are facilitated.
If the actual speed of the PCIe equipment is inconsistent with the actually supported maximum speed, an alarm is sent out, and other PCIe equipment can be selected for detection and other processing.
And S4, configuring a power-on breakpoint program in the BIOS code.
And S5, restarting the machine, and before the breakpoint, detecting and recording the speed of the PCIe equipment by the BIOS.
It should be noted that, before the breakpoint, the rate of the PCIe device detected by the BIOS should be the maximum rate actually supported by the PCIe device.
And S6, when the starting process reaches the breakpoint, the starting process is suspended, and the PCIe equipment is subjected to speed reduction configuration.
And S7, after the starting process is restarted, the BIOS detects the speed of the PCIe equipment again and records the speed.
And S8, after the boot is finished, detecting whether the BMC log contains a PCIe device deceleration log.
S9, if the PCIe device speed reduction function is normal, the BIOS detects that the PCIe device speed reduction function is normal; otherwise, the BIOS detects a PCIe device speed reduction function exception.
The verification method for detecting the speed reduction of the PCIe equipment by the BIOS provided by the embodiment of the invention sets the breakpoint in the starting process, and reduces the speed of the PCIe equipment so as to verify whether the BIOS can successfully detect the speed reduction of the PCIe equipment, and the method does not need to use the fault PCIe equipment, thereby improving the test convenience and the test efficiency.
On the basis of the above embodiment, as a preferred implementation, the CScripts tool is used to configure the boot breakpoint program in the BIOS code, and at the same time, the CScripts tool is used to perform the speed reduction configuration on the PCIe device.
The cscrips tool has many commands, where a break point is set using sv.
To further understand the present invention, a specific example is provided below to further illustrate the present invention, which includes the following steps.
First, look at the PCIe device rate.
And entering the OS, starting CScripts, and using the pci.
Second, the biosctratched 6_ cfg breakpoint is set.
The configuration of the break points exists in the BIOS code, looking for a break point before which the BIOS has scanned the PCIe device and detected the maximum rate supported, after which the BIOS will detect if the actual rate of the PCIe device has dropped. In cscrips, a break point is set using sv. Running to this breakpoint, the machine will stop and then may continue to perform the following steps.
Third, the PCIe device is slowed down.
After the breakpoint comes to a stop, the PCIe device is slowed down. The rate of a PCIe device at a specified location may be changed using the command PCIe. For example, in a first step it is seen that the rate for PCIe devices is Gen4, which is dropped to Gen3. Go () is then executed to let the machine continue running.
Fourthly, the BMC log is checked to see whether a log of the PCIe device speed reduction is generated. If the log exists, the log indicates that the BIOS successfully detects that the PCIe device is decelerated, and reports the log to the BMC.
The above embodiment of the verification method for detecting the PCIe device speed reduction by the BIOS is described in detail, and based on the verification method for detecting the PCIe device speed reduction by the BIOS described in the above embodiment, the embodiment of the present invention further provides a verification device for detecting the PCIe device speed reduction by the BIOS, which corresponds to the verification method.
Fig. 3 is a schematic block diagram of a structure of an authentication apparatus for detecting a PCIe device speed reduction by a BIOS according to an embodiment of the present invention, as shown in fig. 3, the authentication apparatus 300 includes: breakpoint program configuration module 310, first rate detection module 320, speed reduction configuration module 330, second rate detection module 340, log detection module 350, verification result analysis module 360, rate viewing module 370, and rate determination module 380.
Breakpoint program configuration module 310: and configuring a starting breakpoint program in the BIOS code.
The first rate detection module 320: and restarting the machine, and before the breakpoint, detecting the speed of the PCIe device by the BIOS and recording the speed.
The down configuration module 330: and when the starting process reaches the breakpoint, the starting process is suspended, and the PCIe equipment is subjected to speed reduction configuration.
The second rate detection module 340: after the boot process is restarted, the BIOS detects and records the rate of the PCIe device again.
The log detection module 350: and after the boot is finished, detecting whether the BMC log contains a PCIe device deceleration log.
The verification result analysis module 360: if yes, the BIOS detects that the speed reduction function of the PCIe equipment is normal; otherwise, the BIOS detects a PCIe device speed reduction function exception.
The rate view module 370: look at the PCIe device rate.
Rate determination block 380: detecting whether the PCIe device rate is consistent with the actually supported maximum rate; if the two codes are consistent, informing a breakpoint program configuration module to configure a startup breakpoint program in the BIOS code; and if the two are not consistent, an alarm is given.
The breakpoint program configuration module 310 configures a boot breakpoint program in the BIOS code through the csccripts tool. The slowdown configuration module 330 may perform slowdown configuration of the PCIe devices via CScripts tools.
The verification apparatus for detecting the PCIe device speed reduction by the BIOS of this embodiment is used to implement the aforementioned verification method for detecting the PCIe device speed reduction by the BIOS, so a specific implementation of the apparatus may be found in the foregoing part of the verification method for detecting the PCIe device speed reduction by the BIOS, and therefore, the specific implementation thereof may refer to the description of the corresponding embodiments of the respective parts, and is not described herein again.
In addition, since the verification apparatus for detecting the PCIe device speed reduction by the BIOS of this embodiment is used to implement the verification method for detecting the PCIe device speed reduction by the BIOS, the function corresponds to the function of the method, and details are not described here.
Fig. 4 is a schematic structural diagram of a terminal device 400 according to an embodiment of the present invention, including: a processor 410, a memory 420, and a communication unit 430. The processor 410 is configured to implement the following steps when implementing the verification procedure for detecting the PCIe device speed reduction by the BIOS stored in the memory 420:
s1, configuring a power-on breakpoint program in the BIOS code.
And S2, restarting the machine, and before the breakpoint, detecting and recording the speed of the PCIe equipment by the BIOS.
And S3, when the starting process reaches the breakpoint, the starting process is suspended, and the PCIe equipment is subjected to speed reduction configuration.
And S4, after the starting process is restarted, the BIOS detects the speed of the PCIe equipment again and records the speed.
S5, after the boot is finished, detecting whether the BMC log contains a PCIe device deceleration log;
s6, if yes, the BIOS detects that the speed reduction function of the PCIe equipment is normal; otherwise, the BIOS detects a PCIe device speed reduction function exception.
The invention sets the breakpoint in the starting process, and reduces the speed of the PCIe equipment so as to verify whether the BIOS can successfully detect the speed reduction of the PCIe equipment, and the fault PCIe equipment is not needed to be used, so that the test convenience and the test efficiency are improved.
The terminal apparatus 400 includes a processor 410, a memory 420, and a communication unit 430. The components communicate via one or more buses, and those skilled in the art will appreciate that the architecture of the servers shown in the figures is not intended to be limiting, and may be a bus architecture, a star architecture, a combination of more or less components than those shown, or a different arrangement of components.
The memory 420 may be used for storing instructions executed by the processor 410, and the memory 420 may be implemented by any type of volatile or non-volatile storage terminal or combination thereof, such as a Static Random Access Memory (SRAM), an electrically erasable programmable read-only memory (EEPROM), an erasable programmable read-only memory (EPROM), a programmable read-only memory (PROM), a read-only memory (ROM), a magnetic memory, a flash memory, a magnetic disk, or an optical disk. The executable instructions in memory 420, when executed by processor 410, enable terminal 400 to perform some or all of the steps in the method embodiments described below.
The processor 410 is a control center of the storage terminal, connects various parts of the entire electronic terminal using various interfaces and lines, and performs various functions of the electronic terminal and/or processes data by operating or executing software programs and/or modules stored in the memory 420 and calling data stored in the memory. The processor may be formed by an Integrated Circuit (IC), for example, a single packaged IC, or a plurality of packaged ICs with the same or different functions. For example, the processor 410 may include only a Central Processing Unit (CPU). In the embodiment of the present invention, the CPU may be a single operation core, or may include multiple operation cores.
A communication unit 430 for establishing a communication channel so that the storage terminal can communicate with other terminals. And receiving user data sent by other terminals or sending the user data to other terminals.
The present invention also provides a computer storage medium, wherein the storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM) or a Random Access Memory (RAM).
The computer storage medium stores a verification program for detecting the speed reduction of the PCIe device by the BIOS, and the verification program for detecting the speed reduction of the PCIe device by the BIOS realizes the following steps when being executed by a processor:
s1, configuring a power-on breakpoint program in the BIOS code.
And S2, restarting the machine, and before the breakpoint, detecting and recording the speed of the PCIe equipment by the BIOS.
And S3, when the starting process reaches the breakpoint, the starting process is suspended, and the PCIe equipment is subjected to speed reduction configuration.
And S4, after the starting process is restarted, the BIOS detects the speed of the PCIe equipment again and records the speed.
S5, after the boot is finished, detecting whether the BMC log contains a PCIe device deceleration log;
s6, if the PCIe equipment speed reduction function is normal, the BIOS detects that the PCIe equipment speed reduction function is normal; otherwise, the BIOS detects a PCIe device speed reduction function exception.
The invention sets the breakpoint in the starting process, and performs speed reduction on the PCIe equipment to verify whether the BIOS can successfully detect the speed reduction of the PCIe equipment, and the fault PCIe equipment is not needed to be used, so that the test convenience and the test efficiency are improved.
Those skilled in the art will readily appreciate that the techniques of the embodiments of the present invention may be implemented as software plus a required general purpose hardware platform. Based on such understanding, the technical solutions in the embodiments of the present invention may be embodied in the form of a software product, where the computer software product is stored in a storage medium, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and the like, and includes several instructions to make a computer terminal (which may be a personal computer, a server, or a second terminal, a network terminal, and the like) perform all or part of the steps of the methods in the embodiments of the present invention.
In the embodiments provided in the present invention, it should be understood that the disclosed system, apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, a division of a unit is merely a logical division, and an actual implementation may have another division, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
Units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.
The above disclosure is only for the preferred embodiments of the present invention, but the present invention is not limited thereto, and any non-inventive changes that can be made by those skilled in the art and several modifications and amendments made without departing from the principle of the present invention shall fall within the protection scope of the present invention.

Claims (10)

1. A verification method for detecting the speed reduction of PCIe equipment by a BIOS is characterized by comprising the following steps:
configuring a starting breakpoint program in the BIOS code;
restarting the machine, and before the breakpoint, detecting and recording the speed of the PCIe equipment by the BIOS;
when the starting process reaches the breakpoint, the starting process is suspended, and the PCIe equipment is subjected to speed reduction configuration;
after the starting process is restarted, the BIOS detects and records the speed of the PCIe equipment again;
after the boot is finished, detecting whether the BMC log contains a PCIe device deceleration log;
if yes, the BIOS detects that the speed reduction function of the PCIe equipment is normal; otherwise, the BIOS detects the PCIe device speed reduction function exception.
2. The method of claim 1, wherein before the BIOS code configures the boot breakpoint, the method further comprises the steps of:
view PCIe device rate;
detecting whether the PCIe device rate is consistent with the actually supported maximum rate;
if the BIOS codes are consistent, a startup breakpoint program is configured in the BIOS codes; and if the two are not consistent, an alarm is given.
3. The method of claim 2, wherein the boot breakpoint is configured in the BIOS code via a csccripts utility.
4. The verification method for detecting the slowdown of the PCIe device according to claim 3, wherein the PCIe device is configured for slowdown through CScripts tools.
5. A verification device for detecting the speed reduction of PCIe equipment by BIOS is characterized by comprising,
a breakpoint program configuration module: configuring a starting breakpoint program in the BIOS code;
a first rate detection module: restarting the machine, and before the breakpoint, detecting and recording the speed of the PCIe equipment by the BIOS;
a deceleration configuration module: when the starting process reaches the breakpoint, the starting process is suspended, and the PCIe equipment is subjected to speed reduction configuration;
a second rate detection module: after the starting process is restarted, the BIOS detects the speed of the PCIe equipment again and records the speed;
the log detection module: after the boot is finished, detecting whether the BMC log contains a PCIe device deceleration log;
a verification result analysis module: if yes, the BIOS detects that the speed reduction function of the PCIe equipment is normal; otherwise, the BIOS detects the PCIe device speed reduction function exception.
6. The BIOS verification apparatus for detecting a slowdown of a PCIe device of claim 5 further comprising,
a rate viewing module: view PCIe device rate;
a rate judging module: detecting whether the PCIe device rate is consistent with the actually supported maximum rate; if the two codes are consistent, informing a breakpoint program configuration module to configure a startup breakpoint program in the BIOS code; and if the two are not consistent, an alarm is given.
7. The apparatus of claim 6, wherein the breakpoint program configuration module configures the boot breakpoint program in the BIOS code via the csccripts utility.
8. The BIOS verification apparatus for detecting PCIe device slowdown according to claim 7, wherein the slowdown configuration module performs slowdown configuration on the PCIe device through the csccripts tool.
9. A terminal, comprising:
the memory is used for storing a verification program for detecting the speed reduction of the PCIe equipment by the BIOS;
a processor for implementing the steps of the verification method for detecting the speed reduction of the PCIe device by the BIOS according to any one of claims 1-4 when the verification program for detecting the speed reduction of the PCIe device by the BIOS is executed.
10. A readable storage medium having stored thereon a BIOS verification for detecting PCIe device speed degradation, the BIOS verification for detecting PCIe device speed degradation being executed by a processor to implement the steps of the BIOS verification for detecting PCIe device speed degradation method according to any one of claims 1 to 4.
CN202211201061.5A 2022-09-29 2022-09-29 Verification method, device, terminal and medium for detecting PCIe equipment speed reduction by BIOS Pending CN115454752A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202211201061.5A CN115454752A (en) 2022-09-29 2022-09-29 Verification method, device, terminal and medium for detecting PCIe equipment speed reduction by BIOS

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202211201061.5A CN115454752A (en) 2022-09-29 2022-09-29 Verification method, device, terminal and medium for detecting PCIe equipment speed reduction by BIOS

Publications (1)

Publication Number Publication Date
CN115454752A true CN115454752A (en) 2022-12-09

Family

ID=84308970

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202211201061.5A Pending CN115454752A (en) 2022-09-29 2022-09-29 Verification method, device, terminal and medium for detecting PCIe equipment speed reduction by BIOS

Country Status (1)

Country Link
CN (1) CN115454752A (en)

Similar Documents

Publication Publication Date Title
US20240012706A1 (en) Method, system and apparatus for fault positioning in starting process of server
CN109510742B (en) Server network card remote test method, device, terminal and storage medium
CN111488233A (en) Method and system for processing bandwidth loss problem of PCIe device
CN110058920B (en) Virtual machine performance detection method and device, electronic equipment and storage medium
CN114116280B (en) Interactive BMC self-recovery method, system, terminal and storage medium
CN111966380A (en) BMC (baseboard management controller) firmware upgrading method, system, terminal and storage medium
CN112231140A (en) Method, system, terminal and storage medium for fault recovery of BMC (baseboard management controller) of storage device
CN112000535A (en) SAS Expander card-based hard disk abnormity identification method and processing method
CN116820827B (en) Control method and system of substrate management controller of node server
CN114510381A (en) Fault injection method, device, equipment and storage medium
CN111124780B (en) UPI Link speed reduction test method, system, terminal and storage medium
CN112231170B (en) Data interaction card supervision method, system, terminal and storage medium
CN110134546B (en) Batch restarting windows system method, electronic device and storage medium
CN115454752A (en) Verification method, device, terminal and medium for detecting PCIe equipment speed reduction by BIOS
CN115827298A (en) Server startup fault positioning method and device, terminal and storage medium
CN116662050A (en) Error injection support function verification method, device, terminal and medium
CN115098342A (en) System log collection method, system, terminal and storage medium
CN114003416B (en) Memory error dynamic processing method, system, terminal and storage medium
CN112015587A (en) Method and device for enhancing reliability of operating system
CN114374627A (en) Method, device and system for restarting baseboard management controller and server
CN112463504B (en) Double-control storage product testing method, system, terminal and storage medium
CN115168146A (en) Anomaly detection method and device
CN114116276A (en) BMC hang-up self-recovery method, system, terminal and storage medium
CN114153503A (en) BIOS control method, device and medium
CN114461458A (en) Server memory test method, system, terminal and storage medium

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination