CN115454321A - Storage device and electronic equipment - Google Patents
Storage device and electronic equipment Download PDFInfo
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- CN115454321A CN115454321A CN202110644573.8A CN202110644573A CN115454321A CN 115454321 A CN115454321 A CN 115454321A CN 202110644573 A CN202110644573 A CN 202110644573A CN 115454321 A CN115454321 A CN 115454321A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0604—Improving or facilitating administration, e.g. storage management
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0614—Improving the reliability of storage systems
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/062—Securing storage systems
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
- H01R13/00—Details of coupling devices of the kinds covered by groups H01R12/70 or H01R24/00 - H01R33/00
- H01R13/02—Contact members
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- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Charge And Discharge Circuits For Batteries Or The Like (AREA)
Abstract
The application discloses storage device and electronic equipment, this storage device includes: an interface including a pre-charge pin and a power pin; wherein, the pre-charging pin is arranged to protrude out of the power pin; the surge protection circuit receives a pre-charging power supply signal sent by the external terminal through the pre-charging pin and limits the current of the pre-charging power supply signal when the interface is plugged into the external terminal and the pre-charging pin is electrically connected with a corresponding interface contact of the external terminal; the storage function circuit receives the pre-charging power supply signal subjected to current limiting by the surge protection circuit so as to carry out pre-charging; when the power pin is electrically connected with the corresponding interface contact of the external terminal, the storage function circuit receives a working power supply signal sent by the external terminal through the power pin. In this way, this application absorbs the very big surge current that the interface produced with external terminal plug in-process through surge protection circuit to can effectively protect storage device unlikely damaged by the overcurrent, and realize that the cost is lower.
Description
Technical Field
The present application relates to the field of data storage technologies, and in particular, to a storage device and an electronic apparatus.
Background
In the storage device, in order to ensure effective data storage and the requirement of corresponding time sequence, in the process of powering on the storage device, the storage device is usually precharged first before the storage device reaches a stable working state, and a capacitor device in the storage device is precharged, so that the storage device can quickly enter the working state when receiving a working power supply signal.
In order to ensure that the timing sequence of inputting the pre-charge power supply signal and the working power supply signal into the storage device is different, the golden finger corresponding to the interface in the storage device is usually designed by a long metal contact pin and a short metal contact pin, and the long pin is used for pre-charging the storage device in advance in the plugging process. However, because the current of a single metal pin is too large at the moment of realizing the electrical connection by plugging and unplugging, a surge of a higher current generally occurs, the storage device is abraded if the surge is light, and the storage device is directly damaged if the surge is heavy. In the existing protection mode of resisting surge current (instantaneous large current), a current-limiting switch chip or a fuse is used for protecting a rear-stage circuit in a more conventional mode so as to prevent the rear-stage circuit from being damaged by plugging transient current.
However, the cost of the current-limiting switch is usually high and the number of peripheral components is large, which occupies a large device area; the fuse can only be used for overcurrent protection, and the overcurrent condition can break the front-end circuit and the rear-end circuit so as to achieve the effect of protecting the rear-end circuit, but cannot achieve the effect of resisting surge current under the condition of meeting follow current (uninterrupted current).
Disclosure of Invention
The application provides a storage device to solve the anti surge current protection that storage device among the prior art adopted, realize with high costs, occupy more device area, or can't satisfy the problem of anti surge current under the condition of afterflow.
In order to solve the technical problem, the application adopts a technical scheme that: there is provided a storage device, wherein the storage device includes: an interface including a pre-charge pin and a power pin; wherein, the pre-charging pin is arranged to protrude out of the power pin; the surge protection circuit is electrically connected between the pre-charging pin and the power supply pin so as to be inserted into the external terminal at the interface, so that when the pre-charging pin is electrically connected with a corresponding interface contact of the external terminal, a pre-charging power supply signal sent by the external terminal is received through the pre-charging pin, and the pre-charging power supply signal is limited; the storage function circuit is electrically connected with the power supply pin and the surge protection circuit, and receives the pre-charging power supply signal subjected to current limiting by the surge protection circuit so as to pre-charge; when the power pin is electrically connected with the corresponding interface contact of the external terminal, the storage function circuit receives a working power supply signal sent by the external terminal through the power pin.
The number of the pre-charging pins, the number of the power pins and the number of the surge protection circuits are the same, and the pre-charging pins, the number of the power pins and the number of the surge protection circuits are all at least one, wherein each surge protection circuit is electrically connected between the corresponding pre-charging pin and the corresponding power pin.
The power supply pins comprise a first power supply pin and a second power supply pin, the first power supply pin and the second power supply pin are electrically connected and then electrically connected with one end of the surge protection circuit, and the other end of the surge protection circuit is electrically connected with the pre-charging pin.
The power supply pins comprise a first power supply pin and a second power supply pin, the first power supply pin is electrically connected with one end of the surge protection circuit after being electrically connected with the pre-charging pin, and the other end of the surge protection circuit is electrically connected with the second power supply pin.
The surge protection circuit is one of a resistor, a choke coil and a low-pass filter.
The surge protection circuit is a variable resistor, and the variable resistor is in a high-resistance state when instantaneous large current flows through and in a low-resistance state when small current flows through.
The storage device further comprises a power supply conversion circuit, wherein the power supply conversion circuit is electrically connected to the power supply pin, the surge protection circuit and the storage function circuit, so that when a pre-charge power supply signal sent by the surge protection circuit or a working power supply signal sent by the power supply pin is received, the voltage or the current of the pre-charge power supply signal or the working power supply signal is converted into a set value, and then the set value is sent to the storage function circuit.
The interface further comprises a communication pin, the storage function circuit comprises a control sub-circuit and a storage sub-circuit, the communication pin is electrically connected with an external terminal, the control sub-circuit is electrically connected with the communication pin, the power supply conversion circuit and the storage sub-circuit, and the control sub-circuit receives data information sent by the external intelligent terminal through the communication pin and sends the data information to the storage sub-circuit for storage.
Wherein, the interface is an SATA interface.
In order to solve the above technical problem, another technical solution adopted by the present application is: there is provided an electronic device, wherein the electronic device comprises a storage apparatus as defined in any of the above.
The beneficial effect of this application is: unlike the prior art, the storage device in the present application includes: the device comprises an interface, a surge protection circuit and a storage function circuit; the interface comprises a pre-charging pin and a power supply pin, the surge protection circuit is electrically connected between the pre-charging pin and the power supply pin so as to receive a pre-charging power supply signal sent by the external terminal through the pre-charging pin when the interface is plugged into the external terminal and the pre-charging pin is electrically connected with a corresponding interface contact of the external terminal, and the pre-charging power supply signal is sent to the storage function circuit for pre-charging after being limited by the surge protection circuit, so that the storage device can be effectively protected from being damaged by pre-charging over-current, the cost of corresponding realization is low, and a working power supply signal sent by the external terminal can be effectively received through the power supply pin when the subsequent power supply pin is electrically connected to the corresponding interface contact of the external terminal.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts. Wherein:
FIG. 1 is a schematic structural diagram of a first embodiment of a memory device according to the present application;
FIG. 2 is a block diagram of one embodiment of an interface in the memory device of FIG. 1;
FIG. 3 is a schematic structural diagram of a second embodiment of the memory device of the present application;
FIG. 4 is a schematic structural diagram of a third embodiment of the memory device of the present application;
FIG. 5 is a schematic block diagram of an embodiment of a memory device of the present application;
FIG. 6 is a diagram illustrating the function definition corresponding to each pin of the interface in the memory device of FIG. 5.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a memory device according to a first embodiment of the present application. In the present embodiment, the storage device 10 includes: an interface 11, a surge protection circuit 12, and a memory function circuit 13.
The storage device 10 provided in the present application may be one of any reasonable storage electronic devices, such as a storage hard disk, or a USB (universal serial bus) flash disk, and may be electrically connected to an external terminal 20, for example, any reasonable intelligent terminal such as a mobile phone or a personal computer, in a manner of plugging through a communication interface, so as to interact and store data information with the external terminal 20.
It will be appreciated that certain power-up timing requirements are typically also required to be met in order for data storage in the memory device 10 to be efficient. Therefore, when the memory device 10 is powered on through the external terminal 20 to transmit data information thereto, in order to meet the requirement of ensuring the power-on timing of the back-end circuit of the memory device 10, the memory function circuit 13 in the memory device 10 generally needs to be precharged before the memory device enters a stable operating state, so that the memory device 10 can enter the operating state quickly when receiving an operating power signal to prevent a timing error from occurring in data storage.
Specifically, the interface 11 in the storage device 10 specifically includes a pre-charge pin 111 and a power pin 112, so that when the interface 11 is plugged into a communication interface corresponding to the external terminal 20 and is electrically connected to its corresponding interface contact, a power signal sent by the external terminal 20 can be received through the pre-charge pin 111 and the power pin 112, so as to perform a power-on operation.
The pre-charging pin 111 is protruded from the power pin 112, so that when the interface 11 is plugged into a communication interface corresponding to the external terminal 20, the pre-charging pin 111 contacts a corresponding interface contact of the external terminal 20 before the power pin 112, and thus a corresponding power signal can be received from the external terminal 20 more quickly, and pre-charging can be performed through the pre-charging pin 111.
Optionally, in an embodiment, the pin length of the pre-charge pin 111 is greater than the pin length of the power pin 112, and further, the minimum distance between the pre-charge pin 111 and the plane where the opening of the interface 11 is located is smaller than the minimum distance between the power pin 112 and the plane where the opening of the interface 11 is located.
However, since the length of the pin of the pre-charging pin 111 is more protruding than that of the other pins, when the corresponding interface contact of the external terminal 20 is contacted first, usually only one metal pin is electrically connected to the external terminal 20, so that a surge of a higher current, that is, an instantaneous large current, may occur at the moment of plugging, and further, damage may be caused to the corresponding electronic device in the memory device 10, and even insulation breakdown may occur. Therefore, the occurrence of the instantaneous large current needs to be avoided as much as possible in the memory device 10.
Further, the surge protection circuit 12 is electrically connected between the pre-charge pin 111 and the power pin 112, so that when the interface 11 of the memory device 10 is plugged into the communication interface of the external terminal 20, so that the pre-charge pin 111 is electrically connected to the corresponding interface contact of the external terminal 20, the memory device 10 can receive the pre-charge signal sent by the external terminal 20 through the pre-charge pin 111, and the pre-charge signal will further flow to the back-end circuit of the memory device 10 after passing through the surge protection circuit 12.
It can be seen that the surge protection circuit 12 can absorb the pre-charge signal to a certain extent to prevent the pre-charge signal from generating an instantaneous peak current, that is, to limit the current of the pre-charge signal, thereby preventing the back-end circuit of the memory device 10 from being damaged during the pre-charge process.
The storage function circuit 13 is a circuit that performs data information interaction with the external terminal 20, specifically, a circuit that needs to be protected, in the storage device 10. The memory function circuit 13 is further electrically connected to the power supply pin 112 and the surge protection circuit 12, and is capable of sequentially receiving the precharge power supply signal limited by the surge protection circuit 12 and precharging the current. And when the power pin 112 is electrically connected to the corresponding interface contact of the external terminal 20, the memory function circuit 13 can receive the working power signal sent by the external terminal 20 through the power pin 112 to enter a stable working state, so as to perform data information interaction and storage with the external terminal 20.
It can be understood that, after entering the stable operation state, the pre-charge pin 111 can also be used as a backup for the power signal, so that when the power pin 112 fails, the pre-charge pin 111 can receive the operation power signal sent by the external terminal 20, so as to further provide the memory function circuit 13 with operation use.
Optionally, the surge protection circuit 12 is one of a resistor, a choke coil, and a low-pass filter, or a sub-circuit including one or more of any reasonable electronic devices, such as a resistor, a choke coil, and a low-pass filter, which is not limited in this application.
Optionally, the surge protection circuit 12 is a variable resistor, and the variable resistor is in a high-resistance state when an instantaneous large current flows through, so as to be able to suppress the instantaneous large current; and when a small current flows, the low-resistance state is presented so as to be capable of normally receiving working power supply signals.
In an embodiment, as shown in fig. 2, fig. 2 is a schematic structural diagram of an embodiment of an interface in the memory device in fig. 1. The interface 11 is specifically a SATA (Serial ATA ) interface 11, and the surge protection circuit 12 is connected to a pre-charged current-limiting resistor (i.e., the surge protection circuit 12) between a long pin (P7, i.e., the pre-charge pin 111) and a short pin (P8, P9, i.e., the power pin 112) of the 3 pins of the power input in the input end of the interface 11, so that the surge protection circuit can achieve an effect of resisting surge current in the process of plugging and unplugging through the interface 11.
In other embodiments, the interface 11 may also be any other reasonable communication port suitable for an electronic product with a hot plug function or a long and short pin design, and the resistance value of the corresponding current limiting resistor may specifically be set according to the specification requirement of the electronic product, which is not limited in this application.
Referring to fig. 3, fig. 3 is a schematic structural diagram of a memory device according to a second embodiment of the present application. In this embodiment, on the basis of the first embodiment of the memory device 10 provided in the present application, the memory device 10 further includes a power conversion circuit 14.
It can be understood that, for each sub-circuit in the storage device 10, the power signal required for each sub-circuit is different due to the different implementation functions of each sub-circuit, for example, the voltage level required for each sub-circuit is different and is different from the voltage level of the power signal acquired by the external terminal 20 at the interface 11, so that after the power signal transmitted by the external terminal 20 is acquired by the interface 11, the power signal needs to be further subjected to power conversion and then transmitted to the corresponding sub-circuit.
Specifically, the power conversion circuit 14 is electrically connected to the power pin 112, the surge protection circuit 12 and the storage function circuit 13, so as to receive the pre-charge power signal sent by the surge protection circuit 12, convert the voltage or current of the pre-charge power signal into a set value, and send the set value to the storage function circuit 13 to pre-charge the pre-charge power signal; or, when receiving the working power signal transmitted from the power pin 112, the voltage or the current of the working power signal is converted into one or more set values and then transmitted to the corresponding sub-circuit in the memory function circuit 13.
It is understood that the set value may be any reasonable voltage value such as 3.3V, 5V or 6V, and is specifically determined by the specific operating power requirement of the memory function circuit 13, which is not limited in this application.
Referring to fig. 4, fig. 4 is a schematic structural diagram of a memory device according to a third embodiment of the present application. In this embodiment, based on the second embodiment of the memory device provided in the present application, the interface 11 further includes a communication pin 113, and the memory function circuit 13 further includes a control sub-circuit 131 and a memory sub-circuit 132.
The communication pin 113 is electrically connected to the external terminal 20, the control sub-circuit 131 is electrically connected to the communication pin 113, the power conversion circuit 14 and the storage sub-circuit 132, and the control sub-circuit 131 can receive data information sent by the external intelligent terminal through the communication pin 113, so as to send the received data information to the storage sub-circuit 132 for storage.
Please refer to fig. 5 and fig. 6, wherein fig. 5 is a schematic structural diagram of a memory device according to an embodiment of the present application, and fig. 6 is a schematic diagram of a function definition corresponding to each pin of an interface in the memory device of fig. 5.
Specifically, the interface 11 in the memory device 10 includes a plurality of pins to be able to correspondingly receive power signals of a plurality of different voltage levels and correspondingly implement a plurality of different differential communication signals.
Optionally, the number of the pre-charge pins 111, the number of the power pins 112, and the number of the surge protection circuits 12 are the same, and each of the surge protection circuits 12 includes at least one, and each of the pre-charge pins 111 and the power pins 112 corresponds to one of the surge protection circuits 12, so as to form an independent loop capable of receiving the power signal sent by the external terminal 20, that is, each of the surge protection circuits 12 is electrically connected between the corresponding pre-charge pin 111 and the corresponding power pin 112. And the power signals sent by the external terminal 20 and correspondingly received by different surge protection circuits 12 may be the same or different, which is not limited in this application. In other embodiments, when at least two pre-charge pins 111 and at least two power supply pins 112 are provided, only a part or one group of the pre-charge pins 111 and the power supply pins 112 may be connected to the surge protection circuit 12 correspondingly, and the other pre-charge pins 111 and the other group of the power supply pins 112 may be directly connected to the communication interface of the external terminal 20, which is not limited in this application.
In one embodiment, the power pins 112 include a first power pin (not shown) and a second power pin (not shown), and the first power pin is electrically connected to the second power pin, i.e. after short-circuiting, one end of the surge protection circuit 12, and the other end of the surge protection circuit 12 is electrically connected to the pre-charge pin 111.
In another embodiment, the power pins 112 include a first power pin and a second power pin, and the first power pin may be electrically connected to the pre-charge pin 111, that is, after short-circuiting, one end of the surge protection circuit 12, and the other end of the surge protection circuit 12 is electrically connected to the second power pin.
The interface 11 is specifically a SATA interface, and includes S1-S7 signal pins and P1-P15 power pins. Understandably, P7 is the pre-charge pin 111, and P8 and P9 are respectively corresponding to the first power pin and the second power pin, and the voltage level of the corresponding received power signal is 5V; p13, P14, and P15 correspond to another set of the precharge pin 111, the first power pin, and the second power pin, and the voltage level of the corresponding received power signal may be 12V.
It can be seen that P8 and P9 are short-circuited and then electrically connected to the surge protection circuit 12, i.e. one end of the current limiting resistor Rx, and the other end of the current limiting resistor Rx is electrically connected to P7. P13 and P14 may be shorted first and then connected to one end of another current limiting resistor (not shown), and the other end of the current limiting resistor is connected to P15. In other embodiments, another current limiting resistor is not included in the SATA interface, and P13, P14, and P15 are shorted with each other.
In another aspect, the present application also provides an electronic device, wherein the electronic device comprises the storage apparatus 10 as described in any one of the above.
Unlike the prior art, the storage device in the present application includes: the device comprises an interface, a surge protection circuit and a storage function circuit; the interface comprises a pre-charging pin and a power supply pin, the surge protection circuit is electrically connected between the pre-charging pin and the power supply pin so as to receive a pre-charging power supply signal sent by the external terminal through the pre-charging pin when the interface is plugged into the external terminal and the pre-charging pin is electrically connected with a corresponding interface contact of the external terminal, and the pre-charging power supply signal is sent to the storage function circuit for pre-charging after being limited by the surge protection circuit, so that the storage device can be effectively protected from being damaged by pre-charging over-current, the cost of corresponding realization is low, and a working power supply signal sent by the external terminal can be effectively received through the power supply pin when the subsequent power supply pin is electrically connected to the corresponding interface contact of the external terminal.
The above are only embodiments of the present application, and not intended to limit the scope of the present application, and all equivalent structures or equivalent processes performed by the present application and the contents of the attached drawings, which are directly or indirectly applied to other related technical fields, are also included in the scope of the present application.
Claims (10)
1. A storage device, comprising:
an interface comprising a pre-charge pin and a power pin; the pre-charging pin protrudes out of the power supply pin;
the surge protection circuit is electrically connected between the pre-charging pin and the power supply pin so as to be inserted into an external terminal at the interface, so that when the pre-charging pin is electrically connected with a corresponding interface contact of the external terminal, a pre-charging power supply signal sent by the external terminal is received through the pre-charging pin, and the pre-charging power supply signal is limited;
the storage function circuit is electrically connected with the power supply pin and the surge protection circuit, and receives the pre-charging power supply signal subjected to current limiting by the surge protection circuit so as to perform pre-charging; when the power pin is electrically connected with the corresponding interface contact of the external terminal, the storage function circuit receives a working power supply signal sent by the external terminal through the power pin.
2. The storage device of claim 1,
the number of the pre-charging pins, the number of the power pins and the number of the surge protection circuits are the same, and the pre-charging pins, the number of the power pins and the number of the surge protection circuits are all at least one, wherein each surge protection circuit is electrically connected between the corresponding pre-charging pin and the corresponding power pin.
3. The storage device of claim 1,
the power supply pins comprise a first power supply pin and a second power supply pin, the first power supply pin and the second power supply pin are electrically connected and then electrically connected with one end of the surge protection circuit, and the other end of the surge protection circuit is electrically connected with the pre-charging pin.
4. The storage device of claim 1,
the power supply pins comprise a first power supply pin and a second power supply pin, the first power supply pin is electrically connected with one end of the surge protection circuit after being electrically connected with the pre-charging pin, and the other end of the surge protection circuit is electrically connected with the second power supply pin.
5. The storage device of claim 1,
the surge protection circuit is one of a resistor, a choke coil and a low-pass filter.
6. The storage device of claim 1,
the surge protection circuit is a variable resistor, and the variable resistor is in a high-resistance state when instantaneous large current flows through and in a low-resistance state when small current flows through.
7. The storage device of claim 1,
the storage device further comprises a power conversion circuit, wherein the power conversion circuit is electrically connected to the power pin, the surge protection circuit and the storage function circuit, and is used for converting the voltage or the current of the pre-charge power signal or the working power signal into a set value and then sending the set value to the storage function circuit when receiving the pre-charge power signal sent by the surge protection circuit or the working power signal sent by the power pin.
8. The storage device of claim 7,
the interface further comprises a communication pin, the storage function circuit comprises a control sub-circuit and a storage sub-circuit, the communication pin is electrically connected with the external terminal, the control sub-circuit is electrically connected with the communication pin, the power supply conversion circuit and the storage sub-circuit, and the control sub-circuit receives data information sent by the external intelligent terminal through the communication pin and sends the data information to the storage sub-circuit for storage.
9. The storage device of any one of claims 1-8,
the interface is an SATA interface.
10. An electronic device, characterized in that the electronic device comprises a storage means according to any of claims 1-9.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110644573.8A CN115454321A (en) | 2021-06-09 | 2021-06-09 | Storage device and electronic equipment |
| PCT/CN2021/099820 WO2022257131A1 (en) | 2021-06-09 | 2021-06-11 | Storage apparatus and electronic device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110644573.8A CN115454321A (en) | 2021-06-09 | 2021-06-09 | Storage device and electronic equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN115454321A true CN115454321A (en) | 2022-12-09 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110644573.8A Pending CN115454321A (en) | 2021-06-09 | 2021-06-09 | Storage device and electronic equipment |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN115454321A (en) |
| WO (1) | WO2022257131A1 (en) |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050193159A1 (en) * | 2004-03-01 | 2005-09-01 | Yiu-Keung Ng | Embedded power control circuitry for a portable disk drive carrier having a hot-plug application |
| CN102544810B (en) * | 2010-12-24 | 2016-06-08 | 鸿富锦精密工业（深圳）有限公司 | Hot plug connector and adopt the server of this hot plug connector |
| CN103984604B (en) * | 2014-05-23 | 2017-08-25 | 环旭电子股份有限公司 | Control device |
| KR20180024248A (en) * | 2016-08-29 | 2018-03-08 | 삼성전자주식회사 | Precharge circuit for preventing inrush current and electronic device including the same |
| CN209625800U (en) * | 2019-04-08 | 2019-11-12 | 深圳市亿储电子有限公司 | A kind of power circuit of SATA and USB double nip solid state hard disk |
| CN210245073U (en) * | 2019-09-27 | 2020-04-03 | 苏州浪潮智能科技有限公司 | SAS/SATA hard disk backboard |
-
2021
- 2021-06-09 CN CN202110644573.8A patent/CN115454321A/en active Pending
- 2021-06-11 WO PCT/CN2021/099820 patent/WO2022257131A1/en active Application Filing
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| WO2022257131A1 (en) | 2022-12-15 |
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