CN115441717A - Self-adaptive accelerating circuit suitable for voltage mode loop - Google Patents

Self-adaptive accelerating circuit suitable for voltage mode loop Download PDF

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Publication number
CN115441717A
CN115441717A CN202211171225.4A CN202211171225A CN115441717A CN 115441717 A CN115441717 A CN 115441717A CN 202211171225 A CN202211171225 A CN 202211171225A CN 115441717 A CN115441717 A CN 115441717A
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transistor
current
circuit
electrode
output
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CN202211171225.4A
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CN115441717B (en
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徐海峰
易新敏
梁华
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SG Micro Beijing Co Ltd
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SG Micro Beijing Co Ltd
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/32—Means for protecting converters other than automatic disconnection
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0009—Devices or circuits for detecting current in a converter
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0025—Arrangements for modifying reference values, feedback values or error values in the control loop of a converter
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/32—Means for protecting converters other than automatic disconnection
    • H02M1/34—Snubber circuits
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)

Abstract

The present disclosure provides an adaptive accelerating circuit suitable for a voltage mode loop, comprising: the circuit comprises a first conversion circuit, a second conversion circuit, a third conversion circuit, a difference circuit, a multiplication circuit and an output circuit, wherein the first conversion circuit converts a reference voltage into a first reference current and a second reference current; the second conversion circuit converts the output sampling voltage division into output sampling current; the third conversion circuit converts the input sampling voltage division of the voltage mode loop into input sampling current; the difference circuit determines a difference current according to the input sampling current and the output sampling current, and provides the difference current for the multiplication circuit; the multiplication circuit determines an output current according to the difference current, the first reference current and the output sampling current and provides the output current for the output circuit; the output circuit outputs clamping voltage according to the output current and the second reference current, controls the output voltage of the output end of the error amplifier in the voltage mode loop, and clamps the output voltage to the clamping voltage.

Description

Self-adaptive accelerating circuit suitable for voltage mode loop
Technical Field
The disclosure relates to the technical field of integrated circuits, in particular to a self-adaptive accelerating circuit suitable for a voltage mode loop.
Background
With the expansion of the integrated circuit market, a direct current-to-direct current (DC-DC) converter is also rapidly developed, a DC-DC voltage mode topology control loop system has a simple structure, an inductor L and a capacitor C in a voltage mode loop form a second-order LC filter network, but a complicated triple compensation network is required due to the existence of a power level bipolar point and an LC bipolar point, so that the triple compensation network introduces a large capacitor and impedance under the condition of ensuring the loop to be stable, a low-frequency dominant pole and other compensation zero poles are generated, the system bandwidth is small, and the system response speed is slow when jumping under different application conditions is faced.
Aiming at the problem that the system response speed is low when jumping under different application conditions in the related art, an effective technical solution is not provided at present.
Disclosure of Invention
The main objective of the present disclosure is to provide an adaptive accelerating circuit suitable for a voltage mode loop, so as to solve the problem in the related art that the system response speed is slow when the jump of different application conditions is faced.
In order to achieve the above object, the present disclosure provides an adaptive speed-up circuit for a voltage mode loop, the adaptive speed-up circuit comprising: first conversion circuit, second conversion circuit, third conversion circuit, difference circuit, multiplication circuit and output circuit, wherein:
the first converting circuit is configured to convert the reference voltage into a first reference current and a second reference current, and to supply the first reference current to the multiplying circuit and the second reference current to the output circuit;
the second conversion circuit is configured to convert the output sampling division voltage of the voltage mode loop into an output sampling current and provide the output sampling current to the difference circuit and the multiplication circuit respectively, wherein the output sampling division voltage of the voltage mode loop is obtained by sampling the output voltage of the voltage mode loop;
the third conversion circuit is configured to convert an input sampling division voltage of the voltage mode loop into an input sampling current and provide the input sampling current to the difference circuit, wherein the input sampling division voltage of the voltage mode loop is obtained by sampling an input voltage of the voltage mode loop;
the difference circuit is configured to determine a difference current from the input sample current and the output sample current, and provide the difference current to the multiplication circuit;
the multiplication circuit is configured to determine an output current according to the difference current, the first reference current and the output sampling current, and provide the output current to the output circuit; and
the output circuit is configured to output a clamping voltage according to the output current and the second reference current, control an output voltage at an output end of the error amplifier in the voltage mode loop, and clamp the output voltage to the clamping voltage.
Optionally, the first converting circuit comprises a first buffer circuit and a first current mirror circuit, wherein:
the first buffer circuit is configured to convert the reference voltage into a reference current and supply the reference current to the first current mirror circuit;
the first current mirror circuit is configured to copy a reference current, obtain a first reference current and a second reference current, and provide the first reference current to the multiplication circuit and provide the second reference current to the output circuit, wherein the reference current, the first reference current and the second reference current are equal.
Further, the first buffer circuit includes a first operational amplifier, a first transistor, and a first resistor, and the first current mirror circuit includes a second transistor, a third transistor, and a fourth transistor, wherein:
the non-inverting input end of the first operational amplifier is coupled to the reference voltage end, the inverting input end of the first operational amplifier is coupled to the second pole of the first transistor and the first end of the first resistor respectively, the output end of the first operational amplifier is coupled to the control pole of the first transistor, and the first operational amplifier is configured to clamp the reference voltage on the first resistor to obtain a reference current;
the first pole of the first transistor is respectively coupled with the control pole of the second transistor, the second pole of the second transistor, the control pole of the third transistor and the control pole of the fourth transistor;
the control electrode of the second transistor is respectively coupled with the second electrode of the second transistor, the control electrode of the third transistor and the control electrode of the fourth transistor, and the first electrode of the second transistor is respectively coupled with the power supply voltage end, the first electrode of the third transistor and the first electrode of the fourth transistor;
a control electrode of the third transistor is coupled to a control electrode of the fourth transistor, first electrodes of the third transistor and the fourth transistor are respectively coupled to a power supply voltage end and a first electrode of the fourth transistor, a second electrode of the third transistor is coupled to a second end of the multiplication circuit, the third transistor is configured to copy a reference current flowing through the second transistor, obtain a first reference current, and provide the first reference current to the second end of the multiplication circuit from the second electrode;
the first pole of the fourth transistor is coupled to the power supply voltage end, the second pole of the fourth transistor is coupled to the first end of the output circuit, and the fourth transistor is configured to copy the reference current flowing through the second transistor, obtain a second reference current and provide the second reference current from the second pole to the first end of the output circuit.
Optionally, the second conversion circuit comprises a second buffer circuit and a second current mirror circuit, wherein:
the second buffer circuit is configured to convert the output sampling voltage division into an output sampling current and provide the output sampling current to the second current mirror circuit;
the second current mirror circuit is configured to replicate the output sample current and provide the output sample current to the difference circuit and the multiplication circuit, respectively.
Further, the second buffer circuit includes a second operational amplifier, a fifth transistor, and a second resistor, and the second current mirror circuit includes a sixth transistor, a seventh transistor, and an eighth transistor, wherein:
the non-inverting input end of the second operational amplifier is coupled to the output sampling voltage-dividing end, the inverting input end of the second operational amplifier is coupled to the second pole of the fifth transistor and the first end of the second resistor respectively, the output end of the second operational amplifier is coupled to the control pole of the fifth transistor, and the second operational amplifier is configured to clamp the output sampling voltage-dividing end on the second resistor to obtain an output sampling current;
a first electrode of the fifth transistor is respectively coupled to a control electrode of the sixth transistor, a second electrode of the sixth transistor, a control electrode of the seventh transistor and a control electrode of the eighth transistor;
the second end of the second resistor is grounded;
a control electrode of the sixth transistor is respectively coupled to the second electrode of the sixth transistor, the control electrode of the seventh transistor and the control electrode of the eighth transistor, and a first electrode of the sixth transistor is respectively coupled to the power supply voltage terminal, the first electrode of the seventh transistor and the first electrode of the eighth transistor;
a control electrode of the seventh transistor is coupled with a control electrode of the eighth transistor, a first electrode of the seventh transistor is respectively coupled with a power supply voltage end and a first electrode of the eighth transistor, a second electrode of the seventh transistor is coupled with a first end of the difference circuit, and the seventh transistor is configured to copy the output sampling current flowing through the sixth transistor and provide the output sampling current from the second electrode to the first end of the difference circuit;
a first pole of the eighth transistor is coupled to the power supply voltage terminal, a second pole of the eighth transistor is coupled to the second terminal of the multiplication circuit, and the eighth transistor is configured to copy the output sampling current flowing through the sixth transistor and provide the output sampling current from the second pole to the second terminal of the multiplication circuit.
Optionally, the third conversion circuit comprises a third buffer circuit and a third current mirror circuit, wherein:
the third buffer circuit is configured to convert the input sampling divided voltage into an input sampling current and provide the input sampling current to the third current mirror circuit;
the third current mirror circuit is configured to replicate the input sample current and provide the input sample current to the difference circuit.
Further, the third buffer circuit includes a third operational amplifier, a ninth transistor, and a third resistor, and the third current mirror circuit includes a tenth transistor and an eleventh transistor, wherein:
the non-inverting input end of the third operational amplifier is coupled to the input sampling voltage-dividing end, the inverting input end of the third operational amplifier is coupled to the second pole of the ninth transistor and the first end of the third resistor respectively, the output end of the third operational amplifier is coupled to the control pole of the ninth transistor, and the third operational amplifier is configured to clamp the input sampling voltage-dividing end on the third resistor to obtain an input sampling current;
a first electrode of the ninth transistor is coupled to a control electrode of the tenth transistor, a second electrode of the tenth transistor and a control electrode of the eleventh transistor respectively;
the second end of the third resistor is grounded;
a control electrode of the tenth transistor is coupled to the second electrode of the tenth transistor and the control electrode of the eleventh transistor, respectively, and a first electrode of the tenth transistor is coupled to the power supply voltage terminal and the first electrode of the eleventh transistor, respectively;
a first pole of the eleventh transistor is coupled to the power supply voltage terminal, a second pole of the eleventh transistor is coupled to the second terminal of the difference circuit, and the eleventh transistor is configured to copy the input sampling current flowing through the tenth transistor and provide the input sampling current from the second pole to the second terminal of the difference circuit.
Optionally, the difference circuit includes a fourth current mirror circuit including a twelfth transistor and a thirteenth transistor, and a fifth current mirror circuit including a fourteenth transistor and a fifteenth transistor, wherein:
a control electrode of the twelfth transistor is respectively coupled to the first end of the second conversion circuit, the first electrode of the twelfth transistor and the control electrode of the thirteenth transistor, a first electrode of the twelfth transistor is respectively coupled to the first end of the second conversion circuit and the control electrode of the thirteenth transistor, a second electrode of the twelfth transistor is respectively coupled to the second electrode of the thirteenth transistor, the second electrode of the fourteenth transistor, the second electrode of the fifteenth transistor and the ground terminal, wherein an output sampling current provided by the first end of the second conversion circuit flows through the twelfth transistor;
a control electrode of the thirteenth transistor is coupled to the first end of the second conversion circuit, first electrodes of the thirteenth transistor are respectively coupled to the first end of the third conversion circuit and the first electrode of the fourteenth transistor, a second electrode of the thirteenth transistor is respectively coupled to the second electrode of the fourteenth transistor, the second electrode of the fifteenth transistor and the ground terminal, and the thirteenth transistor is configured to copy an output sampling current flowing through the twelfth transistor;
a control electrode of the fourteenth transistor is coupled to the first terminal of the third converting circuit, the first electrode of the fourteenth transistor, and a control electrode of the fifteenth transistor, respectively, a first electrode of the fourteenth transistor is coupled to the first terminal of the third converting circuit and the control electrode of the fifteenth transistor, respectively, a second electrode of the fourteenth transistor is coupled to the second electrode of the fifteenth transistor and the ground terminal, respectively, and the fourteenth transistor is configured to: the current flowing through the fourteenth transistor is a difference current obtained by subtracting the output sampling current flowing through the thirteenth transistor from the input sampling current provided by the first terminal of the third conversion circuit;
a first pole of the fifteenth transistor is coupled to the first terminal of the multiplication circuit, a second pole of the fifteenth transistor is connected to ground, and the fifteenth transistor is configured to copy a difference current flowing through the fourteenth transistor and provide the difference current from the first pole to the first terminal of the multiplication circuit.
Optionally, the multiplication circuit includes a sixth current mirror circuit, a current multiplier, and a seventh current mirror circuit, the sixth current mirror circuit includes a sixteenth transistor and a seventeenth transistor, and the seventh current mirror circuit includes an eighteenth transistor and a nineteenth transistor, wherein:
a control electrode of the sixteenth transistor is respectively coupled to the third end of the difference circuit, a second electrode of the sixteenth transistor and a control electrode of the seventeenth transistor, a first electrode of the sixteenth transistor is respectively coupled to the power supply voltage terminal and a first electrode of the seventeenth transistor, and a second electrode of the sixteenth transistor is respectively coupled to the third end of the difference circuit and the control electrode of the seventeenth transistor;
a control electrode of the seventeenth transistor is coupled to the third terminal of the difference circuit, a first electrode of the seventeenth transistor is coupled to the power supply voltage terminal, a second electrode of the seventeenth transistor is coupled to the first input terminal of the current multiplier, and the seventeenth transistor is configured to copy the difference current flowing through the sixteenth transistor and provide the difference current from the second electrode to the first input terminal of the current multiplier;
the current multiplier is configured to determine an output current according to the difference current of the first input terminal, the first reference current of the second input terminal and the output sampling current of the second output terminal, and provide the output current to the eighteenth transistor from the first output terminal;
a control electrode of the eighteenth transistor is respectively coupled with the first output end of the current multiplier, the second electrode of the eighteenth transistor and the control electrode of the nineteenth transistor, a first electrode of the eighteenth transistor is respectively coupled with the power supply voltage end and the first electrode of the nineteenth transistor, and a second electrode of the eighteenth transistor is respectively coupled with the first output end of the current multiplier and the control electrode of the nineteenth transistor;
a first pole of the nineteenth transistor is coupled to the power supply voltage terminal, a second pole of the nineteenth transistor is coupled to the second terminal of the output circuit, and the nineteenth transistor is configured to replicate the output current flowing through the eighteenth transistor and provide the output current from the second pole to the second terminal of the output circuit.
Optionally, the output circuit comprises a fourth resistor and a fifth resistor, wherein:
a first end of a fourth resistor is coupled to a third end of the multiplication circuit, a second end of the fourth resistor is coupled to a first end of a fifth resistor and a second reference current end of the first conversion circuit, respectively, and a current flowing through the fourth resistor is an output current, wherein a clamping voltage is output from the first end of the fourth resistor to an output end of an error amplifier in the voltage mode loop and is used for clamping the output voltage to the clamping voltage when the output voltage of the error amplifier is smaller than the clamping voltage;
the first end of the fifth resistor is coupled to the second reference current end of the first conversion circuit, the second end of the fifth resistor is grounded, and the current flowing through the fifth resistor is the sum of the output current and the second reference current of the second reference current end.
In the adaptive accelerating circuit applicable to the voltage mode loop, the first converting circuit, the second converting circuit and the third converting circuit all convert voltage into current, the difference current and the output current are sequentially output through the difference circuit and the multiplying circuit, the output circuit outputs clamping voltage according to the output current and the second reference current, the output voltage of the output end of an error amplifier in the voltage mode loop is controlled, the output voltage is clamped to the clamping voltage, the output voltage of the error amplifier can be limited to the stable value of the clamping voltage, the response time of the voltage mode loop is shortened when the voltage mode loop faces load jump or input jump, the stable state is recovered more quickly, and the problem that the system response speed is slow when the voltage mode loop faces different application conditions in the related art is solved.
Drawings
In order to more clearly illustrate the detailed description of the present disclosure or the technical solutions in the prior art, the drawings used in the detailed description or the prior art descriptions will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and other drawings may be obtained by those skilled in the art without inventive efforts.
FIG. 1 is an exemplary circuit diagram of a voltage mode loop;
fig. 2 is an exemplary block diagram of an adaptive speed-up circuit suitable for a voltage mode loop provided by an embodiment of the present disclosure;
fig. 3 is an exemplary circuit diagram of an adaptive accelerating circuit suitable for a voltage mode loop according to an embodiment of the present disclosure.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be described below in detail and completely with reference to the accompanying drawings. It is to be understood that the described embodiments are only a few embodiments of the present disclosure, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without any inventive step, are also within the scope of protection of the disclosure.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the presently disclosed subject matter belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the specification and relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. As used herein, the statement that two or more parts are "connected" or "coupled" together shall mean that the parts are joined together either directly or joined through one or more intermediate components.
In all embodiments of the present disclosure, since the source and the drain of the transistor are symmetrical, the emitter and the collector of the transistor are symmetrical, and the direction of the on-current between the source and the drain of the N-type transistor and the P-type transistor is opposite, and the direction of the on-current between the emitter and the collector of the N-type transistor and the P-type transistor is opposite, in the embodiments of the present disclosure, the controlled middle end of the transistor is referred to as a control electrode, and the other two ends of the transistor are referred to as a first electrode and a second electrode, respectively. The transistors employed in the embodiments of the present disclosure are primarily switching transistors. In addition, terms such as "first" and "second" are only used to distinguish one element (or part of an element) from another element (or another part of an element).
Fig. 1 shows an exemplary circuit diagram of a voltage mode loop. The input voltage of the voltage mode loop is V IN Output voltage of V OUT The PWM signal provides bias voltage for an upper power tube HS and a lower power tube LS through a Drive circuit Drive, an inductor L and a load capacitor C form a second-order LC filter network, rf1 and Rf2 are feedback resistors, the non-inverting input end of a comparator Comp1 is connected with feedback voltage Vfb, the inverting input end of the comparator Comp1 is connected with first reference voltage Vref1, the output end of the comparator Comp1 is feedback output voltage Vfbo, a three-type compensation network is arranged in a dashed frame in fig. 1, comp2 is a second comparator, and Vramp is a ramp signal.
Triple-type compensation is achieved because the presence of power stage bipolar points and LC bipolar points requires a relatively complex triple-type compensation networkUnder the condition that the network ensures the loop to be stable, large capacitors and impedances are introduced, including resistors R1, R2 and R3 and capacitors C1, C2 and C3 in the three-type compensation network, and the resistors and the capacitors can generate low-frequency dominant poles and other compensation zero poles, so that the bandwidth of the system is small, and the system jumps in the face of a load resistor RL or inputs a voltage V IN And when the jump is carried out under different application conditions, such as jump, the response speed is slow.
The non-inverting input end of an error amplifier EA in the three-type compensation network is a second reference voltage Vref2; when the application condition jumps specifically from light load to heavy load of the load resistor RL, the output voltage Veao of the error amplifier EA will increase, the duty ratio of the pulse width modulation signal PWM increases, and the system response speed becomes slow, so that the output voltage Veao of the error amplifier EA rises slowly, the rising speed of the load current is slow, and the voltage mode loop output voltage V is caused to rise slowly OUT The transient response of (2) becomes poor.
In order to solve the problem that the system response speed is slow when a jump is faced with different application conditions, fig. 2 shows an exemplary block diagram of an adaptive accelerating circuit suitable for a voltage mode loop provided by an embodiment of the present disclosure, fig. 3 shows an exemplary circuit diagram of an adaptive accelerating circuit suitable for a voltage mode loop provided by an embodiment of the present disclosure, and fig. 2 includes: a first conversion circuit 21, a second conversion circuit 22, a third conversion circuit 23, a difference circuit 24, a multiplication circuit 25, and an output circuit 26, wherein:
the first conversion circuit 21 is configured to convert the reference voltage Vref into a first reference current Iref1 and a second reference current Iref2, and supply the first reference current Iref1 to the multiplication circuit 25 and the second reference current Iref2 to the output circuit 26;
the second conversion circuit 22 is configured to divide the output sample of the voltage-mode loop by a voltage V OUT K is converted into output sampling current I OUT K and provides output sampling currents I to the difference circuit 24 and the multiplication circuit 25, respectively OUT K, where the output of the voltage mode loop is sampled by a divided voltage V OUT K is the output voltage V to the voltage mode loop OUT Sampling to obtain; to voltage mode loopOutput voltage V of OUT Sampling in real time according to the partial pressure proportionality coefficient k to obtain output sampling partial pressure V OUT /k；
The third conversion circuit is configured to divide the input sample of the voltage mode loop by a voltage V IN K is converted into input sampling current I IN K and provides an input sample current I to the difference circuit 24 IN K, where the input sample of the voltage mode loop is divided by V IN K is the input voltage V to the voltage mode loop IN Sampling to obtain; input voltage V to voltage mode loop IN Real-time sampling is carried out according to the partial pressure proportionality coefficient k, and input sampling partial pressure V can be obtained IN /k；
The difference circuit 24 is configured to sample the current I according to an input IN K and output sampling current I OUT K, determining the difference current and providing the difference current to the multiplying circuit 25;
the multiplying circuit 25 is configured to multiply the difference current, the first reference current Iref1 and the output sampling current I OUT K, determining the output current and providing the output current to the output circuit 26; and
the output circuit 26 is configured to output the clamping voltage Vclamp according to the output current and the second reference current Iref2, control the output voltage Veao at the output terminal of the error amplifier EA in the voltage mode loop, and clamp the output voltage Veao to the clamping voltage Vclamp.
The disclosed embodiments sample the input voltage V of the voltage-mode loop in real time IN And an output voltage V OUT The output voltage Veao output by the error amplifier EA is limited to the clamping voltage Vclamp, the output voltage Veao can be clamped to a system steady-state value of the clamping voltage Vclamp, and other nodes in the whole voltage mode loop are automatically adjusted accurately and slowly according to the self structure of the voltage mode loop until the voltage mode loop system is stable; by clamping the output voltage Veao to the clamp voltage Vclamp, the voltage mode loop jumps facing the load resistance RL or the loop input voltage V IN When jumping, the response time of the voltage mode loop is shortened, the steady state is recovered more quickly, and the problem of the system response speed when jumping facing different application conditions in the related art is solvedThe problem of slow speed.
Optionally, the first converting circuit 21 includes a first buffer circuit and a first current mirror circuit, wherein:
the first buffer circuit is configured to convert the reference voltage Vref into a reference current and supply the reference current to the first current mirror circuit; through the first buffer circuit, the reference voltage Vref can be converted into corresponding reference current;
the first current mirror circuit is configured to copy a reference current, generate a mirror current of the reference current, obtain a first reference current Iref1 and a second reference current Iref2, and provide the first reference current Iref1 to the multiplication circuit 25 and the second reference current Iref2 to the output circuit 26, wherein the reference current, the first reference current Iref1 and the second reference current Iref2 are equal.
In the embodiment of the present disclosure, all the current mirror circuits including the first current mirror circuit have a current ratio of 1:1.
Further, the first buffer circuit includes a first operational amplifier OPA1, a first transistor M1, and a first resistor R 1 The first current mirror circuit includes a second transistor M2, a third transistor M3, and a fourth transistor M4, wherein:
the non-inverting input terminal of the first operational amplifier OPA1 is coupled to the reference voltage terminal, and the inverting input terminal of the first operational amplifier OPA1 is coupled to the second pole of the first transistor M1 and the first resistor R 1 An output terminal of the first operational amplifier OPA1 is coupled to a control electrode of the first transistor M1, the first operational amplifier OPA1 is configured to clamp the reference voltage Vref at the first resistor R 1 Obtaining a reference current;
a first pole of the first transistor M1 is coupled to a control pole of the second transistor M2, a second pole of the second transistor M2, a control pole of the third transistor M3, and a control pole of the fourth transistor M4, respectively; the first transistor M1 is an N-type transistor;
first resistor R 1 The second terminal of (a) is grounded;
the voltage can be converted into corresponding current information by a BUFFER structure, i.e. a BUFFER circuit, formed by the operational amplifier OPA and the N-type transistor.
A control electrode of the second transistor M2 is coupled to the second electrode of the second transistor M2, the control electrode of the third transistor M3, and the control electrode of the fourth transistor M4, respectively, a first electrode of the second transistor M2 is coupled to the power supply voltage terminal, the first electrode of the third transistor M3, and the first electrode of the fourth transistor M4, respectively, and a current flowing through the second transistor M2 is a reference current;
a control electrode of the third transistor M3 is coupled to a control electrode of the fourth transistor M4, first electrodes of the third transistor M3 are respectively coupled to the power supply voltage terminal and a first electrode of the fourth transistor M4, a second electrode of the third transistor M3 is coupled to a second electrode of the multiplication circuit 25, the third transistor M3 is configured to copy the reference current flowing through the second transistor M2, generate a mirror current of the reference current flowing through the second transistor M2, obtain a first reference current Iref1, and provide the first reference current Iref1 from the second electrode to the second electrode of the multiplication circuit 25;
a first pole of the fourth transistor M4 is coupled to the power voltage terminal, a second pole of the fourth transistor M4 is coupled to the first terminal of the output circuit 26, and the fourth transistor M4 is configured to copy the reference current flowing through the second transistor M2, generate a mirror current of the reference current flowing through the second transistor M2, obtain the second reference current Iref2, and provide the second reference current Iref2 from the second pole to the first terminal of the output circuit 26.
Optionally, the second converting circuit 22 includes a second buffer circuit and a second current mirror circuit, where:
the second buffer circuit is configured to divide the output sample into voltage V OUT K is converted into output sampling current I OUT K and provides an output sampling current I to the second current mirror circuit OUT /k；
The second current mirror circuit is configured to duplicate the output sampling current I OUT K, generating an output sampling current I OUT A mirror current of/k and provides an output sampling current I to the difference circuit 24 and the multiplication circuit 25, respectively OUT /k。
Further, the second buffer circuit includes a second operational amplifier OPA2, a fifth transistor M5, and a second resistor R 2 Second current mirrorThe circuit includes a sixth transistor M6, a seventh transistor M7, and an eighth transistor M8, wherein:
the non-inverting input terminal of the second operational amplifier OPA2 is coupled with the output sampling division voltage V OUT A terminal/k, an inverting input terminal of the second operational amplifier OPA2 is coupled to the second terminal of the fifth transistor M5 and the second resistor R 2 An output terminal of the second operational amplifier OPA2 is coupled to a control electrode of the fifth transistor M5, the second operational amplifier OPA2 is configured to divide the output sample voltage V OUT The/k clamp is on the second resistor R 2 To obtain an output sampling current I OUT /k；
A first pole of the fifth transistor M5 is coupled to the control pole of the sixth transistor M6, the second pole of the sixth transistor M6, the control pole of the seventh transistor M7, and the control pole of the eighth transistor M8, respectively; the fifth transistor M5 is an N-type transistor;
second resistor R 2 The second terminal of (a) is grounded;
a control electrode of the sixth transistor M6 is coupled to the second electrode of the sixth transistor M6, the control electrode of the seventh transistor M7, and the control electrode of the eighth transistor M8, respectively, a first electrode of the sixth transistor M6 is coupled to the power voltage terminal, the first electrode of the seventh transistor M7, and the first electrode of the eighth transistor M8, respectively, and a current flowing through the sixth transistor M6 is the output sampling current I OUT /k；
A control electrode of the seventh transistor M7 is coupled to a control electrode of the eighth transistor M8, first electrodes of the seventh transistor M7 and the eighth transistor M8 are respectively coupled to the power voltage terminal and the first electrode of the eighth transistor M8, a second electrode of the seventh transistor M7 is coupled to the first electrode of the difference circuit 24, and the seventh transistor M7 is configured to copy the output sampling current I flowing through the sixth transistor M6 OUT K, generating an output sampling current I flowing through a sixth transistor M6 OUT A mirror current of/k and provides an output sample current I from the second pole to the first terminal of the difference circuit 24 OUT /k；
A first pole of the eighth transistor M8 is coupled to the power voltage terminal, a second pole of the eighth transistor M8 is coupled to the second terminal of the multiplication circuit 25, and the eighth transistor M8 is configured to copy the output sampling current I flowing through the sixth transistor M6 OUT /k，Generating an output sampling current I flowing through a sixth transistor M6 OUT A mirror current of/k and provides an output sample current I from the second pole to the second terminal of the multiplying circuit 25 OUT /k。
Optionally, the third converting circuit includes a third buffer circuit and a third current mirror circuit, wherein:
the third buffer circuit is configured to divide the input sample by a voltage V IN K is converted into input sampling current I IN K, and provides the input sampling current I to the third current mirror circuit IN /k；
The third current mirror circuit is configured to copy the input sampling current I IN K, generating an input sampling current I IN A mirror current of/k and provides an input sample current I to the difference circuit 24 IN /k。
Further, the third buffer circuit includes a third operational amplifier OPA3, a ninth transistor M9, and a third resistor R 3 And, the third current mirror circuit includes tenth and eleventh transistors M10 and M11, wherein:
the non-inverting input terminal of the third operational amplifier OPA3 is coupled to the input sampling voltage division V IN A terminal/k, an inverting input terminal of the third operational amplifier OPA3 is coupled to the second terminal of the ninth transistor M9 and the third resistor R 3 An output terminal of the third operational amplifier OPA3 is coupled to a control electrode of the ninth transistor M9, the third operational amplifier OPA3 is configured to divide the input sample voltage V IN The/k is clamped on a third resistor R3 to obtain an input sampling current I IN /k；
A first pole of the ninth transistor M9 is coupled to the control pole of the tenth transistor M10, the second pole of the tenth transistor M10 and the control pole of the eleventh transistor M11, respectively; the ninth transistor M9 is an N-type transistor;
third resistor R 3 The second terminal of (1) is grounded; third resistor R 3 And the second resistor R 2 Are equal in resistance, i.e. R 3 ＝R 2 ；
A control electrode of the tenth transistor M10 is coupled to the second electrode of the tenth transistor M10 and the control electrode of the eleventh transistor M11, respectively, and the tenth transistor M10Is coupled to the power supply voltage terminal and the first pole of the eleventh transistor M11, respectively, and the current flowing through the tenth transistor M10 is the input sampling current I IN /k；
A first pole of the eleventh transistor M11 is coupled to the power voltage terminal, a second pole of the eleventh transistor M11 is coupled to the second terminal of the difference circuit 24, and the eleventh transistor M11 is configured to copy the input sampling current I flowing through the tenth transistor M10 IN K, generating an input sampling current I flowing through a tenth transistor M10 IN A mirror current of/k and provides an input sample current I from the second pole to the second terminal of the difference circuit 24 IN /k。
Optionally, the difference circuit 24 includes a fourth current mirror circuit configured to generate the output sampling current I and a fifth current mirror circuit OUT A mirror current of/k, a fourth current mirror circuit including a twelfth transistor M12 and a thirteenth transistor M13, the fifth current mirror circuit being configured to generate the input sampling current I IN A mirror current of/k, the fifth current mirror circuit including a fourteenth transistor M14 and a fifteenth transistor M15, wherein:
a control electrode of the twelfth transistor M12 is coupled to the first terminal of the second converting circuit 22, the first electrode of the twelfth transistor M12 and the control electrode of the thirteenth transistor M13, respectively, a first electrode of the twelfth transistor M12 is coupled to the first terminal of the second converting circuit 22 and the control electrode of the thirteenth transistor M13, respectively, a second electrode of the twelfth transistor M12 is coupled to the second electrode of the thirteenth transistor M13, the second electrode of the fourteenth transistor M14, the second electrode of the fifteenth transistor M15 and the ground terminal, respectively, wherein the output sampling current I provided by the first terminal of the second converting circuit 22 OUT The/k flows through the twelfth transistor M12;
a control electrode of the thirteenth transistor M13 is coupled to the first terminal of the second converting circuit 22, first electrodes of the thirteenth transistor M13 are coupled to the first terminals of the third and fourteenth converting circuits M14, respectively, a second electrode of the thirteenth transistor M13 is coupled to the second electrode of the fourteenth transistor M14, the second electrode of the fifteenth transistor M15, and a ground terminal, respectively, and the thirteenth transistor M13 is configured to replicate current flowing through the twelfth transistor M13Output sampling current I of tube M12 OUT K, generating an output sampling current I flowing through the twelfth transistor M12 OUT A mirror current of/k;
a control electrode of the fourteenth transistor M14 is coupled to the first terminal of the third converting circuit, the first electrode of the fourteenth transistor M14 and the control electrode of the fifteenth transistor M15, respectively, a first electrode of the fourteenth transistor M14 is coupled to the first terminal of the third converting circuit and the control electrode of the fifteenth transistor M15, respectively, a second electrode of the fourteenth transistor M14 is coupled to the second electrode of the fifteenth transistor M15 and the ground terminal, respectively, and the fourteenth transistor M14 is configured to: the current flowing through the fourteenth transistor M14 is the input sampling current I provided through the first terminal of the third converting circuit IN K minus the output sample current I flowing through the thirteenth transistor M13 OUT The differential current obtained by/k;
a first pole of the fifteenth transistor M15 is coupled to the first terminal of the multiplication circuit 25, a second pole of the fifteenth transistor M15 is grounded, and the fifteenth transistor M15 is configured to copy the differential current flowing through the fourteenth transistor M14, generate a mirror current of the differential current flowing through the fourteenth transistor M14, and provide the differential current from the first pole to the first terminal of the multiplication circuit 25.
Optionally, the multiplication circuit 25 includes a sixth current mirror circuit, a current multiplier Multa and a seventh current mirror circuit, the sixth current mirror circuit is configured to generate a mirror current of the difference current, the sixth current mirror circuit includes a sixteenth transistor M16 and a seventeenth transistor M17, the seventh current mirror circuit is configured to generate a mirror current of the output current, the seventh current mirror circuit includes an eighteenth transistor M18 and a nineteenth transistor M19, wherein:
a control electrode of the sixteenth transistor M16 is respectively coupled to the third terminal of the difference circuit 24, the second electrode of the sixteenth transistor M16 and the control electrode of the seventeenth transistor M17, a first electrode of the sixteenth transistor M16 is respectively coupled to the power voltage terminal and the first electrode of the seventeenth transistor M17, a second electrode of the sixteenth transistor M16 is respectively coupled to the third terminal of the difference circuit 24 and the control electrode of the seventeenth transistor M17, and a current flowing through the sixteenth transistor M16 is a difference current;
a control electrode of the seventeenth transistor M17 is coupled to the third terminal of the difference circuit 24, a first electrode of the seventeenth transistor M17 is coupled to the power supply voltage terminal, a second electrode of the seventeenth transistor M17 is coupled to the first input terminal of the current multiplier Multa, and the seventeenth transistor M17 is configured to copy the difference current flowing through the sixteenth transistor M16, generate a difference current mirror current flowing through the sixteenth transistor M16, and provide the difference current from the second electrode to the first input terminal of the current multiplier Multa;
the current multiplier Multa is configured to output a sampled current I according to a difference current of the first input terminal in1, a first reference current Iref1 of the second input terminal in2, and an output sampled current I of the second output terminal out2 OUT K, determining an output current and supplying the output current from the first output terminal out1 to the eighteenth transistor M18; the current multiplier Multa can realize the current numerical calculation relationship: in1 in2= out1 out2;
a control electrode of the eighteenth transistor M18 is respectively coupled to the first output end of the current multiplier Multa, the second electrode of the eighteenth transistor M18, and a control electrode of the nineteenth transistor M19, a first electrode of the eighteenth transistor M18 is respectively coupled to the power supply voltage terminal and the first electrode of the nineteenth transistor M19, a second electrode of the eighteenth transistor M18 is respectively coupled to the first output end of the current multiplier Multa and the control electrode of the nineteenth transistor M19, and a current flowing through the eighteenth transistor M18 is an output current;
the first pole of the nineteenth transistor M19 is coupled to the power supply voltage terminal, the second pole of the nineteenth transistor M19 is coupled to the second terminal of the output circuit 26, and the nineteenth transistor M19 is configured to copy the output current flowing through the eighteenth transistor M18, generate a mirror current of the output current flowing through the eighteenth transistor M18, and supply the output current from the second pole to the second terminal of the output circuit 26.
Optionally, the output circuit 26 includes a fourth resistor R 4 And a fifth resistor R 5 Fourth resistor R 4 Is m times the value of the first resistor R1, the fifth resistor R 5 Is n times the value of the first resistor R1, the parameters m and n are both greater than 0, wherein:
fourth resistor R 4 First end ofA fourth resistor R coupled to a third terminal of the multiplication circuit 25 4 Are respectively coupled to the fifth resistors R 5 And the second reference current terminal of the first conversion circuit 21, through the fourth resistor R 4 Is the output current, wherein the output current is the output current from the fourth resistor R 4 The first end of the voltage-mode loop outputs a clamping voltage Vclamp to the output end of an error amplifier EA in the voltage-mode loop, and the clamping voltage Vclamp is used for clamping the output voltage to the clamping voltage Vclamp when the output voltage of the error amplifier EA is smaller than the clamping voltage Vclamp;
the voltage mode loop jumps towards the load resistance RL or the input voltage V of the voltage mode loop IN When the conditions such as jumping and the like exist, the clamping voltage Vclamp can be adjusted in a self-adaptive manner; moreover, when the output voltage Veao of the error amplifier EA is smaller than the clamp voltage Vclamp, the output voltage Veao of the error amplifier EA is limited to be close to the steady-state value of the clamp voltage Vclamp, so that the response time of the voltage mode loop can be greatly shortened.
Fifth resistor R 5 Is coupled to a second reference current terminal of the first conversion circuit 21, a fifth resistor R 5 Is grounded and flows through a fifth resistor R 5 Is the sum of the output current and a second reference current Iref2 at a second reference current terminal.
The operation principle of the adaptive acceleration circuit applied to the voltage mode loop provided by the embodiment of the present disclosure is described below with reference to the exemplary circuit diagram of the adaptive acceleration circuit shown in fig. 3.
The current relationship of each pin of the current multiplier Multa in fig. 3 is as follows:
Figure BDA0003862276300000191
Figure BDA0003862276300000192
Figure BDA0003862276300000201
Figure BDA0003862276300000202
thus, the clamping voltage V clamp The values may be calculated as:
Figure BDA0003862276300000203
taking a Boost topological structure in the DC-DC converter as an example, and setting the duty ratio of a loop as D, then:
V clamp ＝(m+n)V ref D+nV ref
according to actual loop control requirements, such as the slope and the initial value of a ramp signal Vramp, the trimming design of the clamping voltage Vclamp can be realized through parameters m and n. When the loop is adjusting the output voltage Veao of the error amplifier EA to be lower than the clamp voltage V clamp The output voltage Veao of the error amplifier EA can be clamped at a clamp voltage V by a BUFFER structure composed of an operational amplifier OPA and an N-type transistor clamp At a value that makes the loop return to steady state more quickly. For example, when Veao is less than Vclamp, veao may be 0.3V or even grounded directly, in which case the loop recovers at a slower speed, and thus clamping Veao to Vclamp may increase the loop recovery speed when Veao is less than Vclamp.
Since the clamp voltage Vclamp includes information about the duty cycle D of the loop, the loop jumps in the direction of the load resistance RL or the loop input voltage V IN When the voltage mode loop jumps and the like, the clamping voltage Vclamp can be adjusted in a self-adaptive mode, the output voltage Veao of the error amplifier EA is limited to be close to a final steady-state value, and the response time of the voltage mode loop can be greatly shortened. Meanwhile, the value of the clamp voltage Vclamp is reserved for the error amplifier EA to output a sufficient floating space so as to meet the requirement of sufficient slew rate to realize loop regulation, when the duty ratio D is 0, vclamp is a constant term nref, the value of the constant term nref is set to a smaller value, for example, 0.1V, so as to reserve a loop regulation for the duty ratio DThe whole space.
From the above description, it can be seen that the present disclosure achieves the following technical effects:
the disclosed embodiments sample the input voltage V of the voltage-mode loop in real time IN And an output voltage V OUT The output voltage Veao output by the error amplifier EA is limited to the clamping voltage Vclamp, the output voltage Veao can be clamped to a system steady-state value of the clamping voltage Vclamp, and other nodes in the whole voltage mode loop are automatically adjusted accurately and slowly according to the self structure of the voltage mode loop until the voltage mode loop system is stable;
by clamping the output voltage Veao to the clamp voltage Vclamp, the voltage mode loop jumps in the face of the load resistance RL or the loop input voltage V IN During jumping, the response time of a voltage mode loop is shortened, the steady state is recovered more quickly, and the problem that the response speed of a system is low when jumping under different application conditions in the related art is solved;
since the clamp voltage Vclamp contains information about the duty cycle D of the loop, the voltage-mode loop jumps in the face of the load resistance RL or the input voltage V of the voltage-mode loop IN When jumping and other conditions, the clamping voltage Vclamp can be adjusted in a self-adaptive manner; moreover, when the output voltage Veao of the error amplifier EA is smaller than the clamp voltage Vclamp, the output voltage Veao of the error amplifier EA is limited to be close to the steady-state value of the clamp voltage Vclamp, so that the response time of the voltage mode loop can be greatly shortened.
The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of apparatus and methods according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems that perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
As used herein and in the appended claims, the singular forms of words include the plural and vice versa, unless the context clearly dictates otherwise. Thus, when reference is made to the singular, it is generally intended to include the plural of the corresponding term. Similarly, the terms "comprising" and "including" are to be construed as being inclusive rather than exclusive. Likewise, the terms "include" and "or" should be construed as inclusive unless such an interpretation is explicitly prohibited herein. Where the term "example" is used herein, particularly when it comes after a set of terms, it is merely exemplary and illustrative and should not be considered exclusive or extensive.
Further aspects and scope will become apparent from the description provided herein. It should be understood that various aspects of the present application may be implemented alone or in combination with one or more other aspects. It should also be understood that the description and specific examples are intended for purposes of illustration only and are not intended to limit the scope of the present disclosure.
Although the embodiments of the present disclosure have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the present disclosure, and such modifications and variations fall within the scope defined by the appended claims.

Claims (10)

1. An adaptive speed-up circuit for a voltage-mode loop, the adaptive speed-up circuit comprising: first conversion circuit, second conversion circuit, third conversion circuit, difference circuit, multiplication circuit and output circuit, wherein:
the first converting circuit is configured to convert a reference voltage into a first reference current and a second reference current, and to provide the first reference current to the multiplying circuit and the second reference current to the output circuit;
the second conversion circuit is configured to convert an output sampling division voltage of a voltage mode loop into an output sampling current, and provide the output sampling current to the difference circuit and the multiplication circuit respectively, wherein the output sampling division voltage of the voltage mode loop is obtained by sampling an output voltage of the voltage mode loop;
the third conversion circuit is configured to convert an input sampling division voltage of the voltage mode loop into an input sampling current and provide the input sampling current to the difference circuit, wherein the input sampling division voltage of the voltage mode loop is obtained by sampling an input voltage of the voltage mode loop;
the difference circuit is configured to determine a difference current from the input sample current and the output sample current and provide the difference current to the multiplication circuit;
the multiplication circuit is configured to determine an output current from the difference current, the first reference current, and the output sample current, and provide the output current to the output circuit; and
the output circuit is configured to output a clamping voltage according to the output current and the second reference current, control an output voltage of an output end of an error amplifier in the voltage mode loop, and clamp the output voltage to the clamping voltage.
2. The adaptive acceleration circuit of claim 1, wherein the first conversion circuit comprises a first buffer circuit and a first current mirror circuit, wherein:
the first buffer circuit is configured to convert a reference voltage into a reference current and provide the reference current to the first current mirror circuit;
the first current mirror circuit is configured to replicate the reference current, resulting in a first reference current and a second reference current, and to provide the first reference current to the multiplication circuit and the second reference current to the output circuit, wherein the reference current, the first reference current and the second reference current are equal.
3. The adaptive acceleration circuit of claim 2, wherein the first buffer circuit comprises a first operational amplifier, a first transistor, and a first resistor, wherein the first current mirror circuit comprises a second transistor, a third transistor, and a fourth transistor, wherein:
the non-inverting input terminal of the first operational amplifier is coupled to a reference voltage terminal, the inverting input terminals of the first operational amplifier are respectively coupled to the second pole of the first transistor and the first terminal of the first resistor, the output terminal of the first operational amplifier is coupled to the control pole of the first transistor, and the first operational amplifier is configured to clamp the reference voltage across the first resistor to obtain the reference current;
a first electrode of the first transistor is coupled to a control electrode of the second transistor, a second electrode of the second transistor, a control electrode of the third transistor, and a control electrode of the fourth transistor, respectively;
a control electrode of the second transistor is coupled to a second electrode of the second transistor, a control electrode of the third transistor and a control electrode of the fourth transistor, respectively, and a first electrode of the second transistor is coupled to a power supply voltage terminal, a first electrode of the third transistor and a first electrode of the fourth transistor, respectively;
a control electrode of the third transistor is coupled to a control electrode of the fourth transistor, first electrodes of the third transistor are respectively coupled to the power supply voltage terminal and a first electrode of the fourth transistor, a second electrode of the third transistor is coupled to a second electrode of the multiplication circuit, and the third transistor is configured to copy the reference current flowing through the second transistor, obtain a first reference current, and provide the first reference current from the second electrode to the second electrode of the multiplication circuit;
a first pole of the fourth transistor is coupled to the power voltage terminal, a second pole of the fourth transistor is coupled to the first terminal of the output circuit, and the fourth transistor is configured to copy the reference current flowing through the second transistor, obtain a second reference current, and provide the second reference current from the second pole to the first terminal of the output circuit.
4. The adaptive acceleration circuit of claim 1, wherein the second translation circuit comprises a second buffer circuit and a second current mirror circuit, wherein:
the second buffer circuit is configured to convert the output sampling voltage into the output sampling current and provide the output sampling current to the second current mirror circuit;
the second current mirror circuit is configured to replicate the output sample current and provide the output sample current to the difference circuit and the multiplication circuit, respectively.
5. The adaptive acceleration circuit of claim 4, wherein the second buffer circuit comprises a second operational amplifier, a fifth transistor, and a second resistor, and wherein the second current mirror circuit comprises a sixth transistor, a seventh transistor, and an eighth transistor, wherein:
a non-inverting input terminal of the second operational amplifier is coupled to an output sampling voltage-dividing terminal, inverting input terminals of the second operational amplifier are respectively coupled to a second pole of the fifth transistor and a first end of the second resistor, an output terminal of the second operational amplifier is coupled to a control pole of the fifth transistor, and the second operational amplifier is configured to clamp the output sampling voltage-dividing terminal on the second resistor to obtain the output sampling current;
a first electrode of the fifth transistor is coupled to the control electrode of the sixth transistor, the second electrode of the sixth transistor, the control electrode of the seventh transistor, and the control electrode of the eighth transistor, respectively;
a second end of the second resistor is grounded;
a control electrode of the sixth transistor is respectively coupled to the second electrode of the sixth transistor, the control electrode of the seventh transistor, and the control electrode of the eighth transistor, and a first electrode of the sixth transistor is respectively coupled to a power supply voltage terminal, the first electrode of the seventh transistor, and the first electrode of the eighth transistor;
a control electrode of the seventh transistor is coupled to a control electrode of the eighth transistor, a first electrode of the seventh transistor is respectively coupled to the power supply voltage terminal and a first electrode of the eighth transistor, a second electrode of the seventh transistor is coupled to a first terminal of the difference circuit, and the seventh transistor is configured to copy the output sampling current flowing through the sixth transistor and provide the output sampling current from the second electrode to the first terminal of the difference circuit;
a first pole of the eighth transistor is coupled to the power supply voltage terminal, a second pole of the eighth transistor is coupled to the second terminal of the multiplication circuit, and the eighth transistor is configured to replicate the output sample current flowing through the sixth transistor and provide the output sample current from the second pole to the second terminal of the multiplication circuit.
6. The adaptive acceleration circuit of claim 1, wherein the third conversion circuit comprises a third buffer circuit and a third current mirror circuit, wherein:
the third buffer circuit is configured to convert an input sampled divided voltage into an input sampled current and provide the input sampled current to the third current mirror circuit;
the third current mirror circuit is configured to replicate the input sampled current and provide the input sampled current to the difference circuit.
7. The adaptive acceleration circuit of claim 6, wherein the third buffer circuit comprises a third operational amplifier, a ninth transistor, and a third resistor, and wherein the third current mirror circuit comprises a tenth transistor and an eleventh transistor, wherein:
a non-inverting input terminal of the third operational amplifier is coupled to an input sampling voltage-dividing terminal, inverting input terminals of the third operational amplifier are respectively coupled to the second pole of the ninth transistor and the first end of the third resistor, an output terminal of the third operational amplifier is coupled to the control pole of the ninth transistor, and the third operational amplifier is configured to clamp the input sampling voltage-dividing terminal on the third resistor to obtain the input sampling current;
a first electrode of the ninth transistor is coupled to a control electrode of the tenth transistor, a second electrode of the tenth transistor, and a control electrode of the eleventh transistor, respectively;
a second end of the third resistor is grounded;
a control electrode of the tenth transistor is coupled to the second electrode of the tenth transistor and the control electrode of the eleventh transistor, respectively, and a first electrode of the tenth transistor is coupled to a power supply voltage terminal and the first electrode of the eleventh transistor, respectively;
a first pole of the eleventh transistor is coupled to the power supply voltage terminal, a second pole of the eleventh transistor is coupled to the second terminal of the difference circuit, and the eleventh transistor is configured to copy the input sampling current flowing through the tenth transistor and provide the input sampling current from the second pole to the second terminal of the difference circuit.
8. The adaptive boost circuit of claim 1, wherein the difference circuit comprises a fourth current mirror circuit comprising a twelfth transistor and a thirteenth transistor and a fifth current mirror circuit comprising a fourteenth transistor and a fifteenth transistor, wherein:
a control electrode of the twelfth transistor is respectively coupled to the first terminal of the second converting circuit, the first electrode of the twelfth transistor, and the control electrode of the thirteenth transistor, a first electrode of the twelfth transistor is respectively coupled to the first terminal of the second converting circuit and the control electrode of the thirteenth transistor, a second electrode of the twelfth transistor is respectively coupled to the second electrode of the thirteenth transistor, the second electrode of the fourteenth transistor, the second electrode of the fifteenth transistor, and a ground terminal, wherein the output sampling current provided through the first terminal of the second converting circuit flows through the twelfth transistor;
a control electrode of the thirteenth transistor is coupled to the first terminal of the second conversion circuit, first electrodes of the thirteenth transistor are respectively coupled to the first terminal of the third conversion circuit and the first electrode of the fourteenth transistor, a second electrode of the thirteenth transistor is respectively coupled to the second electrode of the fourteenth transistor, the second electrode of the fifteenth transistor and a ground terminal, and the thirteenth transistor is configured to replicate the output sampling current flowing through the twelfth transistor;
a control electrode of the fourteenth transistor is respectively coupled to the first terminal of the third converting circuit, the first electrode of the fourteenth transistor, and the control electrode of the fifteenth transistor, a first electrode of the fourteenth transistor is respectively coupled to the first terminal of the third converting circuit and the control electrode of the fifteenth transistor, a second electrode of the fourteenth transistor is respectively coupled to the second electrode of the fifteenth transistor and a ground terminal, and the fourteenth transistor is configured to: a current flowing through the fourteenth transistor is a difference current obtained by subtracting the output sampling current flowing through the thirteenth transistor from the input sampling current provided through the first terminal of the third conversion circuit;
a first pole of the fifteenth transistor is coupled to the first terminal of the multiplication circuit, a second pole of the fifteenth transistor is coupled to ground, and the fifteenth transistor is configured to copy the difference current flowing through the fourteenth transistor and provide the difference current from the first pole to the first terminal of the multiplication circuit.
9. The adaptive boost circuit of claim 1, wherein the multiplication circuit comprises a sixth current mirror circuit comprising a sixteenth transistor and a seventeenth transistor, a current multiplier, and a seventh current mirror circuit comprising an eighteenth transistor and a nineteenth transistor, wherein:
a control electrode of the sixteenth transistor is respectively coupled to the third terminal of the difference circuit, the second electrode of the sixteenth transistor and the control electrode of the seventeenth transistor, a first electrode of the sixteenth transistor is respectively coupled to a power supply voltage terminal and the first electrode of the seventeenth transistor, and a second electrode of the sixteenth transistor is respectively coupled to the third terminal of the difference circuit and the control electrode of the seventeenth transistor;
a control electrode of the seventeenth transistor is coupled to the third terminal of the difference circuit, a first electrode of the seventeenth transistor is coupled to the power supply voltage terminal, a second electrode of the seventeenth transistor is coupled to the first input terminal of the current multiplier, and the seventeenth transistor is configured to copy the difference current flowing through the sixteenth transistor and provide the difference current from the second electrode to the first input terminal of the current multiplier;
the current multiplier is configured to determine an output current according to the difference current of the first input terminal, the first reference current of the second input terminal and the output sampling current of the second output terminal, and provide the output current from the first output terminal to the eighteenth transistor;
a control electrode of the eighteenth transistor is respectively coupled to the first output end of the current multiplier, the second electrode of the eighteenth transistor and the control electrode of the nineteenth transistor, a first electrode of the eighteenth transistor is respectively coupled to a power supply voltage terminal and the first electrode of the nineteenth transistor, and a second electrode of the eighteenth transistor is respectively coupled to the first output end of the current multiplier and the control electrode of the nineteenth transistor;
a first pole of the nineteenth transistor is coupled to the power supply voltage terminal, a second pole of the nineteenth transistor is coupled to the second terminal of the output circuit, and the nineteenth transistor is configured to replicate an output current flowing through the eighteenth transistor and provide the output current from the second pole to the second terminal of the output circuit.
10. The adaptive acceleration circuit of claim 1, wherein the output circuit comprises a fourth resistor and a fifth resistor, wherein:
a first end of the fourth resistor is coupled to a third end of the multiplication circuit, a second end of the fourth resistor is coupled to a first end of the fifth resistor and a second reference current end of the first conversion circuit, respectively, and a current flowing through the fourth resistor is an output current, wherein a clamping voltage is output from the first end of the fourth resistor to an output end of an error amplifier in the voltage mode loop, and the clamping voltage is used for clamping the output voltage to the clamping voltage when the output voltage of the error amplifier is smaller than the clamping voltage;
the first end of the fifth resistor is coupled to the second reference current end of the first conversion circuit, the second end of the fifth resistor is grounded, and the current flowing through the fifth resistor is the sum of the output current and the second reference current at the second reference current end.
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