CN115441714A - Hiccup mode control circuit for DC-DC converter, and DC-DC converter - Google Patents

Abstract

Embodiments of the present disclosure provide a hiccup mode control circuit for a DC-DC converter. The hiccup mode control circuit includes: a timing circuit, a logic control circuit, and an output circuit. The timing circuit generates first and second indication signals according to an overcurrent indication signal of the DC-DC converter, provides the first indication signal to the output circuit, and provides the second indication signal to the logic control circuit. The first indication signal is inverted to an active level when a first period of time elapses from the inversion of the overcurrent indication signal to the active level. The second indication signal is inverted to the active level when a second period of time elapses from the inversion of the overcurrent indication signal to the active level. The first time period is longer than the second time period. The logic control circuit generates a logic control signal according to the overcurrent indication signal, a zero current indication signal of the DC-DC converter and the second indication signal, and provides the logic control signal for the output circuit. The output circuit generates a hiccup mode indication signal based on the first indication signal and the logic control signal.

Description

Hiccup mode control circuit for DC-DC converter, and DC-DC converter

Technical Field

Embodiments of the present disclosure relate to the field of integrated circuit technology, and in particular, to a hiccup mode control circuit for a DC-DC converter, and a DC-DC converter.

Background

Zero Current Detection (ZCD) is a function of the DC-DC converter to detect the zero value of the inductor current. The corresponding inductor current when the ZCD signal is inverted to an active level is denoted as IL _ZCD . If it is to be IL _ZCD Adjusting too high or too low will reduce the efficiency of the DC-DC converter. Therefore, IL is generally used in designing DC-DC converters _ZCD Adjusted to approximately 0A. However, pre-designed IL _ZCD And the voltage also varies with factors such as process angle, temperature, output voltage and the like, so that the voltage is negative under partial working conditions.

As the application of the DC-DC converter becomes wider, the attention and importance of the fault detection and the circuit protection of the DC-DC converter are increased. HICCUP (hicup) is an overcurrent protection mode of a DC-DC converter. The hicup signal may be used to indicate that the DC-DC converter is turned off to reduce the amount of heat generated by the short circuit current when the output of the DC-DC converter is shorted for a long time. For a BUCK type DC-DC converter (BUCK), because the inductive current is large when the DC-DC converter is overcurrent, in order to prevent the large current from flowing from the body diode of the lower tube and damaging the lower tube after the DC-DC converter is turned off, the lower tube needs to be kept on for a certain time until the inductive current is discharged to 0A to turn off the DC-DC converter. The DC-DC converter is therefore often controlled by the ZCD signal to enter a hicup mode (e.g. the DC-DC converter enters the hicup mode when the ZCD signal flips to a high level), turning off the DC-DC converter. After entering the hicup mode, a timer is used to count the time until a fixed time (e.g. 12 ms) before exiting the hicup mode. After exiting the HICCUP mode, the DC-DC converter may be restarted.

Disclosure of Invention

Embodiments described herein provide a hiccup mode control circuit for a DC-DC converter, and a DC-DC converter.

According to a first aspect of the present disclosure, a hiccup mode control circuit for a DC-DC converter is provided. The hiccup mode control circuit includes: a timing circuit, a logic control circuit, and an output circuit. Wherein the timing circuit is configured to: the first indication signal and the second indication signal are generated according to an overcurrent indication signal of the DC-DC converter, the first indication signal is provided for the output circuit through the first node, and the second indication signal is provided for the logic control circuit through the second node. And when a first time period begins to elapse from the inversion of the overcurrent indicating signal to the active level, the first indicating signal is inverted to the active level. The second indication signal is inverted to the active level when a second period of time elapses from the inversion of the overcurrent indication signal to the active level. The first time period is longer than the second time period. The logic control circuitry is configured to: and generating a logic control signal according to the overcurrent indicating signal, the zero current indicating signal of the DC-DC converter and the second indicating signal, and providing the logic control signal to the output circuit through the third node. The output circuit is configured to: generating a hiccup mode indication signal according to the first indication signal and the logic control signal.

In some embodiments of the present disclosure, the active level of the zero current indication signal indicates that the inductor current of the DC-DC converter drops to 0 amps.

In some embodiments of the present disclosure, the logic control signal is flipped to an active level in a case where the over current indication signal is at an active level and one of the zero current indication signal and the second indication signal of the DC-DC converter is flipped to an active level.

In some embodiments of the disclosure, where the first indication signal is at an inactive level and the logic control signal is at an active level, the hiccup mode indication signal is at a first level to indicate entry into the hiccup mode.

In some embodiments of the disclosure, the hiccup mode indication signal is at a second level to indicate exiting the hiccup mode if the first indication signal is at an active level.

In some embodiments of the present disclosure, the inactive level of the first indication signal is a high level. The active level of the first indication signal is low.

In some embodiments of the present disclosure, the active level of the second indication signal is a high level. The inactive level of the second indicator signal is low.

In some embodiments of the present disclosure, the active level of the logic control signal is a high level. The inactive level of the logic control signal is low.

In some embodiments of the present disclosure, the active level of the over current indication signal is a high level. The inactive level of the over current indication signal is low.

In some embodiments of the present disclosure, the active level of the zero current indication signal is a high level. The inactive level of the zero current indication signal is low.

In some embodiments of the present disclosure, the first level is a high level. The second level is a low level.

In some embodiments of the present disclosure, the logic control circuit comprises: the inverter, the first NOR gate, and the second NOR gate. Wherein the input of the inverter is provided with an over-current indication signal. The output end of the inverter is coupled with the first input end of the first NOR gate. The second input terminal of the first nor gate is coupled to the output terminal of the second nor gate. The output terminal of the first NOR gate is coupled to the first input terminal of the second NOR gate and the third node. The second input of the second nor gate is supplied with a zero current indication signal. The third input terminal of the second nor gate is coupled to the second node.

In some embodiments of the present disclosure, the output circuit includes: and an AND gate. The first input terminal of the AND gate is coupled to the first node. The second input terminal of the AND gate is coupled to the third node. The hiccup mode indication signal is output from the output of the and gate.

In some embodiments of the present disclosure, the over-current indication signal of the DC-DC converter flips to an active level when a number of times an inductor current of the DC-DC converter reaches an over-current peak is equal to a threshold number of times.

In some embodiments of the present disclosure, the threshold number of times is equal to 7.

In some embodiments of the present disclosure, the first time period is 12ms.

In some embodiments of the present disclosure, the second time period is 6ms.

According to a second aspect of the present disclosure, a hiccup mode control circuit for a DC-DC converter is provided. The hiccup mode control circuit includes: the circuit comprises a timing circuit, an inverter, a first NOR gate, a second NOR gate and an AND gate. Wherein the timing circuit is configured to: and generating a first indication signal and a second indication signal according to the overcurrent indication signal of the DC-DC converter, providing the first indication signal to a first input end of the AND gate, and providing the second indication signal to a third input end of the second NOR gate. And when a first time period begins to elapse from the inversion of the overcurrent indicating signal to the active level, the first indicating signal is inverted to the active level. The second indication signal is inverted to the active level when a second period of time elapses from the inversion of the overcurrent indication signal to the active level. The first time period is longer than the second time period. The input of the inverter is provided with an over-current indication signal. The output end of the inverter is coupled with the first input end of the first NOR gate. The second input terminal of the first nor gate is coupled to the output terminal of the second nor gate. The output terminal of the first NOR gate is coupled with the first input terminal of the second NOR gate and the second input terminal of the AND gate. The second input terminal of the second nor gate is supplied with a zero current indication signal of the DC-DC converter. The hiccup mode indication signal is output from the output of the and gate.

According to a third aspect of the present disclosure, a DC-DC converter is provided. The DC-DC converter comprises a hiccup mode control circuit according to the first or second aspect of the present disclosure.

Drawings

To more clearly illustrate the technical aspects of the embodiments of the present disclosure, reference will now be made in brief to the accompanying drawings of the embodiments, it being understood that the drawings described below relate only to some embodiments of the disclosure and are not limiting thereof, and wherein:

FIG. 1 is an exemplary circuit diagram of a hiccup mode control circuit for a DC-DC converter;

FIG. 2 is a timing diagram of some of the signals used in the hiccup mode control circuit shown in FIG. 1;

FIG. 3 is a schematic block diagram of a hiccup mode control circuit for a DC-DC converter in accordance with an embodiment of the present disclosure;

fig. 4 is an exemplary circuit diagram of a hiccup mode control circuit for a DC-DC converter according to an embodiment of the disclosure;

FIG. 5 is an exemplary timing diagram of some of the signals used for the hiccup mode control circuit shown in FIG. 3 or FIG. 4; and

fig. 6 is another exemplary timing diagram of some signals for the hiccup mode control circuit shown in fig. 3 or 4.

In the drawings, the same reference numerals in the last two digits correspond to the same elements. It should be noted that the elements in the figures are schematic and not drawn to scale.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings. It is to be understood that the described embodiments are only a few embodiments of the present disclosure, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without inventive step, are also within the scope of protection of the disclosure.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the presently disclosed subject matter belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the specification and relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. As used herein, the statement that two or more parts are "connected" or "coupled" together shall mean that the parts are joined together either directly or joined through one or more intermediate components. In addition, terms such as "first" and "second" are only used to distinguish one element (or part of an element) from another element (or another part of an element).

Fig. 1 illustrates an exemplary circuit diagram of a hiccup mode control circuit 100 for a DC-DC converter. The hiccup mode control circuit 100 includes: a timer CNT, an inverter NG, a first NOR gate NOR1, a second NOR gate NOR2, AND an AND gate AND. The DC-DC converter is, for example, a step-down DC-DC converter (BUCK).

After the inductor current of the DC-DC converter is overcurrent and a peak of, for example, 7 inductor currents occurs (the peak occurring in the event of overcurrent may be referred to as an "overcurrent peak" in the context), the DC-DC converter may cause the overcurrent indication signal Cycle _7 to flip to a high level. The over-current indication signal Cycle _7 is supplied to an input terminal of the inverter NG. The output terminal of the inverter NG is coupled to the first input terminal of the first NOR gate NOR 1. The second input terminal of the first NOR gate NOR1 is coupled to the output terminal of the second NOR gate NOR2. The output terminal of the first NOR gate NOR1 is coupled to the first input terminal of the second NOR gate NOR2. A second input terminal of the second NOR gate NOR2 is supplied with the ZCD signal. After the overcurrent indicating signal Cycle _7 is inverted to a high level, the lower tube of the DC-DC converter is kept on, so that the inductor current can be continuously reduced to 0A. After detecting that the inductor current is discharged to 0A, the ZCD signal is inverted to a high level. When the ZCD signal flips to a high level, the signal RESET output from the output terminal of the first NOR gate NOR1 flips to a high level. The signal RESET is supplied to the enable terminal of the timer CNT. Therefore, the timer CNT starts counting from the signal RESET being inverted to the high level, and the output signal S12 of the timer CNT is at the high level. Since both input terminals of the AND gate AND are at a high level, the signal hicup output from the AND gate AND is inverted to a high level, thereby controlling the DC-DC converter to enter the hicup mode. In the HICCUP mode, the upper tube and the lower tube of the DC-DC converter are closed.

When the timer CNT reaches, for example, 12ms, the output signal S12 of the timer CNT is inverted to a low level, so that the signal hicup is inverted to a low level to instruct the DC-DC converter to exit the hicup mode. After the DC-DC converter exits the hicup mode, the DC-DC converter restarts.

Fig. 2 shows a timing diagram of some signals for the hiccup mode control circuit shown in fig. 1. After the inductor current IL has, for example, 7 overcurrent peaks, at time t1, the overcurrent indication signal Cycle _7 is inverted to a high level. Over time, the inductor current IL drops to 0A at time t2, and the ZCD signal therefore pulses high. From time t2, the timer CNT starts counting, and the signal hicup is inverted to high level to control the DC-DC converter to enter the hicup mode. In the HICCUP mode, an enable signal ENDC of the DC-DC converter is inverted to a low level, so that an upper tube and a lower tube of the DC-DC converter are closed. Starting from time t2, at time t3, which reaches 12ms, signal hicup toggles low to indicate that the DC-DC converter exits hicup mode. After the DC-DC converter exits the HICCUP mode, an enable signal ENDC of the DC-DC converter is inverted to a high level, thereby controlling the DC-DC converter to restart.

As described above, a pre-designed IL _ZCD And the voltage also changes with the factors of process angle, temperature, output voltage and the like, so that the voltage is negative under partial working conditions. When IL is used _ZCD When the voltage is deviated to a negative value, in the HICCUP mode, because the output voltage of the DC-DC converter is close to 0V, the inductive current cannot be reduced to the negative value, so that the ZCD signal cannot be inverted to a high level, the DC-DC converter cannot enter the HICCUP mode, the lower pipe is always opened, and the DC-DC converter cannot be restarted. In addition, the timing of 12ms begins with the signal HICCUP toggling high, i.e., the ZCD signal toggling high, due to IL _ZCD The value of (c) is not stable, and if the time is counted from the time the ZCD signal is turned over to the high level, the accurate 12ms cannot be obtained, and thus the accurate time for exiting the hicup mode cannot be obtained.

In view of the above problems, embodiments of the present disclosure propose a hiccup mode control circuit for a DC-DC converter. Fig. 3 shows a schematic block diagram of a hiccup mode control circuit 300 for a DC-DC converter according to an embodiment of the disclosure. The hiccup mode control circuit 300 includes: a timing circuit 310, a logic control circuit 320, and an output circuit 330.

The timing circuit 310 may be coupled to the output circuit 330 via the first node N1. The timing circuit 310 may be coupled to the logic control circuit 320 via a second node N2. The timing circuit 310 may be configured to: the first and second indication signals S12 and Cycle _6ms are generated according to the overcurrent indication signal Cycle _7 of the DC-DC converter, the first indication signal S12 is provided to the output circuit 330 via the first node N1, and the second indication signal Cycle _6ms is provided to the logic control circuit 320 via the second node N2. Here, the first indication signal S12 is inverted to the active level when the first period of time elapses from the inversion of the overcurrent indication signal Cycle _7 to the active level. The second indication signal Cycle _6ms is flipped to the active level when the second period of time elapses from the time when the overcurrent indication signal Cycle _7 is flipped to the active level. The first time period is longer than the second time period. In some embodiments of the present disclosure, the first time period is 12ms. The second period of time is 6ms.

In some embodiments of the present disclosure, the inactive level of the first indication signal S12 is a high level. The active level of the first indicator signal S12 is low. The active level of the second indication signal Cycle _6ms is high level. The inactive level of the second indication signal Cycle _6ms is low. The active level of the overcurrent indication signal Cycle _7 is high. The inactive level of the overcurrent indication signal Cycle _7 is low.

In some embodiments of the present disclosure, the over-current indication signal Cycle _7 of the DC-DC converter is flipped to an active level when the number of times the inductor current of the DC-DC converter reaches the over-current peak is equal to the threshold number of times. In some embodiments of the present disclosure, the threshold number of times is equal to 7.

The logic control circuit 320 may be coupled to the timing circuit 310 via a second node N2. The logic control circuit 320 may be coupled to the output circuit 330 via a third node N3. The logic control circuit 320 may be configured to: the logic control signal RESET is generated from the overcurrent indication signal Cycle _7, the zero-current indication signal ZCD of the DC-DC converter, and the second indication signal Cycle _6ms, and is supplied to the output circuit 330 via the third node N3. In some embodiments of the present disclosure, the active level of the zero current indication signal ZCD indicates that the inductor current of the DC-DC converter drops to 0 amps. In other embodiments of the present disclosure, the active level of the zero current indication signal ZCD indicates that the inductor current of the DC-DC converter has dropped to a negative value depending on process corner, temperature, output voltage, and the like.

The output circuit 330 may be coupled to the timing circuit 310 via a first node N1. The output circuit 330 may be coupled to the logic control circuit 320 via a third node N3. The output circuit 330 may be configured to: the HICCUP mode indication signal hicup is generated in dependence of the first indication signal S12 and the logic control signal RESET.

In some embodiments of the present disclosure, in a case where the overcurrent indication signal Cycle _7 is at an active level and one of the zero-current indication signal ZCD of the DC-DC converter and the second indication signal Cycle _6ms flips to an active level, the logic control signal RESET flips to an active level.

In some embodiments of the present disclosure, in case the first indication signal S12 is at an inactive level and the logic control signal RESET is at an active level, the HICCUP mode indication signal hicup is at a first level to indicate entering the HICCUP mode. In case the first indication signal S12 is at an active level, the HICCUP mode indication signal hicup is at a second level to indicate that the HICCUP mode is exited.

In some embodiments of the present disclosure, the active level of the logic control signal RESET is a high level. The inactive level of the logic control signal RESET is low. The active level of the zero current indication signal ZCD is high. The inactive level of the zero current indication signal ZCD is low. The first level is a high level. The second level is a low level.

The hiccup mode control circuit according to embodiments of the present disclosure introduces timing control in parallel with the zero current indication signal ZCD control. In the case where the zero-current indication signal ZCD can be inverted to a high level, the DC-DC converter can be brought into the hicup mode by the zero-current indication signal ZCD. At IL _ZCD When the deviation is negative and the zero current indicating signal ZCD cannot be inverted to the high level, the DC-DC converter is forced to enter the hicup mode after the lower tube is opened for a second time period (for example, 6 ms), and the restart of the DC-DC converter is not affected.

In addition, the timing (first period) of exiting the hicup mode starts from the transition of the overcurrent indication signal Cycle _7 to the active level, rather than from the transition of the zero-current indication signal ZCD to the active level, and by looking at the time corresponding to the last peak of the inductor current before the DC-DC converter enters the hicup mode, the exit time of the hicup mode can be accurately obtained.

Fig. 4 illustrates an exemplary circuit diagram of a hiccup mode control circuit for a DC-DC converter according to an embodiment of the present disclosure. The timing circuit 410 may be a timer. The over-current indication signal Cycle _7 is supplied to the enable terminal EN of the timer. The timer starts counting from the inversion of the overcurrent indication signal Cycle _7 to the high level. When a second time period (e.g., 6 ms) is timed out, the second indication signal Cycle _6ms flips to the active level. When a first time period (e.g., 12 ms) is timed out, the first indication signal S12 is inverted to an active level.

The logic control circuit 420 may include: an inverter NG, a first NOR gate NOR1, and a second NOR gate NOR2. Wherein the input of the inverter NG is supplied with the over-current indication signal Cycle _7. The output terminal of the inverter NG is coupled to the first input terminal of the first NOR gate NOR 1. The second input terminal of the first NOR gate NOR1 is coupled to the output terminal of the second NOR gate NOR2. An output terminal of the first NOR gate NOR1 is coupled to a first input terminal of the second NOR gate NOR2 and the third node N3. A second input terminal of the second NOR gate NOR2 is supplied with the zero current indication signal ZCD. A third input terminal of the second NOR gate NOR2 is coupled to the second node N2.

The output circuit 430 may include: AND an AND gate AND. The first input terminal of the AND gate AND is coupled to the first node N1. A second input terminal of the AND gate AND is coupled to the third node N3. The HICCUP mode indication signal hicup is output from the output of the AND gate AND.

Those skilled in the art will appreciate that variations to the circuit shown in fig. 4 based on the above inventive concepts are intended to fall within the scope of the present disclosure. In this variant, the effective levels of the individual signals and the gates may also have a different arrangement than in the example shown in fig. 4.

The operating principle of the hiccup mode control circuit according to an embodiment of the present disclosure is described below with reference to fig. 5 and 6.

As shown in fig. 5 and 6, the overcurrent indication signal Cycle _7 is inverted to the high level when the number of times the inductor current IL of the DC-DC converter reaches the overcurrent peak is equal to 7 times (time T1). The timer starts counting (indicated by CNT). Before the second period of time (e.g., 6 ms) is counted, the second indication signal Cycle _6ms is at a low level. Before the first time period (e.g., 12 ms) is counted, the first indicator signal S12 (not shown in fig. 5 and 6) is at a high level.

Since the input signal of the inverter NG is the overcurrent indicating signal Cycle _7 of the high level, the output signal of the inverter NG is a low level signal. The low level signal is supplied to a first input terminal of the first NOR gate NOR 1.

In case the zero-current indication signal ZCD can be inverted to a high level (at time T2) (as in the example of fig. 5), the second NOR gate NOR2 outputs a low level signal. At this time, both input terminals of the first NOR gate NOR1 are inputted with a low level signal, and thus the output logic control signal RESET thereof is inverted to a high level. Since both input terminals of the AND gate AND are inputted with the high level signal, the HICCUP mode indication signal hicup outputted therefrom is inverted to the high level at time T2, causing the DC-DC converter to enter the hicup mode. In the HICCUP mode, an enable signal ENDC of the DC-DC converter is inverted to a low level, so that an upper tube and a lower tube of the DC-DC converter are closed.

At time T3, a first period of time (e.g., 12 ms) is counted, and the first indicator signal S12 is inverted to a low level. Therefore, the HICCUP mode indication signal hicup output from the AND gate AND is toggled to a low level at time T3, causing the DC-DC converter to exit the hicup mode, AND the enable signal endec of the DC-DC converter is toggled to a high level, thereby controlling the DC-DC converter to restart. As can be seen from fig. 5, the time difference between time T1 and time T3 is 12ms.

In the case where the zero-current instruction signal ZCD cannot be inverted to the high level (as in the example of fig. 6), at time T2', a second time period (for example, 6 ms) is counted, and the second instruction signal Cycle _6ms is inverted to the high level. The second NOR gate NOR2 outputs a low level signal. At this time, both input terminals of the first NOR gate NOR1 are inputted with a low level signal, and thus the output logic control signal RESET thereof is inverted to a high level. Since both input terminals of the AND gate AND are inputted with the high level signal, the HICCUP mode indication signal hicup outputted therefrom is inverted to the high level at time T2', so that the DC-DC converter enters the hicup mode. In the HICCUP mode, an enable signal ENDC of the DC-DC converter is inverted to a low level, so that an upper tube and a lower tube of the DC-DC converter are closed.

At time T3, a first period of time (e.g., 12 ms) is counted, and the first indicator signal S12 is inverted to a low level. Therefore, the HICCUP mode indication signal hicup output from the AND gate AND is toggled to a low level at time T3, causing the DC-DC converter to exit the hicup mode, AND the enable signal endec of the DC-DC converter is toggled to a high level, thereby controlling the DC-DC converter to restart. As can be seen from fig. 6, the time difference between time T1 and time T3 is 12ms.

As can be seen from the examples of fig. 5 and 6, the HICCUP mode control circuit according to the embodiment of the present disclosure can still control the DC-DC converter to enter the hicup mode without affecting the restart of the DC-DC converter in case the zero current indication signal ZCD cannot be flipped high by introducing a timing control in parallel with the control of the zero current indication signal ZCD. And the time at which the DC-DC converter exits the hicup mode is unambiguous.

In summary, the hiccup mode control circuit according to embodiments of the present disclosure introduces timing control in parallel with the zero current indication signal ZCD control. In the case where the zero-current indication signal ZCD can be inverted to a high level, the DC-DC converter can be brought into the hicup mode by the zero-current indication signal ZCD. In IL _ZCD When the deviation is negative and the zero current indicating signal ZCD cannot be inverted to the high level, the DC-DC converter is forced to enter the hicup mode after the lower tube is opened for a second time period (for example, 6 ms), and the restart of the DC-DC converter is not affected. In addition, the timing (first time period) for exiting the hicup mode starts from the inversion of the overcurrent indication signal Cycle _7 to the active level, rather than the inversion of the zero-current indication signal ZCD to the active level, and by looking at the time corresponding to the last peak of the inductor current before the DC-DC converter enters the hicup mode, the exit time of the hicup mode can be accurately obtained.

As used herein and in the appended claims, the singular forms of words include the plural and vice versa, unless the context clearly dictates otherwise. Thus, when reference is made to the singular, it is generally intended to include the plural of the corresponding term. Similarly, the terms "comprising" and "including" are to be construed as being inclusive rather than exclusive. Likewise, the terms "include" and "or" should be construed as inclusive unless such an interpretation is explicitly prohibited herein. Where the term "example" is used herein, particularly when it comes after a set of terms, it is merely exemplary and illustrative and should not be considered exclusive or extensive.

Further aspects and ranges of adaptability will become apparent from the description provided herein. It should be understood that various aspects of the present application may be implemented alone or in combination with one or more other aspects. It should also be understood that the description and specific examples are intended for purposes of illustration only and are not intended to limit the scope of the present disclosure.

Several embodiments of the present disclosure have been described in detail above, but it is apparent that various modifications and variations can be made to the embodiments of the present disclosure by those skilled in the art without departing from the spirit and scope of the present disclosure. The scope of the disclosure is defined by the appended claims.

Claims (10)

1. A hiccup mode control circuit for a DC-DC converter, comprising: a timing circuit, a logic control circuit, and an output circuit,

wherein the timing circuit is configured to: generating a first indication signal and a second indication signal according to an overcurrent indication signal of the DC-DC converter, providing the first indication signal to the output circuit through a first node, and providing the second indication signal to the logic control circuit through a second node; wherein the first indication signal is inverted to an active level when a first time period elapses since the overcurrent indication signal is inverted to an active level, and the second indication signal is inverted to an active level when a second time period elapses since the overcurrent indication signal is inverted to an active level, the first time period being longer than the second time period;

the logic control circuitry is configured to: generating a logic control signal according to the over-current indication signal, a zero-current indication signal of the DC-DC converter and the second indication signal, and providing the logic control signal to the output circuit via a third node;

the output circuit is configured to: generating a hiccup mode indication signal according to the first indication signal and the logic control signal.

2. The hiccup mode control circuit of claim 1, wherein an active level of the zero current indication signal indicates that an inductor current of the DC-DC converter drops to 0 amps.

3. The hiccup mode control circuit of claim 1, wherein the logic control signal toggles to an active level if the over-current indication signal is at an active level and one of a zero current indication signal and the second indication signal of the DC-DC converter toggles to an active level.

4. The hiccup mode control circuit of claim 1, wherein in the event that the first indication signal is at an inactive level and the logic control signal is at an active level, the hiccup mode indication signal is at a first level to indicate entry into hiccup mode; in the event that the first indication signal is at an active level, the hiccup mode indication signal is at a second level to indicate exiting the hiccup mode.

5. The hiccup mode control circuit according to any of claims 1 to 4, wherein an inactive level of the first indication signal is high and an active level of the first indication signal is low.

6. The hiccup mode control circuit of claim 1, wherein the logic control circuit comprises: an inverter, a first NOR gate, and a second NOR gate,

wherein an input terminal of the inverter is provided with the over-current indication signal, and an output terminal of the inverter is coupled to a first input terminal of the first nor gate;

a second input terminal of the first nor gate is coupled to an output terminal of the second nor gate, and an output terminal of the first nor gate is coupled to a first input terminal of the second nor gate and the third node;

a second input of the second nor gate is supplied with the zero current indication signal, and a third input of the second nor gate is coupled to the second node.

7. The hiccup mode control circuit of claim 1, wherein the output circuit comprises: an AND gate is connected to the first and second switches,

wherein the first input terminal of the AND gate is coupled to the first node, the second input terminal of the AND gate is coupled to the third node, and the hiccup mode indication signal is output from the output terminal of the AND gate.

8. The hiccup mode control circuit of claim 1, wherein the over-current indication signal of the DC-DC converter flips to an active level when a number of times an inductor current of the DC-DC converter reaches an over-current peak is equal to a threshold number of times.

9. A hiccup mode control circuit for a DC-DC converter, comprising: a timing circuit, an inverter, a first NOR gate, a second NOR gate, and an AND gate,

wherein the timing circuit is configured to: generating a first indication signal and a second indication signal according to an overcurrent indication signal of the DC-DC converter, providing the first indication signal to a first input end of the AND gate, and providing the second indication signal to a third input end of the second NOR gate; wherein the first indication signal is inverted to an active level when a first time period elapses since the overcurrent indication signal is inverted to an active level, and the second indication signal is inverted to an active level when a second time period elapses since the overcurrent indication signal is inverted to an active level, the first time period being longer than the second time period;

an input end of the inverter is provided with the over-current indicating signal, and an output end of the inverter is coupled with a first input end of the first NOR gate;

a second input terminal of the first nor gate is coupled to an output terminal of the second nor gate, and an output terminal of the first nor gate is coupled to a first input terminal of the second nor gate and a second input terminal of the and gate;

a second input terminal of the second NOR gate is provided with a zero current indication signal of the DC-DC converter;

outputting a hiccup mode indication signal from an output of the AND gate.

10. A DC-DC converter comprising: the hiccup mode control circuit of any one of claims 1 to 9.

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