CN115438779A

CN115438779A - Read-write method and system for batch write-in of forgetting memory bridge cross architecture

Info

Publication number: CN115438779A
Application number: CN202211060846.5A
Authority: CN
Inventors: 黄军建; 陈玲; 王一帆; 李传东; 黄廷文
Original assignee: Southwest University
Current assignee: Southwest University
Priority date: 2022-08-31
Filing date: 2022-08-31
Publication date: 2022-12-06

Abstract

The invention provides a read-write method and a read-write system for writing a forgetting memristor bridge cross architecture in batches. The method comprises the steps that a memristor cross architecture is constructed by writing a forgetting memristor bridge in batches, and input signals of the memristor cross architecture comprise a staff spectrum row signal and a column signal; the row signals are used for determining a selected row and a non-selected row, the selected row and the non-selected row are connected with different write signals, the voltage of a memristor bridge on the selected row is higher than a set threshold value, and the voltage of the memristor bridge on the non-selected row is lower than the set threshold value; and memorizing positive and negative weights and zero weights when writing into the memristor bridge in the selected row according to the duty ratio of the column signal, and performing circuit protection on the unselected row. The method has the advantages of wider write weight range, stronger function, more convenient control and higher circuit safety.

Description

Read-write method and system for batch write-in of forgetting memory bridge cross architecture

Technical Field

The invention relates to the field of forgetting memory resistance bridges, in particular to a read-write method and a read-write system for writing forgetting memory resistance bridge cross architectures in batches.

Background

The weights set by synapses of a traditional memristive bridge are single long-term memory weights, and the long-term memory weights and the short-term memory weights of synapses of a traditional memristive bridge are caused by the long-term memory characteristics of the forgetting memristive bridge, and the two types of weights work at different times, so that the forgetting synapses have more powerful functions under the same structure; on the other hand, the short-time memory weight is automatically switched to the long-time memory weight through time change, and no signal needs to be added, so that the power consumption of the system cannot be increased by forgetting the synapse of the memristive bridge. Compared with the synapse of a traditional memristor bridge, the synapse of the forgetting memristor bridge has higher application value, single forgetting memristor synapses, series forgetting memristor synapses, independent write-in forgetting memristor synapses and batch write-in forgetting memristor synapses can only represent positive weights, independent write-in forgetting memristor synapses are complex in circuit structure and are not suitable for constructing a large-scale memristor cross architecture, batch write-in forgetting memristor bridge synapses have the highest requirement on the characteristics of memristors, but can represent positive weights, negative weights and zero weights, the circuit structure is simple, control is facilitated, and the circuit structure is more suitable for large-scale integrated batch write-in forgetting memristor bridge cross architectures.

The cross architecture is a basic structure of the memory, and the memory architecture represented by the memristor is one of important breakthrough directions of the novel memory. Different types of memristors and combinations among the memristors can form various memristive cross architectures, but the corresponding control modes are different. At present, most memristor cross structures are concentrated on nonvolatile memristors, namely only long-term memory exists, and the read-write of the memristor cross structures with the long-term memory and the short-term memory simultaneously is less. The prior design of the memristor cross architecture with long-time and short-time memory switching adopts two memristor cross architectures to respectively correspond to long-time memory and short-time memory, then adopts a switching controller to realize the switching between the two memristor cross architectures corresponding to the long-time memory and the short-time memory, and does not control the long-time and short-time memory of a memristor. Compared with the prior art, the method has the advantages that the long-term memory weight and the short-term memory weight are written into one memristor cross framework simultaneously, automatic switching is carried out, devices and energy consumption are saved, and the characteristic of writing the forgetting memristor bridge in batches can be fully utilized. However, the long-term memory weights written into the forgetting memristive bridges in batch are various, so that the reading and writing of the long-term memory weights are more complicated, and how to simultaneously read and write the random long-term memory weights of a plurality of memristive bridges written into the forgetting memristive cross architecture in batch are not interfered with each other, so that no corresponding scheme exists at present.

Disclosure of Invention

In order to overcome the defects in the prior art, the invention aims to provide a read-write method and a read-write system for writing a forgetting memristive bridge cross architecture in batches.

In order to achieve the above object, the present invention provides a read/write method for batch writing of a forgetting memory bridge cross architecture,

adopting a batch write-in forgetting memristor bridge to construct a memristor cross architecture, wherein input signals of the memristor cross architecture comprise row signals and column signals;

the row signals are used for determining a selected row and a non-selected row, the selected row and the non-selected row are connected with different write signals, the voltage of a memristor bridge on the selected row is higher than a set threshold value, and the voltage of the memristor bridge on the non-selected row is lower than the set threshold value;

and memorizing positive and negative weight values and zero weight values for the short and long write-in time of the memristor bridge in the selected row according to the duty ratio of the column signal, and performing circuit protection on the unselected rows.

According to the read-write method for batch write-in of the forgetting memristor bridge cross architecture, selected rows and unselected rows are distinguished through signals, row signals and column signals are combined to initialize memristors and reset weights to set the weights in batches, and the fast setting of the batch write-in of the forgetting memristor bridge cross architecture weights is achieved.

The preferred scheme of the read-write method for batch write of the forgotten memristor bridge cross architecture is as follows: designing a staff signal as an input signal, and writing a long-term memory weight and a short-term memory weight of the memristor cross architecture;

when writing, the positive weight value and the negative weight value are separately written, and each staff writing signal comprises eight time slices: a positive long-term memory initialization time slice, a positive long-term memory setting time slice, a negative long-term memory initialization time slice, a negative long-term memory setting time slice, a positive short-term memory initialization time slice, a positive short-term memory setting time slice, a negative short-term memory initialization time slice, and a negative short-term memory setting time slice;

the staff signals comprise a line staff writing signal and a column staff writing signal;

the line-five-line spectrum writing signals are five lines of line positive long-time threshold Vthl, line positive short-time threshold Vths, line 0, line negative short-time threshold-Vths and line negative long-time threshold-Vthl;

the column staff spectrum writing signals are five lines including a column positive long-time threshold Vtl, a column positive short-time threshold Vts, a column 0, a column negative short-time threshold-Vts and a column negative long-time threshold-Vtl;

the write signal of each memristive bridge in the memristive cross architecture in eight time slices is: in the time slices corresponding to the eight time slices, subtracting a column staff writing signal of a column where the current memristive bridge is located from a row staff writing signal of the current memristive bridge, wherein the duty ratio is based on the duty ratio of the column staff writing signal.

In the preferred scheme, the staff signals can realize the batch writing of positive, negative and zero-time memory weights and short-time memory weights of the forgotten memory resistance bridge cross structure, and the batch writing of the forgotten memory resistance bridge cross structure is more convenient to control and has higher circuit safety.

Preferably, the signal amplitudes corresponding to eight time slices of the staff-to-staff spectral write signal of the selected row are respectively: vths, vthl, -Vthl, -Vthl, vthl, vths, -Vths, -Vths, vths; the signal amplitudes corresponding to eight time slices of the WV signal of the unselected row are: 0, -Vths, vths, vths, -Vths, -Vths, vths, vths, -Vths;

the eight time slices of the row-staff spectrum write signal are divided into four types according to the write-in long-time memory weight value, (1) when the long time is a positive weight value, and when the short time is also a positive weight value, the eight time slice signals are respectively: -Vtl,0 with duty cycle dl, -Vts, 0 with duty cycle ds; (2) When the long time is a positive weight and the short time is a negative weight, the eight time slice signals are respectively: -Vtl, vtl with duty cycle dl, 0, vts with duty cycle ds; (3) The long time is a negative weight, the short time is a positive weight, and the eight time slice signals are: 0, vtl, -Vts with a duty cycle of dl, vts with a duty cycle of ds, 0; (4) When the long time is a negative weight and the short time is also a negative weight, the eight time slice signals are: 0, vtl, duty cycle dl-Vtl, 0, vts, duty cycle ds-Vts.

Preferably, when the positive long-term memory weight is written, all the memory time memories of the memristive bridge are initialized to 1; the long-term memory of the memristor bridge of the selected middle row is written into a corresponding resistance value through the duty ratio of the row-to-staff spectrum writing signal, the setting of the long-term memory of all the selected middle rows is completed, and the unselected middle rows are protected;

when the negative long-term memory weight is written, initializing long-term memory of all memristors to-1; writing the long-term memory of the selected row memristor bridge into a corresponding resistance value through the duty ratio of the row-staff spectrum write signal to complete the setting of the long-term memory of all the selected rows, and protecting the unselected rows;

when the positive short-time memory weight is written, initializing all the short-time memories of the memristors to 1; the short-time memory of the selected row memristor bridge is written into a corresponding resistance value through the duty ratio of the row-to-staff spectrum write signal, the setting of the short-time memory of all selected rows is completed, and unselected rows are protected;

when the negative short-time memory weight is written, initializing all the short-time memories of the memristors to-1; and writing the short-time memory of the selected row memristor bridge into the corresponding resistance value through the duty ratio of the row-to-staff spectrum write signal to complete the setting of the short-time memory of all the selected rows, wherein the unselected rows are protected.

The preferred scheme of the read-write method for batch write-in of the forgotten memristor bridge cross architecture is as follows: the amplitude of the unselected row circuit signal satisfies | Vtl-Vths | < | Vths |.

The preferred scheme of the read-write method for batch write of the forgotten memristor bridge cross architecture is as follows: the staff signals also comprise line staff reading signals and column staff reading signals, the line staff reading signals of the selected lines are Vths, the line staff reading signals of the non-selected lines are 0, the column staff reading signals are 0, time slices corresponding to the line staff reading signals are before or after the eight time slices, time slices corresponding to the column staff reading signals are before or after the eight time slices, and the time slices corresponding to the line staff reading signals are the same as the time slices corresponding to the column staff reading signals. The addition of the read signal is convenient for knowing the weight of a memristor bridge in the current memristor cross architecture.

The invention further provides a reading and writing system for writing the forgotten memristor bridge cross architecture in batch, which comprises a processing unit and a storage unit, wherein the processing unit is in communication connection with the storage unit, a control signal output end of the processing unit is connected with a voltage source control end of the forgotten memristor bridge cross architecture, the storage is used for storing at least one executable instruction, and the executable instruction enables the processing unit to execute the operation corresponding to the reading and writing method for writing the forgotten memristor bridge cross architecture in batch.

The invention has the beneficial effects that:

the method not only can realize the writing of memorizing the positive and negative weight and the zero weight when the forgetting memory bridge cross architecture is written in batch, but also can lead the batch writing of the forgetting memory bridge cross architecture to be more convenient to control and has higher circuit safety.

The method adopts a time slot technology to finish batch reading and writing of a batch write-in forgetting memristor bridge cross framework, selects rows and non-selected rows through signal distinguishing, combines row signals and column signals of the selected rows to carry out initialization and weight resetting of memristors to set weights in batches, and the memristors on the non-selected rows also have voltage signals but are all lower than a threshold value, so that a protection function is realized, the safety of the cross structure is improved through circuit protection signals, and the method is particularly suitable for a nanoscale circuit.

The invention can be applied to a neural network, can realize a debit network and a native network on the same framework, and realizes two corresponding modes of quick response and slow response.

Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.

Drawings

The above and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:

FIG. 1 is a schematic diagram of a batch write forget memristive bridge architecture;

FIG. 2 is a schematic diagram of a batch write forget memristive bridge control pulse signal;

FIG. 3 is a schematic diagram of an erroneous reverse protection signal corrupting an unselected row;

FIG. 4 is a diagram of memristor symbol correspondence in a batch write-in forgetting memristor bridge cross architecture;

FIG. 5 is a diagram of a forgotten memristive bridge crossover architecture and write timing diagram;

FIG. 6 is a neural network write timing diagram based on a forgetting memristive bridge;

FIG. 7 is a diagram showing the result of fast response of an input face test picture in a BP neural network as emotion;

FIG. 8 is a schematic diagram of the result of a human face in a slow response of an input human face test picture in a BP neural network;

fig. 9 is a graph showing the recognition rate of the debit network and the native network as a function of the decay time.

Detailed Description

Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention and are not to be construed as limiting the present invention.

In the description of the present invention, unless otherwise specified and limited, it is to be noted that the terms "mounted," "connected," and "connected" are to be interpreted broadly, and may be, for example, a mechanical connection or an electrical connection, a communication between two elements, a direct connection, or an indirect connection via an intermediate medium, and specific meanings of the terms may be understood by those skilled in the art according to specific situations.

The application introduces a weight writing method for writing forgetting memristor bridges in batches, wherein the batch writing of the forgetting memristor bridges is based on the batch writing of the forgetting memristors of a current sourceA bridge having a long-term memory resistance change part Δ M _L And short-term memory resistance change part Δ M _S Equal to the duty cycle of the input voltage signals v1 and v 2.

As shown in fig. 1, parameters of a first forgetting memristor, a second forgetting memristor, a third forgetting memristor and a fourth forgetting memristor in a forgetting memristive bridge are the same, the first forgetting memristor and the second forgetting memristor are reversed, the third forgetting memristor and the fourth forgetting memristor are reversed, and a resistance value of each forgetting memristor is mapped between [0 and 1], wherein a maximum resistance value of each forgetting memristor is mapped to 1, a minimum resistance value is mapped to 0, and resistance values of the first forgetting memristor, the second forgetting memristor, the third forgetting memristor and the fourth forgetting memristor are respectively represented by M1, M2, M3 and M4 and are mapped to values between [0 and 1 ]; because the first forgetting memory resistor and the second forgetting memory resistor are reversed, and the third forgetting memory resistor and the fourth forgetting memory resistor are reversed, M1+ M2=1 can be obtained, and the resistance increment of the first forgetting memory resistor is equal to the resistance decrement of the second forgetting memory resistor.

Forget the voltage division formula of the memristive bridge:

the mathematical relationship between the input and output voltages and the weight of the forgetting memristor bridge is as follows: vout = wVin, forget to remember the weight of the memristor bridge

Since M1= M4 and M2= M3, the weight w of the forgetting memristive bridge can be abbreviated as: w = (M2-M1)/(M1 + M2).

When M2 is greater than M1, the weight value is positive, when M2 is less than M1, the weight value is negative, and the demonstration of weight value table is enclosed in [ -1,1]In the meantime. Since M1+ M2=1 and the portion of M1 that increases is equal to the portion of M2 that decreases, the change Δ w in the long-term memory and short-term memory weights of the forgetting-memory-resistive bridge is changed according to the formula w = (M2-M1)/(M1 + M2) _L And Δ w _s Can be written as:

ΔM _L and Δ M _S For the first forgetting memristor/firstAnd the mapping values of the variable quantities of the memory resistance values of the four forgetting memristors and the second forgetting memristor/third forgetting memristor are memorized at long and short times. According to this formula, Δ M by setting a single memristor _L And Δ M _S To set the long and short time memory weight w of the forgotten memory resistance bridge _L And w _s While the resistance of a single memristor may be through v ₁ And v ₂ The setting is carried out, so that the memristor bridge can be controlled only by integrating voltage pulse signals with different amplitudes at the Vin end.

In order to set the resistances of all the forgetting memristors in the forgetting memristor bridge in batch, the limitation that the short-time memory of the forgetting memristors is cancelled must be smaller than the long-time memory is cancelled, that is, the short-time resistance converges to the long-time resistance no matter what the value of the long-time resistance is. The long-term memory resistance differential equation of the current source memristor model is as follows: dM _L ＝k _L sign(i ₁ )i ₁ ^2,if i ₁ >i _th ；

The short-time memory resistance differential equation is adjusted as follows:

in this model, M is the number of memory cells in which a short-term memory is greater than a long-term memory _S Attenuation of M _L When the short-term memory is less than the long-term memory, M _S Increase to M _L 。

For this type of memristive bridge, all memristors in the memristive bridge are set in batches through the input voltage signal Vin. Because the parameters of the four memristors in the memristive bridge are the same, the directions of the first forgetting memristor/fourth forgetting memristor and the directions of the second forgetting memristor/third forgetting memristor are opposite, the current flowing through each memristor is the same, and the resistance of the memristor is mapped into the range of [0,1], so that M1+ M2=1 is always kept unchanged. The input voltage signal Vin adopts a pulse signal with a fixed amplitude, which means that the current flowing through the memristor is in a fixed proportion to the input voltage signal Vin, and as the resistance of M1+ M2 is mapped to 1, which is equivalent to that the current of the memristor is equal to the input voltage signal Vin in value, the resistance of the memristor can be directly rewritten through a voltage source signal, and the control of the weight of the memristor bridge is realized.

When i1= Vin = v1, the long-term memristive change value of the memristor may be written as: Δ M _L ＝k _L sign(v ₁ )v ₁ ^2t；

When i2= Vin = v2, the memristor short-time memristor change value may be written as:

t is the pulse duration, which is determined by the duty cycle. Normally, the value changes when the external voltage signal v1 or v2 acts

As small as negligible, the short-time memristance may be approximated as: Δ M _s ＝k _s sign(v ₂ )v ₂ ^2t。

The long-time and short-time resistance of a single memristor can pass through v ₁ And v ₂ The setting is performed. Therefore, control over the forgotten memristor bridge can be achieved only by integrating Vin voltage pulse signals with different amplitudes. Initializing a long-time memory resistance value and a short-time memory resistance value of each forgetting memristor in the forgetting memristor bridge according to the reset mode, initializing a positive weight and a 0 weight of the forgetting memristor bridge to be 1, and initializing a negative weight to be-1;

according to the obtained change relation between the weight variation of the forgetting memory resistor bridge and the resistance variation of the forgetting memory resistor:

and a long-term memory resistance change value formula delta M according to the memristor _L ＝k _L sign(v ₁ )v ₁ Formula for memorizing resistance change value in short time for ^2t and memristor

The calculated mapping value delta M of the long-time memory resistance value variation of the memristor corresponding to the memory weight variation delta wl and the memory weight variation delta ws of the forgetting memristor during the bridge length _L Short-term memristor change of and forgetting memristorMapped value of quantity Δ M _S The action time of a required voltage signal, the positive and negative directions of the signal are determined according to the change of the weight value, the duty ratio of a write-in signal is determined according to the action time, and the long-term memory weight value and the short-term memory weight value of the forgetting memory resistance bridge reach corresponding target weight values based on the positive and negative directions and the duty ratio of the write-in signal. And the long-time memory voltage reset signal and the short-time memory voltage reset signal sequentially pass through the Vin end to act on all the memristors, and the long-time memory resistors and the short-time memory resistors of all the memristors are set as target values, so that the required long-time memory weight is obtained. For the synapse of the forgetting memristive bridge, the long-time memory and the short-time memory of four memristors in the memristive bridge can be set together, so that the control of the long-time memory weight value and the short-time memory weight value is more convenient.

The memristor settings are the same as above. Although the memristive bridge is a current source model, since the current flowing through the memristor is equal to the voltage in value, we can also utilize Δ M through the port Vin _l And Δ M _s And the resistance value of a memristor in the memristive bridge is controlled in a mode of being equal to the duty ratio of the input voltage signals v1 and v 2.

In order to facilitate the uniform setting of the weights, the long-term memory resistance value and the short-term memory resistance value corresponding to each memristor are set together as a group of weights, and the weights are called as reset signals. The reset signals are divided into two types, namely a long-time memory reset signal and a short-time memory reset signal, the long-time memory reset signal adopts a high voltage v1 which is larger than a threshold value, the unit action period is T1, the short-time memory reset signal adopts a low voltage v2 which is smaller than the threshold value, and the unit action time is T2. V1 can make the long-term memory change from the minimum resistance to the maximum resistance in the unit period T1, and v2 can make the short-term memory change from the minimum resistance to the maximum resistance in the unit period T2. The T1 and the T2 are used as fixed pulse periods, so that the setting of different memristor weights can be synchronously controlled. All reset signals comprise two parts, the first part is an initialization signal, the long-time memory or the short-time memory of the memristor is initialized, a positive weight and a 0 weight are initialized to be 1, a negative weight is initialized to be-1, the second part is a setting signal, and the long-time memory or the short-time memory is set to a corresponding weight according to the duty ratio of a voltage signal designed by a corresponding long-time and short-time target weight. Because v1> v2, the long-time memory is reset firstly, the short-time memory is reset later, after the v1 is used up, the subsequent short-time memory voltage v2 can reinitialize the short-time memory, and the v2 cannot influence the long-time memory because the amplitude is smaller than the long-time memory threshold. Between the set long-time memory resistance values, the memory resistor is firstly in a short-time memory resistance state, the short-time memory resistance changes into a long-time memory resistance along with time change, and the memory resistor does not change along with time after reaching the long-time memory resistance state, but can return to the short-time memory resistance state again through a short-time memory reset signal.

Setting two groups of target weights for comparison, setting a long-term memory change constant k in a memristor model by taking mA and mus as standard units _l ＝10 ^-5 Memory change constant k in short time _s ＝10 ^-2 Taking voltage source signal v ₁ =100mV, unit period T1 being 10 μ s, v ₂ =10mV, unit period T2 is 1 μ s.

A first group: the long-time memory target weight is 0.2, and the short-time memory target weight is 0.5;

second group: the long-term memory target weight is 0.1, and the short-term memory target weight is-0.1.

When setting up the first group, according to the formula

To obtain

Δw _l 0.2 in the =0.2-1 is a long-term memory target weight, 1 is an initialized positive weight, 0.2-1 is a variation of a memory weight of the forgetting memory resistance bridge in a long term, and the Δ w is obtained by the same method _s =0.5-1, further according to Δ M _L ＝k _L sign(v ₁ )v ₁ T =4 μ s calculated from ^2T, Δ M since the period T1 is 10 μ s _l1 The duty ratio of the write signal corresponding to = -0.4 is 0.4, and the Δ M is obtained in the same way _s1 Write signal duty cycle of 0.25, where Δ M corresponds to = -0.25 _L1 And Δ M _S1 The negative sign in the graph represents that the resistance value is reduced to obtain the write-in signal amplitude of the first group of weightsThe value and duty cycle are in turn (v) ₁ ，1)(-v ₁ ，0.4)(v ₂ ，1)，(-v ₂ 0.25) as shown in fig. 2.

Similarly, when setting the second group, the formula is based on

To obtain

Δ M herein _L1 The negative sign of the inner indicates a decrease in resistance, Δ M _S1 The positive sign inside indicates an increase in resistance. The amplitude and duty ratio of the control signal of the second group of weights are sequentially (v) ₁ ，1)，(-v ₁ ，0.45)，(-v ₂ ，1)，(v ₂ 0.45), as shown in fig. 2.

Comparing the two sets of target weights, Δ M can be known _L And Δ M _S Are respectively equal to the input voltage signal v ₁ And v ₂ The duty cycle of (c).

Considering the sensitivity of a nanometer circuit environment, the invention provides an embodiment of a reading and writing method for writing forgetting memory-resistance bridge cross architecture in batch, and a specific voltage signal is designed for the forgetting memory-resistance bridge cross architecture to perform circuit protection and reading and writing. Adopting a batch write-in forgetting memristor bridge to construct a memristor cross architecture, wherein input signals of the memristor cross architecture comprise row signals and column signals; the row signals are used for determining a selected row and a non-selected row, the selected row and the non-selected row are connected with different write signals, the voltage of a memristor bridge on the selected row is higher than a set threshold value, and the voltage of the memristor bridge on the non-selected row is lower than the set threshold value; and memorizing positive and negative weight values and zero weight values for the short and long write-in time of the memristor bridge in the selected row according to the duty ratio of the column signal, and performing circuit protection on the unselected rows. The threshold value refers to a voltage signal threshold value for changing the resistance value of the memristor, namely, a corresponding voltage threshold value when the long-time resistance or the short-time resistance of the memristor changes.

In this embodiment, a staff signal is designed to write the long-term memory weight and the short-term memory weight of the memristor cross structure. The staff spectrum signals comprise a row staff spectrum writing signal and a column staff spectrum writing signal, wherein the row staff spectrum writing signal comprises five lines of row positive long-time threshold Vthl, row positive short-time threshold Vths, row 0, row negative short-time threshold Vths and row negative long-time threshold Vthl; the column staff spectrum writing signals are five lines including column positive long-time threshold Vtl, column positive short-time threshold Vts, column 0, column negative short-time threshold-Vts and column negative long-time threshold-Vtl. The two-column line is used to distinguish the column staff spectrum write signal and the output current.

The signal modes of the row staff spectrum write signal of the selected row, the row staff spectrum write signal of the unselected row and the column staff spectrum write signal are different, but the three staff spectrum write signals can be ensured to act on the memristor cross framework together, so that the memristor cross framework performs long-time memory and short-time memory weight write in a row unit, and protects the unselected row.

Each staff signal comprises eight time slices, a positive long-term memory initialization time slice, a positive long-term memory setting time slice, a negative long-term memory initialization time slice, a negative long-term memory setting time slice, a positive short-term memory initialization time slice, a positive short-term memory setting time slice, a negative short-term memory initialization time slice and a negative short-term memory setting time slice. Different time slices finish different types of data operation, and the duty ratio d in the column signal controls the writing weight value.

In the present embodiment, the staff signals further include a row staff reading signal and a column staff reading signal, which are used for reading the long-term memory weight and the short-term memory weight of the memristor cross-bar architecture. The line staff reading signal of the selected row is Vths, the line staff reading signal of the non-selected row is 0, the column staff reading signal is 0, the time slice corresponding to the line staff reading signal is before or after the eight time slices, the time slice corresponding to the column staff reading signal is before or after the eight time slices, and the time slice corresponding to the line staff reading signal is the same as the time slice corresponding to the column staff reading signal. The method realizes that the memristor cross architecture reads and writes in a row unit, the resistance value of the memristor is read by adopting a uniform read signal, and the long-time memory weight value and the short-time memory weight value are respectively written by adopting different signals. Determination of selected and non-selected rows by different WV spectral write signalsThe resistance value is written through the column staff spectrum writing signal, the resistance value corresponds to the duty ratio of the column staff spectrum writing signal on different time slices, different writing signals are connected with the selected row and the unselected rows, the voltage which is finally acted on the memristor of the selected row is higher than the threshold value, and the voltage of the unselected rows is lower than the threshold value. In this embodiment, resistance values are written into a selected row in a row unit according to the weight value writing method for writing the forgetting memory resistance bridges in batches, specifically, action time of a voltage signal required by resistance value variation of the memristor corresponding to the length memory weight variation of the forgetting memory resistance bridges is calculated based on a memristor length memory resistance differential equation, positive and negative directions of a writing signal are determined according to the variation of the weight values, duty ratio of the writing signal is determined according to the action time, the required signal is set in a time slice corresponding to a staff spectrum row and column signal, and long-term memory weight values and short-term memory weight values of the forgetting memory resistance bridges both reach corresponding target weight values. The signals higher than the threshold value realize the write operation, the signals lower than the threshold value carry out the circuit protection, the corresponding processing and change are carried out on the write signal according to the difference of the forgetting devices forming the memristor cross framework, and the attention needs to be paid here that when the memristor bridge forms the memristor bridge cross framework, the output signal is the voltage signal V output by the double ports _AB The current signal I needs to be converted into a current signal I output by a single port through a mirror circuit _AB As shown in fig. 4, the batch write-in forgetting memristor bridge cross structure has a double-row structure, one row line Out is used for current output, the other row line is used for column staff signal input, for the batch write-in forgetting memristor bridge, only one signal port of Vin is provided, and the final signal of Vin is the difference value of two staff signals of the row and column. As shown in fig. 5, a staff spectrum read-write signal of an LSM memristor cross architecture is shown, the duty ratio of the signal is default to 1, and the signal amplitudes corresponding to eight time slices of the staff spectrum write signal of the selected row are respectively: vthl, -Vthl, -Vthl, vthl, vths, -Vths, -Vths, vths, wherein the amplitude of the signal corresponding to the time slice of the row staff spectrum reading signal of the selected row is Vths, and the time slices corresponding to the row staff spectrum reading signal and the column staff spectrum reading signal are in the read-write of the LSM memristor cross frameworkBefore the eight time slices, the signal amplitudes corresponding to nine time slices of the row-to-row staff spectrum signal of the selected row are Vths, vthl, -Vthl, -Vthl, vthl, vths, -Vths, -Vths, vths respectively; the signal amplitudes corresponding to eight time slices of the WV signal of the unselected row are: -Vths, vths, vths, -Vths, -Vths, vths, vths, -Vths; the signal amplitude corresponding to the time slice of the row staff spectrum reading signal of the non-selected row is 0, so the signal amplitudes corresponding to the nine time slices of the row staff spectrum signal of the non-selected row are: 0, -Vths, vths, vths, -Vths, -Vths, vths, vths, -Vths;

at this time, the row staff signal also includes row staff read signal and row staff write signal, so the row staff signal also corresponds to nine time slices, the nine time slice signals are divided into four kinds according to the write-in time memory weight value, (1) when the long time is positive weight value, and when the short time is positive weight value, the nine time slice signals are respectively: 0, -Vtl, vtl with duty cycle dl, 0, -Vts, vts with duty cycle ds, 0; (2) When the long time is a positive weight and the short time is a negative weight, the nine time slice signals are: 0, -Vtl, vtl with duty cycle dl, 0, vts, and-Vts with duty cycle ds; (3) The long time is a negative weight, the short time is a positive weight, and the nine time slice signals are: 0, vtl, -Vts with a duty cycle dl, vts,0 with a duty cycle ds; (4) When the long time is a negative weight and the short time is also a negative weight, the nine time slice signals are: 0, vtl, -Vtl with a duty cycle of dl, 0, vts, and-Vts with a duty cycle of ds. Signals in the middle of the batch write-in forgetting memristor bridge cross framework are also signals finally acting on the Vin end of each batch write-in forgetting memristor bridge. The method comprises the following specific steps: (1) The long time is positive weight, the short time is also positive weight, and nine time slice signals in the selected row are respectively: vths, vthl + Vtl, -Vthl, vthl, vths + Vts with a duty cycle dl, -Vths-Vts, -Vths, vths with a duty cycle ds; nine time slice signals of the unselected row are respectively: 0, -Vths + Vtl, vths-Vths, -Vths, -Vths + Vts of duty cycle dl, vths-Vts, vths, -Vths of duty cycle ds; (2) The long time is a positive weight, the short time is a negative weight, and nine time slice signals in the selected row are as follows: vths, vthl + Vtl, vthl-Vthl, vthl, vths, -Vths, -Vths with a duty cycle dl, vths + Vts with a duty cycle ds; nine time slice signals of the unselected row are respectively: 0, -Vths + Vtl, vths-Vtl with a duty cycle of dl, vths, -Vths, -Vths, vths, vths-Vts, and-Vths + Vts with a duty cycle of ds; (3) The long time is a negative weight, the short time is a positive weight, and nine time slice signals in the selected row are as follows: vths, vthl, -Vthl, -Vthl-Vtl, vthl + Vtl with a duty cycle of dl, vths + Vts, vths-Vts, -Vths, vths with a duty cycle of ds; nine time slice signals of the unselected row are respectively: 0, -Vths, vths, vths-Vtl, -Vths + Vtl with a duty cycle of dl, vths-Vts, vths, -Vths with a duty cycle of ds; (4) The long time is a negative weight, the short time is also a negative weight, and nine time slice signals in the selected row are as follows: vths, vthl, -Vthl, -Vthl-Vtl, vthl + Vtl with a duty cycle of dl, vths, -Vths, -Vths-Vts, vths + Vts with a duty cycle of ds; nine time slice signals of the unselected row are respectively: 0, -Vths, vths, vths-Vtl, -Vths, vths-Vts with a duty cycle of dl, -Vths, vths-Vts, and-Vths + Vts with a duty cycle of ds.

Specifically, when the positive long-term memory weight is written, all the memory time memories of the memristive bridge are initialized to 1; the long-term memory of the memristor bridge of the selected middle row is written into a corresponding resistance value through the duty ratio of the row-to-staff spectrum writing signal, the setting of the long-term memory of all the selected middle rows is completed, and the unselected middle rows are protected;

To avoid rewriting the reverse long-term protection voltage in the reverse initialization time slice for short-term memory, as shown in fig. 3, the amplitude of the unselected row circuit signal needs to satisfy | Vtl-Vths | < | Vths |.

Here we set the thresholds for the spectral lines of the staff signal to:

v1＝Vthl+Vtl＝100mV，Vthl＝90mV，Vt1＝10mV，

v2＝Vths+Vths＝10mV，Vths＝7mV，Vts＝3mV。

if the above-mentioned setting example of the memristive bridge weights is two forgetting memristive bridge weights that need to be written together in the same row, then the duty ratio of the corresponding column signal can be obtained according to the calculation result, that is, the first group: the long-term memory target weight is 0.2, the short-term memory target weight is 0.5, and the amplitude and duty ratio of the write signal are (v) ₁ ，1)(-v ₁ ，0.4)(v ₂ ，1)，(-v ₂ 0.25), the case where both the long term weight and the short term weight are positive weights is satisfied, and dl =0.4 and ds =0.25, therefore, the corresponding column staff signal should be: 0, -Vtl, vtl with a duty cycle of 0.4, 0, -Vts, vts with a duty cycle of 0.25, 0; . Second group: the long-term memory target weight is 0.1, the short-term memory target weight is-0.1, and the amplitude and duty ratio of the write signal are (v) ₁ ，1)，(-v ₁ ，0.45)，(-v ₂ ，1)，(v ₂ 0.45), the case that the long-term weight is a positive weight and the short-term weight is a negative weight is satisfied, and dl =0.45 and ds =0.45, therefore, the corresponding column staff signal should be: 0, -Vtl, vtl with a duty cycle of 0.45, 0, vts, and-Vts with a duty cycle of 0.45.

In combination with the voltage signals acting on each memristive bridge by each time slice of the row-column staff in the batch write-in forgetting memristive bridge cross architecture in fig. 5, that is, the input signals of the final Vin end, the signals corresponding to the first group should be: the signals of nine time slices in the selected row are respectively as follows: vths, vthl + Vtl, -Vthl, vthl, vths + Vts with a duty cycle of 0.4, -Vths-Vts, -Vths, vths with a duty cycle of 0.25; nine time slice signals of the unselected row are respectively: 0, -Vths + Vtl, vths-Vtl with a duty cycle of 0.4, vths, -Vths, -Vths + Vts, vths-Vts with a duty cycle of 0.25, vths, -Vths; the corresponding signals should be: the signals of nine time slices in the selected row are: vths, vthl + Vtl, duty cycle 0.45-Vthl-Vtl, -Vthl, vthl, vths, -Vths, -Vths, duty cycle 0.45 Vths + Vts; nine time slice signals of the unselected row are respectively: 0, -Vths + Vtl, vths-Vtl with a duty cycle of 0.45, vths, -Vths, -Vths, vths, vths-Vts, and-Vths + Vts with a duty cycle of 0.45. The specific parameters are: the first set of corresponding signals should be: the nine time slice signals of the selected part are respectively as follows: 90 100, -100, 90, 10 with a duty cycle of 0.4, -10, -7,7 with a duty cycle of 0.25; nine time slice signals of the non-selected part are respectively as follows: 0,3, -3,7, -7, -4 with a duty cycle of 0.4, 4,7, -7 with a duty cycle of 0.25; the second set of corresponding signals should be: the nine time slice signals in the selected part are: 7,100, duty cycle of-100, -90,90,7, -7, -10, duty cycle of 10 of 0.45; nine time slice signals of the unselected row are respectively: 0,3, duty cycle of-3, 7, -7, 4 of 0.45, duty cycle of-4 of 0.45. The threshold characteristic of the forgetting memristor model is combined, independent writing of positive and negative weights can be guaranteed, and mutual interference is avoided.

Since the memristor is a basic element forming the memristor bridge cross architecture, the characteristics of the memristor bridge cross architecture can directly influence the read-write circuit of the memristor bridge cross architecture. Therefore, according to the characteristics of the memristor, the read-write circuit of the memristor bridge cross architecture can be correspondingly adjusted and changed. For the characteristics of the current physical memristor, when the long-term memory of a single memristor is a fixed value Roff, the short-term memory is an arbitrary value, and then only the short-term memory of the positive weight can be written, so that only two write time slices of the staff write signal are needed, the positive weight is initialized for the short-term memory, and the positive weight is set for the short-term memory. When the long-term memory of a single memristor is any high resistance value larger than the short-term memory, the short-term memory and the long-term memory of the positive weight value can be read and written, the short-term memory and the long-term memory weight value can be set, but the long-term memory resistance value is always ensured to be higher than the short-term memory resistance value, so that four writing time slices are available, the positive-weight long-term memory is initialized, the positive-weight long-term memory is set, the positive-weight short-term memory is initialized, and the positive-weight short-term memory is set. If there is no limitation between the sizes of the long and short term memory weights, the writing processes of the long and short term memory weights are independent of each other, and as described above, the memristor bridge constructed based on the memristor has the widest range when expressing the long and short term memory weights.

The application of the batch write forgetting memristor bridge cross architecture read-write method in the neural network is described below.

In the neural network, the connection between the neurons corresponds to a weight matrix, and most weight matrices of the neural network comprise both positive weights and negative weights, so that the weight matrix is represented by a memristor cross architecture based on a memristor bridge, the weight matrix can be set to any value, the input and output of the neurons and the reading and writing of the weight matrix are respectively listed in different rows and columns, and the current directions are controlled by double transistors, so that the training and the testing of the network can independently run, as shown in fig. 6, the working voltage of the neural network is set to be between-1 mV and +1mV, which is smaller than the minimum writing signal of short-term memory and long-term memory of a forgetting memristor, and due to the threshold characteristic of the memristor bridge, the working of the neural network and the long-term memory writing of the memristor bridge are not interfered with each other. The memory resistance cross framework is arranged to store the long-term memory template and the short-term memory template, when the long-term memory template is equal to the long-term memory template, the effect of the neural network based on the forgetting memory resistance bridge is the same as that of the traditional neural network, and when the long-term memory template and the forgetting memory template are different, the neural network shows two modes of short-term memory and long-term memory. The short-term memory mode automatically changes to the long-term memory mode along with the lapse of time, and the required time is determined by the decay speed. The short-time memory mode does not interfere with the long-time memory mode, so that the neural network based on the forgetting memory resistance bridge can operate two different neural networks on the same network hardware.

The short-term memory network is regarded as a debit network, and the long-term memory network is a native network. When the native network is idle, the network resources are borrowed to other networks, and the borrowing network cannot damage the native network because the long-term memory and the short-term memory are not interfered with each other. For the borrowed network, as long as hardware support is provided, input and output can be different from the original network, but the longer the borrowed time is, the worse the operation effect of the borrowed network is. Although the loss can be reduced by adjusting the decay rate, the resource borrowing is accompanied by a certain performance loss compared with the original network.

In the text, a BP neural network is adopted, and face and emotion recognition is carried out by utilizing an ORL database. Corresponding emotion recognition is memorized in short time, two emotions of happy emotion and non-happy emotion are recognized, and 50 sample pictures of the two emotions are respectively displayed. The long-term memory corresponds to face recognition, 40 persons are recognized, and 10 sample pictures of each person are obtained. The emotion recognition network is a debit network, and the face recognition network is a native network. The trained network inputs a face test picture, fast response is emotion, the output result is happy, as shown in fig. 7, slow response is face, the output result is to identify the person who is, as shown in fig. 8, the two are combined, and the final conclusion is that someone who is happy. In the training phase, the short-time memory decay effect is negligible because the memristive crossbar architecture is continuously written. In the testing stage, the memristor cross architecture stops writing, but the corresponding weight of the memristor cross architecture gradually changes due to the attenuation effect. For synapses without short-term memory output weight in the face recognition network, default short-term memory output weight is 0, f of all synapses is set to be 0.02, and the change of the recognition rate of the debit network and the native network with time is shown in fig. 9. The recognition rate of the debit network gradually decreases with time from 93% of the conventional network to 37% of the chaotic state, while the recognition rate of the native network gradually increases with time from 2.5% of the chaotic state to 97.75% of the conventional network and remains stable.

The application also provides a read-write system for writing in the forgotten memristive bridge cross architecture in batch, which comprises a processing unit and a storage unit, wherein the processing unit is in communication connection with the storage unit, a control signal output end of the processing unit is connected with a voltage source control end of the forgotten memristive bridge cross architecture, the storage is used for storing at least one executable instruction, and the executable instruction enables the processing unit to execute the operation corresponding to the read-write method for writing in the forgotten memristive bridge cross architecture in batch.

In the description of the specification, reference to the description of "one embodiment," "some embodiments," "an example," "a specific example," or "some examples" or the like means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

While embodiments of the present invention have been shown and described, it will be understood by those of ordinary skill in the art that: various changes, modifications, substitutions and alterations can be made to the embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.

Claims

1. A read-write method for batch write-in of forgetting memory bridge cross architecture is characterized in that,

the method comprises the steps that a memristor cross architecture is constructed by writing a forgetting memristor bridge in batches, and input signals of the memristor cross architecture comprise row signals and column signals;

the row signals are used for determining a selected row and a non-selected row, the selected row and the non-selected row are connected with different write signals, the voltage of a memristive bridge on the selected row is higher than a set threshold, and the voltage of the memristive bridge on the non-selected row is lower than the set threshold;

2. The read-write method for batch write-in of a forgetting memristive bridge cross architecture according to claim 1, characterized in that:

designing a staff signal as an input signal, and writing a long-term memory weight and a short-term memory weight of the memristor cross architecture;

when writing, the positive weight value and the negative weight value are written separately, and each staff writing signal comprises eight time slices: a positive long-term memory initialization time slice, a positive long-term memory setting time slice, a negative long-term memory initialization time slice, a negative long-term memory setting time slice, a positive short-term memory initialization time slice, a positive short-term memory setting time slice, a negative short-term memory initialization time slice, and a negative short-term memory setting time slice;

the staff signal comprises a line staff writing signal and a column staff writing signal;

the line-staff spectrum writing signals are five lines including line positive long-time threshold Vthl, line positive short-time threshold Vths, line 0, line negative short-time threshold-Vths and line negative long-time threshold-Vthl;

the column staff spectrum writing signals are five lines of column positive long-time threshold Vtl, column positive short-time threshold Vts, column 0, column negative short-time threshold-Vts and column negative long-time threshold-Vtl;

3. The read-write method for batch write-in of a forgetting memristive bridge cross architecture according to claim 2, characterized in that:

the signal amplitudes corresponding to the eight time slices of the staff spectrum write signal of the selected row are respectively as follows: vths, vthl, -Vthl, -Vthl, vthl, vths, -Vths, -Vths, vths; the signal amplitudes corresponding to eight time slices of the WV signal of the unselected row are: 0, -Vths, vths, vths, -Vths, -Vths, vths, vths, -Vths;

the eight time slices of the row-staff spectrum write signal are divided into four types according to the write-in long-time memory weight value, (1) when the long time is a positive weight value, and when the short time is also a positive weight value, the eight time slice signals are respectively: -Vtl,0 with duty cycle dl, -Vts, 0 with duty cycle ds; (2) When the long time is a positive weight and the short time is a negative weight, the eight time slice signals are respectively: -Vtl, vtl with duty cycle dl, 0, vts, and-Vts with duty cycle ds; (3) The long time is a negative weight, the short time is a positive weight, and the eight time slice signals are: 0, vtl, -Vts with a duty cycle of dl, vts with a duty cycle of ds, 0; (4) When the long time is a negative weight and the short time is also a negative weight, the eight time slice signals are: 0, vtl, duty cycle dl-Vtl, 0, vts, duty cycle ds-Vts.

4. The method for writing in batch the forgotten memristive bridge cross architecture according to claim 2, wherein when the normal-time memory weight is written, all the long-time memories of the memristive bridges are initialized to 1; writing the long-term memory of the memristor bridge of the selected row into a corresponding resistance value through the duty ratio of the row-staff spectrum writing signal to complete the setting of the long-term memory of all the selected rows, and protecting the unselected rows;

when the negative long-term memory weight is written, initializing long-term memory of all memristors to-1; writing the long-term memory of the selected row memristor bridge into a corresponding resistance value through the duty ratio of a row-to-staff spectrum writing signal to complete the setting of the long-term memory of all selected rows, and protecting unselected rows;

5. The method of claim 2 or 3, wherein the amplitude of the unselected row input signals satisfies | Vtl-Vths | < | Vths |.

6. The method according to claim 2 or 3, wherein the staff signals further include a row staff spectrum read signal and a column staff spectrum read signal, the row staff spectrum read signal of the selected row is Vths, the row staff spectrum read signal of the unselected row is 0, the column staff spectrum read signal is 0, the time slice corresponding to the row staff spectrum read signal is before or after the eight time slices, the time slice corresponding to the column staff spectrum read signal is before or after the eight time slices, and the time slice corresponding to the row staff spectrum read signal is the same as the time slice corresponding to the column staff spectrum read signal.

7. The method for reading and writing a batch-written forgetting memory-resistance bridge cross architecture according to claim 2, wherein when the long-term memory of a single memristor is a fixed value Roff, the short-term memory is an arbitrary value, only the short-term memory of a positive weighting value is written, and only two time slices of a staff write signal are provided: the positive weight value is initialized in short time, and the positive weight value is set in short time.

8. The method for writing in batch a forgotten memristor bridge cross architecture according to claim 2, wherein when the long-term memory of a single memristor is any high resistance value larger than the short-term memory, the short-term memory and the long-term memory of the weight are written on the premise that the long-term memory resistance value is always ensured to be higher than the short-term memory resistance value, and there are four time slices for writing signals in the staff spectrum: initializing the long-term memory of the positive weight, setting the long-term memory of the positive weight, initializing the short-term memory of the positive weight, and setting the short-term memory of the positive weight.

9. A reading and writing system for writing in batch into a forgetting memory bridge cross architecture is characterized by comprising a processing unit and a storage unit, wherein the processing unit is in communication connection with the storage unit, a control signal output end of the processing unit is connected with a voltage source control end of the forgetting memory bridge cross architecture, the storage is used for storing at least one executable instruction, and the executable instruction enables the processing unit to execute the operation corresponding to the reading and writing method for writing in batch into the forgetting memory bridge cross architecture according to any one of claims 1 to 8.