CN115436721A - Test circuit and charger for aging experiment - Google Patents

Abstract

The utility model provides a test circuit and charger for ageing experiments, this test circuit includes: one end of the power device is connected with the power supply end through the connected main switching tube, the other end of the power device is connected with the load end, and the power device and the main switching tube are synchronously switched on or off; the test module is connected to a connection node of the power device and the load end through an inductor and used for simulating an aging period in a charge-discharge process and providing electric energy for the load end; and the positive end of the capacitor is connected with the test module, the negative end of the capacitor is grounded, and the capacitor is used for charging or releasing energy in cooperation with the charging and discharging process of the test circuit. Therefore, the switching of the voltage boosting mode and the voltage reducing mode can be easily realized through the conduction and the disconnection of the main switch tube by the test circuit, the charge and discharge process is simulated, the time of an aging experiment and the required power quantity can be effectively shortened, the operability of the experiment is improved, and the cost is saved and the efficiency is improved.

Description

Test circuit and charger for aging experiment

Technical Field

The disclosure relates to the technical field of integrated circuits, in particular to a test circuit and a charger for an aging experiment.

Background

With the popularity of handheld digital products such as smart phones, tablet computers, digital cameras and the like, the smart devices with large power consumption have promoted products such as fast-charging chargers, mobile power supplies (namely, charge pal), fast-charging mobile power supplies and the like to enter the market. The quick charging technology and the portable power source provide a better solution for the defects of high power consumption and low endurance of the intelligent equipment, can quickly charge a mobile phone, a tablet personal computer, a digital camera battery and the like, are convenient to carry, can be charged along with walking, and are expected to occupy most markets in a short period. Along with the application of the quick-charging products, the aging test problem of the quick-charging charger, the mobile power supply, the quick-charging mobile power supply and other similar products in production is brought, and equipment with quality guarantee, low cost, high efficiency and capability of performing aging test in batches is widely required.

The aging test for these three types of products in the market currently faces a lot of difficulties.

For example, manufacturers use a dc constant voltage power supply to charge a product, and one power supply correspondingly charges one product, such devices have the following disadvantages: the cost is high, the charging time needs manual control, the charging data cannot be conveniently recorded in real time, and the intelligent degree is low.

For example, the actual magnitude of the discharge current and the magnitude of the discharge power cannot be monitored, the discharge speed and efficiency cannot be determined, and the discharge time needs manual timing and manual stopping.

If the electronic load instruments are used for discharging the products, a single load instrument is used for discharging and aging corresponding to a single product, although the magnitude of the discharging and aging voltage and current can be determined, the discharging and aging voltage and current has the disadvantages of high cost and discharging time of a plurality of electronic load instruments when a plurality of products are aged, and low efficiency of manual control and calculation of discharging capacity.

In all three cases, charging and discharging, and automatic conversion between discharging and charging cannot be realized.

In addition, if the quick-charging charger and the quick-charging mobile power supply can only use special instruments to realize quick-charging function test and aging test of voltage boosting and reducing of quick charging, and in the face of various quick-charging technical protocols in the current market, various test instruments are required to be used for aging test, so that the cost is high, and the compatibility is low.

The chip (IC) of the charger generally needs to verify two functions, namely a battery charging mode and a battery discharging mode, the two modes are verified independently, the total time of two aging experiments is long, the number of power supplies is large, the aging tests of the two modes can be carried out simultaneously when the power supplies are enough, batch experiments are needed when the power supplies are insufficient, and the efficiency is low and the device is extremely inconvenient.

Disclosure of Invention

In order to solve the technical problem, the present disclosure provides a test circuit and a charger for an aging test, which can effectively shorten the test time and the number of power supplies and improve the operability of the test.

In one aspect, the present disclosure provides a test circuit for an aging test, the test circuit being connected to a power supply terminal through a main switch tube, wherein the test circuit includes:

the power device is connected between the main switching tube and the load end and is synchronously switched on or off with the main switching tube;

the test module is connected to a connection node of the power device and the load end through an inductor and used for simulating an aging period in a charge-discharge process and providing electric energy for the load end;

and the positive end of the capacitor is connected with the test module, the negative end of the capacitor is grounded, and the capacitor is used for charging or releasing energy in cooperation with the charging and discharging process of the test circuit.

Preferably, the aforementioned power device is one of a field effect transistor and a bipolar transistor.

Preferably, the testing module comprises a first switch tube, a second switch tube and a third switch tube which are connected in series between the positive terminal of the capacitor and the ground,

the first end of the first switch tube is grounded, the second end is connected with the inductor,

the first end of the second switch tube is connected with the connection node of the first switch tube and the inductor,

the first end of the third switch tube is connected with the second end of the second switch tube, and the second end of the third switch tube is connected with the positive electrode end of the capacitor.

Preferably, the control end of the first switch tube is connected to a first control signal, the control end of the second switch tube is connected to a second control signal,

the first switch tube and the second switch tube are alternatively conducted to match the charging and discharging process of the test circuit.

Preferably, the first switch tube and the second switch tube have the same channel type, and the first control signal and the second control signal are opposite phase signals;

or, the channel types of the first switch tube and the second switch tube are opposite, and the first control signal and the second control signal are the same signal.

Preferably, the main switching tube and the power device are both in a closed conduction state, the test circuit works in a boost mode, and the power supply end supplies power to the load end and charges the capacitor at the same time;

the main switching tube and the power device are both in an off state, the testing circuit works in a voltage reduction mode, and the capacitor supplies power to the load end through the inductor through energy release in the discharging process.

Preferably, the aforementioned test circuit further comprises:

and the detection control module is used for detecting the stored electric quantity of the capacitor and adjusting the duty ratio of a control signal accessed by the control end of the main switching tube according to the detection information.

Preferably, the aforementioned power device, the inductance and the aforementioned test module are integrated on the same chip.

In another aspect the present disclosure provides a charger comprising a test circuit as described above.

The beneficial effects of this disclosure are: the present disclosure provides a test circuit and a charger for aging experiments, wherein, the test circuit includes: one end of the power device is connected with the power supply end through the connected main switching tube, the other end of the power device is connected with the load end, and the power device and the main switching tube are synchronously switched on or off; the test module is connected to a connection node of the power device and the load end through an inductor and used for simulating an aging period in a charge-discharge process and providing electric energy for the load end; and the positive end of the capacitor is connected with the test module, the negative end of the capacitor is grounded, and the capacitor is used for charging or releasing energy in cooperation with the charging and discharging process of the test circuit. Therefore, the switching of two modes (boosting and reducing) can be easily realized by switching on and off the main switch tube, the charging and discharging process is completed by utilizing the circuit structure to simulate, compared with the prior art, the aging experiment time and the required power supply quantity can be effectively shortened, the operability of the experiment is improved, and the cost is saved and the efficiency is improved.

Drawings

The above and other objects, features and advantages of the present disclosure will become more apparent from the following description of the embodiments of the present disclosure with reference to the accompanying drawings.

FIG. 1 is a schematic diagram illustrating a test circuit provided by an embodiment of the disclosure;

FIG. 2 is a timing diagram illustrating the operation of various control signals of the test circuit shown in FIG. 1;

FIG. 3 is an equivalent circuit diagram of the charging process of the test circuit of FIG. 1 in boost mode;

FIG. 4 is an equivalent circuit diagram of the discharge process of the test circuit of FIG. 1 operating in buck mode;

fig. 5 is a schematic diagram of a chip with a part of the structure of the test circuit shown in fig. 1 integrated with a charger according to an embodiment of the disclosure.

Detailed Description

To facilitate an understanding of the present disclosure, the present disclosure will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present disclosure are set forth in the accompanying drawings. This disclosure may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used in the description of the disclosure herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure.

The present disclosure is described in detail below with reference to the accompanying drawings.

Fig. 1 shows a schematic structural diagram of a test circuit provided in an embodiment of the present disclosure.

Referring to fig. 1, in one aspect, an embodiment of the present disclosure provides a test circuit 100 for an aging test, taking a charger as an example, where the test circuit 100 is embedded in a charger chip, and in a factory test, for example, a charging and discharging process of a charger in normal use may be simulated by matching with other structures or circuits of an aging test platform, so as to obtain detection data of each signal in the test circuit in the aging test process, and by using the detection data, performance evaluation of the charger may be completed, quality and yield of factory products may be improved, and safety of the factory products may be improved.

The input end of the test circuit 100 is connected to the power supply end through a main switch tube Q1 and is connected to a power supply voltage VB, the control end of the main switch tube Q1 is connected to an enable signal EN, and the enable signal EN is used for controlling the on and off of the main switch tube Q1. Specifically, the test circuit 100 at least includes: a power device Qa, an inductor L, a test module 101 and a capacitor CSTR,

in this embodiment, a control end of the power device Qa is connected to a control signal Sa, and the control signal Sa and the enable signal EN may be, for example, the same pulse signals, as shown in fig. 2, in other alternative embodiments, the high levels of the control signal Sa and the enable signal EN may also be adapted to respective conduction voltages of the power device Qa and the main switch Q1, as long as the same frequency and the same period of the two are satisfied;

the test module 101 is connected to a connection node between the power device Qa and the load end Rload through an inductor L, and is configured to simulate an aging period in a charging and discharging process and provide electric energy for the load end Rload;

the positive terminal of the capacitor CSTR is connected to the test module 101, and the negative terminal is grounded, and the capacitor CSTR is used for charging or releasing energy in cooperation with the charging and discharging process of the test circuit 100.

In a disclosed embodiment, the power device Qa is one of a Field Effect Transistor (FET) and a Bipolar Junction Transistor (BJT).

In a disclosed embodiment, the test module 101 includes a first switch transistor Qb, a second switch transistor Qc and a third switch transistor Qd connected in series between the positive terminal of the capacitor CSTR and the ground, a first terminal of the first switch transistor Qb is grounded, and a second terminal is connected to the inductor L; a first end of the second switch tube Qc is connected to a connection node between the first switch tube Qb and the inductor L; the first end of the third switch tube Qd is connected to the second end of the second switch tube Qc, and the second end is connected to the positive terminal of the capacitor CSTR.

In a further embodiment of the present disclosure, the power device Qa, the first switching tube Qb, the second switching tube Qc, and the third switching tube Qd are all Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), so that the area of the chip can be controlled by a MOS process during production, the integration level is improved, and the miniaturization of the product is facilitated.

In a disclosed embodiment, the control terminal of the first switch tube Qb is connected to the first control signal Sb, and the control terminal of the second switch tube Qc is connected to the second control signal Sc, and in an experiment, the first switch tube Qb and the second switch tube Qc are alternately turned on to match the charging and discharging process of the test circuit 100.

In a disclosed embodiment, the channel types of the first switch tube Qb and the second switch tube Qc are the same, for example, both are N-channel MOS tubes, and the first control signal Sb and the second control signal Sc are opposite phase signals, as shown in fig. 2.

In another disclosed embodiment, the channel types of the first switch tube Qb and the second switch tube Qc may be opposite, for example, the first switch tube Qb is an N-channel MOS transistor, and the second switch tube Qc is a P-channel MOS transistor, so that the first control signal Sb and the second control signal Sc are the same signal, the former is in a conducting state when the first control signal Sb is at a high level, and the latter is in an off state when the second control signal Sc is at a high level, thereby realizing the alternate conduction of the first switch tube Qb and the second switch tube Qc.

For convenience of description, in the following disclosed embodiments, the aforementioned main switch Q1, the power device Qa, the first switch Qb, the second switch Qc and the third switch Qd are all N-channel MOS transistors, and their respective control timings are shown in fig. 2.

Specifically, in a disclosed embodiment, the power supply terminal is connected to a normal dc power supply, the power supply voltage VB required by the circuit is stably provided, for example, 12V, when the enable signal EN is at a logic high level, the main switch Q1 is in a closed conducting state, the test circuit 100 is connected to the input voltage Vin to start supplying power to the test module 101, and the control signal Sa connected to the control terminal of the power device Qa is the same as the enable signal EN, so that the main switch Q1 and the power device Qa are both in the closed conducting state at this time, the test circuit 100 operates in the boost mode, the control terminal of the third switch Qd is connected to the third control signal Sd, the third control signal Sd continues to be at a logic high level, the third switch Qd is maintained in the conducting state, the first switch Qb and the second switch Qc are alternately conducted, and the power supply terminal supplies power to the circuit load terminal Rload through the main switch Q1 and also charges the capacitor CSTR at this time, the circuit equivalent state is shown in fig. 3, so as to simulate the normal charging process of the charger. As shown in fig. 2, the load terminal Rload outputs a stable voltage Vout, while the voltage VSTR at the positive terminal of the capacitor CSTR is maintained at a stable level state after the charging voltage is saturated until the falling edge of the enable signal EN arrives;

with the charging of the capacitor CSTR completed, the enable signal EN and the control signal Sa are converted into logic low levels, the main switch Q1 and the power device Qa are both turned off, the power supply end stops supplying power to the load end Rload of the circuit, the test circuit 100 operates in a step-down mode, the capacitor CSTR discharges through the energy release of the discharging process, the inductor L connected with the test module 101 is used for discharging, and electric energy is supplied to the load end Rload, and the circuit state at this time is equivalent to fig. 4, so that the discharging process of the charger under normal operation is simulated. As shown in fig. 2, the load terminal Rload keeps outputting a stable voltage Vout, and the voltage VSTR at the positive terminal of the capacitor CSTR starts to decrease until the rising edge of the enable signal EN of the next period arrives.

With this through test circuit 100 alternative work under the continuous cycle under step up and step down the mode to the charge-discharge process under the normal operational environment of simulation charger has realized ageing experiment, compares in prior art, can effectively shorten the time and the required power quantity of ageing experiment, improves the maneuverability of experiment, and then saves the cost, and in addition utilize the testing result of each signal in the work, accomplish the capability test of charger, improvement efficiency of experiments that can be very big.

In a disclosed embodiment, the aforementioned test circuit 100 further includes:

the detection control module (not shown) is used for controlling and processing various information in the experimental process, for example, the detection control module can be used for detecting the stored electric quantity of the capacitor CSTR, when the energy stored in the capacitor CSTR is insufficient to supply power to the load end Rload of the circuit, the logic of the enable signal EN is set to be high, and the enable signal EN is switched to the power supply end to supply power to the load end Rload, so that the duty ratio of the enable signal EN accessed to the control end of the main switching tube Q1 is adjusted according to the detection information of the capacitor CSTR, and the output power is effectively controlled.

In a disclosed embodiment, the test circuit 100 may further be connected with: and the upper computer monitoring module (not shown) can be in communication connection with the test circuit and the detection control module, and displays and controls various sent information to realize data monitoring.

In a disclosed embodiment, the aforementioned power device Qa, the inductor L and the aforementioned test module 101 are integrated on the same chip, as shown in fig. 5. Therefore, on one hand, the integration level of the chip can be improved, the circuit area is reduced, and meanwhile, the capacitor and the load end are isolated outside the chip by utilizing the on-chip technology, so that the heat dissipation problem and the interference between signals are avoided, and the circuit stability is improved.

In another aspect, the present disclosure provides a charger, wherein the charger may include the test circuit 100 as previously described.

In summary, the test circuit 100 and the charger for the aging experiment provided in the present disclosure include: one end of the power device Qa is connected with a power supply end through a main switching tube Q1 connected with the power device Qa, the other end of the power device Qa is connected with a load end Rload, and the power device Qa and the main switching tube Q1 are synchronously switched on or off; the testing module 101 is connected to a connection node between the power device Qa and the load end Rload through an inductor L, and is used for simulating an aging period in a charging and discharging process and providing electric energy for the load end Rload; and the positive end of the capacitor CSTR is connected with the test module 101, the negative end of the capacitor CSTR is grounded, and the capacitor CSTR is used for charging or releasing energy in a charging and discharging process matched with the test circuit 100. Therefore, the test circuit 100 can easily realize the switching of two modes (boosting and reducing voltage) by switching on and off the main switching tube Q1, utilizes the circuit structure to simulate and complete the charging and discharging process, and compared with the prior art, the test circuit can effectively shorten the time of an aging experiment and the required power quantity, improves the operability of the experiment, and further saves the cost and improves the efficiency.

It should be noted that in the description of the present disclosure, it is to be understood that the terms "upper", "lower", "inner", and the like, indicate orientation or positional relationship, are only for convenience in describing the present disclosure and simplifying the description, but do not indicate or imply that the referenced components or elements must have a particular orientation, be constructed and operated in a particular orientation, and therefore should not be construed as limiting the present disclosure.

In addition, in this document, the terms "include", "include" or any other variation thereof are intended to cover a non-exclusive inclusion, so that a process, a method, an article or an apparatus including a series of elements includes not only those elements but also other elements not explicitly listed or inherent to such process, method, article or apparatus. Without further limitation, an element defined by the phrases "comprising a," "8230," "8230," or "comprising" does not exclude the presence of additional like elements in a process, method, article, or apparatus that comprises the element.

In addition, in this document, descriptions related to "first", "second", and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the feature. In addition, technical solutions between various embodiments may be combined with each other, but must be realized by a person skilled in the art, and when the technical solutions are contradictory or cannot be realized, such a combination should not be considered to exist, and is not within the protection scope of the present invention.

Finally, it should be noted that: it should be understood that the above examples are only for clearly illustrating the present disclosure, and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. This need not be, nor should it be exhaustive of all embodiments. And obvious variations or modifications of the invention as herein taught are within the scope of the present disclosure.

Claims (9)

1. A test circuit for burn-in experiments, the test circuit is connected to a power supply terminal through a main switch tube, wherein the test circuit comprises:

the power device is connected between the main switching tube and the load end and is synchronously switched on or off with the main switching tube;

the test module is connected to a connection node of the power device and the load end through an inductor and used for simulating an aging period in a charging and discharging process and providing electric energy for the load end;

and the positive end of the capacitor is connected with the test module, the negative end of the capacitor is grounded, and the capacitor is used for charging or releasing energy in cooperation with the charging and discharging process of the test circuit.

2. The test circuit of claim 1, wherein the power device is one of a field effect transistor or a bipolar transistor.

3. The test circuit of claim 1, wherein the test module comprises a first switch tube, a second switch tube and a third switch tube connected in series between the positive terminal of the capacitor and ground,

the first end of the first switch tube is grounded, the second end of the first switch tube is connected with the inductor,

the first end of the second switch tube is connected with the connection node of the first switch tube and the inductor,

and the first end of the third switching tube is connected with the second end of the second switching tube, and the second end of the third switching tube is connected with the positive electrode end of the capacitor.

4. The test circuit of claim 3, wherein a control terminal of the first switch tube is coupled to the first control signal, and a control terminal of the second switch tube is coupled to the second control signal,

the first switch tube and the second switch tube are alternately conducted to match the charging and discharging process of the test circuit.

5. The test circuit of claim 4, wherein the first switch tube and the second switch tube have the same channel type, and the first control signal and the second control signal are opposite signals;

or, if the channel types of the first switching tube and the second switching tube are opposite, the first control signal and the second control signal are the same signal.

6. The test circuit of claim 4, wherein the main switching tube and the power device are both in a closed conducting state, the test circuit operates in a boost mode, and a power supply terminal supplies power to a load terminal and charges the capacitor at the same time;

the main switching tube and the power device are both in an off state, the test circuit works in a voltage reduction mode, the capacitor releases energy in a discharging process, and power is supplied to the load end through the inductor.

7. The test circuit of claim 5, further comprising:

and the detection control module is used for detecting the stored electric quantity of the capacitor and adjusting the duty ratio of a control signal accessed by the control end of the main switching tube according to the detection information.

8. The test circuit of claim 1, wherein the power device, inductor, and test module are integrated on the same chip.

9. A charger, comprising:

a test circuit as claimed in any one of claims 1 to 8.

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