CN115425949A - Voltage-controlled oscillator and clock generator based on same - Google Patents

Voltage-controlled oscillator and clock generator based on same Download PDF

Info

Publication number
CN115425949A
CN115425949A CN202210839346.5A CN202210839346A CN115425949A CN 115425949 A CN115425949 A CN 115425949A CN 202210839346 A CN202210839346 A CN 202210839346A CN 115425949 A CN115425949 A CN 115425949A
Authority
CN
China
Prior art keywords
voltage
delay unit
mos transistor
controlled oscillator
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202210839346.5A
Other languages
Chinese (zh)
Inventor
雒超
薛棋文
郭国平
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
University of Science and Technology of China USTC
Original Assignee
University of Science and Technology of China USTC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by University of Science and Technology of China USTC filed Critical University of Science and Technology of China USTC
Priority to CN202210839346.5A priority Critical patent/CN115425949A/en
Priority to PCT/CN2022/112451 priority patent/WO2024011705A1/en
Publication of CN115425949A publication Critical patent/CN115425949A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/03—Astable circuits
    • H03K3/0315—Ring oscillators
    • H03K3/0322—Ring oscillators with differential cells
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0995—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop

Abstract

The present disclosure provides a voltage controlled oscillator including: m time delay units, M time delay unit annular series connection sets up, forms M level delay circuit, every time delay unit includes: an output module including a positive output node and a negative output node for outputting a differential signal; a rising edge receiving module, configured to receive a rising edge of the differential signal output by the nth delay unit; a falling edge receiving module, configured to receive a falling edge of the differential signal output by the previous delay unit connected to the nth delay unit; the feedback module is connected between the rising edge receiving module and the falling edge receiving module and is used for controlling the turnover time of the differential signal and realizing the control of the output frequency of the voltage-controlled oscillator; wherein M is more than or equal to 3, M is more than or equal to N is more than or equal to 1. The present disclosure also provides a clock generator based on the voltage-controlled oscillator, which can generate a high-frequency clock signal at an extremely low temperature through low power consumption.

Description

Voltage controlled oscillator and clock generator based on same
Technical Field
The disclosure relates to the technical field of clock generators, in particular to a voltage-controlled oscillator capable of working at-269.15 ℃ and lower temperature and a clock generator based on the voltage-controlled oscillator.
Background
In modern integrated circuit design, the working temperature range of a commercial-grade chip is 0-70 ℃, the working temperature range of an industrial-grade chip is-40-85 ℃, the working temperature range of an automobile-grade chip is-40-120 ℃, and the working temperature range of a military chip which has the strictest requirements is only-55-150 ℃. However, under certain extreme conditions, the chip operating temperature requirements are more stringent. For example, the chip used for deep space probing must work properly at 77K (-196.15 ℃). With the development of quantum computers, the circuit design of 4K (-269.15 ℃) and even lower working temperature becomes more important. In 2017, a Dutch Dawlett packard university publishes circuits such as a very low temperature low noise amplifier, a voltage-controlled oscillator, an FPGA control module and the like which can work under 4K (-269.15 ℃). Since then, related work of extremely low temperature circuit design is published in related international top-level journals and conferences every year, but the field is still blank at home, and at extremely low temperature, the threshold voltage of a transistor, namely, the turn-on voltage is increased, the turn-on time of a load tube is longer, and the frequency is seriously reduced.
Therefore, how to provide a very low temperature clock generator capable of operating at-269.15 ℃ and lower is a technical issue to be solved.
Disclosure of Invention
Technical problem to be solved
Based on the above problems, the present disclosure provides a voltage controlled oscillator and a clock generator based on the same to alleviate the technical problems that the clock generator in the prior art is difficult to provide accurate and effective signals all the time in a very low temperature environment.
(II) technical scheme
In one aspect of the present disclosure, there is provided a voltage controlled oscillator including: m time delay units, M time delay unit annular series sets up, forms M level delay circuit, every time delay unit includes: the device comprises an output module, a rising edge receiving module, a falling edge receiving module and a feedback module.
The output module comprises a positive output node and a negative output node and is used for outputting differential signals; the rising edge receiving module is used for receiving the rising edge of the differential signal output by the Nth time delay unit; the falling edge receiving module is used for receiving the falling edge of the differential signal output by the previous delay unit connected with the Nth delay unit; the feedback module is connected between the rising edge receiving module and the falling edge receiving module and used for controlling the turning time of the differential signal and realizing the control of the output frequency of the voltage-controlled oscillator; wherein M is more than or equal to 3, M is more than or equal to N is more than or equal to 1.
According to an embodiment of the present disclosure, a rising edge receiving module includes: the first negative input node is connected to the grid electrode of the first MOS transistor M1; a first positive input node connected to the gate of the second MOS transistor M2; the first MOS tube M1 and the second MOS tube M2 form a differential pair tube, and the source electrodes of the first MOS tube M1 and the second MOS tube M2 are grounded.
According to an embodiment of the present disclosure, a falling edge receiving module includes: a second positive input node connected to the gate of the seventh MOS transistor M7; the second negative input node is connected to the grid electrode of the eighth MOS transistor M8; the seventh MOS transistor M7 and the eighth MOS transistor M8 form a differential pair transistor, and the source electrodes of the seventh MOS transistor M7 and the eighth MOS transistor M8 are connected to a power supply input end Vdd.
According to an embodiment of the present disclosure, a feedback module includes: control voltage receiving port C ctrl For receiving a control voltage; a third MOS tube M3, wherein the grid electrode is connected to the control voltage receiving port, and the source electrodes are connected to the drain electrode of the first MOS tube M1 and are connected to the positive output node together; a fourth MOS tube M4, wherein the grid electrode is connected to the control voltage receiving port, and the source electrode is connected to the drain electrode of the second MOS tube M2 and is connected to the negative output node together; a fifth MOS transistor M5, the source electrode is connected to the power supply input end Vdd, the drain electrode is connected to the drain electrode of the seventh MOS transistor M7 and is connected to the positive output node together, and the grid electrode is connected to the drain electrode of the fourth MOS transistor M4; a source electrode of the sixth MOS transistor M6 is connected to a power supply input end Vdd, drain electrodes of the sixth MOS transistor M6 are connected to the drain electrode of the eighth MOS transistor M8 and are connected to a negative output node together, and a grid electrode of the sixth MOS transistor M6 is connected to the drain electrode of the third MOS transistor M3; the control voltage received by the control voltage receiving port controls the gate voltages of the third MOS transistor M3 and the fourth MOS transistor M4, so as to control the turning time of the differential signal.
According to the embodiment of the disclosure, the first MOS transistor M1 and the second MOS transistor M2 are N-type MOS transistors. The seventh MOS transistor M7 and the eighth MOS transistor M8 are P-type MOS transistors.
According to the embodiment of the disclosure, the voltage-controlled oscillator includes four delay units connected in series in a ring shape, which are a first delay unit, a second delay unit, a third delay unit, and a fourth delay unit in sequence. Wherein: the rising edge receiving module of the first delay unit is connected to the output module of the fourth delay unit and used for receiving a fourth differential output signal, and the falling edge receiving module is connected to the output module of the third delay unit and used for receiving a third differential output signal; a rising edge receiving module of the second delay unit is connected to an output module of the first delay unit and used for receiving the first differential output signal, and a falling edge receiving module is connected to an output module of the fourth delay unit and used for receiving the fourth differential output signal; a rising edge receiving module of the third delay unit is connected to an output module of the second delay unit and used for receiving a second differential output signal, and a falling edge receiving module is connected to an output module of the first delay unit and used for receiving a first differential output signal; the rising edge receiving module of the fourth delay unit is connected to the output module of the third delay unit for receiving the third differential output signal, and the falling edge receiving module is connected to the output module of the second delay unit for receiving the second differential output signal.
Another aspect of the present disclosure provides a clock generator, including: a phase frequency detector, a charge pump, a loop filter, a frequency divider and the voltage-controlled oscillator of any one of the above parts; wherein: output signal F of voltage controlled oscillator out The integer frequency division is realized after the frequency divider, and then the integer frequency division is input into a phase frequency detector, and the phase frequency detector compares the output signal of the frequency divider with an external reference signal F ref The voltage of the loop filter is changed to control the output frequency of the voltage-controlled oscillator, so that the voltage-controlled oscillator outputs a signal with stable frequency.
(III) advantageous effects
According to the technical scheme, the voltage-controlled oscillator and the clock generator based on the voltage-controlled oscillator have at least one or part of the following beneficial effects:
(1) The opening time greatly reduces the time delay, thereby improving the frequency;
(2) The generation of high-frequency clock signals at extremely low temperature (4K) can be realized through lower power consumption.
Drawings
FIG. 1 is a schematic diagram of a clock generator according to an embodiment of the present disclosure;
FIG. 2 is a schematic diagram of a conventional ring-type VCO delay cell;
fig. 3 is a schematic diagram of a delay unit of a voltage controlled oscillator according to an embodiment of the disclosure;
fig. 4 is a schematic diagram of a voltage controlled oscillator of an embodiment of the present disclosure;
FIG. 5 is a diagram illustrating an output frequency curve of a VCO at very low temperature (4K) according to an embodiment of the disclosure;
FIG. 6 is a schematic diagram of a frequency spectrum of a 600MHz signal output by a clock generator according to an embodiment of the disclosure;
fig. 7 is a graph illustrating phase noise curves of 600MHz signals output by the clock generator according to the embodiment of the disclosure.
Detailed Description
The clock generator comprises a phase frequency detector, a charge pump, a frequency divider, a loop filter and a double-edge receiving differential annular voltage-controlled oscillator to form a phase-locked loop. The signal of the voltage-controlled oscillator realizes integer frequency division after passing through the frequency divider, and then is input into the phase frequency detector, the phase frequency detector compares the frequency difference and the phase difference of the output signal of the frequency divider and an external reference signal, thereby generating a specific UP (UP) or Down (DN) voltage pulse signal, the pulse signal is input into the charge pump, the charge pump is controlled to release charge or absorb charge, the voltage of the loop filter is changed, and then the output frequency of the voltage-controlled oscillator is controlled, and the voltage-controlled oscillator outputs a signal with stable frequency. The voltage-controlled oscillator and the clock generator based on the voltage-controlled oscillator avoid the influence of device performance change caused by extremely low temperature on a circuit structure, and realize good functions.
For the purpose of promoting a better understanding of the objects, aspects and advantages of the present disclosure, reference is made to the following detailed description taken in conjunction with the accompanying drawings.
In an embodiment of the present disclosure, a voltage controlled oscillator is provided, which is shown in fig. 3 and 4, and includes: m time delay units, M time delay unit annular series sets up, forms M level delay circuit, every time delay unit includes: the device comprises an output module, a rising edge receiving module, a falling edge receiving module and a feedback module.
The output module comprises a positive output node V out+ And a negative output node V out- For outputting a differential signal;
the rising edge receiving module is used for receiving the rising edge of the differential signal output by the Nth time delay unit;
the falling edge receiving module is used for receiving the falling edge of the differential signal output by the previous delay unit connected with the Nth delay unit; and
the feedback module is connected between the rising edge receiving module and the falling edge receiving module (not shown in fig. 4), and is used for controlling the turning time of the differential signal and realizing the control of the output frequency of the voltage-controlled oscillator; m is greater than or equal to 3, M is greater than or equal to N is greater than or equal to 1, and as shown in FIG. 4, the voltage-controlled oscillator includes four delay units, namely a first delay unit 1, a second delay unit 2, a third delay unit 3 and a fourth delay unit 4.
Fig. 2 shows a delay unit of a conventional differential ring voltage-controlled oscillator, which only has a rising edge receiving path (Vin +, vin-), the on-time of the load transistors (M7, M8) is longer, and the signal time of each stage is longer, so that higher output frequency cannot be realized. Especially at extremely low temperatures, the threshold voltage, i.e., the turn-on voltage, of the transistor increases, and the turn-on time of the load tube becomes longer, resulting in a serious frequency drop.
The novel double-edge receiving differential ring voltage-controlled oscillator delay unit modifies a load tube of a traditional differential ring voltage-controlled oscillator delay unit into an input tube of a falling edge receiving module. Taking fig. 3 in combination with the first three stages of delay units of the sub-controlled oscillator of fig. 4 as an example, M1-M2 are input tubes of the rising edge receiving module to receive the output signal of the previous stage, and M7-M8 are input tubes of the falling edge receiving module to receive the input signal of the previous stage, that is, the output signal of the delay unit of the previous stage connected to the previous stage, so that M7-M8 are turned on in advance to accelerate the turning speed of the output signal of the current stage; the M3-M6 forms a positive feedback module, the intensity of positive feedback can be controlled by controlling the grid voltage of the M3-M4, and then the signal turning time is controlled, and the voltage control of frequency is realized. For example, in an initial state, the first-stage output negative terminal is 1, the second-stage output negative terminal is 0, the third-stage output negative terminal is 1, when the second-stage output negative terminal is a rising edge, the positive input end of the third stage receives the rising edge of the second-stage output, the NMOS (M1, M2) input tube in the delay unit is turned on, and the output point potential of the third stage starts to be pulled down, and meanwhile, the falling edge of the first stage is received by the PMOS (M7, M8) input tube of the third stage, and the PMOS tube is gradually turned on, so that the PMOS is turned on before the output voltage of the third stage is pulled up, the delay is greatly reduced, and the frequency is improved.
According to an embodiment of the present disclosure, the rising edge receiving module includes: first negative input node Vin 1- First positive input node Vin 1+ The first MOS transistor M1 and the second MOS transistor M2. Wherein:
first negative input node Vin 1- A grid connected to the first MOS transistor M1;
first positive input node Vin 1+ A grid electrode connected to the second MOS tube M2;
the first MOS tube M1 and the second MOS tube M2 form a differential pair tube, and the source electrodes of the first MOS tube M1 and the second MOS tube M2 are grounded.
According to an embodiment of the present disclosure, the falling edge receiving module includes: second positive input node Vin 2+ Second negative input node Vin 2- A seventh MOS transistor M7 and an eighth MOS transistor M8. Wherein:
second positive input node Vin 2+ A gate connected to the seventh MOS transistor M7;
second negative input node Vin 2- Is connected toA grid electrode of the eighth MOS transistor M8;
a seventh MOS transistor M7 and an eighth MOS transistor M8 form a differential pair transistor, and the source electrodes of the seventh MOS transistor M7 and the eighth MOS transistor M8 are connected to the power input end V dd 。
According to an embodiment of the present disclosure, the feedback module includes: control voltage receiving port C ctrl A third MOS transistor M3, a fourth MOS transistor M4, a fifth MOS transistor M5, and a sixth MOS transistor M6. Wherein:
control voltage receiving port C ctrl For receiving a control voltage;
the grid electrode of the third MOS tube M3 is connected to the control voltage receiving port, and the source electrodes are connected to the drain electrode of the first MOS tube M1 and are connected to the positive output node together;
the grid electrode of the fourth MOS tube M4 is connected to the control voltage receiving port, and the source electrodes are connected to the drain electrode of the second MOS tube M2 and are connected to the negative output node together;
the source electrode of the fifth MOS transistor M5 is connected to the power input end V dd The drain electrode of the fourth MOS transistor M4 is connected to the drain electrode of the seventh MOS transistor M7, and the drain electrodes of the fourth MOS transistor M4 and the seventh MOS transistor M7 are connected together to form a positive output node; and
the source electrode of the sixth MOS transistor M6 is connected to the power input end V dd The drain electrode is connected to the drain electrode of the eighth MOS transistor M8 and is connected to the negative output node together, and the grid electrode is connected to the drain electrode of the third MOS transistor M3;
the control voltage received by the control voltage receiving port controls the gate voltages of the third MOS transistor M3 and the fourth MOS transistor M4, thereby controlling the inversion time of the differential signal.
According to the embodiment of the disclosure, the first MOS transistor M1 and the second MOS transistor M2 are N-type MOS transistors. The seventh MOS transistor M7 and the eighth MOS transistor M8 are P-type MOS transistors.
The voltage controlled oscillator of claim 8, wherein:
a rising edge receiving module of the first delay unit is connected to an output module of the fourth delay unit and used for receiving a fourth differential output signal, and a falling edge receiving module is connected to an output module of the third delay unit and used for receiving a third differential output signal;
a rising edge receiving module of the second delay unit is connected to an output module of the first delay unit and used for receiving the first differential output signal, and a falling edge receiving module is connected to an output module of the fourth delay unit and used for receiving the fourth differential output signal;
a rising edge receiving module of the third delay unit is connected to an output module of the second delay unit and used for receiving the second differential output signal, and a falling edge receiving module is connected to an output module of the first delay unit and used for receiving the first differential output signal;
the rising edge receiving module of the fourth delay unit is connected to the output module of the third delay unit for receiving the third differential output signal, and the falling edge receiving module is connected to the output module of the second delay unit for receiving the second differential output signal.
The present disclosure also provides a clock generator, which is constructed based on the voltage-controlled oscillator; as shown in fig. 1, the clock generator includes: a phase frequency detector, a charge pump, a loop filter, a frequency divider, and any one of the voltage controlled oscillators; wherein:
output signal F of voltage controlled oscillator out The integer frequency division is realized after the frequency divider, and then the integer frequency division is input into a phase frequency detector, and the phase frequency detector compares the output signal of the frequency divider with an external reference signal F ref Thereby generating a specific UP (UP) or Down (DN) voltage pulse signal and inputting the generated signal to a charge pump connected in series, and controlling the charge pump to release or absorb charges, thereby changing the voltage of the loop filter (the voltage is connected to a control voltage receiving port C of the voltage-controlled oscillator) ctrl ) And then the output frequency of the voltage-controlled oscillator is controlled, so that the voltage-controlled oscillator outputs a signal with stable frequency.
As shown in fig. 5-7, compared to the conventional commercial clock chip that cannot work normally at low temperature, the voltage-controlled oscillator of the present disclosure has significant advantages, for example, through experimental verification, the voltage-controlled oscillator of the present disclosure can output an output signal of 330-890MHz at very low temperature (4K), and the reference spur of the output clock signal of 600MHz is about-39.32 dBc; the phase noise at the frequency offset of 10KHz is-95.53 dBc/Hz, the phase noise at the frequency offset of 1MHz is-102.73 dBc/Hz, the RMS jitter is about 4.8ps (12 KHz-20 MHz), the clock generator disclosed by the invention also has good noise performance at low temperature, and can be completely and directly applied to actual projects at low temperature.
So far, the embodiments of the present disclosure have been described in detail with reference to the accompanying drawings. It is to be noted that, in the attached drawings or in the description, the implementation modes not shown or described are all the modes known by the ordinary skilled person in the field of technology, and are not described in detail. In addition, the above definitions of the various elements and methods are not limited to the specific structures, shapes or modes of operation set forth in the examples, which may be readily modified or substituted by those of ordinary skill in the art.
From the above description, a person skilled in the art should have a clear understanding of the disclosed voltage controlled oscillator and the clock generator based thereon.
In summary, the present disclosure provides a voltage-controlled oscillator and a clock generator based on the same, which achieve generation of a high-frequency clock signal at a very low temperature (4K) through low power consumption.
It should also be noted that the directional terms mentioned in the embodiments, such as "upper", "lower", "front", "back", "left", "right", etc., are only directions referring to the drawings, and are not intended to limit the protection scope of the present disclosure. Throughout the drawings, like elements are represented by like or similar reference numerals. Conventional structures or constructions will be omitted when they may obscure the understanding of the present disclosure. And the shapes and sizes of the respective components in the drawings do not reflect actual sizes and proportions, but merely illustrate the contents of the embodiments of the present disclosure.
The use of ordinal numbers such as "first," "second," "third," etc., in the specification and claims to modify a corresponding element does not by itself connote any ordinal number of the element or any ordering of one element relative to another or relative to a method of manufacture, and is used merely to allow a given element having a certain name to be clearly distinguished from another element having a same name.
In addition, unless steps are specifically described or must occur in sequence, the order of the steps is not limited to that listed above and may be changed or rearranged as desired by the desired design. The embodiments described above may be mixed and matched with each other or with other embodiments based on design and reliability considerations, i.e., technical features in different embodiments may be freely combined to form further embodiments.
The above-mentioned embodiments are intended to illustrate the objects, aspects and advantages of the present disclosure in further detail, and it should be understood that the above-mentioned embodiments are only illustrative of the present disclosure and are not intended to limit the present disclosure, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present disclosure should be included in the scope of the present disclosure.

Claims (9)

1. A voltage controlled oscillator comprising:
m time delay units, M time delay unit annular series sets up, forms M level delay circuit, every time delay unit includes:
an output module including a positive output node and a negative output node for outputting a differential signal;
the rising edge receiving module is used for receiving the rising edge of the differential signal output by the Nth delay unit;
a falling edge receiving module, configured to receive a falling edge of the differential signal output by the previous delay unit connected to the nth delay unit; and
the feedback module is connected between the rising edge receiving module and the falling edge receiving module and is used for controlling the turning time of the differential signal and realizing the control of the output frequency of the voltage-controlled oscillator;
wherein M is more than or equal to 3, M is more than or equal to N is more than or equal to 1.
2. The voltage controlled oscillator of claim 1, the rising edge receiving module, comprising:
the first negative input node is connected to the grid electrode of the first MOS transistor M1;
a first positive input node connected to the gate of the second MOS transistor M2;
the first MOS tube M1 and the second MOS tube M2 form a differential pair tube, and the source electrodes of the first MOS tube M1 and the second MOS tube M2 are grounded.
3. The voltage controlled oscillator of claim 1, the falling edge receiving module, comprising:
a second positive input node connected to the gate of the seventh MOS transistor M7;
the second negative input node is connected to the grid electrode of the eighth MOS transistor M8;
the seventh MOS transistor M7 and the eighth MOS transistor M8 form a differential pair transistor, and the sources of the seventh MOS transistor M7 and the eighth MOS transistor M8 are connected to a power supply input terminal Vdd.
4. The voltage controlled oscillator of claim 1, the feedback module, comprising:
control voltage receiving port C ctrl For receiving a control voltage;
a third MOS tube M3, wherein the grid electrode is connected to the control voltage receiving port, and the source electrodes are connected to the drain electrode of the first MOS tube M1 and are connected to the positive output node together;
a fourth MOS tube M4, wherein the grid electrode is connected to the control voltage receiving port, and the source electrode is connected to the drain electrode of the second MOS tube M2 and is connected to the negative output node together;
a fifth MOS transistor M5 having a source connected to the power input terminal Vdd, a drain connected to the drain of the seventh MOS transistor M7 and connected to the positive output node, and a gate connected to the drain of the fourth MOS transistor M4; and
a sixth MOS transistor M6, the source is connected to the power input end Vdd, the drain is connected to the drain of the eighth MOS transistor M8 and to the negative output node together, and the gate is connected to the drain of the third MOS transistor M3;
the control voltage received by the control voltage receiving port controls the gate voltages of the third MOS transistor M3 and the fourth MOS transistor M4, so as to control the turning time of the differential signal.
5. The voltage controlled oscillator according to claim 2, wherein the first MOS transistor M1 and the second MOS transistor M2 are N-type MOS transistors.
6. The voltage-controlled oscillator as claimed in claim 3, the seventh MOS transistor M7 and the eighth MOS transistor M8 are P-type MOS transistors.
7. The voltage-controlled oscillator as claimed in claim 1, the voltage-controlled oscillator comprising four delay units serially connected in a ring shape, and sequentially comprising a first delay unit, a second delay unit, a third delay unit and a fourth delay unit.
8. The voltage controlled oscillator of claim 7, wherein:
the rising edge receiving module of the first delay unit is connected to the output module of the fourth delay unit and used for receiving a fourth differential output signal, and the falling edge receiving module is connected to the output module of the third delay unit and used for receiving a third differential output signal;
a rising edge receiving module of the second delay unit is connected to an output module of the first delay unit and used for receiving the first differential output signal, and a falling edge receiving module is connected to an output module of the fourth delay unit and used for receiving the fourth differential output signal;
a rising edge receiving module of the third delay unit is connected to an output module of the second delay unit and used for receiving the second differential output signal, and a falling edge receiving module is connected to an output module of the first delay unit and used for receiving the first differential output signal;
the rising edge receiving module of the fourth delay unit is connected to the output module of the third delay unit for receiving the third differential output signal, and the falling edge receiving module is connected to the output module of the second delay unit for receiving the second differential output signal.
9. A clock generator, comprising: a phase frequency detector, a charge pump, a loop filter, a frequency divider, and a voltage controlled oscillator according to any one of claims 1-8; wherein:
output signal F of voltage controlled oscillator out The integer frequency division is realized after the frequency divider, and then the integer frequency division is input into a phase frequency detector which compares the frequency of the frequency divider with the phase frequency detectorComparing the output signal of the frequency divider with an external reference signal F ref The voltage difference and the phase difference of the voltage-controlled oscillator are controlled to generate a specific rising or falling voltage pulse signal and input the specific rising or falling voltage pulse signal into a charge pump connected in series, and the charge pump is controlled to release charges or absorb charges, so that the voltage of the loop filter is changed, the output frequency of the voltage-controlled oscillator is further controlled, and the voltage-controlled oscillator outputs a signal with stable frequency.
CN202210839346.5A 2022-07-14 2022-07-14 Voltage-controlled oscillator and clock generator based on same Pending CN115425949A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN202210839346.5A CN115425949A (en) 2022-07-14 2022-07-14 Voltage-controlled oscillator and clock generator based on same
PCT/CN2022/112451 WO2024011705A1 (en) 2022-07-14 2022-08-15 Voltage-controlled oscillator and clock generator based on voltage-controlled oscillator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210839346.5A CN115425949A (en) 2022-07-14 2022-07-14 Voltage-controlled oscillator and clock generator based on same

Publications (1)

Publication Number Publication Date
CN115425949A true CN115425949A (en) 2022-12-02

Family

ID=84196448

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202210839346.5A Pending CN115425949A (en) 2022-07-14 2022-07-14 Voltage-controlled oscillator and clock generator based on same

Country Status (2)

Country Link
CN (1) CN115425949A (en)
WO (1) WO2024011705A1 (en)

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009260607A (en) * 2008-04-16 2009-11-05 Nec Electronics Corp Voltage-controlled oscillator and phase synchronization circuit
CN106100585B (en) * 2016-06-02 2019-01-01 中国科学技术大学先进技术研究院 A kind of wideband orthogonal voltage controlled oscillator of the low phase error of low noise
CN108199699B (en) * 2017-12-15 2022-01-11 北京时代民芯科技有限公司 Clock circuit with stable duty ratio and low jitter
CN112468137A (en) * 2020-12-04 2021-03-09 中科威发半导体（苏州）有限公司 Voltage controlled oscillator, phase-locked loop circuit and clock chip

Also Published As

Publication number Publication date
WO2024011705A1 (en) 2024-01-18

Similar Documents

Publication Publication Date Title
US7592877B2 (en) Variable frequency oscillator and communication circuit with it
CN102356547B (en) Injection-locked frequency divider and pll circuit
CN102195642B (en) Phase-locked loop circuit, semiconductor integrated circuit, electronic device
WO2016118936A1 (en) Phase frequency detector and accurate low jitter high frequency wide-band phase lock loop
US20060280278A1 (en) Frequency divider circuit with a feedback shift register
JPS639409B2 (en)
US7863991B1 (en) Wide range/high speed low power CMOS VCO
Islam et al. Design and analysis of 3 stage ring oscillator based on MOS capacitance for wireless applications
CN110518896B (en) Clock generating circuit and chip for providing arbitrary frequency and duty ratio
Zhao et al. A wide tuning range voltage-controlled ring oscillator dedicated to ultrasound transmitter
Shepherd et al. 500 kHz–5 MHz phase-locked loops in high-temperature silicon carbide CMOS
KR100714586B1 (en) Voltage controlled oscillator with duty correction
US6946917B2 (en) Generating an oscillating signal according to a control current
RU2455755C1 (en) Ring cmos voltage controlled oscillator
CN108847843B (en) Orthogonal ring oscillator based on resistance enhanced feedforward
CN115425949A (en) Voltage-controlled oscillator and clock generator based on same
Buhr et al. Low power 16 phase ring oscillator and PLL for use in sub-ns time synchronization over Ethernet
US6861911B2 (en) Self-regulating voltage controlled oscillator
CN111641409B (en) Charge pump phase-locked loop circuit
Wang et al. Delay-locked loop based frequency quadrupler with wide operating range and fast locking characteristics
US7321270B2 (en) Current-controlled CMOS ring oscillator circuit
CN115694481A (en) 1.5 frequency divider based on delay locked loop
Talwekar et al. A high-speed, low power consumption positive edge triggered D flip-flop for high speed phase frequency detector in 180 nm CMOS technology
Tsimpos et al. A low-power frequency multiplier for multi-GHz applications
JP2021034784A (en) Injection synchronous frequency divider

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination