CN115425635A - Asymmetric parameter low-frequency harmonic suppression circuit and method based on fractional order capacitance - Google Patents
Asymmetric parameter low-frequency harmonic suppression circuit and method based on fractional order capacitance Download PDFInfo
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J1/00—Circuit arrangements for dc mains or dc distribution networks
- H02J1/02—Arrangements for reducing harmonics or ripples
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J3/00—Circuit arrangements for ac mains or ac distribution networks
- H02J3/36—Arrangements for transfer of electric power between ac networks via a high-tension dc link
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J3/00—Circuit arrangements for ac mains or ac distribution networks
- H02J3/38—Arrangements for parallely feeding a single network by two or more generators, converters or transformers
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J3/00—Circuit arrangements for ac mains or ac distribution networks
- H02J3/36—Arrangements for transfer of electric power between ac networks via a high-tension dc link
- H02J2003/365—Reducing harmonics or oscillations in HVDC
Abstract
The invention discloses an asymmetric parameter low-frequency harmonic suppression circuit and method based on fractional order capacitance, comprising a harmonic suppression branch and a fractional order capacitance C foc (ii) a The harmonic suppression branch is connected in parallel at two ends of the direct current bus. Wherein, a fractional order capacitor C foc Equivalent to an ideal current source and a capacitor C 2 Are connected in parallel. The harmonic suppression method absorbs low-frequency harmonic power at the end of the direct-current bus and enables energy to be transmitted between the direct-current bus and the branch circuit, so that the purpose of harmonic suppression is achieved, and the influence on a load is small. Meanwhile, the method can control the switch tube S a And S b Change C 1 And C foc The instantaneous power of the power converter achieves a good harmonic suppression effect. By controlling the switching tube S c And S d Changing the size of the equivalent current sourceMethod can be applied to fractional order capacitance C foc Is adjusted in a capacitor C 1 And C 2 And parameter matching is realized under the condition that actual parameters are asymmetrical, so that better low-frequency harmonic suppression is obtained.
Description
Technical Field
The invention relates to the technical field of power quality, in particular to an asymmetric parameter low-frequency harmonic suppression circuit and method based on fractional order capacitance.
Background
With the rapid development of the direct-current micro-grid system, the micro-converter is widely applied. When multiple loads are connected to the dc bus, several harmonic currents, such as those generated by a single-phase inverter, are generated on the dc bus. The second harmonic current can reduce the output power and conversion efficiency of the converter, influence the realization of maximum power point tracking in photovoltaic application, shorten the service life of a power supply and equipment and the like.
At present, two effective methods for suppressing the second harmonic current aiming at the direct current bus can be divided into two methods. The first method does not change the original circuit structure, but only changes the control loop. For example, adding virtual impedances, notch filters, and resonance adjusters to the front-end converter control loop of a cascade system can suppress harmonic currents. But the harmonic current is transferred into the bus capacitance, causing voltage ripple on the dc bus. The second method adds or modifies part of the circuit structure to make the whole system have harmonic suppression capability, such as a double-end active capacitor structure, a symmetrical half-bridge circuit and a negative-order capacitor. The structures can inhibit harmonic waves, replace a large capacitor on the original direct current bus and improve power density. The two capacitors have the same parameters, the voltage changes in a mirror image mode, the sum of the voltages is kept unchanged, the stability of the bus voltage is kept, and the fluctuation of the total power counteracts the pulsating power generated by the load. However, these circuits are all of symmetrical structures, and at the same time, the same device parameters are also required, and the adopted passive devices may change with time, and the harmonic suppression effect is reduced by the parameter error.
Ignoring errors in device parameters may result in reduced harmonic suppression, while blindly selecting high-precision components may significantly increase cost. The method has application in various fields, such as an interleaved boost converter, a modular multilevel converter, an electromagnetic interference filter and the like, for compensating parameter errors. Although these methods provide reference, they are not directly applicable to active filters of symmetrical structure. The variable capacitor can effectively solve the error of capacitance value parameters, but the range of equivalent capacitance value change is only smaller than the actual capacitance value, and in order to obtain a larger capacitance value, the capacitor voltage needs to be additionally increased, and the voltage stress of the device is increased. The other method is to compensate the voltage deviation caused by parameter errors by adjusting a central voltage point, but the maximum adjustable range of the capacitor voltage can be reduced, and the maximum harmonic suppression capability is reduced.
Disclosure of Invention
The invention mainly aims to provide a low-frequency harmonic suppression circuit and a low-frequency harmonic suppression method based on a fractional order capacitor, which can compensate impedance in a large range by adjusting the order of the fractional order capacitor under the condition that the capacitor parameters are asymmetric, and do not need an additional independent power supply.
The invention adopts the following technical scheme:
an asymmetric parameter low-frequency harmonic suppression circuit based on fractional order capacitance is characterized in that: comprises a harmonic suppression branch and a fractional order capacitor C foc The harmonic suppression branch is connected in parallel with two ends of the direct current bus to absorb harmonic power, and the fractional order capacitor is equivalent to a capacitor C 2 And is connected in parallel with an ideal current source.
The harmonic suppression branch comprises a first bridge arm and an inductor L r Capacitor C 1 And a capacitor C 2 The first bridge arm comprises a switch tube S a And a switching tube S b Switching tube S a D pole and switch tube S b The S poles of the bridge arms are respectively connected with the positive pole and the negative pole of the direct current bus, and the midpoint of the first bridge arm is connected with an inductor L r One terminal of (1), inductance L r The other end of the capacitor C is connected with a capacitor C 1 Negative plate and capacitor C 2 Positive plate and capacitor C 1 Positive plate and capacitor C 2 The negative plate is connected with the positive and negative electrodes of the direct current bus.
The fractional order capacitor C foc Comprises a second bridge arm and an inductor L c Capacitor C 3 (ii) a The second bridge arm comprises a switch tube S c And a switching tube S d Switching tube S c D pole and switch tube S d S poles of the two capacitors are respectively connected with a capacitor C 3 The middle point of the second bridge arm is connected with an inductor L c One terminal of (1), inductance L c Is connected with the capacitor C at the other end 2 Positive plate of (1), capacitor C 3 And the capacitor C 2 Is connected with the negative plate, and the harmonic suppression branch circuit and the fractional order capacitor share a capacitor C 2 。
An asymmetric parameter low-frequency harmonic suppression method based on fractional order capacitance is characterized in that: the asymmetric parameter low-frequency harmonic suppression circuit based on the fractional order capacitor is suitable for the occasions where the actual capacitor parameter is asymmetric and the secondary harmonic current is suppressed.
Preferably, in the harmonic suppression branch, the capacitor C 2 Voltage u of C2 By using capacitor voltage outer loop and inductor current L r The inner-ring double-closed-loop control method specifically comprises the following steps:
by acquiring the output voltage u o And an output current i o And calculating to obtain the capacitance C 2 Reference voltage u of C2-ref (ii) a The capacitor C 2 Voltage u of C2 I.e. fractional order capacitor C foc Voltage u across Cfoc (ii) a Will collect the capacitance C 2 Voltage u of C2 And a reference voltage u C2-ref The difference value input voltage outer loop PI compensator outputs the difference value as an inner loop inductor L r Reference of current, and actual inductor current i Lr After comparison, the switching tube S is controlled by sine pulse width modulation a And S b Make and break of (2).
Preferably, the fractional order capacitor part adopts a parallel double closed-loop control method, which specifically comprises the following steps:
one of the closed loops collects the current i of the direct current bus bus Calculating to obtain the inductance L C Reference current i of Lc-ref With the actual inductor current i Lc After comparison, the signals are input into a first PI compensator to obtain a modulation signal v 1 (ii) a The other closed loop obtains the capacitance C from the voltage constraint condition 3 Reference voltage u C3-ref The value range of (a); will collect the capacitance C 3 Voltage u of C3 Comparing with reference voltage, inputting into a second PI compensator to obtain a modulation signal v 2 (ii) a Modulating signal v 1 And v 2 The modulated signals m are obtained after superposition through an adder,finally, the switching tube S is controlled by SPWM c And a switching tube S d The on-off of the capacitor C is ensured while the inductive current is accurately output 3 And (5) stabilizing the voltage.
Preferably, in the harmonic suppression branch, a capacitor C 1 And a fractional order capacitance C foc The sum of the instantaneous power of the alternating current components is equal to the secondary pulse power generated by the load, and when the phases are opposite, the absorption of the secondary harmonic current can be realized, and the total constraint of the direct current bus voltage is met.
Preferably, the load is a load for generating secondary pulsating power in the dc bus.
Preferably, the load comprises a single-phase inverter or a single-phase rectifier.
Preferably, the fractional order capacitance C is controlled when the actual capacitance parameter is shifted foc The size of the equivalent current source is changed by the on-off of part of the switch tubes, thereby the fractional order capacitor C is controlled foc The equivalent capacitance value and the resistance value are adjusted to realize parameter matching.
As can be seen from the above description of the present invention, compared with the prior art, the present invention has the following advantages:
(1) The invention provides a construction mode of a fractional order capacitor, which has simple structure and easy realization, can regulate the equivalent impedance of the capacitor in a larger range on the premise of not needing an additional independent power supply, and can realize the negative resistance characteristic.
2) According to the invention, the matching of the capacitance parameters in the symmetrical structure can be realized, and the influence of capacitance parameter errors on the suppression of the second harmonic current can be compensated.
3) According to the invention, under the condition of asymmetric parameters, the first harmonic current caused by capacitance parameter errors can be suppressed.
Drawings
FIG. 1 is a circuit diagram of the present invention;
FIG. 2 is a control block diagram of the present invention;
FIG. 3 is a block diagram of the fractional order capacitance control of the present invention;
FIGS. 4 (a) -4 (c) are simulation results of the present invention with harmonic suppression;
wherein, the capacitor C 1 First component capacitance of the harmonic suppression branch, capacitance C 2 -the second forming capacitance of the harmonic suppression branch and the first forming capacitance of the fractional order capacitance, the inductance L r The harmonic suppression branch constitutes an inductor, a switching tube S a First component of the harmonic suppression branch, the switching tube S b A second component of the harmonic suppression branch, the capacitor C 3 -fractional order capacitance C foc The second component of (1) is a capacitor, an inductor L c Fractional order capacitance C foc Form an inductor, a capacitor S c -fractional order capacitance C foc The first component of (1) switch tube, switch tube S d -fractional order capacitance C foc Second component of (1) switching tube, voltage U bus -direct bus voltage, current I bus -direct bus current, voltage u C1 -a capacitance C 1 Voltage of, voltage u C2 -a capacitance C 2 Voltage of, voltage u C3 -a capacitance C 3 Voltage, current i of C1 -a capacitance C 1 Current of, current i C2 -a capacitance C 2 Current of (i), current i Lr Inductance L r Current of (i), current i Lc -inductance L c Of the current of (c).
The invention is described in further detail below with reference to the figures and specific examples.
Detailed Description
The invention is further described below by means of specific embodiments.
The present invention is further described with reference to the accompanying drawings and specific examples, which are intended to be illustrative only and not to be limiting of the scope of the invention, and various equivalent modifications of the invention will occur to those skilled in the art upon reading the present invention and fall within the scope of the appended claims.
Referring to fig. 1, an asymmetric parameter low-frequency harmonic suppression circuit based on fractional order capacitance includes a harmonic suppression branch and a fractional order capacitance C foc The harmonic suppression branch is connected in parallel with two ends of the direct current bus to absorb harmonic power, and the fractional order capacitor is equivalent to a capacitor C 2 And is connected in parallel with an ideal current source. Capacitor C in harmonic suppression branch 1 And a fractional order capacitance C foc The sum of the instantaneous power of the alternating current components is equal to the secondary pulse power generated by the load, and when the phases are opposite, the absorption of the secondary harmonic current can be realized, and the total constraint of the direct current bus voltage is met; when the actual capacitance parameter is deviated, the size of the equivalent current source is changed by controlling the on-off of the fractional order part switch tube, so that the fractional order capacitance C can be adjusted foc The equivalent capacitance value and the resistance value of the capacitor are adjusted to realize parameter matching.
Furthermore, the harmonic suppression branch comprises a first bridge arm and an inductor L r Capacitance C 1 And a capacitor C 2 The first bridge arm comprises a switch tube S a And a switching tube S b Switching tube S a D pole and switch tube S b The S poles of the bridge arms are respectively connected with the positive pole and the negative pole of the direct current bus, and the midpoint of the first bridge arm is connected with an inductor L r One terminal of (1), inductance L r The other end of the capacitor C is connected with a capacitor C 1 Negative plate of (1) and capacitor C 2 Positive plate and capacitor C 1 Positive plate and capacitor C 2 The negative plate is connected with the positive and negative electrodes of the direct current bus.
Fractional order capacitor C foc Comprises a second bridge arm and an inductor L c Capacitor C 3 (ii) a The second bridge arm comprises a switch tube S c And a switching tube S d Switching tube S c D pole and switch tube S d S poles of the capacitors are respectively connected with a capacitor C 3 The middle point of the second bridge arm is connected with an inductor L c One end of (1), an inductance L c The other end of the capacitor C is connected with a capacitor C 2 Positive plate of (1), capacitor C 3 Negative plate and capacitor C 2 Is connected with a common capacitor C of the harmonic suppression branch and the fractional order capacitor 2 。
The invention also provides an asymmetric parameter low-frequency harmonic suppression method based on the fractional order capacitor, which is realized by adopting the asymmetric parameter low-frequency harmonic suppression circuit based on the fractional order capacitor and is suitable for the secondary harmonic current suppression occasion with the asymmetric actual capacitor parameter.
Further, in harmonic suppression branches, electricityContainer C 2 Voltage u of C2 By using capacitor voltage outer loop and inductor current L r The inner-ring double-closed-loop control method specifically comprises the following steps:
by collecting the output voltage u o And an output current i o And calculating to obtain the capacitance C 2 Reference voltage u C2-ref (ii) a Capacitor C 2 Voltage u of C2 I.e. fractional order capacitor C foc Voltage u across Cfoc (ii) a Will collect the capacitance C 2 Voltage u of C2 And a reference voltage u C2-ref The difference value input voltage outer loop PI compensator outputs the difference value as an inner loop inductor L r Reference of current, and actual inductor current i Lr After comparison, the switching tube S is controlled by Sinusoidal Pulse Width Modulation (SPWM) a And S b Make and break of (2).
The fractional order capacitor part adopts a parallel double closed-loop control method, which comprises the following steps:
one of the closed loops is used for collecting the current i of the direct current bus bus And calculating to obtain the inductance L C Reference current i of Lc-ref With the actual inductor current i Lc After comparison, the signals are input into a first PI compensator to obtain a modulation signal v 1 (ii) a The other closed loop obtains the capacitance C from the voltage constraint condition 3 Reference voltage u C3-ref The value range of (a); will collect the capacitance C 3 Voltage u of C3 Comparing with reference voltage, inputting into a second PI compensator to obtain a modulation signal v 2 (ii) a Modulating signal v 1 And v 2 Obtaining a modulation signal m after superposition of an adder, and finally controlling a switching tube S through SPWM c And a switching tube S d On/off of the capacitor C, the inductor current is accurately output, and the capacitor C is ensured 3 And (5) stabilizing the voltage.
In the harmonic suppression branch, a capacitor C 1 And a fractional order capacitance C foc The sum of the instantaneous power of the alternating current components is equal to the secondary pulse power generated by the load, and when the phases are opposite, the absorption of the secondary harmonic current can be realized, and the total constraint of the direct current bus voltage is met. When the actual capacitance parameter is deviated, the fractional order capacitance C is controlled foc The switch tube in (1) is connectedChanging the magnitude of the equivalent current source to thereby control the fractional order capacitance C foc The equivalent capacitance value and the resistance value are adjusted to realize parameter matching.
The load is a load which enables the direct current bus to generate secondary pulsating power, and specifically, the load comprises a single-phase inverter or a single-phase rectifier.
Fractional order theory has been more and more widely applied to the field of power electronics, a fractional order capacitor is one of fractional order devices, and the impedance characteristics of the fractional order capacitor can be adjusted in a large range in a complex plane by changing the order of the fractional order capacitor. Therefore, the fractional order capacitor with the adjustable order number is used for replacing a common capacitor, so that the errors of the capacitance value and the resistance value can be compensated simultaneously, a larger capacitance value can be obtained on the premise of not increasing the voltage stress of a device, and the maximum harmonic suppression capability cannot be reduced.
The invention adopts the following control mode:
first component switch tube S of harmonic suppression branch a The driving signal applied between the grid and the source and the harmonic suppression branch circuit form a switching tube S b The driving signals applied between the gate and the source of (1) are complementary. Fractional order capacitor first composition switch tube S c A driving signal applied between the gate and the source and a fractional order capacitor d The driving signals applied between the gate and the source of (1) are complementary.
The harmonic suppression branch circuit comprises a first switch tube S a And a second component switching tube S b The first component of fractional order capacitor is a switch tube S c And a second component switching tube S d The switching-on and the switching-off of the switching-off circuit are controlled by adopting SPWM, and the switching frequency is reasonably selected by comprehensively considering the system capacity, the voltage and current stress of a switching tube, the optimization of the system efficiency and other factors.
Suppose a single-phase inverter output voltage u o And an output current i o Are respectively as
Wherein, U o ，I o Are respectively asThe amplitude of the output voltage and the output current, ω is the angular frequency and θ is the initial phase of the output current.
Then the output power p o Can be expressed as
The pulsating power contains a DC component and a double frequency AC component, and when fed back to the DC side, a second harmonic current i appears on the DC bus in_2nd
Wherein, U bus Is the dc bus voltage.
In order to suppress the second harmonic current, a capacitor C is provided 1 And a capacitor C 2 Voltages are respectively
Wherein u is C1 ，u C2 Respectively represent a capacitor C 1 Capacitor C 2 Voltage of u h Is the alternating component of the capacitor voltage, U h And β is each u h K is a proportionality coefficient, determines the capacitance C 1 ，C 2 Dc bias of the voltage.
By power matching, when the instantaneous power p of the harmonic suppression branch is all The second harmonic current can be suppressed when the second ripple power is equal to the second ripple power brought by the load and the phases are opposite, namely
When C is present 1 ＝C 2 When the harmonic suppression branch circuit is in the state of k =0.5, C can obtain the maximum power decoupling capacity when the harmonic suppression branch circuit is in the state of C 1 、C 2 Are respectively a capacitor C 1 Capacitor C 2 The capacitance value of (2). And because the inductance is small enough, the instantaneous power p of the harmonic suppression branch circuit all Can be simplified into
From (4), (5) and (6), when the secondary pulsating power is completely suppressed, U is obtained h And beta should satisfy
Thus, the capacitance C 1 ，C 2 Reference voltage u of C1-ref ，u C2-ref Are respectively as
However, the above conclusion is that at the capacitance C 1 And C 2 Capacity values are equal, and Equivalent Series Resistance (ESR) is not existed. Considering the actual situation, the capacitance values of the two capacitors may not be equal, and there may be ESR, then the instantaneous power p of the harmonic suppression branch at this time all2 Is composed of
Wherein r is 1 And r 2 Respectively represent a capacitor C 1 And a capacitor C 2 The ESR of (a) in the series of (a),
and
are respectively a capacitor C 1 And a capacitor C 2 The initial phase of the voltage.
Compared with (6), the harmonic suppression circuit increases the primary power in addition to the secondary pulsating power, and generates a primary harmonic current on the direct current bus. The variable capacitor can only change the capacitance value and cannot meet the requirement, so that the parameter needs to be compensated by introducing the fractional order capacitor with adjustable capacitance value and ESR.
From the above analysis, when the capacitance parameters are different, the first harmonic current appears on the dc bus, which can be expressed as
Neglecting the inductance L r Current on, when the capacitor C 1 And C 2 When the parameters are symmetrical, the sum of the currents is zero, and when the parameters are different, the output current i of the fractional order part can be obtained Lc Is composed of
i C1 +i C2 ＝ω(C 1 -C 2 )U h cos(ωt+θ)＝2I har-1 (11)
Capacitor C in harmonic suppression branch 2 Voltage u C2 By using capacitor voltage outer ring and inductor current L r An inner ring double closed loop control method. By acquiring the output voltage u o And an output current i o And calculating to obtain the capacitance C 2 Reference voltage u of C2-ref The above-mentioned capacitor C 2 Voltage u of C2 I.e. fractional order capacitor C foc Voltage u across Cfoc . By collecting the capacitance C 2 Voltage u of C2 With a reference voltage u C2-ref The difference value input voltage outer loop PI compensator outputs the difference value as an inner loop inductor L r Reference of current, and actual inductor current i Lr After comparison, the switching tube S is controlled by Sinusoidal Pulse Width Modulation (SPWM) a And S b Make and break of (2). As shown in fig. 2.
The fractional order capacitor part adopts a parallel double closed-loop control method. One of the closed loops is used for collecting the current i of the direct current bus bus And calculating to obtain the inductance L c Reference current i of Lc-ref And the actual inductanceCurrent i Lc After comparison, the signals are input into a first PI compensator to obtain a modulation signal v 1 . The other closed loop can obtain the capacitance C by the voltage constraint condition 3 Reference voltage u C3-ref By collecting the capacitance C 3 Voltage u of C3 Comparing with reference voltage, inputting into a second PI compensator to obtain a modulation signal v 2 Modulating signal v 1 And v 2 Obtaining a modulation signal m after superposition of an adder, and finally controlling a switching tube S through SPWM c And S d The on-off of the capacitor C is ensured while the inductive current is accurately output 3 And (5) stabilizing the voltage. As shown in fig. 3.
From the above analysis, the capacitance C 1 And C 2 Should be chosen according to the parameter symmetry and related to the bus voltage and the secondary ripple power, as shown in the following formula, where P har_2 Is secondary pulsating power
According to the ripple index regulation of GB/T14549, to reduce L r And C 1 、C 2 The influence of resonant sub-ripple on the system is such that L r And C 1 、C 2 The resonant frequency is greater than 21 times the operating frequency of the circuit. Let the working frequency be f w (i.e., inverter output voltage frequency), the inductance L r Has a maximum value of
Suppose a capacitance C 1 Is a standard value, then C 1 Instantaneous change of charge and voltage Δ q 1 And Δ u 1 Is composed of
Δq 1 ＝∫i C1 dt (14)
When the harmonic current in the bus is completely suppressed, the bus voltage is a fixed value, and the capacitor C 1 And C 2 Should be varied in opposite directions
Δu C1 ＝-Δu C2 ＝U h (16)
As known from the circuit structure, the circuit of the fractional order capacitor is actually a buck-boost circuit, so the input and output voltages and the duty ratio d should satisfy
The current relationship can be obtained by the same method
Then the capacitance C 3 Change in electric charge of
Δq 3 ＝∫i C3 dt＝d(Δq 1 -Δq 2 ) (19)
Combine (16), (17) and (19) to obtain a capacitor C 3 Voltage u of C3
Suppose a capacitance C 3 Initial charge amount of 3,init Then the instantaneous value q of its charge amount 3 Is composed of
q 3 ＝Q 3,init +Δq 3 (21)
From q 3 ＝C 3 u C3 One quadratic equation of unity with respect to the duty cycle d can be derived
Assume that the parameter error of the capacitor C2 is Δ C, andsatisfies C 1 ＝C 2 + Δ C, duty cycle d between 0 and 1, which is obtained by solving the equation of one-dimensional quadratic
The parameters of the asymmetric parameter harmonic suppression method based on fractional order capacitance are designed as shown in the table, and the DC bus voltage U is obtained by simulation according to the parameter selection mode and comprehensively considering the system efficiency dc 350V, capacitance C 1 A capacity value of 150 μ F, r 1 Is 0.3, capacitance C 2 A capacity value of 120 μ F, r 2 Is 0.8 (C) 2 In series with a small 0.5 resistor), capacitor C 2 Capacitance value of 20 μ F, inductance L r 150 muH, inductance L c At 1mH, switching frequency f s Is 15kHz.
According to the analysis, the inverter can generate second harmonic current on a direct current bus, and the second harmonic current is suppressed by adopting an asymmetric parameter harmonic suppression method based on a fractional order capacitor.
FIG. 4 (a) shows the capacitance C 1 And C 2 When the parameters are symmetrical, the output voltage u o Capacitor voltage u C1 、u C2 And bus current I bus The simulated waveform of (a) and the FFT results. Due to the symmetrical capacitance parameters, the second harmonic current is well suppressed and the first harmonic current does not appear in the bus current.
FIG. 4 (b) is a diagram when the capacitor C 1 And C 2 When the parameter is asymmetric (C) 1 ＝1.25C 2 ) Output voltage u o Capacitor voltage u C1 、u C2 And bus current I bus The simulated waveform of (a) and the FFT results. Due to the influence of asymmetry of capacitance parameters, primary harmonic current appears in bus current, the ratio of the relative DC component is 22.1%, and the secondary harmonic current is increased to 8.21%.
FIG. 4 (C) is a diagram when the capacitor C 1 And C 2 Parameter asymmetry (C) 1 ＝1.25C 2 ) And when the fractional order capacitor is used for compensation, the output voltage u o Capacitor voltage u C1 、u C2 And bus current I bus And FFT result, current i Lclp Is an inductive current i Lc The waveform after low pass filtering. The first harmonic current and the second harmonic current are well suppressed and both are reduced to below 4%.
The above description is only an embodiment of the present invention, but the design concept of the present invention is not limited thereto, and any insubstantial modifications made by using the design concept should fall within the scope of infringing the present invention.
Claims (10)
1. The utility model provides an asymmetric parameter low frequency harmonic suppression circuit based on fractional order electric capacity which characterized in that: comprises a harmonic suppression branch and a fractional order capacitor C foc The harmonic suppression branch is connected in parallel with two ends of the direct current bus to absorb harmonic power, and the fractional order capacitor is equivalent to a capacitor C 2 And is connected in parallel with an ideal current source.
2. The fractional order capacitance-based asymmetric parameter low frequency harmonic suppression circuit of claim 1, wherein: the harmonic suppression branch comprises a first bridge arm and an inductor L r Capacitance C 1 And a capacitor C 2 The first bridge arm comprises a switch tube S a And a switching tube S b Switching tube S a D pole and switch tube S b The S poles of the bridge arms are respectively connected with the positive pole and the negative pole of the direct current bus, and the midpoint of the first bridge arm is connected with an inductor L r One terminal of (1), an inductorL r The other end of the capacitor C is connected with a capacitor C 1 Negative plate and capacitor C 2 Positive plate and capacitor C 1 Positive plate and capacitor C 2 The negative plate is connected with the positive and negative electrodes of the direct current bus.
3. The fractional order capacitance based asymmetric parametric low frequency harmonic suppression circuit of claim 2, wherein: the fractional order capacitor C foc Comprises a second bridge arm and an inductor L c Capacitor C 3 (ii) a The second bridge arm comprises a switch tube S c And a switching tube S d Switching tube S c D pole and switch tube S d S poles of the two capacitors are respectively connected with a capacitor C 3 The middle point of the second bridge arm is connected with an inductor L c One end of (1), an inductance L c Is connected with the capacitor C at the other end 2 Positive plate of (1), capacitor C 3 And the capacitor C 2 Is connected with the negative plate of the fractional order capacitor, and the harmonic suppression branch circuit and the fractional order capacitor share a capacitor C 2 。
4. An asymmetric parameter low-frequency harmonic suppression method based on fractional order capacitance is characterized in that: the circuit is realized by the asymmetric parameter low-frequency harmonic suppression circuit based on the fractional order capacitor of any one of claims 1 to 3, and is suitable for the occasion of second harmonic current suppression with asymmetric actual capacitor parameters.
5. The asymmetric parameter low-frequency harmonic suppression method based on the fractional order capacitance as claimed in claim 4, characterized in that: in the harmonic suppression branch, the capacitor C 2 Voltage u of C2 By using capacitor voltage outer loop and inductor current L r The inner-ring double-closed-loop control method specifically comprises the following steps:
by acquiring the output voltage u o And an output current i o And calculating to obtain the capacitance C 2 Reference voltage u of C2-ref (ii) a The capacitor C 2 Voltage u of C2 I.e. fractional order capacitor C foc Voltage u across Cfoc (ii) a Will collect the capacitance C 2 Voltage u of C2 And a reference voltage u C2-ref The difference value input voltage outer loop PI compensator outputs the difference value as an inner loop inductor L r Reference of current, and actual inductor current i Lr After comparison, the switching tube S is controlled by sine pulse width modulation a And S b Make and break of (2).
6. The asymmetric-parameter low-frequency harmonic suppression method based on the fractional-order capacitance of claim 5, characterized in that: the fractional order capacitor part adopts a parallel double closed-loop control method, which comprises the following steps:
one of the closed loops is used for collecting the current i of the direct current bus bus Calculating to obtain the inductance L C Reference current i of Lc-ref With the actual inductor current i Lc After comparison, the signals are input into a first PI compensator to obtain a modulation signal v 1 (ii) a The other closed loop obtains the capacitance C from the voltage constraint condition 3 Reference voltage u C3-ref The value range of (a); will collect the capacitance C 3 Voltage u of C3 Comparing with reference voltage, inputting into a second PI compensator to obtain a modulation signal v 2 (ii) a Modulating signal v 1 And v 2 Obtaining a modulation signal m after superposition by an adder, and finally controlling a switching tube S by SPWM c And a switching tube S d The on-off of the capacitor C is ensured while the inductive current is accurately output 3 And (5) stabilizing the voltage.
7. The asymmetric-parameter low-frequency harmonic suppression method based on the fractional-order capacitance of claim 5, characterized in that: in the harmonic suppression branch, a capacitor C 1 And a fractional order capacitance C foc The sum of the instantaneous power of the alternating current components is equal to the secondary pulse power generated by the load, and when the phases are opposite, the absorption of the secondary harmonic current can be realized, and the total constraint of the direct current bus voltage is met.
8. The asymmetric parameter low-frequency harmonic suppression method based on fractional order capacitance of claim 7, characterized in that: the load is used for enabling the direct current bus to generate secondary pulse power.
9. The asymmetric-parameter low-frequency harmonic suppression method based on the fractional-order capacitance of claim 7, characterized in that: the load comprises a single-phase inverter or a single-phase rectifier.
10. The asymmetric-parameter low-frequency harmonic suppression method based on the fractional-order capacitance of claim 5, characterized in that: when the actual capacitance parameter is deviated, the fractional order capacitance C is controlled foc The size of the equivalent current source is changed by the on-off of part of the switch tubes, thereby the fractional order capacitor C is controlled foc The equivalent capacitance value and the resistance value of the capacitor are adjusted to realize parameter matching.
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