CN115424937A - Fin structure forming method of device - Google Patents
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- CN115424937A CN115424937A CN202211130462.6A CN202211130462A CN115424937A CN 115424937 A CN115424937 A CN 115424937A CN 202211130462 A CN202211130462 A CN 202211130462A CN 115424937 A CN115424937 A CN 115424937A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
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- Microelectronics & Electronic Packaging (AREA)
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Abstract
The invention discloses a method for forming a fin structure of a device, which comprises the following steps: obtaining a substrate on which a first fin portion, shallow trench isolation and a well region are formed; performing first low-temperature oxidation on the surface of the first fin part, and forming a first oxide layer on the surface of the first fin part in a shape-preserving manner; removing the first oxide layer in situ, and forming an intrinsic layer on the surface of the first fin portion in a shape-preserving manner; carrying out second low-temperature oxidation on the intrinsic layer, and forming a second oxidation layer on the surface of the intrinsic layer in a shape-preserving manner; forming a first gate oxide layer on the second oxide layer by using a low-temperature deposition process; and hardening and annealing the first gate oxide layer and the second oxide layer at low temperature to form a compact second gate oxide layer consisting of the first gate oxide layer and the second oxide layer below the first gate oxide layer and a size-repaired second fin part consisting of the intrinsic layer and the first fin part inside the intrinsic layer. The method can repair the fin part size and the damaged crystal lattice, form a densified gate oxide layer and improve the performance of the device.
Description
Technical Field
The invention relates to the technical field of semiconductor integrated circuit processes, in particular to a method for forming a fin structure of a device.
Background
As FinFET device dimensions continue to shrink, the critical dimensions of fins are also shrinking accordingly. However, multiple steps in the fin process, such as shallow trench isolation annealing, gate oxide formation, etc., consume the fin, resulting in loss of critical dimensions of the fin.
Moreover, the lattice structure on the surface of the fin portion will also be damaged during the fin portion manufacturing process. After the well region ions are injected, the lattice structure of the fin part is damaged, and impurity ions are left on the fin part; the shallow trench isolation annealing process with certain oxidizability will diffuse oxygen to the fin surface. The damage of crystal lattices on the surface of the fin part can cause the trap density of the interface of the fin part and a gate oxide interface to be increased, the performance of a device is reduced, and meanwhile, the flicker noise of the device is increased.
In addition, conventional gate oxide generation methods, such as in-situ steam oxidation, post-nitridation annealing, and other high temperature steps, may cause ion diffusion problems in the N-well and the P-well, thereby degrading device performance.
Based on the problems of fin critical dimension loss, fin surface lattice damage and high temperature thermal budget, a new method for forming low temperature thermal budget gate oxide is needed to repair fin surface lattice and reduce fin critical dimension loss.
Disclosure of Invention
The present invention is directed to overcoming the above-mentioned drawbacks of the prior art and providing a method for forming a fin structure of a device.
In order to achieve the purpose, the technical scheme of the invention is as follows:
a method for forming a fin structure of a device comprises the following steps:
obtaining a substrate on which a first fin portion, shallow trench isolation and a well region are formed;
performing first low-temperature oxidation on the surface of the first fin part, and forming a first oxide layer on the surface of the first fin part in a shape-preserving manner;
removing the first oxidation layer in situ, and then forming an intrinsic layer of the first fin material on the exposed surface of the first fin in a shape-preserving manner;
carrying out second low-temperature oxidation on the intrinsic layer, and forming a second oxidation layer on the surface of the intrinsic layer in a conformal mode;
forming a first gate oxide layer on the second oxide layer by adopting a low-temperature deposition process;
and hardening and low-temperature annealing treatment are carried out on the first gate oxide layer and the second oxide layer.
Further, the first low-temperature oxidation and the second low-temperature oxidation methods include a low-temperature oxidation method using oxygen plasma as an oxidizing agent.
Further, the in-situ removal process includes a chemical oxide removal process.
Further, the conformally forming the intrinsic layer of the first fin material on the surface of the exposed first fin includes:
forming a single-crystal-shaped nuclear layer of the first fin part material on the surface of the first fin part in a shape-preserving manner by adopting an atomic layer deposition process;
then, a single-crystal intrinsic layer of the first fin material is formed conformally along the surface of the single-crystal nucleation layer.
Further, the low temperature deposition process comprises an atomic layer deposition process.
Further, the hardening treatment specifically includes:
firstly, enabling the first gate oxide layer and the second oxide layer to be in ozone for permeation treatment;
then, ultraviolet irradiation treatment is performed on the first gate oxide layer and the second oxide layer.
Further, the temperature of the infiltration treatment is 100 ℃ or less.
Further, the low temperature annealing treatment includes a rapid thermal annealing treatment.
Further, the time of the rapid thermal annealing is within 1 millisecond.
Further, the low temperature is 400 ℃ or lower.
According to the technical scheme, the surface of the first fin part (original fin part) is subjected to low-temperature oxidation treatment, the damaged lattice surface of the first fin part is converted into an oxide layer, and after in-situ removal, an intrinsic layer of a first fin part material is formed on the surface of the remaining first fin part in a shape-preserving manner, so that the size of the fin part and the damaged lattice are repaired; the intrinsic layer is subjected to low-temperature oxidation treatment, and an oxide layer formed on the surface of the intrinsic layer is used as a barrier layer, so that the consumption of oxygen to the fin part in the subsequent gate oxide process can be prevented; through hardening and low-temperature annealing treatment, a densified gate oxide layer can be formed. The invention adopts a low-temperature gate oxide forming process below 400 ℃, greatly reduces the ion diffusion problem of an N well and a P well caused by the conventional high-temperature thermal budget, can repair the crystal lattice damage on the surface of the fin part, and simultaneously ensures the size of the fin part and the quality of a gate oxide film layer, thereby improving the performance of the device.
Drawings
Fig. 1 is a flow chart illustrating a method of forming a fin structure of a device in accordance with a preferred embodiment of the present invention;
fig. 2-8 are schematic diagrams illustrating process steps for fabricating a fin structure of a device according to the method of fig. 1 in accordance with a preferred embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below, and it is obvious that the described embodiments are a part of the embodiments of the present invention, but not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention. Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. As used herein, the word "comprising" and similar words are intended to mean that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items.
The following describes embodiments of the present invention in further detail with reference to the accompanying drawings.
Referring to fig. 1, fig. 1 is a flow chart illustrating a method for forming a fin structure of a device according to a preferred embodiment of the invention. As shown in fig. 1, a method for forming a fin structure of a device according to the present invention may include:
step S1: and obtaining the substrate on which the first fin part, the shallow trench isolation and the well region are formed.
Please refer to fig. 2. A substrate 100 having a FinFET device portion structure formed thereon may be obtained, for example, by fabricating the silicon substrate 100 having the first fin 101, the shallow trench isolation 102, and the well region formed thereon by conventional processes.
In the conventional process, the lattice damage region 1011 is generated at the edge of the first fin 101 after the well implantation process. The following method of the present invention can be used to ameliorate this problem.
Step S2: and performing first low-temperature oxidation on the surface of the first fin portion, and forming a first oxidation layer on the surface of the first fin portion in a shape-preserving manner.
Please refer to fig. 3. In a preferred embodiment, when performing the first low temperature oxidation on the surface of the first fin 101, the first oxide layer 103 may be conformally formed on the surface of the first fin 101 by using a low temperature oxidation method using oxygen plasma as an oxidizing agent.
For example, an oxygen plasma atomic layer deposition process may be adopted, and the oxygen plasma is used to replace the reaction precursor, so that the oxygen plasma contacts the surface of the first fin 101, and is used as an oxidizing agent to oxidize the silicon material on the surface of the first fin 101, thereby conformally forming the silicon dioxide first oxide layer 103 on the surface of the first fin 101 by utilizing the characteristics of the atomic layer deposition process.
In the atomic layer deposition process, the silicon material on the surface of the first fin 101 may be oxidized by using an inert gas such as helium or argon as a carrier gas, but only an oxygen plasma as an oxidizing agent without using a conventional precursor.
The silicon dioxide first oxide layer 103 may be formed on the surface of the first fin 101 to a thickness of 2nm or less by controlling the atomic layer deposition process conditions.
By forming the first oxide layer 103 to a certain thickness on the surface of the first fin 101, the silicon in the lattice damage region 1011 existing on the surface of the first fin 101 may be converted into oxide for subsequent removal.
In a preferred embodiment, the low temperature oxidation temperature during the deposition of the atomic layer in this step may be below 400 ℃. For example, the low-temperature oxidation treatment temperature in this step may be 100 to 400 ℃.
And step S3: the first oxide layer is removed in situ, and then an intrinsic layer of the first fin material is conformally formed on the exposed surface of the first fin.
Please refer to fig. 4. In a preferred embodiment, the in-situ removal process may include a chemical oxide removal process. For example, HF or NH-containing chemical gas etching system method or COR (chemical oxide removal) chemical oxide removal system method, etc. under the trademark Certas can be used 3 The reaction method capable of removing oxide in (1) removes the first oxide layer 103 in situ, so that the shape of the first fin 101 after removing the first oxide layer 103 can be maintained.
After the first oxide layer 103 is removed, impurities on the surface of the first fin 101 are removed by oxidation, so that the remaining first fin 101 has a new surface with complete crystal lattices, and thus good repair is obtained.
Please refer to fig. 5. Next, a single crystal silicon layer needs to be formed on the surface of the first fin 101 after the first oxide layer 103 is removed, so as to repair the first fin 101 with a reduced size.
In a preferred embodiment, when performing the dimension repair on the first fin portion 101, an atomic layer deposition process may be adopted to form a single crystal silicon nucleation layer 104 conformal to the silicon material of the first fin portion 101 on the surface of the first fin portion 101; then, a monocrystalline silicon intrinsic layer (body layer) 105 is formed conformally along the surface of the monocrystalline silicon nucleation layer 104.
For example, an atomic layer deposition process may be used and a hot silicon nucleation layer 104 of single crystal silicon may be conformally formed on the silicon surface of the first fin 101 using diisopropylaminosilane (trade name LTO 520) as a precursor. Then, DS (disilane) is used as a precursor, and decomposition of DS along the surface of the single-crystal silicon nucleation layer 104 is caused, thereby forming a single-crystal silicon intrinsic layer 105 further conformally on the surface of the formed single-crystal silicon nucleation layer 104.
The single crystal silicon thermal silicon nucleation layer 104 and the single crystal silicon intrinsic layer 105 constitute a single crystal silicon liner layer 106 with a good step coverage profile on the first fin 101. Also, the newly grown monocrystalline silicon liner layer 106 on the first fin 101 has a perfect lattice with no defects.
In a preferred embodiment, the process temperature of the deposition process of the atomic layer in this step may be below 400 ℃. For example, the process temperature in this step may be 300 to 400 ℃; preferably, the process temperature in this step may be 380 ℃.
In a preferred embodiment, the thickness of the single crystal silicon hot silicon nucleation layer 104 formed in this step may be less than 2 nm.
Further, the thickness of the monocrystalline silicon pad layer 106 formed in this step may be 4nm or less.
In this step, a monocrystalline silicon liner layer 106 with a certain thickness is formed on the surface of the first fin 101 after the first oxide layer 103 is removed, so that the fin size and the damaged crystal lattice can be well repaired.
And step S4: and performing second low-temperature oxidation on the intrinsic layer to form a second oxidation layer on the surface of the intrinsic layer in a conformal manner.
Please refer to fig. 6. In a preferred embodiment, when performing the second low temperature oxidation on the surface of the intrinsic layer 105 made of monocrystalline silicon, the second oxide layer 108 is conformally formed on the surface of the intrinsic layer 105 made of monocrystalline silicon by a low temperature oxidation method using oxygen plasma as an oxidizing agent.
For example, an oxygen plasma atomic layer deposition process may be adopted, and oxygen plasma is substituted for the reaction precursor, so that the oxygen plasma contacts the surface of the monocrystalline silicon intrinsic layer 105, and is used as an oxidizing agent to oxidize the silicon material on the surface of the monocrystalline silicon intrinsic layer 105, thereby conformally forming the silicon dioxide second oxidation layer 108 on the surface of the monocrystalline silicon intrinsic layer 105 by utilizing the characteristics of the atomic layer deposition process.
In the atomic layer deposition process in this step, an inert gas such as helium or argon may be used as a carrier gas, but a conventional precursor is not used, and only oxygen plasma is used as an oxidizing agent to oxidize the silicon material on the surface of the monocrystalline silicon intrinsic layer 105.
A silicon dioxide second oxide layer 108 having a thickness of 2nm or less may be formed on the surface of the single crystal silicon intrinsic layer 105 (single crystal silicon liner layer 106) by controlling the atomic layer deposition process conditions.
In a preferred embodiment, the low temperature oxidation temperature during the deposition of the atomic layer in this step may be below 400 ℃. For example, the low-temperature oxidation treatment temperature in this step may be 100 to 400 ℃.
By forming the second oxide layer 108 with a certain thickness on the surface of the monocrystalline silicon intrinsic layer 105, the formed second oxide layer 108 can be used as a barrier layer to prevent the consumption of oxygen to the fin portion in the subsequent gate oxide deposition process.
Meanwhile, the radio frequency power in the atomic layer deposition process can be utilized to reduce hydrogen bonds in the monocrystalline silicon liner layer 106 and densify the monocrystalline silicon liner layer 106.
Step S5: and forming a first gate oxide layer on the second oxide layer by using a low-temperature deposition process.
Please refer to fig. 7. In a preferred embodiment, the low temperature deposition process may comprise an atomic layer deposition process.
For example, a high quality silicon dioxide first gate oxide layer 109 with a thickness of 1 to 4nm may be epitaxially grown on the silicon dioxide second oxide layer 108 using a conventional atomic layer deposition process.
At this time, since the fin portion is covered with the second oxide layer 108, a barrier layer is formed, so that the consumption of oxygen to the fin portion in the ald gate oxide process can be prevented.
Step S6: and hardening and low-temperature annealing treatment are carried out on the first gate oxide layer and the second oxide layer.
Please refer to fig. 8. In a preferred embodiment, when the first gate oxide layer 109 and the second oxide layer 108 are hardened, the first gate oxide layer 109 and the second oxide layer 108 may be subjected to an infiltration treatment in ozone; then, ultraviolet light irradiation treatment is performed on the first gate oxide layer 109 and the second oxide layer 108.
For example, the device having the above structure may be placed in a sealed cavity, ozone may be introduced into the sealed cavity, the first gate oxide layer 109 and the second oxide layer 108 are in an ozone atmosphere, the first gate oxide layer 109 and the second oxide layer 108 are subjected to permeation treatment with ozone, and hydrogen in the first gate oxide layer 109 and the second oxide layer 108 is replaced with oxygen.
In a preferred embodiment, the temperature of the infiltration process may be below 100 ℃.
Then, the first gate oxide layer 109 and the second oxide layer 108 are further subjected to ultraviolet irradiation treatment, and the irradiation energy of ultraviolet light is utilized to promote the breakage of the redundant hydrogen bonds in the first gate oxide layer 109 and the second oxide layer 108, and oxygen is used for substitution, so that the second gate oxide layer 110 which is more compact and can be highly close to the gate oxide quality formed by high-temperature oxidation or an ISSG process can be generated.
The first gate oxide layer 109 and the second oxide layer 108 located thereunder form a dense second gate oxide layer 110.
In a preferred embodiment, the low temperature annealing process may comprise a rapid thermal annealing process.
Further, the rapid thermal annealing may have a treatment temperature of 400 ℃ or less and a treatment time of 1 millisecond or less.
The second gate oxide layer 110 can be further densified by the low-temperature rapid thermal annealing treatment.
The second gate oxide layer 110 formed by the present invention has a film quality close to that of a gate oxide formed by a high temperature oxidation or ISSG process, so that high temperature steps such as DPN (decoupled plasma nitridation) and PNA (chemical vapor deposition) can be omitted.
Meanwhile, through the method, the second fin portion 107 with the repaired size, which is formed by the monocrystalline silicon intrinsic layer 105, the monocrystalline silicon nucleation layer 104 and the first fin portion 101 inside the monocrystalline silicon intrinsic layer, is formed.
In summary, the surface of the first fin portion 101 (original fin portion) is subjected to low-temperature oxidation treatment, so that the damaged lattice surface of the first fin portion 101 is converted into an oxide layer, and after in-situ removal, the intrinsic layer 105 of the material of the first fin portion 101 is conformally formed on the surface of the remaining first fin portion 101, and the repairing of the fin portion size and the damaged lattice is realized; the surface of the intrinsic layer 105 is subjected to low-temperature oxidation treatment, and the formed oxide layer is used as a barrier layer, so that the consumption of oxygen to the fin part in the subsequent gate oxide process can be prevented; through the hardening and low-temperature annealing treatment, a densified gate oxide layer (second gate oxide layer 110) may be formed. The invention adopts the low-temperature gate oxide forming process below 400 ℃, greatly reduces the ion diffusion problem of an N well and a P well caused by the traditional high-temperature thermal budget, can repair the crystal lattice damage on the surface of the fin part, and simultaneously ensures the size of the fin part and the quality of a gate oxide film layer, thereby improving the performance of the device.
Although the embodiments of the present invention have been described in detail hereinabove, it is apparent to those skilled in the art that various modifications and variations can be made to these embodiments. However, it is to be understood that such modifications and variations are within the scope and spirit of the present invention as set forth in the following claims. Moreover, the invention as described herein is capable of other embodiments and of being practiced or of being carried out in various ways.
Claims (10)
1. A method for forming a fin structure of a device, comprising:
obtaining a substrate on which a first fin portion, shallow trench isolation and a well region are formed;
performing first low-temperature oxidation on the surface of the first fin part, and forming a first oxide layer on the surface of the first fin part in a shape-preserving manner;
removing the first oxidation layer in situ, and then forming an intrinsic layer of the first fin material on the exposed surface of the first fin in a shape-preserving manner;
carrying out second low-temperature oxidation on the intrinsic layer, and forming a second oxidation layer on the surface of the intrinsic layer in a shape-preserving mode;
forming a first gate oxide layer on the second oxide layer by adopting a low-temperature deposition process;
and hardening and annealing the first gate oxide layer and the second oxide layer at a low temperature.
2. The method of claim 1, wherein the first low temperature oxidation and the second low temperature oxidation comprise low temperature oxidation with oxygen plasma as an oxidant.
3. The method of claim 1, wherein the in-situ removal comprises a chemical oxide removal.
4. The method of claim 1, wherein the conformally forming the intrinsic layer of the first fin material on the exposed surface of the first fin comprises:
forming a single-crystal-shaped nuclear layer of the first fin part material on the surface of the first fin part in a shape-preserving manner by adopting an atomic layer deposition process;
then, a single-crystal intrinsic layer of the first fin material is formed conformally along the surface of the single-crystal nucleation layer.
5. The method of claim 1, wherein the low temperature deposition process comprises an atomic layer deposition process.
6. The method of claim 1, wherein the hardening specifically comprises:
firstly, the first gate oxide layer and the second oxide layer are in ozone for permeation treatment;
then, ultraviolet irradiation treatment is performed on the first gate oxide layer and the second oxide layer.
7. The method of claim 6, wherein the temperature of the infiltration process is less than or equal to 100 ℃.
8. The method of claim 1, wherein the low temperature annealing process comprises a rapid thermal annealing process.
9. The method of claim 8, wherein the rapid thermal anneal is within 1 millisecond.
10. The method of claim 1, wherein the low temperature is less than 400 ℃.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211130462.6A CN115424937A (en) | 2022-09-15 | 2022-09-15 | Fin structure forming method of device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211130462.6A CN115424937A (en) | 2022-09-15 | 2022-09-15 | Fin structure forming method of device |
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