CN115423109A - Quantum state measuring method and device for sub-quantum circuit and quantum computer operating system - Google Patents

Quantum state measuring method and device for sub-quantum circuit and quantum computer operating system Download PDF

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CN115423109A
CN115423109A CN202110601286.9A CN202110601286A CN115423109A CN 115423109 A CN115423109 A CN 115423109A CN 202110601286 A CN202110601286 A CN 202110601286A CN 115423109 A CN115423109 A CN 115423109A
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方圆
俞磊
赵东一
窦猛汉
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Origin Quantum Computing Technology Co Ltd
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Abstract

The application discloses a quantum state measuring method and device of a quantum circuit and a quantum computer operating system, wherein the method comprises the following steps: obtaining the cut sub-quantum circuit; respectively preparing the initial quantum state of the quantum bit to a first quantum state and a second quantum state through a unitary matrix; and measuring the final quantum state of the quantum bit after the quantum wire is operated on the first measuring base and the second measuring base respectively. By adopting the method and the device, the cut sub-quantum wires can be converted into the sub-quantum wires which are actually operated on the quantum computing equipment, and the quantum state measurement can be carried out on the sub-quantum wires which are actually operated.

Description

Quantum state measuring method and device for sub-quantum circuit and quantum computer operating system
Technical Field
The present application relates to the field of quantum computing technologies, and in particular, to a method and an apparatus for measuring quantum states of a quantum line, and a quantum computer operating system.
Background
Human beings are currently in the key age of Quantum technology development-medium Quantum (NISQ) devices containing noise. Noise, such as limited coherence time, frequency selection of individual qubits, crosstalk between qubits, and limited control bandwidth, increases with increasing number of qubits, limiting the development of NISQ techniques. It is increasingly difficult to build a reliable quantum computing device.
At present, a commonly used method is to cut a quantum line with a large number of quantum bits into a plurality of sub-quantum lines with a small number of quantum bits, then operate the sub-quantum lines on a quantum computing device, and synthesize results obtained by the operation to obtain a simulation result of the quantum line before cutting. This approach is more reliable than running quantum wires with many qubits directly on a quantum computing device. One of the core problems of this approach is how the cut sub-quantum wires are converted into sub-quantum wires that actually run on the quantum computing device and quantum state measurements are performed on the actually running sub-quantum wires.
Disclosure of Invention
The embodiment of the application provides a quantum state measurement method and device for a sub-quantum line and a quantum computer operating system, which are used for converting the cut sub-quantum line into a sub-quantum line which actually runs on a quantum computing device and carrying out quantum state measurement on the actually running sub-quantum line.
In a first aspect, an embodiment of the present application provides a method for measuring a quantum state of a quantum wire, including:
acquiring a cut sub-quantum line, wherein the sub-quantum line comprises a first quantum bit and a second quantum bit, the time line of the first quantum bit is not cut, and the time line of the second quantum bit is cut;
preparing an initial quantum state of the first qubit to a first quantum state by a first unitary matrix; if the time line of the second quantum bit is the cut upstream time line, preparing the initial quantum state of the second quantum bit to the first quantum state through the first unitary matrix; if the time line of the second quantum bit is a downstream time line after cutting, preparing the initial quantum state of the second quantum bit to a second quantum state through a second unitary matrix, wherein the upstream time line is a time line before a cutting position, and the downstream time line is a time line after the cutting position;
measuring an end-quantum state of the first qubit after running the sub-quantum wire on a first measurement basis; if the time line of the second quantum bit is the downstream time line after cutting, measuring the last quantum state of the second quantum bit after operating the quantum circuit on the first measuring base; and if the time line of the second quantum bit is the cut upstream time line, measuring the final quantum state of the second quantum bit after the quantum circuit is operated on a second measuring base.
Alternatively, the quantum state points with the center O of the sphere in the Bloch sphere to a point S on the sphere i Directed line segment between
Figure BDA0003092798160000021
Represents the second quantum state
Figure BDA0003092798160000022
Pointed vertex S i Constituting a regular tetrahedron in the bloch sphere, wherein i is equal to 0,1, 2 or 3.
Optionally, the first quantum state is |0>Said second quantum state
Figure BDA0003092798160000023
A first unitary matrix corresponding to the first quantum state and the second quantum state is the same as the first quantum state
Figure BDA0003092798160000024
The corresponding second unitary matrix is an identity matrix I;
wherein, the
Figure BDA0003092798160000025
Optionally, the
Figure BDA0003092798160000026
Is composed of
Figure BDA0003092798160000027
The above-mentioned
Figure BDA0003092798160000028
Is composed of
Figure BDA0003092798160000029
The above-mentioned
Figure BDA00030927981600000210
Is composed of
Figure BDA00030927981600000211
The above-mentioned
Figure BDA00030927981600000212
Corresponding to the second unitary matrix of
Figure BDA00030927981600000213
The above-mentioned
Figure BDA00030927981600000214
Corresponding to the second unitary matrix of
Figure BDA00030927981600000215
The above-mentioned
Figure BDA00030927981600000216
Corresponding to the second unitary matrix of
Figure BDA00030927981600000217
Wherein,
Figure BDA00030927981600000218
optionally, the first measurement base is Z, and the second measurement base is Z, X, Y; wherein, the
Figure BDA00030927981600000219
The above-mentioned
Figure BDA00030927981600000220
The above-mentioned
Figure BDA00030927981600000221
Optionally, the Pauli characteristic state corresponding to Z is
Figure BDA00030927981600000222
Or
Figure BDA00030927981600000223
The characteristic state of the Pauli corresponding to the X is
Figure BDA00030927981600000224
Or
Figure BDA00030927981600000225
The characteristic state of the Pauli corresponding to the Y is
Figure BDA00030927981600000226
Or
Figure BDA00030927981600000227
In a second aspect, an embodiment of the present application provides a quantum line quantum state measurement apparatus, including:
a line obtaining unit, configured to obtain a cut sub-quantum line, where the sub-quantum line includes a first qubit and a second qubit, a timeline in which the first qubit is located is not cut, and a timeline in which the second qubit is located is already cut;
a quantum state preparation unit, configured to prepare an initial quantum state of the first qubit to a first quantum state by a first unitary matrix; if the time line of the second quantum bit is the cut upstream time line, preparing the initial quantum state of the second quantum bit to the first quantum state through the first unitary matrix; if the time line of the second quantum bit is a downstream time line after cutting, preparing the initial quantum state of the second quantum bit to a second quantum state through a second unitary matrix, wherein the upstream time line is a time line before a cutting position, and the downstream time line is a time line after the cutting position;
a quantum state measurement unit for measuring an end quantum state of the first qubit after the quantum circuit is operated on a first measurement basis; if the time line of the second quantum bit is the downstream time line after cutting, measuring the last quantum state of the second quantum bit after operating the quantum circuit on the first measuring base; and if the time line of the second quantum bit is the cut upstream time line, measuring the final quantum state of the second quantum bit after the quantum circuit is operated on a second measuring base.
In a third aspect, an embodiment of the present application provides an electronic device, including a processor, a memory, a communication interface, and one or more programs, where the one or more programs are stored in the memory and configured to be executed by the processor, and the program includes instructions for executing steps in the method according to the first aspect of the embodiment of the present application.
In a fourth aspect, the present application provides a computer-readable storage medium, where the computer-readable storage medium stores a computer program for electronic data exchange, where the computer program makes a computer perform some or all of the steps described in the method according to the first aspect of the present application.
In a fifth aspect, the present application provides a computer program product, where the computer program product includes a non-transitory computer-readable storage medium storing a computer program, where the computer program is operable to cause a computer to perform some or all of the steps described in the method according to the first aspect of the present application. The computer program product may be a software installation package.
In a sixth aspect, the present application provides a quantum computer operating system, wherein the quantum computer operating system measures the quantum state of the sub-quantum wire according to some or all of the steps described in the method according to the first aspect of the present application.
It can be seen that, in the embodiment of the present application, the initial quantum state of the first qubit is prepared to a first quantum state by a first unitary matrix; if the time line of the second quantum bit is the cut upstream time line, preparing the initial quantum state of the second quantum bit to the first quantum state through the first unitary matrix; if the time line of the second quantum bit is the downstream time line after cutting, the initial quantum state of the second quantum bit is prepared to the second quantum state through a second unitary matrix, the upstream time line is the time line before the cutting position, the downstream time line is the time line after the cutting position, and the quantum bits are prepared to different initial quantum states through different unitary matrices according to the type of the time line of the quantum bit, so that the preparation of the initial quantum state of each quantum bit of the sub-quantum circuit after cutting is realized, and further, the sub-quantum circuit after cutting is converted into the sub-quantum circuit which actually runs on the quantum computing device.
Simultaneously, measuring an end quantum state of the first qubit after the quantum wire is operated on a first measurement basis; if the time line of the second quantum bit is the downstream time line after cutting, measuring the last quantum state of the second quantum bit after operating the quantum circuit on the first measuring base; and if the time line of the second quantum bit is the cut upstream time line, measuring the last quantum state of the second quantum bit after the operation of the sub-quantum circuit on a second measuring basis, and measuring the last quantum state of each quantum bit on different measuring bases according to the type of the time line of the quantum bit, thereby realizing the measurement of the last quantum state of each quantum bit of the actually operated sub-quantum circuit.
These and other aspects of the present application will be more readily apparent from the following description of the embodiments.
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In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the embodiments or the prior art descriptions will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1A is a block diagram of a hardware structure of a computer terminal of a quantum wire quantum state measurement method according to an embodiment of the present disclosure;
FIG. 1B is a schematic diagram of a graphical display of a quantum wire as provided in an embodiment of the present application;
fig. 2A is a schematic flowchart of a quantum state measurement method of a quantum wire according to an embodiment of the present disclosure;
fig. 2B is a schematic diagram of a process of cutting quantum wires into sub-quantum wires according to an embodiment of the present application;
fig. 2C is a schematic diagram of a bloch sphere provided in an embodiment of the present application;
fig. 2D is a schematic structural diagram of a second quantum state provided in an embodiment of the present application;
fig. 3 is a schematic structural diagram of an electronic device according to an embodiment of the present disclosure;
fig. 4 is a schematic structural diagram of a quantum wire quantum state measurement apparatus according to an embodiment of the present disclosure.
Detailed Description
In order to make the technical solutions of the present application better understood by those skilled in the art, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only some embodiments of the present application, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The following are detailed below.
The terms "first," "second," "third," and "fourth," etc. in the description and claims of this application and in the accompanying drawings are used for distinguishing between different elements and not for describing a particular sequential order. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.
Fig. 1A is a block diagram of a hardware structure of a computer terminal of a quantum line quantum state measurement method according to an embodiment of the present disclosure.
Referring to fig. 1A, the computer terminal may include one or more (only one is shown in fig. 1A) processors 102 (the processors 102 may include, but are not limited to, a processing device such as a microprocessor MCU or a programmable logic device FPGA) and a memory 104 for storing data, and optionally, a transmission device 106 for communication functions and an input-output device 108. It will be understood by those skilled in the art that the structure shown in fig. 1A is only an illustration, and is not intended to limit the structure of the computer terminal. For example, the computer terminal may also include more or fewer components than shown in FIG. 1A, or have a different configuration than shown in FIG. 1A.
The memory 104 may be used to store software programs and modules of application software, such as program instructions/modules corresponding to the quantum state measurement method of the sub-quantum wire in the embodiment of the present application, and the processor 102 executes various functional applications and data processing by running the software programs and modules stored in the memory 104, so as to implement the above-mentioned method. The memory 104 may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include memory located remotely from the processor 102, which may be connected to the computer terminal 10 via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
The transmission device 106 is used for receiving or transmitting data via a network. Specific examples of the network described above may include a wireless network provided by a communication provider of the computer terminal 10. In one example, the transmission device 106 includes a Network adapter (NIC) that can be connected to other Network devices through a base station so as to communicate with the internet. In one example, the transmission device 106 can be a Radio Frequency (RF) module, which is used to communicate with the internet in a wireless manner.
It should be noted that, the quantum program referred to in the embodiments of the present application is a program written in a classical language and representing a qubit and its evolution, where the qubit, a quantum logic gate, and the like related to quantum computation are all represented by corresponding classical codes.
A quantum circuit, which is an embodiment of a quantum program and also a weighing sub-logic circuit, is the most common general quantum computation model, and represents a circuit that operates on a quantum bit under an abstract concept, and the circuit includes the quantum bit, a circuit (timeline), and various quantum logic gates, and finally, a result is often read through a quantum measurement operation. The quantum wires may be presented in a sequence of quantum logic gates arranged in a certain execution sequence.
Specifically, for example, a quantum program:
QCircuitcir；
cir<<H(q[0])<<H(q[1])<<H(q[2])<<H(q[3])<<RZ(q[0],PI/2)<<RY(q[1],PI/4)<<RZ(q[2],PI/4)<<CNOT(q[0],q[1])<<CR(q[1],q[2],PI/3)<<CNOT(q[2],q[3])<<CNOT(q[0],q[3]).
the corresponding quantum wire (denoted as 1# quantum wire) can be expressed as:
q[0]:H(q[0])、RZ(q[0],PI/2)
q[1]:H(q[1])、RY(q[1],PI/4)、CNOT(q[0],q[1])
q[2]:H(q[2])、RZ(q[2],-PI/4)、CR(q[1],q[2],PI/3)
q[3]:H(q[3])、CNOT(q[2],q[3])、CNOT(q[0],q[3])
wherein q [0]]、q[1]、q[2]、q[3]Refers to a qubit with bits from 0 to 3, which can also be generally denoted as q 0 、q 1 、q 2 、q 3 。
In a more visual presentation, a quantum circuit diagram corresponding to the quantum logic gate sequence is shown with reference to fig. 1B.
Unlike conventional circuits that are connected by metal lines to pass either voltage or current signals, in quantum circuits, the lines can be viewed as being connected by time, i.e., the state of a qubit evolves naturally over time, in the process being operated on by the hamiltonian until encountering a quantum logic gate.
A quantum program corresponds to an overall quantum circuit as a whole, and the quantum program refers to the overall quantum circuit, wherein the total number of quantum bits in the overall quantum circuit is the same as the total number of quantum bits of the quantum program. It can be understood that: a quantum program may consist of quantum wires, measurement operations for quantum bits in the quantum wires, registers to hold measurement results, and control flow nodes (jump instructions), and a quantum wire may contain tens to hundreds or even thousands of quantum gate operations. The execution process of the quantum program is a process executed for all the quantum logic gates according to a certain time sequence. It should be noted that the timing is the time sequence in which the single quantum logic gate is executed.
It should be noted that in the classical calculation, the most basic unit is a bit, and the most basic control mode is a logic gate, and the purpose of the control circuit can be achieved through the combination of the logic gates. Similarly, the way qubits are handled is quantum logic gates. The quantum state can be evolved by using quantum logic gates, which are the basis for forming quantum circuits, including single-bit quantum logic gates (or single-quantum logic gates, abbreviated as "single gates"), such as Hadamard gates (H gates, hadamard gates), pauli-X gates (X gates), pauli-Y gates (Y gates), pauli-Z gates (Z gates), RX gates, RY gates, RZ gates, and the like; two-bit quantum logic gates (or double quantum logic gates, abbreviated as "double gates"), such as CNOT gates, CR gates, SWAP gates, isswap gates, and so on; a multi-bit quantum logic gate (or a multi-quantum logic gate, abbreviated as "multi-gate"), such as a Toffoli gate, etc. Quantum logic gates are typically represented using unitary matrices, which are not only matrix-form but also an operation and transformation. The function of a general quantum logic gate on a quantum state is calculated by multiplying a unitary matrix by a matrix corresponding to a quantum state right vector.
For example, a quantum state right vector |0>Corresponding vector is
Figure BDA0003092798160000081
Quantum state right vector |1>Corresponding vector is
Figure BDA0003092798160000082
A quantum state, i.e., the logical state of a qubit. In quantum algorithms (or quantum programs), binary representation is adopted for quantum states of a group of quantum bits included in a quantum circuit, for example, a group of quantum bits are q0, q1, and q2, which represent 0 th, 1 st, and 2 nd quantum bits, and are ordered from high to low in the binary representation as q2q1q0, and quantum states corresponding to the group of quantum bits have 2 quanta to the power of the total number of quantum bits, that is, 8 eigenstates (determined states): |000>、|001>、|010>、|011>、|100>、|101>、|110>、|111>The bits of each quantum state correspond to qubits, e.g. |001>State 001 from high to low corresponding to q2q1q0, a>Is a dirac symbol. For a bit containing N quanta q 0 、q 1 、…、q n 、…、q N-1 The order of the binary representation quantum state of the quantum line is q N-1 q N-2 …、q 1 q 0 。
Illustrated in the form of a single quantum bit,the logic state psi of a single qubit may be at |0>State, |1>State, |0>Sum of states |1>The superimposed state (indeterminate state) of the states can be expressed specifically as ψ = a |0>+b|1>Where a and b are complex numbers representing the amplitude (amplitude of probability) of the quantum state, the square of the modulus of the amplitude represents the probability, a 2 、b 2 Respectively indicate that the logic states are |0>State, |1>Probability of state, | a 2 +|b| 2 =1. In short, a quantum state is a superposition state of the eigenstates, and is in a uniquely determined eigenstate when the probability of other states is 0.
The following further describes a quantum wire quantum state measurement method provided by an embodiment of the present application with reference to the drawings.
Referring to fig. 2A, fig. 2A is a schematic flow chart of a method for measuring a quantum state of a quantum wire according to an embodiment of the present disclosure, where the method includes:
step 201: and acquiring the cut sub-quantum line, wherein the sub-quantum line comprises a first quantum bit and a second quantum bit, the time line of the first quantum bit is not cut, and the time line of the second quantum bit is cut.
As shown in fig. 2B, fig. 2B is a schematic diagram of a process of cutting a quantum wire into sub-quantum wires according to an embodiment of the present disclosure. The raw quantum wire is cut into two sub-quantum wires by the two cutting positions illustrated: sub-quantum wires 1 and sub-quantum wires 2. The time lines of qubits q1 and q 3 in the original qubit line are cut, while the time lines of qubits q0 and q2 are not cut.
Step 202: preparing an initial quantum state of the first qubit to a first quantum state by a first unitary matrix; if the time line of the second quantum bit is the cut upstream time line, preparing the initial quantum state of the second quantum bit to the first quantum state through the first unitary matrix; and if the time line of the second qubit is a downstream time line after cutting, preparing the initial quantum state of the second qubit to a second quantum state through a second unitary matrix, wherein the upstream time line is a time line before the cutting position, and the downstream time line is a time line after the cutting position.
The initial quantum state may be |0>, |1>, or a superposition of |0> and |1 >. In quantum algorithms and experiments, the initial quantum state is generally defaulted to the ground state |0>.
As shown in FIG. 2B, the time line of the qubit q [1] in the sub-quantum line 1 is the downstream time line, and the time line of the qubit q [3] is the upstream time line; the time line in which qubit q [1] is located in sub-quantum line 2 is the upstream time line, and the time line in which qubit q [3] is located is the downstream time line.
Step 203: measuring an end-quantum state of the first qubit after the execution of the sub-quantum wire on a first measurement basis; if the time line of the second quantum bit is a downstream time line after the cutting position, measuring the final quantum state of the second quantum bit after the operation of the sub-quantum circuit on the first measuring base; and if the time line of the second quantum bit is the upstream time line after the cutting position, measuring the final quantum state of the second quantum bit after the quantum circuit is operated on a second measuring base.
Wherein the cut sub-quantum wires are first sub-quantum wires, and the sub-quantum wires that allow actual operation in the electronic device after the quantum bits in the first sub-quantum wires are prepared into the quantum state are second sub-quantum wires. The number of the second sub-quantum wires is determined based on the second quantum state, the first measurement base, an upstream timeline and a downstream timeline in the first sub-quantum wire.
Further, the number of the second quantum states is m, the number of the second measurement bases is n, the number of upstream timelines in the first sub-quantum circuit is p, the number of downstream timelines in the first sub-quantum circuit is q, and then the number of the second sub-quantum circuits is m p ·n q 。
It can be seen that in the embodiments of the present application, the initial quantum state of the first qubit is prepared to a first quantum state by a first unitary matrix; if the time line of the second quantum bit is the cut upstream time line, preparing the initial quantum state of the second quantum bit to the first quantum state through the first unitary matrix; if the time line of the second quantum bit is the downstream time line after cutting, the initial quantum state of the second quantum bit is prepared to the second quantum state through a second unitary matrix, the upstream time line is the time line before the cutting position, the downstream time line is the time line after the cutting position, and the quantum bits are prepared to different initial quantum states through different unitary matrices according to the type of the time line of the quantum bit, so that the preparation of the initial quantum state of each quantum bit of the sub-quantum circuit after cutting is realized, and further, the sub-quantum circuit after cutting is converted into the sub-quantum circuit which actually runs on the quantum computing device.
Simultaneously, measuring an end quantum state of the first qubit after the operation of the sub-quantum wire on a first measurement basis; if the time line of the second quantum bit is the downstream time line after cutting, measuring the last quantum state of the second quantum bit after the quantum circuit is operated on the first measurement base; and if the time line of the second quantum bit is the cut upstream time line, measuring the last quantum state of the second quantum bit after the operation of the sub-quantum circuit on a second measuring basis, and measuring the last quantum state of each quantum bit on different measuring bases according to the type of the time line of the quantum bit, thereby realizing the measurement of the last quantum state of each quantum bit of the actually operated sub-quantum circuit.
In one embodiment of the present application, the quantum state is directed in a Bloch sphere with the center O pointing to a point S on the sphere surface i Directed line segment between
Figure BDA0003092798160000101
Represents the second quantum state
Figure BDA0003092798160000102
Pointed vertex S i Constituting a regular tetrahedron in the Bloch sphere, wherein i is equal to 0,1. 2 or 3.
Referring to fig. 2C, fig. 2C is a schematic diagram of a bloch ball according to an embodiment of the present disclosure. As shown in fig. 2C, the sphere center of bloch coincides with the origin O of the rectangular coordinate system. For any point S in the Bloch sphere i Can use the coordinates of a sphere
Figure BDA0003092798160000103
Representing or using rectangular coordinates
Figure BDA0003092798160000104
Figure BDA0003092798160000105
Which shows that the radius r of the bloch sphere is 1. For directed line segments
Figure BDA0003092798160000106
The corresponding quantum state can be represented as:
Figure BDA0003092798160000107
theta is in the range of [0, pi ]]，
Figure BDA0003092798160000108
The value range is [0, 2]]。
It can be seen that in the embodiment of the present application, by taking the four vertices of the inscribed regular tetrahedron of the bloch sphere as the second quantum states, the preparation of the initial quantum states of the second qubits is achieved. In an embodiment of the present application, the first quantum state is |0>The second quantum state
Figure BDA0003092798160000109
A first unitary matrix corresponding to the first quantum state and the second quantum state is the same as the first quantum state
Figure BDA00030927981600001010
The corresponding second unitary matrix is an identity matrix I;
wherein, the
Figure BDA0003092798160000111
For the first quantum state |0>:
Figure BDA0003092798160000112
according to the formula of the angle of two times of trigonometric function, S can be obtained 0 Has a rectangular coordinate of (0, 1). According to the relation between the height h of a regular tetrahedron and the radius r of a circumscribed Bloch sphere: h =4r/3, S can be obtained 1 、S 2 、S 3 Is located at x 2 +y 2 8/9,z = -1/3 circle.
Wherein, the quantum state is unchanged after the unit matrix acts on |0>, and is still |0>.
It can be seen that in the embodiments of the present application, the first quantum state and the second quantum state are formed by
Figure BDA0003092798160000113
Is set to |0>And the preparation of the initial quantum state of the first qubit and the second qubit is realized. In an embodiment of the present application, the
Figure BDA0003092798160000114
Is composed of
Figure BDA0003092798160000115
The described
Figure BDA00030927981600001131
Is composed of
Figure BDA0003092798160000116
The described
Figure BDA0003092798160000117
Is composed of
Figure BDA0003092798160000118
The above-mentioned
Figure BDA0003092798160000119
Corresponding to the second unitary matrix of
Figure BDA00030927981600001110
The above-mentioned
Figure BDA00030927981600001111
Corresponding to the second unitary matrix of
Figure BDA00030927981600001112
The described
Figure BDA00030927981600001113
Corresponding to the second unitary matrix of
Figure BDA00030927981600001114
Wherein,
Figure BDA00030927981600001115
referring to fig. 2D, fig. 2D is a schematic structural diagram of a second quantum state provided in the embodiment of the present application. Wherein, according to S 0 (0,0,1), cos θ = -1/3 can be obtained.
For the
Figure BDA00030927981600001116
Figure BDA00030927981600001117
According to the formula of double angles of trigonometric function, S can be obtained 1 Has rectangular coordinates of
Figure BDA00030927981600001118
Similarly, the coordinates of the other three vertexes of the regular tetrahedron can be determined as S 0 (0，0，1)，
Figure BDA00030927981600001119
Figure BDA00030927981600001120
It can be seen that in the embodiments of the present application, the first quantum state and the second quantum state are formed by
Figure BDA00030927981600001121
Is set to |0>Second quantum state
Figure BDA00030927981600001122
Is arranged as
Figure BDA00030927981600001123
Second quantum state
Figure BDA00030927981600001124
Is arranged as
Figure BDA00030927981600001125
Second quantum state
Figure BDA00030927981600001126
Is arranged as
Figure BDA00030927981600001127
The preparation of the initial quantum state of the first qubit and the second qubit is realized.
In an embodiment of the present application, the first measurement base is Z, and the second measurement base is Z, X, Y; wherein, the
Figure BDA00030927981600001128
The above-mentioned
Figure BDA00030927981600001129
The above-mentioned
Figure BDA00030927981600001130
Wherein,the quantum logic gate corresponding to the measurement operation on the second measurement base Z is the I gate, the quantum logic gate corresponding to the measurement operation on the second measurement base X is the H gate, and the quantum logic gate corresponding to the measurement operation on the second measurement base Y is the H gate
Figure BDA0003092798160000121
And H;
wherein,
Figure BDA0003092798160000122
in the examples of this application, the second quantum state is
Figure BDA0003092798160000123
The number is 4; the first measuring bases are X, Y and Z, and the number of the first measuring bases is 3; for the first sub-quantum-wire shown in fig. 2B: sub-quantum wires 1 and 2, m being the number of the second sub-quantum wires p ·n q Each of the first sub-quantum wires may be obtained as 12 second sub-quantum wires.
In an embodiment of the present application, the Pauli characteristic state corresponding to Z is
Figure BDA0003092798160000124
Or
Figure BDA0003092798160000125
The characteristic state of the Pauli corresponding to the X is
Figure BDA0003092798160000126
Or
Figure BDA0003092798160000127
The characteristic state of the Pauli corresponding to the Y is
Figure BDA0003092798160000128
Or
Figure BDA0003092798160000129
The pauli characteristic state corresponding to the first measurement basis can be determined according to the long-term equation H | ψ > = E | ψ >, where H is the hamilton, E is the eigenvalue corresponding to H, and | ψ > is the eigenstate corresponding to H. For example, for the second measurement base Z, according to the long term equation:
Figure BDA00030927981600001210
it is possible to obtain, E =1,
Figure BDA00030927981600001211
E＝-1，
Figure BDA00030927981600001212
similarly, X corresponds to the Pauli characteristic state X p And X m The characteristic state of Pauli corresponding to Y p And Y m All can be calculated by the long term equation.
In accordance with the embodiment shown in fig. 2A, please refer to fig. 3, fig. 3 is a schematic structural diagram of an electronic device according to an embodiment of the present application, and as shown in fig. 3, the electronic device includes a processor, a memory, a communication interface, and one or more programs, where the one or more programs are stored in the memory and configured to be executed by the processor, and the program includes instructions for performing the following steps:
obtaining a cut sub-quantum circuit, wherein the sub-quantum circuit comprises a first quantum bit and a second quantum bit, the time line of the first quantum bit is not cut, and the time line of the second quantum bit is cut;
preparing an initial quantum state of the first qubit to a first quantum state by a first unitary matrix; if the time line of the second quantum bit is the cut upstream time line, preparing the initial quantum state of the second quantum bit to the first quantum state through the first unitary matrix; if the time line of the second quantum bit is the downstream time line after cutting, the initial quantum state of the second quantum bit is prepared to a second quantum state through a second unitary matrix, the upstream time line is the time line before the cutting position, and the downstream time line is the time line after the cutting position;
measuring an end-quantum state of the first qubit after running the sub-quantum wire on a first measurement basis; if the time line of the second quantum bit is a downstream time line after the cutting position, measuring the final quantum state of the second quantum bit after the operation of the sub-quantum circuit on the first measuring base; and if the time line of the second quantum bit is the upstream time line after the cutting position, measuring the final quantum state of the second quantum bit after the quantum circuit is operated on a second measuring base.
In one embodiment of the present application, the quantum state is directed in a Bloch sphere with the center O pointing to a point S on the sphere surface i Directed line segment between
Figure BDA0003092798160000131
Represents the second quantum state
Figure BDA0003092798160000132
Pointed vertex S i Constituting a regular tetrahedron in the bloch sphere, wherein i is equal to 0,1, 2 or 3.
In an embodiment of the present application, the first quantum state is |0>Said second quantum state
Figure BDA0003092798160000133
A first unitary matrix corresponding to the first quantum state and the second quantum state is the same as the first quantum state
Figure BDA0003092798160000134
The corresponding second unitary matrix is an identity matrix I.
In an embodiment of the present application, the
Figure BDA0003092798160000135
Is composed of
Figure BDA0003092798160000136
The described
Figure BDA0003092798160000137
Is composed of
Figure BDA0003092798160000138
The above-mentioned
Figure BDA0003092798160000139
Is composed of
Figure BDA00030927981600001310
The above-mentioned
Figure BDA00030927981600001311
Corresponding to the second unitary matrix being U 3 (-1.9106332, π, 0), said
Figure BDA00030927981600001312
Corresponding to the second unitary matrix being U 3 (-1.9106332, π/3,0), said
Figure BDA00030927981600001313
The corresponding second unitary matrix is U 3 (-1.9106332, - π/3,0); wherein, the
Figure BDA00030927981600001314
Figure BDA00030927981600001315
In an embodiment of the present application, the first measurement base is Z, and the second measurement base is Z, X, Y; wherein, the
Figure BDA00030927981600001316
The above-mentioned
Figure BDA00030927981600001317
The described
Figure BDA00030927981600001318
In an embodiment of the present application, the pauli characteristic state corresponding to Z is
Figure BDA00030927981600001319
Or
Figure BDA00030927981600001320
The characteristic state of the Pauli corresponding to the X is
Figure BDA00030927981600001321
Or
Figure BDA00030927981600001322
The characteristic state of the Pauli corresponding to the Y is
Figure BDA00030927981600001323
Or
Figure BDA00030927981600001324
It should be noted that, for the specific implementation process of the present embodiment, reference may be made to the specific implementation process described in the above method embodiment, and a description thereof is omitted here.
In the embodiment of the present application, the electronic device may be divided into the functional units according to the method example, for example, each functional unit may be divided corresponding to each function, or two or more functions may be integrated into one processing unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit. It should be noted that the division of the unit in the embodiment of the present application is schematic, and is only a logic function division, and there may be another division manner in actual implementation.
The following is an embodiment of the apparatus of the present application, which is used to execute the method implemented by the embodiment of the method of the present application. Referring to fig. 4, fig. 4 is a schematic structural diagram of a quantum wire quantum state measurement apparatus according to an embodiment of the present application, including:
a line obtaining unit 401, configured to obtain a cut sub-quantum line, where the sub-quantum line includes a first qubit and a second qubit, a time line of the first qubit is not cut, and a time line of the second qubit is cut;
a quantum state preparation unit 402 configured to prepare an initial quantum state of the first qubit to a first quantum state by a first unitary matrix; if the time line of the second quantum bit is the cut upstream time line, preparing the initial quantum state of the second quantum bit to the first quantum state through the first unitary matrix; if the time line of the second quantum bit is the downstream time line after cutting, the initial quantum state of the second quantum bit is prepared to a second quantum state through a second unitary matrix, the upstream time line is the time line before the cutting position, and the downstream time line is the time line after the cutting position;
a quantum state measurement unit 403, configured to measure an end quantum state of the first qubit after the quantum wire is operated on a first measurement basis; if the time line of the second quantum bit is the downstream time line after cutting, measuring the last quantum state of the second quantum bit after operating the quantum circuit on the first measuring base; and if the time line of the second quantum bit is the cut upstream time line, measuring the final quantum state of the second quantum bit after the quantum circuit is operated on a second measuring base.
In one embodiment of the present application, the quantum state is directed in a Bloch sphere with the center O pointing to a point S on the sphere surface i Directed line segment between
Figure BDA0003092798160000141
Represents the second quantum state
Figure BDA0003092798160000142
Pointed vertex S i Constituting a regular tetrahedron in the bloch sphere, wherein i is equal to 0,1, 2 or 3.
In an embodiment of the present application, theThe first quantum state is |0>Said second quantum state
Figure BDA0003092798160000143
A first unitary matrix corresponding to the first quantum state and the second quantum state is the same as the first quantum state
Figure BDA0003092798160000144
The corresponding second unitary matrix is an identity matrix I.
In an embodiment of the present application, the
Figure BDA0003092798160000145
Is composed of
Figure BDA0003092798160000146
The above-mentioned
Figure BDA0003092798160000147
Is composed of
Figure BDA0003092798160000148
The above-mentioned
Figure BDA0003092798160000149
Is composed of
Figure BDA00030927981600001410
The above-mentioned
Figure BDA00030927981600001411
Corresponding to the second unitary matrix of
Figure BDA00030927981600001412
The described
Figure BDA00030927981600001413
Corresponding to the second unitary matrix of
Figure BDA00030927981600001414
The above-mentioned
Figure BDA00030927981600001415
The corresponding second unitary matrix is
Figure BDA00030927981600001416
Wherein, the
Figure BDA00030927981600001417
Figure BDA0003092798160000151
In an embodiment of the present application, the first measurement base is Z, and the second measurement base is Z, X, Y; wherein, the
Figure BDA0003092798160000152
The above-mentioned
Figure BDA0003092798160000153
The described
Figure BDA0003092798160000154
In an embodiment of the present application, the pauli characteristic state corresponding to Z is
Figure BDA0003092798160000155
Or
Figure BDA0003092798160000156
The characteristic state of the Pauli corresponding to the X is
Figure BDA0003092798160000157
Or
Figure BDA0003092798160000158
The characteristic state of the Pauli corresponding to the Y is
Figure BDA0003092798160000159
Or
Figure BDA00030927981600001510
It should be noted that the line obtaining unit 401, the quantum state preparing unit 402, and the quantum state measuring unit 403 may be implemented by a processor.
Embodiments of the present application further provide a computer-readable storage medium, where the computer-readable storage medium stores a computer program for electronic data exchange, the computer program enables a computer to execute some or all of the steps of any one of the methods as set forth in the above method embodiments, and the computer includes an electronic device.
Embodiments of the present application also provide a computer program product comprising a non-transitory computer readable storage medium storing a computer program operable to cause a computer to perform some or all of the steps of any one of the methods as set out in the above method embodiments. The computer program product may be a software installation package, the computer comprising an electronic device.
The embodiments of the present application further provide a quantum computer operating system, which implements the cutting processing of the quantum computing circuit according to part or all of the steps of any one of the methods described in the above method embodiments.
It should be noted that, for simplicity of description, the above-mentioned method embodiments are described as a series of acts or combination of acts, but those skilled in the art will recognize that the present application is not limited by the order of acts described, as some steps may occur in other orders or concurrently depending on the application. Further, those skilled in the art should also appreciate that the embodiments described in the specification are preferred embodiments and that the acts and modules referred to are not necessarily required in this application.
In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus may be implemented in other manners. For example, the above-described embodiments of the apparatus are merely illustrative, and for example, the above-described division of the units is only one type of division of logical functions, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of some interfaces, devices or units, and may be an electric or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one position, or may be distributed on multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The integrated unit may be stored in a computer readable memory if it is implemented in the form of a software functional unit and sold or used as a stand-alone product. Based on such understanding, the technical solution of the present application may be substantially implemented or a part of or all or part of the technical solution contributing to the prior art may be embodied in the form of a software product stored in a memory, and including several instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the above-mentioned method of the embodiments of the present application. And the aforementioned memory comprises: a U-disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic or optical disk, and other various media capable of storing program codes.
Those skilled in the art will appreciate that all or part of the steps in the methods of the above embodiments may be implemented by associated hardware instructed by a program, which may be stored in a computer-readable memory, which may include: flash Memory disks, read-Only memories (ROMs), random Access Memories (RAMs), magnetic or optical disks, and the like.
The foregoing detailed description of the embodiments of the present application has been presented to illustrate the principles and implementations of the present application, and the above description of the embodiments is only provided to help understand the method and the core concept of the present application; meanwhile, for a person skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.

Claims (10)

1. A method for measuring a quantum state of a quantum wire, comprising:
acquiring a cut sub-quantum line, wherein the sub-quantum line comprises a first quantum bit and a second quantum bit, the time line of the first quantum bit is not cut, and the time line of the second quantum bit is cut;
preparing an initial quantum state of the first qubit to a first quantum state by a first unitary matrix; if the time line of the second quantum bit is the cut upstream time line, preparing the initial quantum state of the second quantum bit to the first quantum state through the first unitary matrix; if the time line of the second quantum bit is the downstream time line after cutting, the initial quantum state of the second quantum bit is prepared to a second quantum state through a second unitary matrix, the upstream time line is the time line before the cutting position, and the downstream time line is the time line after the cutting position;
measuring an end-quantum state of the first qubit after running the sub-quantum wire on a first measurement basis; if the time line of the second quantum bit is the downstream time line after the cutting position, measuring the last quantum state of the second quantum bit after the quantum circuit is operated on the first measurement base; and if the time line of the second quantum bit is the upstream time line after the cutting position, measuring the final quantum state of the second quantum bit after the quantum circuit is operated on a second measuring base.
2. The method of claim 1, wherein the quantum state is directed in the bloch sphere with the center O to a point S on the sphere i Directional line segment between
Figure FDA0003092798150000011
Represent the second quantum state
Figure FDA0003092798150000012
Pointed vertex S i A regular tetrahedron is constructed in the bloch sphere, wherein i is equal to 0,1, 2 or 3.
3. The method of claim 2, wherein the first quantum state is |0>Said second quantum state
Figure FDA0003092798150000013
A unitary matrix corresponding to the first quantum state and the second quantum state
Figure FDA0003092798150000014
The corresponding second unitary matrix is an identity matrix I;
wherein, the
Figure FDA0003092798150000015
4. The method of claim 3, wherein the step of applying the coating comprises applying a coating to the substrate
Figure FDA0003092798150000016
Is composed of
Figure FDA0003092798150000017
The above-mentioned
Figure FDA0003092798150000018
Is composed of
Figure FDA0003092798150000019
The above-mentioned
Figure FDA00030927981500000110
Is composed of
Figure FDA00030927981500000111
The above-mentioned
Figure FDA00030927981500000112
Corresponding to the second unitary matrix of
Figure FDA00030927981500000113
The above-mentioned
Figure FDA00030927981500000114
Corresponding to the second unitary matrix of
Figure FDA00030927981500000115
Figure FDA00030927981500000116
The above-mentioned
Figure FDA00030927981500000117
Corresponding to the second unitary matrix of
Figure FDA00030927981500000118
Wherein,
Figure FDA0003092798150000021
5. the method of claim 1, wherein the first measurement base is Z and the second measurement base is the Z, X, Y; wherein, the
Figure FDA0003092798150000022
The described
Figure FDA0003092798150000023
The described
Figure FDA0003092798150000024
6. The method of claim 5, wherein the Pauli eigenstate for Z correspondence is
Figure FDA0003092798150000025
Or
Figure FDA0003092798150000026
The characteristic state of the Pauli corresponding to the X is
Figure FDA0003092798150000027
Or
Figure FDA0003092798150000028
The characteristic state of the Pauli corresponding to the Y is
Figure FDA0003092798150000029
Or
Figure FDA00030927981500000210
7. A quantum wire quantum state measurement device, comprising:
the circuit acquisition unit is used for acquiring the cut sub-quantum circuit, the sub-quantum circuit comprises a first quantum bit and a second quantum bit, the time line of the first quantum bit is not cut, and the time line of the second quantum bit is cut;
a quantum state preparation unit, configured to prepare an initial quantum state of the first qubit to a first quantum state by a first unitary matrix; if the time line of the second quantum bit is the cut upstream time line, preparing the initial quantum state of the second quantum bit to the first quantum state through the first unitary matrix; if the time line of the second quantum bit is a downstream time line after cutting, preparing the initial quantum state of the second quantum bit to a second quantum state through a second unitary matrix, wherein the upstream time line is a time line before a cutting position, and the downstream time line is a time line after the cutting position;
a quantum state measurement unit for measuring an end quantum state of the first qubit after the quantum circuit is operated on a first measurement basis; if the time line of the second quantum bit is the downstream time line after cutting, measuring the last quantum state of the second quantum bit after operating the quantum circuit on the first measuring base; and if the time line of the second quantum bit is the cut upstream time line, measuring the final quantum state of the second quantum bit after the quantum circuit is operated on a second measuring base.
8. An electronic device comprising a processor, memory, a communication interface, and one or more programs stored in the memory and configured to be executed by the processor, the programs including instructions for performing the steps in the method of any of claims 1-6.
9. A computer-readable storage medium, characterized in that the computer-readable storage medium stores a computer program, which is executed by a processor to implement the method of any of claims 1-6.
10. A quantum computer operating system, wherein the quantum computer operating system implements measurement of quantum states of a sub-quantum wire according to the method of any of claims 1-6.
CN202110601286.9A 2021-05-31 2021-05-31 Quantum state measuring method and device for sub-quantum circuit and quantum computer operating system Pending CN115423109A (en)

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