CN115422106A

CN115422106A - Interrupt request processing method and device

Info

Publication number: CN115422106A
Application number: CN202211208422.9A
Authority: CN
Inventors: 刘庆喜
Original assignee: New H3C Information Technologies Co Ltd
Current assignee: New H3C Information Technologies Co Ltd
Priority date: 2022-09-30
Filing date: 2022-09-30
Publication date: 2022-12-02

Abstract

The invention discloses a method and a device for processing an interrupt request, wherein the method is applied to a bridge chip and comprises the following steps: receiving, by a second port of a bridge chip, a first interrupt request from a PCIe endpoint, the first interrupt request including a first interrupt request type and a first device identification of the PCIe endpoint; the method comprises the steps of searching a first interrupt vector identification matched with a first interrupt request type and a first equipment identification in a mapping table, generating a second interrupt request according to the first interrupt vector identification and the first interrupt request, and sending the second interrupt request to a CPU through a first port of a bridge chip.

Description

Interrupt request processing method and device

Technical Field

The present invention relates to the field of network communication technologies, and in particular, to a method and an apparatus for processing an interrupt request.

Background

Network equipment has been widely used in various industries to implement interconnection and intercommunication within and among various backbone networks. The PCI-Express (peripheral component interconnect Express) bus of the high-speed serial computer is different from the traditional input/output (I/O) bus, and adopts a serial and point-to-point interconnection mode to realize the communication among devices, thereby providing a high-speed, high-performance and full-duplex communication mode for the interconnection of network devices. The primary features of the PCIe bus, such as application models, storage fabrics, software interfaces, etc., are consistent with the traditional PCI/PCI-X bus and take advantage of advanced point-to-point interconnects, switching and packet-based protocols to achieve new bus capabilities and features.

Since the PCIe bus is a point-to-point switched bus architecture, each device in the system has its own bus, point-to-point communications can be established by connecting directly to a bridge (Switch) device. PCIe maintains the same memory, I/O, and configuration address space models as traditional PCI, so existing operating system and driver software can run on the PCIe system without any modifications or brief adaptations.

The interrupt plays an important role in a PCIe system computing unit of the network device, and is used for informing the network device computing unit to receive and process messages such as data, protocols, control and the like of the network. The traditional PCI equipment generates an interrupt request through an INTx sideband signal, wherein INTx can be any one of INTA, INTB, INTC and INTD interrupt type requests, when the number of PCIe endpoint equipment is large, the same kind of interrupt needs to be submitted in an interrupt sharing mode, and the interrupt is converted into an INTR signal after passing through an interrupt controller and then sent to a CPU. By adopting the interrupt sharing mode, if the message is large, the CPU needs to search and confirm the PCIe endpoint device submitting the interrupt request by using software, which may affect the message service efficiency and generate additional overhead.

Disclosure of Invention

Based on the introduction of the background, the invention mainly solves the following problems: when an interrupt request is submitted by a PCIe endpoint device EP interconnected with a bridge piece downlink port in a network device PCIe system, the bridge piece uplink port needs to submit the interrupt request of each PCIe endpoint in a sharing mode, and further, the technical problem that extra overhead is generated when a CPU searches and confirms an interrupt source is caused. In order to solve the technical problem, the embodiment of the application discloses the following technical scheme:

in a first aspect, an embodiment of the present invention provides a method for processing an interrupt request, where the method is applied to a network bridge, where the bridge includes a first port and at least one second port, the first port is an uplink port, and the second port is a downlink port, where the method includes:

receiving, via the second port, a first interrupt request from a PCIe endpoint, the first interrupt request comprising a first interrupt request type and a first device identification of the PCIe endpoint; according to the first interrupt request type and the first device identification, searching a mapping table for a first interrupt vector identification matched with the first interrupt request type and the first device identification, wherein the mapping table comprises at least one of the following corresponding relations: interrupt request type, device identification and interrupt vector identification; generating a second interrupt request according to the first interrupt vector identification and the first interrupt request; and sending the second interrupt request to the CPU through the first port.

Wherein the first interrupt request is an INTx interrupt request.

With reference to the first aspect, in a possible implementation manner of the first aspect, before searching for the first interrupt vector identifier matching the first interrupt request type and the first device identifier in the mapping table, the method further includes:

receiving the mapping table sent by the CPU; or generating the mapping table according to the acquired type of the at least one interrupt request, the device identifier of each PCIe endpoint and the at least one interrupt vector identifier.

With reference to the first aspect, in another possible implementation manner of the first aspect, the interrupt vector identifier includes message data of a message signal interrupt MSI capability set and an interrupt vector number; wherein the MSI capability set message data is used to indicate message addresses and data having a unique mapping relationship with a device identification and an interrupt request type of a PCIe endpoint; the interrupt vector number and the MSI capability set message data are used to jointly indicate an interrupt request for the PCIe endpoint.

Optionally, the device identifier includes: the bus number, device number and function number of the INTx message.

With reference to the first aspect, in yet another possible implementation manner of the first aspect, the method further includes: and if the first interrupt request is the MSI interrupt request, sending the first interrupt request to the CPU through the first port.

In a second aspect, an embodiment of the present invention further provides a method for processing an interrupt request, where the method is applied to a CPU, and the CPU is connected to a first port of a bridge chip, and the method includes:

receiving a second interrupt request sent by a first port of the bridge chip;

analyzing the second interrupt request to obtain a first interrupt vector identifier, wherein the first interrupt vector identifier has a one-to-one correspondence relationship with a first device identifier and a first interrupt request type of a PCIe endpoint, and the first interrupt vector identifier indicates MSI capability set message data and an interrupt vector number of the PCIe endpoint;

and calling a corresponding interrupt service program to provide services for the PCIe endpoint according to the MSI capability set message data and the interrupt vector number.

With reference to the second aspect, in a possible implementation manner of the second aspect, the method further includes: acquiring at least one interrupt vector identifier bound with a first port of the bridge chip;

acquiring at least one device identifier bound with at least one second port of the bridge piece and at least one interrupt request type; generating a mapping table according to the at least one interrupt vector identifier, the at least one device identifier, and the at least one interrupt request type, where the mapping table includes at least one of the following correspondence relationships: the interrupt request type, the equipment identifier and the interrupt vector identifier are in one-to-one correspondence;

and sending the mapping table to a first port of the bridge chip, so that the bridge chip determines a matched first interrupt vector identifier for the PCIe endpoint sending the first interrupt request according to the mapping table, wherein the first interrupt vector identifier is one of the at least one interrupt vector identifier.

With reference to the second aspect, in another possible implementation manner of the second aspect, the obtaining at least one interrupt vector identifier bound to the first port of the bridge chip includes: acquiring at least one MSI capability set message data and at least one interrupt vector number; generating the at least one interrupt vector identification based on the at least one MSI capability set message data and the at least one interrupt vector number.

In a third aspect, an embodiment of the present invention provides an apparatus for processing an interrupt request, where the apparatus is connected to a CPU and at least one PCIe endpoint, and the apparatus includes:

a receiving unit, configured to receive a first interrupt request from a PCIe endpoint, where the first interrupt request includes a first interrupt request type and a first device identifier of the PCIe endpoint;

a searching unit, configured to search, according to the first interrupt request type and the first device identifier, a first interrupt vector identifier that matches the first interrupt request type and the first device identifier in a mapping table, where the mapping table includes at least one of the following correspondence relationships: interrupt request type, device identification and interrupt vector identification;

a generating unit, configured to generate a second interrupt request according to the first interrupt vector identifier and the first interrupt request;

a sending unit, configured to send the second interrupt request to the CPU.

Furthermore, the unit module in the interrupt request processing apparatus is further configured to implement the method according to the foregoing various implementation manners of the first aspect.

In a fourth aspect, an embodiment of the present invention provides another apparatus for processing an interrupt request, where the apparatus includes:

the receiving unit is used for receiving a second interrupt request sent by the first port of the bridge chip;

the analysis unit is used for analyzing the second interrupt request to obtain a first interrupt vector identifier, the first interrupt vector identifier has a one-to-one correspondence relationship with a first device identifier and a first interrupt request type of a PCIe endpoint, and the first interrupt vector identifier indicates MSI capability set message data and an interrupt vector number of the PCIe endpoint;

and the processing unit is used for calling a corresponding interrupt service program to provide service for the terminal equipment according to the MSI capability set message data and the interrupt vector number.

Furthermore, the unit module in the interrupt request processing apparatus is further configured to implement the method described in the foregoing various implementation manners of the second aspect.

In a fifth aspect, an embodiment of the present invention further provides a bridge piece, including: the device comprises a processing module, a first port and at least one second port, wherein the first port is an uplink port, and the second port is a downlink port;

the second port is configured to receive a first interrupt request from a PCIe endpoint, the first interrupt request including a first interrupt request type and a first device identification of the PCIe endpoint;

the processing module is configured to search, according to the first interrupt request type and the first device identifier, a mapping table for a first interrupt vector identifier that matches the first interrupt request type and the first device identifier, and generate a second interrupt request according to the first interrupt vector identifier; wherein the mapping table includes at least one of the following correspondence relations: interrupt request type, device identification and interrupt vector identification;

the first port is used for sending the second interrupt request to the CPU.

In a sixth aspect, an embodiment of the present invention further provides a processor, where the processor is coupled with a memory; wherein the memory stores computer program instructions executable by the processor, the instructions being executed by the processor to cause the processor to perform a method of handling interrupt requests as described in the second aspect or any implementation manner of the second aspect.

In addition, an embodiment of the present invention further provides a computer-readable storage medium, on which a computer program is stored, where the computer program, when executed by a processor, implements the method for processing an interrupt request according to the first aspect or any of the implementations of the first aspect, or the second aspect and any of the implementations of the second aspect.

In a seventh aspect, an embodiment of the present invention further provides a network device, where the network device includes: the bridge chip comprises a first port and at least one second port, the first port is interconnected with the CPU, and the at least one second port is interconnected with the at least one PCIe endpoint;

the at least one PCIe endpoint is to send at least one interrupt request to the bridge; the bridge chip is used for executing the processing method of the interrupt request according to the first aspect or any implementation manner of the first aspect; the CPU is configured to execute the method for processing the interrupt request according to any one of the foregoing second aspect and the second implementation manner.

Alternatively, the network device may be a network switch.

The method and the device for processing the interrupt request provided by the embodiment of the invention establish one-to-one mapping between the uplink interrupt vector identifier and the downlink equipment identifier and the interrupt request type through the uplink port and the at least one downlink port of the bridge chip, thereby converting the original interrupt request reported by the PCIe endpoint into a new interrupt request with a unique interrupt vector identifier by using the mapping relation, and reporting the new interrupt request to the CPU, so that the CPU can directly analyze and determine the PCIe endpoint corresponding to the original interrupt request after receiving the new interrupt request, further avoiding the CPU side from searching and confirming the interrupt source, and avoiding generating additional overhead.

The method solves the problem that in the PCIe network system, different PCIe endpoint devices send interrupt requests to the bridge chip, the uplink port of the bridge chip submits the interrupt request messages of the same type to the CPU in a sharing mode, and the CPU system computing unit needs to inquire and confirm the shared interrupt and then submits the result to each PCIe endpoint, thereby introducing extra overhead.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.

Fig. 1 is a schematic diagram illustrating a scenario of PCIe system cabinet interrupt request submission according to an embodiment of the present invention;

FIG. 2 is a diagram illustrating INTx remapping in a bridge chip of a PCIe system according to an embodiment of the present invention;

FIG. 3 is a diagram illustrating INTx mapping MSI in a PCIe bridge slice according to an embodiment of the present invention;

fig. 4 is a flowchart of a method for processing an interrupt request according to an embodiment of the present invention;

FIG. 5 is a diagram illustrating mapping of MSI TLP transactions to PCIe bridge segments INTx according to an embodiment of the present invention;

FIG. 6 is a flowchart illustrating processing logic for processing an interrupt request according to an embodiment of the present invention;

FIG. 7 is a flowchart of another interrupt request processing method according to an embodiment of the present invention;

fig. 8 is a block diagram of an interrupt request processing apparatus according to an embodiment of the present invention;

fig. 9 is a block diagram of another interrupt request processing apparatus according to an embodiment of the present invention;

fig. 10 is a diagram illustrating a structure of a CPU according to an embodiment of the present invention.

Detailed Description

The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without making any creative effort based on the embodiments in the present invention, belong to the protection scope of the present invention.

First, a technical scenario of the technical solution of the present application is introduced.

Referring to fig. 1, a scenario diagram of an embodiment of a network device PCIe system cabinet interrupt request submission is provided. The scenario diagram includes a CPU 10, a bridge 20, and at least one PCIe endpoint 30. The CPU 10 includes a root node, a memory, and other components, and further, the root node includes an interrupt controller, which is configured to receive and process at least one interrupt request sent from at least one PCIe endpoint 30, parse the interrupt request, convert the interrupt request into a message format recognizable by the CPU 10, and report the message format to the CPU. Further, the memory may be provided outside the CPU 10.

Optionally, the Root node is a Root multiplexer (RC). The RC is used for interconnecting with the upstream port of the bridge 20, in this case, the RC serves as a connection port between the CPU 10 and the bridge 20, for example, as a PCIe port.

The bridge 20, or Switch device, includes at least one port, such as an upstream port and a downstream port, and is coupled to the CPU 10 via the upstream port and to at least one PCIe endpoint 30 via the at least one downstream port.

The PCIe endpoint is also called PCIe endpoint device (EP), or PCIe end device such as PC, mobile phone terminal, tablet, portable device, wearable device, and so on. In addition, the PCIe endpoint may also be a PCIe interface network card for connecting peripheral devices.

In addition, since the PCIe endpoint inherits all interrupt characteristics of the PCI, including: INTx, message Signaled Interrupt (MSI) or other MSIx, so that at least one PCIe endpoint 30 may send one or more Interrupt requests to the bridge slice 20, such as by INTA-INTD, MSI or PCIe-PCI bridge.

It should be noted that the PCIe system is compatible with the conventional PCI interrupt method, and mainly uses an interrupt message to simulate a PCI interrupt signal (also referred to as a virtual INTx signal), and generally, the virtual interrupt number INTx uses any one of 4 types of INTA, INTB, INTC, and INTD.

In a PCIe network system, a PCIe bridge is usually used to extend PCIe links, so as to implement interconnection and interworking between an RC and multiple PCIe endpoint devices, as shown in fig. 1. In view of the fact that the interrupt request modes submitted by different PCIe endpoint devices are different, for example, the interrupt request modes include an INTx interrupt mode or an MSI interrupt mode, when a PCIe endpoint connected to a downstream port of a bridge slice submits an interrupt request by INTx interrupt, different PCIe endpoints use the same virtual interrupt signal (INTA/INTB INTC/INTD), so that an interrupt sharing mode is inevitably adopted in the interrupt request process submitted to a CPU by the bridge slice, which results in a large message, and the CPU searches for and confirms the EP device submitted for interrupt in a software mode, which may affect the message service efficiency.

At present, a bridge chip based on a PCIe system submits an INTx interrupt request to a downstream port of the bridge chip through transparent transmission of an INTx interrupt message, that is, a PCIe endpoint EP routes to a unique upstream port of the bridge chip, and the bridge chip submits to an RC through a sharing method at the upstream port. As shown in the left diagram of FIG. 2, before port resource remapping, both PCIe endpoints send interrupt requests to the bridge using INTA message types, pass through the bridge to the upstream port of the bridge, and share INTA message types.

In order to avoid that the bridge downstream port submits the same INTx interrupt request, which results in sharing of the virtual INTx interrupt message submitted to the RC by the bridge upstream port, the bridge employs a downstream port remapping INTx manner, as shown in the right diagram of fig. 2. The bridge chip remaps the interrupt requests of one INTB type and the other INTC type into interrupt requests of one INTB type and the other INTC type after receiving the interrupt requests of the two PCIe endpoints which send the INTA through the downstream port, so that the remapped interrupt requests of the INTB type and the INTC type are different from the INTA type originally reported by the PCIe endpoints.

Although the bridge remaps the INTx interrupt submitted by the downstream port, compared with the PCIe system directly transparently transmitting the INTx interrupt to the RC (as shown in fig. 2, "before remapping"), the problem that many PCIe endpoints share the INTx interrupt can be solved, but because the PCIe endpoint of the network device supports many types of INTx interrupt requests, the INTx type interrupt submitted by the downstream port still results in being not fixed to a certain INTx type, and thus sharing overhead still occurs, and the problem that the CPU needs to confirm to submit the interrupt request through software and generate additional overhead due to the interrupt sharing INTx type message cannot be solved.

The technical scheme provided by the embodiment of the application mainly solves the technical problem that when PCIe endpoints interconnected with bridge piece downlink ports in a PCIe system of network equipment submit various INTx type interrupt requests, the bridge piece uplink ports need to submit the INTx interrupt requests in a sharing mode, and further extra overhead is generated when a CPU searches and confirms interrupt sources.

In order to solve the above technical problem, an embodiment of the present application designs a mapping relationship between an INTx message type of a downstream port of a bridge piece of a network device PCIe system and MSI capability set message data of an upstream port, and by using the mapping, an INTx interrupt request requested by each PCIe endpoint may be mapped into a unique MSI interrupt message type and submitted to an interrupt controller of a CPU, and then the interrupt controller submits the interrupt request to the CPU in a PCIe dedicated manner, and the CPU receives the interrupt request and then calls an interrupt service program corresponding to the PCIe endpoint to provide a service for the PCIe endpoint device requesting an interrupt.

In particular, in a possible application scenario, as shown in fig. 3, the bridge piece 20 comprises: a first port 201, at least one second port 202 and a processing module 203. The first port 201 is an upstream port and is configured to be interconnected with a root node of the CPU 10, the second port 202 is a downstream port and is configured to be interconnected with the first PCIe endpoint 31 and/or the second PCIe endpoint 32, and the processing module 203 is configured to execute the method for processing the interrupt request provided in this embodiment.

The processing module 203 may be a logic circuit, a processing chip, or the like, and may control the first port 201 and the at least one second port 202 to perform receiving or sending operations of messages and data.

Referring to fig. 4, a flowchart of a method for processing an interrupt request according to an embodiment of the present application is provided. The method is applicable to a bridge plate 20 as shown in fig. 3, and more specifically, to a processing module 203 of the bridge plate 20, and the method includes:

step 101: receiving, via the second port, a first interrupt request from a PCIe endpoint, the first interrupt request including a first interrupt request type and a first device identification of the PCIe endpoint.

The PCIe endpoint sends a first interrupt request to the bridge chip, wherein the first interrupt request is an INTx interrupt request, and the type of the first interrupt request is any one of INTA, INTB, INTC and INTD.

Additionally, the first device identification of the PCIe endpoint is used to uniquely identify the PCIe endpoint. Specifically, the first device identification includes: at least one of a PCIe message bus number, a device (device) number and a function (function) number of the interrupt request can uniquely determine which PCIe endpoint the device sending the first interrupt request is.

When only one PCIe endpoint exists in the system, the first device identifier comprises a bus number and a function number, and may not comprise a device number; when two or more PCIe endpoints are included in the system, the device identification of each PCIe endpoint includes a bus number, a device number, and a function number.

In one embodiment, the bridge chip may obtain the first device identifier by parsing the first interrupt request message. For example, the bridge chip receives an INTA interrupt message sent by the PCIe endpoint 1, and obtains the device identifier of the PCIe endpoint 1 and the used message type is the INTA type by parsing the INTx interrupt message.

In addition, other information, such as payload, message data, etc., is included in the first interrupt request.

Step 102: and searching a first interrupt vector identifier matched with the first interrupt request type and the first equipment identifier in a mapping table according to the first interrupt request type and the first equipment identifier.

Wherein, the mapping table includes at least one of the following corresponding relations: interrupt request type, device identification, and interrupt vector identification. The interrupt vector identification includes: MSI capability set message data and interrupt vector number (or interrupt vector identification); further, the MSI capability set message data is used to indicate message addresses and data that have a unique mapping relationship with the device identification and interrupt request type of a PCIe endpoint; the interrupt vector number and the MSI capability set message data are used to jointly indicate an interrupt request for a PCIe endpoint.

Moreover, a first binding relationship exists between the interrupt vector identifier and the first port of the bridge, a second binding relationship exists between the device identifier and the interrupt request type and a second port, and a resource mapping between the upstream port and at least one downstream port can be established through the first binding relationship and the second binding relationship, for example, see table 1, which shows a mapping table.

Table 1, mapping relation table of bridge piece INTx message and interrupt vector identification

It should be understood that more or fewer mappings may be included in table 1 above, and the present embodiment is not limited thereto.

In a specific example, according to the step 101, if the PCIe endpoint 1 sends a first interrupt request to the bridge, where the first interrupt request type is INTC, and the corresponding device identifiers are bus number, dev number, and fun number, a matched first interrupt vector identifier is obtained based on the mapping relationship in the table 1, where the first interrupt vector identifier includes: MSI capability set message data 3 and interrupt vector number 2.

Alternatively, the interrupt vector number may be any one of values 0 to 31.

Step 103: and generating a second interrupt request according to the first interrupt vector identifier and the first interrupt request.

Specifically, the second interrupt request is generated by packaging according to the first interrupt vector identifier (for example, including the MSI capability set message data 3 and the interrupt vector number 2) determined in the previous step and by combining the data and information in the original first interrupt request. The second interrupt request includes a mapped Message Address (Message Address), message Data (Message Data), and a corresponding interrupt vector number.

The second interrupt request is an MSI TLP.

Step 104: and sending the second interrupt request to the CPU through the first port.

The bridge chip sends the generated second interrupt request, such as the MSI TLP, to the interrupt controller of the CPU through the first port, so that the interrupt controller parses and processes the second interrupt request.

Correspondingly, the method further comprises: the CPU receives a second interrupt request sent by a first port of the bridge chip; analyzing the second interrupt request to obtain a first interrupt vector identifier, wherein the first interrupt vector identifier has a one-to-one correspondence relationship with a first device identifier and a first interrupt request type of the PCIe endpoint, and the first interrupt vector identifier indicates MSI capability set message data and an interrupt vector number of the PCIe endpoint; and calling a corresponding interrupt service program to provide service for the PCIe endpoint according to the MSI capability set message data and the interrupt vector number.

For example, in this example, the CPU parses the second interrupt request, obtains MSI capability set message data 3 and interrupt vector number 2, obtains an interrupt request of 5 (5 =3+ 2), further determines that the first interrupt request sent by the PCIe endpoint is the 5 th interrupt request (or marked as "interrupt request 5"), and then determines the service request to be invoked according to the interrupt request 5, and provides the interrupt service to the PCIe endpoint.

In the method provided by this embodiment, the uplink interrupt vector identifier is established through the uplink port and the at least one downlink port of the bridge chip, and the one-to-one mapping between the downlink device identifier and the interrupt request type is established, so that the original interrupt request reported by the PCIe endpoint is converted into a new interrupt request with a unique interrupt vector identifier by using the mapping relationship, and then the new interrupt request is reported to the CPU, so that the CPU can directly analyze and determine the PCIe endpoint corresponding to the original interrupt request after receiving the new interrupt request, thereby avoiding the CPU side from searching and confirming the interrupt source again, and avoiding generating additional overhead.

Optionally, in another embodiment, in the step 102, obtaining the mapping table may be performed in two ways:

the first mode is as follows: and the bridge chip receives the mapping table sent by the CPU and stores the mapping table.

In a second mode, the bridge chip obtains information of each parameter in the mapping table, including: a type of the at least one interrupt request, a device identification of each PCIe endpoint, and at least one interrupt vector identification; and then generating the mapping table according to the acquired type of the at least one interrupt request, the device identification of each PCIe endpoint and the at least one interrupt vector identification.

First, a detailed description is given of a process of generating a mapping table by a CPU in a first mode, which specifically includes:

the first step is as follows: and acquiring at least one interrupt vector identifier bound with the first port of the bridge chip.

Each interrupt vector identification includes: one MSI capability set (MSI capability) message data and interrupt vector number. The MSI capability set Message Data reflects Data of the MSI capability set, and includes information such as MSI Message Data (Message Data), message Address (Message Address), and extensible Message Data (Extended Message Data), as shown in table 2. While table 1 shows the structure of an MSI capability set data of a 32-bit message address, it should be understood that a message address of 64 or more bits may also be provided, which is not limited in this embodiment.

TABLE 2 MSI capability set data Structure (32 bit message Address)

The interrupt vector number is an offset, and in the configuration of the 32-bit address message, the range of the interrupt vector number is 0 to 31. In addition, the first port may be identified by a port number, such as port ID 1.

The above-mentioned "first step" may be obtained by obtaining at least one interrupt vector identifier when the CPU system is enabled.

The second step is that: at least one device identification bound to at least one second port of the bridge piece and at least one interrupt request type are obtained.

Wherein, the device identifier and the terminal request type bound to each second port are also called as second binding relations, and each second binding relation includes: a correspondence between the device identification of a second port and a PCIe endpoint and an interrupt request type. Each second port may also be represented by a port number, for example, one second port corresponds to the port number being port ID 2.

Since each PCIe endpoint device may use 4 INTx message types, the device identification of one PCIe endpoint may establish 4 second binding relationships with 4 INTx message types. If there are m second ports, m × 4 second binding relationships will be bound, so the bridge chip can establish the binding relationships between the device identifiers of all PCIe endpoints and the m second ports in an enumeration manner.

It should be noted that the order between the first step and the second step may be interchanged, that is, the order of the bridge chip obtaining the first binding relationship and establishing the at least one second binding relationship, which is not limited in this embodiment.

The third step: generating a mapping table according to the at least one interrupt vector identifier, the at least one device identifier, and the at least one interrupt request type, where the mapping table includes at least one of the following correspondence relationships: the interrupt request type, the device identifier and the interrupt vector identifier are in one-to-one correspondence.

Specifically, the CPU first obtains at least one MSI capability set message data and at least one interrupt vector number, and then generates at least one interrupt vector identifier according to the at least one MSI capability set message data and the at least one interrupt vector number.

The fourth step: and sending the mapping table to a first port of the bridge chip.

Specifically, the CPU sends the generated mapping table to the first port of the bridge chip through the RC.

In the method provided by this embodiment, the binding between the upstream port and the at least one downstream port is established through the first binding relationship of the upstream port and the at least one second binding relationship of the at least one downstream port of the PCIe bridge, so as to obtain the unique mapping relationship between the device identifier of each PCIe endpoint device, the INTx message type, and the MSI capability set message data and the interrupt vector number of the upstream resource, thereby implementing resource sharing between the at least one downstream port and the upstream port of the PCIe bridge.

It should be noted that, when an interrupt is triggered, the CPU starts a memory write transaction, where a write memory address is exclusively allocated by the system and used for interrupt submission (the written data is an interrupt vector corresponding to an interrupt request device), and a target points to an interrupt controller of a root node (RC), and thus the interrupt controller is distinguished from other write transactions and submitted to the CPU in a PCIe dedicated manner; and after receiving the interrupt vector number, the CPU calls an interrupt service program according to the interrupt vector number, thereby providing service for the equipment requesting the interrupt.

Further, as a possible implementation, in the process of using the upstream port (first port) by the PCIe bridge to start MSI capability set configuration, enable MSI interrupt message, and construct MSI capability set message data, as shown in fig. 5, specifically, the method includes:

when the PCIe system is initialized, the PCIe MSI capability set of the upstream port of the PCIe bridge is configured, so as to enable MSI multi-Message configuration (for example, according to the PCIe specification, the MSI supports 32-bit addresses at most), and addresses and data required by the MSI messages, in view that the number of interrupt vectors used by the network device to extend the PCIe link downstream port through the PCIe bridge is usually not more than 8, in this embodiment, on the upstream MSI capability register set of the PCIe system bridge, the network device system configures an MSI 32-bit Address, that is, the low 32 bits of the Message Address register, corresponding to the upstream MSI register write transaction header, and the MSI Message Address (Message Address) of the low 32-bit bridge configured in the MSI capability set is [ 31.

In this embodiment, 32 MSI interrupt vector numbers (numbered 0 to 31) are set, which can meet the requirements of general network devices. It should be understood that more bits of MSI address and interrupt vector number may be set, and the embodiment is not limited thereto.

The above-described "second mode" will be described in detail below.

As shown in fig. 6, the bridge slice acquires MSI capability set message data and at least one interrupt vector number through a first port (PCIe upstream port), and enables MSI capability set message data, and establishes a unique mapping relationship with the MSI capability set message data and the interrupt vector number using INTx message types that may be submitted by at least one downstream port, including establishing a device identification (bus number, dev number, fun number), INTx message type of at least one downstream port, and a one-to-one correspondence relationship between at least one MSI capability set message data and interrupt vector number of the upstream port; a mapping table as shown in table 1 is generated.

After a downstream port of the PCIe bridge receives a first request packet (for example, an INTx TLP) sent by a PCIe endpoint, searching, in the established mapping table, a mapping relationship matching the INTx interrupt request type and the device identifier carried in the packet, and determining unique MSI capability set message data and an interrupt vector number according to the mapping relationship, to obtain an interrupt vector identifier having a unique mapping relationship; and generating a second request Packet corresponding to the first request Packet based on the interrupt vector identifier, wherein the second request Packet is an MSI TLP (Transaction Layer Packet) Packet. And finally, the PCIe bridge chip sends the second request message to the interrupt controller of the RC through the uplink port. More specifically, please refer to steps 101 to 104 of the previous embodiment, which will not be described herein.

In the method provided by this embodiment, the bridge chip establishes a mapping relationship between the MSI capability set message data and the interrupt vector number of the at least one PCIe endpoint of the downstream port and the upstream port according to the resource information of the upstream port and the downstream port, and provides a unique interrupt vector identifier, that is, an allocated unique message address and an interrupt vector number, for the requested PCIe endpoint through the mapping relationship, thereby solving the problem that different terminal devices send an interrupt request message to the bridge chip, and the upstream port of the bridge chip submits the same type of interrupt request message to the CPU in a shared manner, so that additional overhead is generated in the process of querying and confirming the interrupt source by the CPU.

In addition, aiming at least one downlink port of an internet protocol (EP) of a network device PCIe system bridge chip, a method for establishing an INTx message type and mapping a device identifier of a terminal device to MSI capability set message data in a software configuration mode is adopted, so that the bridge chip can support 32 MSI interrupt vector numbers at most, and the one-to-one mapping relation between the interrupt vector identifier of a root node and an INTx message submitted by the EP is realized.

Referring to fig. 7, a flowchart of an interrupt request processing method according to another embodiment of the present application is provided. The method comprises the following steps:

step 301: upon initialization, the CPU's enabled bridge fragments' MSI capability set, configuration MSI capability set message address, data, and at least one interrupt vector number.

Step 302: a mapping table having a unique mapping relationship is established based on at least one MSI capability set message data and at least one interrupt vector number, a message type of at least one downstream port, and a device identification of a PCIe endpoint.

Step 303: the CPU sends the mapping table to the bridge. Correspondingly, the bridge chip receives the mapping table through the uplink port.

Step 304: the bridge receives a first interrupt request sent by any PCIe endpoint. Specifically, the bridge chip receives the first interrupt request through a downstream port.

Step 305: the bridge chip judges whether the first interrupt request is an INTx message; if yes, go to step 306; if not, step 310 is performed.

Step 306: if it is an INTx message, such as any of INTA to INTD, then a matching interrupt vector identification is looked up in the mapping table according to the device identification and INTx message type in the first interrupt request.

The mapped MSI message address and data may be uniquely determined according to the interrupt vector number and the MSI capability set message data in the found interrupt vector identifier, and the specific process may be described with reference to the embodiment in fig. 4, which is not described herein again.

Step 307: and the bridge chip generates a second interrupt request according to the searched MSI message address, data, interrupt vector number, load and other information in the first interrupt request, wherein the second interrupt request is an MSI TLP message.

Step 308: the bridge chip sends a second interrupt request to an interrupt controller of the CPU through the uplink port. Correspondingly, the interrupt controller receives the second interrupt request.

Step 309: and after receiving the second interrupt request, the interrupt controller of the CPU executes the processing flow of the interrupt request.

Specifically, the processing flow includes: and analyzing and processing the second interrupt request according to a PCIe proprietary mode, reporting to the CPU, and calling a corresponding interrupt processing program after the CPU receives the second interrupt request and finishing an interrupt request task.

Furthermore, the interrupt controller converts the second interrupt request into an address and data of a PCIe bridge MSI capability set configured according to the initialization of the PCIe system of the network device, identifies which PCIe endpoint the interrupt request source is, sends an interrupt request message corresponding to the PCIe endpoint to the CPU in a PCIe proprietary mode, and the CPU calls a corresponding interrupt processing program after receiving the interrupt request message, executes and completes an interrupt request task of the PCIe endpoint.

In addition, the determination at step 305 further includes:

step 310: if not, namely, the request message is judged not to be an INTx message but an MSI interrupt message, the bridge chip sends the received MSI message (namely, the first interrupt request) to the CPU by using the upstream port.

And an interrupt controller of the CPU receives the MSI message and carries out interrupt processing according to a preset flow.

It should be noted that, in step 310, the processing procedure of the MSI message reported by the CPU to the bridge slice is the same as or similar to the processing procedure of the network device PCIe system to the MSI message, which is not described in detail herein.

In the method provided by this embodiment, a unique mapping relationship is established between the requested INTx message type, the device identifier of the PCIe endpoint, the MSI capability set message data, and the interrupt vector number, so that when the PCIe system endpoint device submits an INTx interrupt request, the same type of interrupt request is submitted to the CPU through the uplink port of the bridge in a sharing manner, and the CPU needs to query and confirm an interrupt source for shared interrupt, thereby introducing an additional overhead problem.

The method uses the unique mapping relation to process the message of CPU inquiring and confirming the interrupt EP by the bridge slice, thereby avoiding the extra expense, and the method uses the interrupt mode of the method of mapping the MSI capability set message data with the INTx message type to map the MSI interrupt message as the MSI interrupt message of the unique interrupt vector before the bridge slice submits the INTx interrupt message to the CPU, and the CPU can directly confirm the interrupt request source according to the submitted MSI interrupt request and directly call the interrupt service program, thereby avoiding the introduction of the extra expense.

The embodiment of the invention also discloses an interrupt request processing device which is connected with the CPU and at least one PCIe endpoint and is used for realizing the interrupt request processing method of the embodiment.

Specifically, as shown in fig. 8, the interrupt request processing apparatus 800 includes: the receiving unit 810, the searching unit 820, the generating unit 830 and the sending unit 840, and the apparatus may further include other more or fewer units and modules, such as a storage unit, a mapping unit, and the like, which is not limited in this embodiment.

The receiving unit 810 is configured to receive a first interrupt request from a PCIe endpoint, where the first interrupt request includes a first interrupt request type and a first device identifier of the PCIe endpoint.

A searching unit 820, configured to search, according to the first interrupt request type and the first device identifier, a first interrupt vector identifier matching the first interrupt request type and the first device identifier in a mapping table, where the mapping table includes at least one of the following correspondence relationships: interrupt request type, device identification, and interrupt vector identification.

A generating unit 830, configured to generate a second interrupt request according to the first interrupt vector identifier and the first interrupt request.

A sending unit 840, configured to send the second interrupt request to the CPU.

Furthermore, the interrupt request processing apparatus 800 is also used to implement other method steps of the processing method of the interrupt request in the foregoing embodiment.

Optionally, the interrupt request processing apparatus 800 is a bridge, such as a PCIe bridge.

In addition, in another embodiment, another interrupt request processing apparatus is provided for implementing the method steps in the CPU. Specifically, as shown in fig. 9, the interrupt request processing apparatus 900 includes: the receiving unit 910, the parsing unit 920, the processing unit 930, and the sending unit 940, and in addition, the apparatus may further include other more or fewer units and modules, which is not limited in this embodiment.

The receiving unit 910 is configured to receive a second interrupt request sent by the first port of the bridge chip.

An analyzing unit 920, configured to analyze the second interrupt request to obtain a first interrupt vector identifier, where the first interrupt vector identifier has a one-to-one correspondence with a first device identifier of a PCIe endpoint and a first interrupt request type, and the first interrupt vector identifier indicates MSI capability set message data and an interrupt vector number of the PCIe endpoint.

And a processing unit 930, configured to invoke a corresponding interrupt service routine to provide services for the terminal device according to the MSI capability set message data and the interrupt vector number.

Further, in a specific embodiment, the processing unit 930 is further configured to obtain at least one interrupt vector identifier bound to the first port of the bridge chip; acquiring at least one device identifier bound with at least one second port of the bridge piece and at least one interrupt request type; generating a mapping table according to the at least one interrupt vector identifier, the at least one device identifier, and the at least one interrupt request type, where the mapping table includes at least one of the following correspondence relationships: the interrupt request type, the device identifier and the interrupt vector identifier are in one-to-one correspondence.

A sending unit 940, configured to send the mapping table to the first port of the bridge chip, so that the bridge chip determines, according to the mapping table, a matched first interrupt vector identifier for the PCIe endpoint that sends the first interrupt request, where the first interrupt vector identifier is one of the at least one interrupt vector identifier.

Optionally, the number of the interruption vector numbers of the MSI supported by the MSI capability set message data does not exceed 32.

Optionally, the interrupt request processing apparatus 900 is a processor, such as a CPU.

It should be noted that, for the specific limitations of the interrupt request processing apparatus shown in fig. 8 and 9 in this embodiment, reference may be made to the limitations of the method of the interrupt request processing apparatus in the foregoing embodiments, and details are not described here again. The units and modules of the interrupt request processing apparatus in this embodiment may be wholly or partially implemented by software, hardware, or a combination thereof. The modules may be embedded in a hardware form or may be independent of a processor of the electronic device, or may be stored in a memory of the electronic device in a software form, so that the processor calls and executes operations corresponding to the modules.

In terms of hardware implementation, this embodiment further provides a bridge, and the structure of the bridge may be as shown in fig. 3, where: a first port 201 and at least one second port 202 and a processing module 203.

Further, the receiving unit 810 in the interrupt request processing apparatus shown in fig. 8 may be implemented by at least one second port 202, configured to receive the first interrupt request from the PCIe endpoint; the searching unit 820 and the generating unit 830 may be implemented by the processing module 203, and are configured to search a mapping table for a first interrupt vector identifier matching the first interrupt request type and the first device identifier, and generate a second interrupt request according to the first interrupt vector identifier; the function of the sending unit 840 may be implemented through the first port 201.

In addition, an embodiment of the present invention further provides a processor, as shown in fig. 10, the processor 110 is coupled to the memory 120, where the processor 110 and the memory 120 may be connected through a bus or in another manner, and fig. 10 illustrates the connection through the bus as an example.

Further, the processor may be connected to at least one port, including a PCIe port or the like, at least one port not shown in fig. 10. It should be understood that the processor may also be connected with other hardware modules or units, or with other hardware modules, and the embodiment is not limited thereto.

The processor 110 may be a Central Processing Unit (CPU). The Processor 110 may also be other general purpose processors, digital Signal Processors (DSPs), application Specific Integrated Circuits (ASICs), field Programmable Gate Arrays (FPGAs) or other Programmable logic devices, discrete Gate or transistor logic devices, discrete hardware components, or any combination thereof.

The memory 120, which is a non-transitory computer-readable storage medium, may be used to store non-transitory software programs, non-transitory computer-executable programs, and modules, such as program instructions/modules corresponding to the interrupt request processing method in the embodiments of the present invention. The processor 110 executes various functional applications and data processing of the processor 110 by executing the non-transitory software program instructions stored in the memory 120, that is, implements the interrupt request processing method in the above method embodiment.

The memory 120 may include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required for at least one function; the memory data area may store data created by processor 110, MSI capability set message data, interrupt vector numbers, device identifications, INTx message types, and the like. Further, the memory 120 may include high speed random access memory, and may also include non-transitory memory, such as at least one magnetic disk storage device, flash memory device, or other non-transitory solid state storage device. In some embodiments, memory 120 optionally includes memory located remotely from processor 110, and these remote memories may be connected to processor 110 via a network. Examples of such networks include, but are not limited to, various network devices in a PCIe network system.

In addition, at least one port may also be used for connecting other external devices, such as communicating with various terminal devices, remote network devices, and the like. Optionally, at least one port may also be used for connecting peripheral input/output devices, such as a keyboard, a display screen, etc.

The one or more modules are stored in the memory 120 and, when executed by the processor 110, perform a method of processing an interrupt request as in the embodiments shown in fig. 4 and 7.

The present embodiment further provides a network device, the structure of which can be seen in fig. 1 to 3, where the network device includes: CPU 10, bridge 20, and at least one PCIe endpoint 30, further, bridge 20 is interconnected with CPU 10 through the first port, and interconnected with at least one PCIe endpoint 30 through at least one second port.

Wherein the at least one PCIe endpoint 30 is operable to send at least one interrupt request, such as a first interrupt request, to the bridge chip 20; the bridge chip 20 is used for executing the processing method of the interrupt request described in fig. 4 or fig. 7 in the foregoing embodiment; the CPU 10 is configured to execute the interrupt request processing method described in fig. 4 or fig. 7 in the foregoing embodiment.

The structure of the CPU 10 may be the same as that shown in fig. 10.

The architecture of the PCIe endpoint may also be similar to that shown in FIG. 10, including components such as a processor and memory.

Optionally, the network device may be a network switch or a PCIe device.

The details of the network system may be understood with reference to the corresponding related description and effects in the embodiment shown in fig. 1, and are not described herein again.

It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by a computer program, which can be stored in a computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. The storage medium may be a magnetic Disk, an optical Disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a Flash Memory (Flash Memory), a Hard Disk (Hard Disk Drive, HDD), a Solid-State Drive (SSD), or the like; the storage medium may also comprise a combination of memories of the kind described above.

Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the invention, and such modifications and variations fall within the scope defined by the appended claims.

Claims

1. A method for processing an interrupt request, wherein the method is applied to a bridge chip, the bridge chip includes a first port and at least one second port, the first port is an upstream port, and the second port is a downstream port, the method includes:

receiving, via the second port, a first interrupt request from a PCIe endpoint, the first interrupt request comprising a first interrupt request type and a first device identification of the PCIe endpoint;

according to the first interrupt request type and the first device identification, searching a mapping table for a first interrupt vector identification matched with the first interrupt request type and the first device identification, wherein the mapping table comprises at least one of the following corresponding relations: interrupt request type, device identification and interrupt vector identification;

generating a second interrupt request according to the first interrupt vector identifier and the first interrupt request;

and sending the second interrupt request to the CPU through the first port.

2. The method of claim 1, prior to looking up a first interrupt vector identification in the mapping table that matches the first interrupt request type and the first device identification, further comprising:

receiving the mapping table sent by the CPU;

or,

and generating the mapping table according to the acquired type of the at least one interrupt request, the device identifier of each PCIe endpoint and the at least one interrupt vector identifier.

3. The method of claim 2 wherein said interrupt vector identification comprises message signaled interrupt MSI capability set message data and an interrupt vector number;

wherein the MSI capability set message data is used to indicate message addresses and data having a unique mapping relationship with a device identification and an interrupt request type of a PCIe endpoint; the interrupt vector number and the MSI capability set message data are used to jointly indicate an interrupt request for the PCIe endpoint.

4. The method according to any of claims 1-3, wherein the device identification comprises: the bus number, device number and function number of the INTx message.

5. The method according to any one of claims 1-3, further comprising:

and if the first interrupt request is the MSI interrupt request, sending the first interrupt request to the CPU through the first port.

6. A method for processing an interrupt request, the method being applied to a CPU, the CPU being connected to a first port of a bridge, the method comprising:

receiving a second interrupt request sent by a first port of the bridge chip;

7. The method of claim 6, further comprising:

acquiring at least one interrupt vector identifier bound with a first port of the bridge chip;

acquiring at least one device identifier bound with at least one second port of the bridge piece and at least one interrupt request type;

generating a mapping table according to the at least one interrupt vector identifier, the at least one device identifier, and the at least one interrupt request type, where the mapping table includes at least one of the following correspondence relationships: the interrupt request type, the equipment identifier and the interrupt vector identifier are in one-to-one correspondence;

8. The method of claim 7, wherein obtaining at least one interrupt vector identification bound to a first port of the bridge tile comprises:

acquiring at least one MSI capability set message data and at least one interrupt vector number;

generating the at least one interrupt vector identification based on the at least one MSI capability set message data and the at least one interrupt vector number.

9. An apparatus for processing interrupt requests, the apparatus being coupled to a CPU and at least one PCIe endpoint, the apparatus comprising:

a sending unit, configured to send the second interrupt request to the CPU.

10. An apparatus for processing an interrupt request, the apparatus comprising:

11. A bridge plate, comprising: the device comprises a processing module, a first port and at least one second port, wherein the first port is an uplink port, and the second port is a downlink port;

the processing module is configured to search a mapping table for a first interrupt vector identifier matching the first interrupt request type and the first device identifier according to the first interrupt request type and the first device identifier, and generate a second interrupt request according to the first interrupt vector identifier; wherein the mapping table includes at least one of the following corresponding relations: interrupt request type, equipment identification and interrupt vector identification;

the first port is used for sending the second interrupt request to the CPU.

12. A processor coupled with a memory, wherein the memory has stored thereon computer-readable program instructions,

the instructions, when executed by the processor, implement a method of handling interrupt requests as claimed in any one of claims 6 to 8.

13. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out a method of handling an interrupt request according to any one of claims 1 to 8.

14. A network device, characterized in that the network device comprises: the bridge chip comprises a first port and at least one second port, the first port is interconnected with the CPU, and the at least one second port is interconnected with the at least one PCIe endpoint;

the at least one PCIe endpoint is to send at least one interrupt request to the bridge;

the bridge chip is used for executing the interrupt request processing method of any one of claims 1 to 5;

the CPU is configured to execute the method of processing an interrupt request according to any one of claims 6 to 8.