CN115421799A - Integrated satellite-borne computer system applied to micro-nano satellite - Google Patents
Integrated satellite-borne computer system applied to micro-nano satellite Download PDFInfo
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- CN115421799A CN115421799A CN202211057300.4A CN202211057300A CN115421799A CN 115421799 A CN115421799 A CN 115421799A CN 202211057300 A CN202211057300 A CN 202211057300A CN 115421799 A CN115421799 A CN 115421799A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/4401—Bootstrapping
- G06F9/4405—Initialisation of multiprocessor systems
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0751—Error or fault detection not based on redundancy
- G06F11/0754—Error or fault detection not based on redundancy by exceeding limits
- G06F11/0757—Error or fault detection not based on redundancy by exceeding limits by exceeding a time limit, i.e. time-out, e.g. watchdogs
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/4401—Bootstrapping
- G06F9/4406—Loading of operating system
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/445—Program loading or initiating
- G06F9/44505—Configuring for program initiating, e.g. using registry, configuration files
Abstract
The invention belongs to the technical field of micro/nano satellite computer integration optimization design, and provides an integrated on-board computer system applied to a micro/nano satellite. The invention improves the integration level and the processing capacity of the satellite-borne computer system, adopts a multi-stage fault-tolerant design, ensures that the high-integration integrated satellite-borne computer reliably works in a space environment, and uses the internally integrated GPU and the video coding and decoding unit for accelerating the processing of load data. The invention breaks the boundary of a plurality of subsystems on the satellite, realizes the cross-subsystem fusion of on-satellite processing resources, and provides computing resources for housekeeping, attitude control calculation, task planning, health management, load data processing and the like by a low-cost, high-integration and high-performance satellite-borne computing processing platform.
Description
Technical Field
The invention belongs to the technical field of micro/nano satellite computer integrated optimization design, and particularly relates to an integrated on-board computer system applied to a micro/nano satellite.
Background
The micro-nano satellite generally refers to a small satellite with the weight of less than 100Kg, has the characteristics of low development cost, short development period, flexible carrying and launching and the like, and is more and more widely applied in the fields of communication, navigation, remote sensing and new technology scientific experiments. With the development of the micro-nano satellite technology, functions borne by the micro-nano satellite are more and more complex, the satellite formation and the constellation networking are more and more applied, and higher requirements are provided for the capabilities of micro-nano satellite function density, task autonomous management, health management, function reconstruction, rapid application and the like.
Firstly, in the field of traditional small satellite design, although the limitation of each subsystem product is broken through by adopting comprehensive electrons, the problems of weak processing capacity, low fusion degree, non-uniform interface types and the like still exist; secondly, the fast application of the satellite has higher and higher requirements on the timeliness of load data processing, the on-orbit processing requirements of the load data are more and more urgent, and higher requirements are put forward on the satellite-borne data processing capability. Finally, redundant backup can be added in the system design to improve the reliability of the system, but because the computer processing resources in the satellite are dispersed, corresponding backup systems are added, the design complexity of the satellite computer system can be increased, the volume and the mass of the whole satellite are increased, and the development cost of the satellite-borne computer system is increased.
Disclosure of Invention
Aiming at solving the problems in the background technology and aiming at the application of the low-cost micro-nano satellite, a computer system with high integration, platform control and load data processing integration is designed. Hardware resources such as a multi-core high-performance processor hard core, a video coding and decoding unit and the like are embedded in the large-scale FPGA, and a high-integration integrated spaceborne computer system is designed, wherein the specific scheme is as follows:
an integrated on-board computer system applied to a micro-nano satellite comprises an MPSOC unit and a monitoring and configuration management unit FPGA, wherein:
the MPSOC unit integrates a PS processing module, a programmable logic PL module and a plurality of interface modules;
the PS processing module is internally integrated with a 4-core high-performance processor Arm core-A53, a dual-core Arm core-R5 and an image processing unit GPU, and the PL part is integrated with a coding and decoding unit and a digital signal processing unit and used for hardware acceleration of image and video stream processing;
the monitoring and configuration management unit FPGA is an external watchdog of the MPSOC and monitors the normal operation of an MPSOC program; configuring a starting mode of the MPSOC; receiving an external command, and performing configuration management on the MPSOC; and communicating with the MPSOC to perform data interaction, acquiring important parameters of the MPSOC and performing state monitoring.
Further, the interface module integrates expansion CAN bus, RS422, LVDS, USB, ethernet, SATA, PCIE, rapidIO interfaces, and designs 4 paths of CAN bus: the platform CAN A/B is used as a system bus and is used for transmitting telemetering and remote control information and time broadcast, and the attitude control CAN realizes the acquisition of attitude measurement data, engineering telemetering and the transmission of attitude control actuating mechanism control information of the attitude control sensor, and the like; SATA and PCIE are used to connect storage devices, and RS422, LVDS, USB, ethernet, rapidIO interfaces are used to access typical payloads.
Further, the Arm Cortex-a53 core runs an embedded Linux operating system and is used for processing complex application programs such as image processing, target identification, task planning, health management and the like; arm Cortex-R5 is used for running application programs with high requirements on reliability and real-time performance, such as housekeeping management, attitude control calculation, track calculation, equipment management and the like, and a dual-core FreeOS operating system runs.
Furthermore, the monitoring and configuration management unit FPGA is provided with a program guide module for MPSOC, and supports external eMMC Flash and SD card guide connected through MPSOC, or guide is realized through a guide file and a mapping file in QSPI-Flash and NAND Flash stored in the monitoring and configuration management unit FPGA respectively through a QSPI interface or an 8-bit parallel interface MIO [ 25.
Furthermore, the monitoring and configuration management unit FPGA is provided with a fault-tolerant module, the fault-tolerant module records the last successful guide MODE word in the external MRAM, and the value is read and the PS _ MODE [0:3] is configured after power-on; in the boot process, the fault-tolerant module monitors PSDONE and PS _ ERROR _ OUT signals in real time, and boot is started according to the priority sequence from the last successful boot mode until the program is booted successfully.
Further, the monitoring and configuration management unit FPGA determines the boot MODE by configuring PS _ MODE [0:3], and the priority is sequentially set as: QSPI-Flash, nand Flash, i.e., parallel port MIO [25 ].
The invention achieves the following beneficial effects:
the invention provides a low-cost, high-integration and high-performance spaceborne computer system scheme, which utilizes a high-performance 4-core application processor APU integrated by an MPSOC to complete the functions of task planning, health management and load data processing, utilizes a dual-core processor RPU facing high real-time application to complete the functions of housekeeping management, attitude control computer, power management, time management and the like, and simultaneously, an internally integrated GPU and a video coding and decoding unit are used for accelerating the processing of load data. Based on the consideration of space environment, a Flash type FPGA with rich flight experience and verification is adopted as a product guiding and operation monitoring unit to identify spatial single event upset or locking events and take recovery measures to ensure the on-orbit reliable and stable work of the satellite-borne computer. The boundary of a plurality of subsystems on the satellite is broken through, the on-satellite processing resources are fused across the subsystems, and the low-cost, high-integration and high-performance satellite-borne computing processing platform provides computing resources for satellite affair management, attitude control computing, task planning, health management, load data processing and the like.
The invention improves the integration level and the processing capacity of the satellite-borne computer system, and simultaneously adopts a multi-stage fault-tolerant design to ensure that the high-integration satellite-borne computer reliably works in a space environment.
Drawings
FIG. 1 is an architecture diagram of an integrated satellite-borne computer system applied to a micro/nano satellite according to the invention;
FIG. 2 is a software architecture diagram of an integrated satellite-borne computer system applied to a micro/nano satellite according to the present invention;
FIG. 3 is a multi-mode fault-tolerant guiding scheme of an integrated satellite-borne computer system applied to a micro/nano satellite according to the invention;
fig. 4 is an application case of the spaceborne computer of embodiment 1.
Detailed Description
To facilitate understanding of the present invention for those skilled in the art, the following description will be given with reference to the accompanying drawings.
In order to reduce the cost, improve the processing capacity of an on-board computer and take processing requirements of housekeeping management, attitude control calculation, load processing, task planning, health management and the like into consideration, the invention provides an on-board high-integration integrated on-board computer system which adopts Xilinx Zynq UltraScale + MPSoC ZU7EV as a core and is applied to a micro-nano satellite, a quad-core Arm core-A53, a dual-core Arm core-R5, programmable Logic (PL) and image processing unit GPU resources are integrated in the on-board computer system, and CAN, UART and I resources CAN be provided in the aspect of interfaces 2 C. Interfaces such as USB, ethernet, PCIE, SATA, rapidIO and the like provide abundant interface resources for the design of the spaceborne computer.
As shown in fig. 1, the satellite-borne computer system is designed with MPSOC as a core, and meanwhile, based on reliability consideration, the MPSOC is monitored and configured and managed by using a low-power-consumption Flash type FPGA proaasic 3, and mainly completed functions are as follows:
(1) Monitoring the normal operation of an MPSOC program by using an external watchdog of the MPSOC, and restarting the MPSOC or sending a tripping pulse instruction if the MPSOC does not feed the dog; monitoring MPSOC operation important signals PS _ ERROR _ OUT and the like, and taking recovery measures such as restarting or power on/off and the like;
(2) Configuring the starting mode of the MPSOC, and configuring the PSMode [0: the pin determines which guide mode is adopted by the MPSOC, and specifically comprises 4 QSPI Flash, NAND Flash, eMMC Flash and SD card;
(3) Receiving an external command, reading from NandFlash or receiving a configuration file through an external interface, and performing configuration management on the MPSOC through an 8-bit parallel port MIO [ 25;
(4) The method comprises the steps that communication is carried out with an MPSOC through a serial port UART, and the communication is used as a channel for data interaction, including but not limited to MPSOC important parameter states and state monitoring;
the external power supply is adaptive to 5.6-21V, and 5.2V, 3.3V, 1.8V, 1.2V, 0.9V, 0.85V and other voltages required by MPSOC are generated by an integrated power chip TPS6508641 chip of TI company.
In the interface design mode, an IP core and rich IO resources integrated in the MPSOC are fully utilized, interfaces such as a CAN bus, RS422, LVDS, USB, ethernet, SATA, PCIE, rapidIO and the like are integrated and expanded, wherein 4 paths of CAN buses are designed in total, a platform CAN A/B is used as a system bus of a satellite-borne electronic system and used for transmitting telemetering and remote control information and time broadcasting, and the attitude control CAN is mainly used for realizing attitude measurement data of an attitude control sensor, collecting engineering telemetering and sending attitude control execution mechanism control information and the like. SATA and PCIE are used for connecting storage equipment, interfaces such as RS422, LVDS, USB, ethernet, rapidIO and the like are used for accessing typical loads, abundant load equipment interfaces are designed, and high-medium-speed and low-speed load common interfaces of different interfaces are convenient to adapt.
In terms of storage resources, 4 pieces of magnesium light 512M 16DDR4 are connected to the PS terminal, and 1 piece of magnesium light 512M 16DDR4 is connected to the PL terminal, and is used for storing data when the processor and the FPGA run; the system comprises a PS terminal 32MB QSPI Flash1, a 8GB eMMC Flash1 and an SD card, and is used for storing ARM application programs, system files, other user data files and the like. The signal was amplified by a PS-terminal PSMODE [0:3] determining the starting mode of the PS.
An image processing unit GPU Mali-400 MP2 is integrated in the internal PS part of the MPSOC, the working dominant frequency is above 600MHz, an H.264/H.265 coding and decoding unit and a digital signal processing resource DSP Slice are integrated in the PL part, and the above resources provide a hardware acceleration processing platform for processing images and video streams and support the processing of the video streams of 8K x 4K @15fps or 4K x 2K60fps.
A 4-core high-performance processor Arm Cortex-A53 and a dual-core Arm Cortex-R5 are integrated in the PS, wherein the Arm Cortex-A53 core runs an embedded Linux operating system and is used for processing complex application programs such as image processing, target recognition, task planning, health management and the like; the Arm Cortex-R5 is used for running application programs with high requirements on reliability and real-time performance, such as housekeeping management, attitude control calculation, track calculation, equipment management and the like, a FreeOS operating system runs in dual cores, and the reliability of the system is improved by adopting a dual core lock step running mode. The design of the multi-core spaceborne computer software architecture is shown in fig. 2.
As shown in fig. 2, for an Arm-Cortex a53 multi-core processor, a Linux operating system is applied to perform multi-task scheduling management, and complex tasks such as autonomous task planning, health management, load data processing, software APP configuration management and the like are mainly run; the Arm-Cortex R5 dual-core processor adopts a dual-core step locking operation mode, a FreeOS operating system is applied to carry out multi-task scheduling management, and tasks such as housekeeping management, attitude and orbit control calculation, power management, safety management, upper note management and the like are mainly operated.
The reliability and fault-tolerant design of the invention is as follows:
the MPSOC integrates APU, RPU, FPGA resources and the like, and the reliable guide of the program is very important. Therefore, a multi-MODE fault-tolerant guiding scheme is provided, a ProcASIC3 FPGA management guiding process which is immune to a single event effect and has rich flight experience is utilized, and a starting guiding MODE is flexibly selected by configuring a PS _ MODE (0:3) of an MPSOC (multi-phase programmable chip system on chip).
The scheme provides a multi-mode fault-tolerant guiding scheme, which supports guiding of external eMMC Flash and SD card connected from MPSOC, and simultaneously supports monitoring of error-tolerant guiding files and mapping files stored in the QSPI-Flash and NAND Flash by a ProcASIC3 FPGA through a QSPI interface or an 8-bit parallel port MIO [25 ]. The ProcASIC3 FPGA determines a guidance MODE by configuring PS _ MODE [0:3], and the priority is sequentially set as: QSPI-Flash → Nand Flash (parallel port MIO [25 ]) → eMMC Flash → SD card, according to the actual guiding situation, record the last successful guiding MODE word in external MRAM by fault-tolerant FPGA, read the value and dispose PS _ MODE [0:3] after powering up. In the boot process, the fault-tolerant FPGA monitors PSDONE and PS _ ERROR _ OUT signals in real time, and the boot is started according to the priority sequence from the last successful boot mode until the program is successfully booted.
In order to prevent the space single event effect from damaging the guide file and the mapping file, the guide file and the mapping file are stored in a multi-mode (N is more than or equal to 5) in a fault-tolerant FPGA plug-in QSPI/Nand Flash, and the guide file and the mapping file are accompanied by CRC (cyclic redundancy check) for error detection. When the boot is conducted through a QSPI interface or an 8-bit parallel port MIO [25 ]. The fault-tolerant FPGA confirms that the boot process is correct and the software is successfully loaded through monitoring signals such as PS _ DONE (PL configuration completion flag), PS _ ERROR _ OUT and WDT. In addition, the boot files and the image files in the QSPI Flash and the NandFlash which are externally hung on the fault-tolerant FPGA can be injected and updated through an uplink channel of the satellite transponder.
The invention has the structural design that:
the low-cost high-integration high-performance satellite-borne computer is designed to be a single module plug-in, 2 modules are adopted to form main and standby machine cold backup redundancy during practical application, the modular structure adopts the CPCI 3U standard, the PCB size is 165mm x 100mm, a plug-in type structure is adopted, modules are connected through a backboard, a J-30J micro rectangular connector is selected for an external connector, a CPCI series connector is selected for an internal backboard connector, a locking strip is designed for a frame, the locking strip is used for locking when the modules form a whole machine and increasing the contact area between the modules and the frame so as to increase the heat dissipation capacity of the modules, and the modular structural design is shown in figure 4.
In the case of the example 1, the following examples are given,
in this embodiment, as shown in fig. 4, the low-cost high-integration high-performance on-board computer provided by the present invention adopts a dual-computer cold backup design when applied, the on-board computer serves as a master node of a dual-redundancy CAN bus and is responsible for scheduling the CAN bus, and other modules serve as slave nodes and are connected to the CAN bus; the RapidIO exchange module is used as a center of high-speed data exchange and is connected with the solid storage module, the satellite borne computer (main), the satellite borne computer (standby), the load, the data transmission and the like to complete the exchange of high-speed data; the satellite-borne computer is responsible for completing on-orbit data processing, target identification and the like of load data; and meanwhile, receiving an uploading instruction and data of the measurement and control responder, completing analysis, execution, distribution and the like of the instruction, completing telemetering framing and downloading through the measurement and control responder.
The above embodiments of the present invention do not limit the scope of the present invention. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present invention should be included in the scope of the claims of the present invention.
Claims (6)
1. An integrated on-board computer system applied to a micro-nano satellite is characterized by comprising an MPSOC unit and a monitoring and configuration management unit FPGA, wherein:
the MPSOC unit integrates a PS processing module, a programmable logic PL module and a plurality of interface modules;
the PS processing module is integrated with a 4-core high-performance processor Arm core-A53, a dual-core Arm core-R5 and an image processing unit GPU, and the PL part is integrated with a coding and decoding unit and a digital signal processing unit and used for hardware acceleration of image and video stream processing;
the monitoring and configuration management unit FPGA is an external watchdog of the MPSOC and monitors the normal operation of an MPSOC program; configuring a starting mode of the MPSOC; receiving an external command, and performing configuration management on the MPSOC; and the MPSOC is communicated with the MPSOC and interacts data to acquire important parameters of the MPSOC and monitor the state.
2. An integrated on-board computer system applied to micro-nano satellites according to claim 1, wherein the computer system comprises: the interface module integrates expansion CAN bus, RS422, LVDS, USB, ethernet, SATA, PCIE and RapidIO interfaces, and designs 4 paths of CAN buses: the platform CAN A/B is used as a system bus and is used for transmitting remote measurement and remote control information and time broadcast, and the attitude control CAN realizes attitude measurement data of the attitude control sensor, collection of engineering remote measurement, sending of attitude control actuating mechanism control information and the like; SATA and PCIE are used to connect storage devices, and RS422, LVDS, USB, ethernet, rapidIO interfaces are used to access typical payloads.
3. An integrated on-board computer system applied to micro-nano satellites according to claim 1, wherein the computer system comprises: the Arm Cortex-A53 core runs an embedded Linux operating system and is used for processing complex application programs of image processing, target identification, task planning and health management; arm Cortex-R5 is used for running star management, attitude control calculation, track calculation and equipment management application programs, and a dual-core FreeOS operating system.
4. An integrated on-board computer system applied to micro-nano satellites according to claim 1, wherein the computer system comprises: the monitoring and configuration management unit FPGA is provided with a program guide module for MPSOC, supports external eMMC Flash and SD card guide connected through the MPSOC, or realizes guide through a QSPI interface or an 8-bit parallel port MIO [ 25.
5. An integrated on-board computer system applied to micro/nano satellites according to claim 4, wherein the computer system comprises: the monitoring and configuration management unit FPGA is provided with a fault-tolerant module, the fault-tolerant module records the last successful guide MODE word in the external MRAM, and the value is read and the PS _ MODE [0:3] is configured after power-on; in the boot process, the fault-tolerant module monitors PSDONE and PS _ ERROR _ OUT signals in real time, and the last successful boot mode starts to boot according to the priority order until the program is booted successfully.
6. An integrated on-board computer system applied to micro/nano satellites according to claim 5, wherein: the monitoring and configuration management unit FPGA determines the guidance MODE by configuring PS _ MODE [0:3], and the priority is sequentially set as: QSPI-Flash, nand Flash, i.e., parallel port MIO [25 ].
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115934631A (en) * | 2022-12-30 | 2023-04-07 | 武汉麓谷科技有限公司 | Intelligent storage platform based on MPSoC |
| CN116501508A (en) * | 2023-06-29 | 2023-07-28 | 中国电子科技集团公司第十五研究所 | Space-based edge calculation module and device |
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2022
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115934631A (en) * | 2022-12-30 | 2023-04-07 | 武汉麓谷科技有限公司 | Intelligent storage platform based on MPSoC |
| CN115934631B (en) * | 2022-12-30 | 2023-10-27 | 武汉麓谷科技有限公司 | Intelligent storage platform based on MPSoC |
| CN116501508A (en) * | 2023-06-29 | 2023-07-28 | 中国电子科技集团公司第十五研究所 | Space-based edge calculation module and device |
| CN116501508B (en) * | 2023-06-29 | 2023-09-29 | 中国电子科技集团公司第十五研究所 | Space-based edge calculation module and device |
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