CN115412132B

CN115412132B - Hardware safety type Zigbee terminal based on environment energy supply

Info

Publication number: CN115412132B
Application number: CN202210846625.4A
Authority: CN
Inventors: 杨平
Original assignee: Sichuan Vocational College of Chemical Technology
Current assignee: Sichuan Vocational College of Chemical Technology
Priority date: 2022-07-19
Filing date: 2022-07-19
Publication date: 2023-08-18
Anticipated expiration: 2042-07-19
Also published as: CN115412132A

Abstract

The invention relates to the technical field of equipment of the Internet of things, in particular to a hardware safety type Zigbee terminal based on energy supply of environmental energy, the environmental energy is accessed through a P2 interface, a step-up transformer T1 steps up collected electric energy and sends the electric energy into an energy management chip U3, the energy management chip U3 integrates and optimally manages the collected environmental energy, a stable voltage is output through a voltage rail to supply power for a microprocessor U1, and meanwhile, an LDO in the energy management chip U3 supplies energy for a safety management chip U2. The microprocessor U1 starts the power supply of the sensor module in real time according to the requirement of the working mode, collects and processes the data collected by the sensor, and transmits the data meeting the wireless transmission protocol to the antenna to realize communication with the zigbee coordinator.

Description

Hardware safety type Zigbee terminal based on environment energy supply

Technical Field

The invention relates to the technical field of Internet of things equipment, in particular to a hardware safety type Zigbee terminal based on energy supply of environmental energy.

Background

The reduction of the power consumption of the terminal node is one of the core subjects in the development of the Internet of things, a plurality of technical innovations are generated in the past time, the reduction of the power consumption of the node of the Internet of things is obvious, and the terminal node has been developed into the field which is most concerned by the industry of the Internet of things in recent years. However, at present, the existing internet of things node with low power consumption technical support still needs various forms of active power supply, and even if most of active power supply only needs a common battery or a button battery, the life cycle of the application scene of the node is often longer than that of the battery, so that higher maintenance cost is generated, and a large amount of waste batteries bring great pressure to environmental protection. Based on this, to overcome the above problems, we have devised a hardware-safe Zigbee terminal based on environmental energy power.

Disclosure of Invention

The invention aims to provide a hardware safety type Zigbee terminal based on environmental energy supply, which is used for solving the technical problems.

The embodiment of the invention is realized by the following technical scheme:

hardware-safe Zigbee terminals based on environmental energy supply, comprising: the system comprises a microprocessor U1, a safety management chip U2, an energy management chip U3, a transmitting antenna circuit, a capacitor C19, a capacitor C20, a capacitor C21, a capacitor C22, a capacitor C23, a capacitor C24, a capacitor Cin1, a step-up transformer T1 and an environmental energy collector access interface P2; the C1 end 13 pin of the energy management chip U3 is connected with one end of a capacitor C20, the C2 end 14 pin of the energy management chip U3 is connected with one end of a capacitor C22, the other end of the capacitor C20 and the other end of the capacitor C22 are respectively connected with one end of a step-up transformer T1, the other end of the step-up transformer T1 is respectively connected with the anode of a capacitor Cin1 and the No. 1 interface of an environment energy collector access interface P2, the cathode of the capacitor Cin1 is respectively connected with the No. 2 interface of the environment energy collector access interface P2, the VS2 end 10 pin of the energy management chip U3 and the GND end 9 pin of the energy management chip U3 and is grounded, the DIO_8end 25 pin of the microprocessor U1 is connected with the SDA end 5 pin of the safety management chip U2, the GND end 4 pin of the safety management chip U2 is connected with the GND end 1 pin of the energy management chip U3, one end of the capacitor C19, the negative electrode of the capacitor C23 and one end of the second power supply and is grounded, the VCC end 8 pin of the safety management chip U2 is connected with the first power supply, the other end of the capacitor C19 is respectively connected with the VAUX end 2 pin of the energy management chip U3 and the VS1 end 11 pin of the energy management chip U3, the other end of the second power supply is connected with the negative electrode of the capacitor C21, the positive electrode of the capacitor C21 is connected with the VSTORE end 3 pin of the energy management chip U3, the VOUT end 4 pin of the energy management chip U3 is respectively connected with the positive electrode of the capacitor C23 and the third power supply, and the RF_N end 2 pin of the microprocessor U1 and the RF_P end 1 pin of the microprocessor U1 are respectively connected with a transmitting antenna circuit.

Optionally, the device further comprises a crystal oscillator circuit, a reset circuit, a first power supply filter circuit, a second power supply filter circuit, an interface P1 and a capacitor C10; the VDDS end 27 pin of the microprocessor U1, the VDDS2 end 11 pin of the microprocessor U1 and the VDDS_DCDC end 19 pin of the microprocessor U1 are respectively connected with a first power supply filter circuit and a reset circuit, the nRESET end 21 pin of the microprocessor U1 is connected with the reset circuit, the DCDC_SW end 18 pin of the microprocessor U1, the VDDR_RF end 32 pin of the microprocessor U1 and the VDDR end 28 pin of the microprocessor U1 are respectively connected with a second power supply filter circuit, the DCOUPL end 12 pin of the microprocessor U1 is connected with one end of a capacitor C10, the other end of the capacitor C10 is respectively connected with the VSS end 3 pin of the microprocessor U1, the VSS end 7 pin of the microprocessor U1, the VSS end 17 pin of the microprocessor U1, the VSS end 20 pin of the microprocessor U1, the VSS end 29 pin of the microprocessor U1 and the EGP end 33 pin of the microprocessor U1, the X32K_Q1 end 5 pin of the microprocessor U1, the X32K_Q2 end 6 pin of the microprocessor U1, the X24M_N end 30 pin of the microprocessor U1 and the X24M_P end 31 pin of the microprocessor U1 are respectively connected with a crystal oscillator circuit, the crystal oscillator circuit is connected with the GND end 16 pin of the energy management chip U3, the VLD0 end 6 pin of the energy management chip U3 is connected with one end of the capacitor C24, the GND end 8 pin of the energy management chip U3 is connected with the other end of the capacitor C2 and is grounded, the DIO_4 end 16 pin of the microprocessor U1 is connected with the VOUT2_EN end 12 pin of the energy management chip U3, the DIO_5 end 22 pin of the microprocessor U1 is connected with the No. 4 interface of the interface P1, the DIO_6 end 23 pin of the microprocessor U1 is connected with the No. 3 interface of the interface P1, the DIO_7 end 24 pin of the microprocessor U1 is connected with the No. 2 interface of the interface P1, the No. 1 interface of the interface P1 is grounded, and the No. 5 interface of the interface P1 is connected with the VOUT2 end 5 pin of the energy management chip U3.

Optionally, the transmitting antenna circuit includes an inductor L1, an inductor L2, a capacitor C7, a capacitor C8, a capacitor C9, and a transmitting antenna J1; the RF_N end 2 pin of the microprocessor U1 is connected with one end of an inductor L2, the other end of the inductor L2 is respectively connected with the RF_Pend 1 pin of the microprocessor U1, one end of a capacitor C8 and one end of the inductor L1, the other end of the inductor L1 is respectively connected with one end of a capacitor C7 and one end of a capacitor C9, the other end of the capacitor C7 is connected with the No. 1 port of a transmitting antenna J1, the No. 2 interface of the transmitting antenna J1, the No. 3 interface of the transmitting antenna J1, the No. 4 interface of the transmitting antenna J1 and the No. 5 interface of the transmitting antenna J1 are respectively connected with the other end of a capacitor C8 and the other end of the capacitor C9 and grounded.

Optionally, the crystal oscillator circuit comprises a capacitor C11, a capacitor C12, a capacitor C17, a capacitor C18, a crystal oscillator Y1 and a crystal oscillator Y2; the X24M_N end 30 pin of the microprocessor U1 is respectively connected with one end of the crystal oscillator Y1 and one end of the capacitor C11, the X24M_P end 31 pin of the microprocessor U1 is respectively connected with the other end of the crystal oscillator Y1 and one end of the capacitor C12, the other end of the capacitor C11 is connected with the other end of the capacitor C12 and grounded, the X32K_Q1 end 5 pin of the microprocessor U1 is respectively connected with one end of the crystal oscillator Y2 and one end of the capacitor C18, the X32K_Q2 end 6 pin of the microprocessor U1 is respectively connected with the other end of the crystal oscillator Y2 and one end of the capacitor C17, and the other end of the capacitor C18 is respectively connected with the other end of the capacitor C17 and the GND end 16 pin of the energy management chip U3 and grounded.

Optionally, the reset circuit includes a capacitor C6 and a resistor R1; the nRESET end 21 pin of the microprocessor U1 is respectively connected with one end of a capacitor C6 and one end of a resistor R1, the other end of the capacitor C6 is grounded, and the other end of the resistor R1 is connected with the VDDS end 27 pin of the microprocessor U1, the VDDS2 end 11 pin of the microprocessor U1, the VDDS_DCDC end 19 pin of the microprocessor U1 and a first power supply filter circuit.

Optionally, the first power supply filter circuit includes a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, a capacitor C5, and an inductor FL1; the other end of the resistor R1, the pin VDDS end 27 of the microprocessor U1, the pin VDDS2 end 11 of the microprocessor U1, and the pin vdds_dcdc end 19 of the microprocessor U1 are respectively connected to one end of the capacitor C1, one end of the capacitor C2, one end of the capacitor C3, one end of the capacitor C4, one end of the capacitor C5, and one end of the inductor FL1, the other end of the capacitor C2, the other end of the capacitor C3, the other end of the capacitor C4, and the other end of the capacitor C5 are respectively grounded, and the other end of the inductor FL1 is connected to a fourth power supply.

Optionally, the second power supply filter circuit includes a capacitor C13, a capacitor C14, a capacitor C15, and an inductor L3; the dcdc_sw terminal 18 of the microprocessor U1 is connected to one end of the inductor L3, and the other end of the inductor L3 is respectively connected to the vddr_rf terminal 32 of the microprocessor U1, the VDDR terminal 28 of the microprocessor U1, one end of the capacitor C13, one end of the capacitor C14, and one end of the capacitor C15, and the other end of the capacitor C13, the other end of the capacitor C14, and the other end of the capacitor C15 are respectively grounded.

The technical scheme of the embodiment of the invention has at least the following advantages and beneficial effects:

the embodiment adopts an environment energy conversion energy supply mode, so that the requirement on a battery is saved, the running and maintenance cost of the whole system is reduced, and the pressure of environmental protection is reduced; meanwhile, the hardware safety protection is added, the terminal node is prevented from being attacked and controlled, and the safety of the whole system is ensured.

Drawings

Fig. 1 is a schematic circuit diagram of a hardware safety type Zigbee terminal based on environmental energy supply according to the present invention;

FIG. 2 is a schematic diagram illustrating a circuit connection of a microprocessor U1 according to the present invention;

fig. 3 is a schematic circuit connection diagram of an energy management chip U3 according to the present invention.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. The components of the embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.

As shown in fig. 1, 2 and 3, the present invention provides one of the embodiments: hardware-safe Zigbee terminals based on environmental energy supply, comprising: the system comprises a microprocessor U1, a safety management chip U2, an energy management chip U3, a transmitting antenna circuit, a capacitor C19, a capacitor C20, a capacitor C21, a capacitor C22, a capacitor C23, a capacitor C24, a capacitor Cin1, a step-up transformer T1 and an environmental energy collector access interface P2; the C1 end 13 pin of the energy management chip U3 is connected with one end of a capacitor C20, the C2 end 14 pin of the energy management chip U3 is connected with one end of a capacitor C22, the other end of the capacitor C20 and the other end of the capacitor C22 are respectively connected with one end of a step-up transformer T1, the other end of the step-up transformer T1 is respectively connected with the anode of a capacitor Cin1 and the No. 1 interface of an environment energy collector access interface P2, the cathode of the capacitor Cin1 is respectively connected with the No. 2 interface of the environment energy collector access interface P2, the VS2 end 10 pin of the energy management chip U3 and the GND end 9 pin of the energy management chip U3 and is grounded, the DIO_8end 25 pin of the microprocessor U1 is connected with the SDA end 5 pin of the safety management chip U2, the GND end 4 pin of the safety management chip U2 is connected with the GND end 1 pin of the energy management chip U3, one end of the capacitor C19, the negative electrode of the capacitor C23 and one end of the second power supply and is grounded, the VCC end 8 pin of the safety management chip U2 is connected with the first power supply, the other end of the capacitor C19 is respectively connected with the VAUX end 2 pin of the energy management chip U3 and the VS1 end 11 pin of the energy management chip U3, the other end of the second power supply is connected with the negative electrode of the capacitor C21, the positive electrode of the capacitor C21 is connected with the VSTORE end 3 pin of the energy management chip U3, the VOUT end 4 pin of the energy management chip U3 is respectively connected with the positive electrode of the capacitor C23 and the third power supply, and the RF_N end 2 pin of the microprocessor U1 and the RF_P end 1 pin of the microprocessor U1 are respectively connected with a transmitting antenna circuit.

The device also comprises a crystal oscillator circuit, a reset circuit, a first power supply filter circuit, a second power supply filter circuit, an interface P1 and a capacitor C10; the VDDS end 27 pin of the microprocessor U1, the VDDS2 end 11 pin of the microprocessor U1 and the VDDS_DCDC end 19 pin of the microprocessor U1 are respectively connected with a first power supply filter circuit and a reset circuit, the nRESET end 21 pin of the microprocessor U1 is connected with the reset circuit, the DCDC_SW end 18 pin of the microprocessor U1, the VDDR_RF end 32 pin of the microprocessor U1 and the VDDR end 28 pin of the microprocessor U1 are respectively connected with a second power supply filter circuit, the DCOUPL end 12 pin of the microprocessor U1 is connected with one end of a capacitor C10, the other end of the capacitor C10 is respectively connected with the VSS end 3 pin of the microprocessor U1, the VSS end 7 pin of the microprocessor U1, the VSS end 17 pin of the microprocessor U1, the VSS end 20 pin of the microprocessor U1, the VSS end 29 pin of the microprocessor U1 and the EGP end 33 pin of the microprocessor U1, the X32K_Q1 end 5 pin of the microprocessor U1, the X32K_Q2 end 6 pin of the microprocessor U1, the X24M_N end 30 pin of the microprocessor U1 and the X24M_P end 31 pin of the microprocessor U1 are respectively connected with a crystal oscillator circuit, the crystal oscillator circuit is connected with the GND end 16 pin of the energy management chip U3, the VLD0 end 6 pin of the energy management chip U3 is connected with one end of the capacitor C24, the GND end 8 pin of the energy management chip U3 is connected with the other end of the capacitor C2 and is grounded, the DIO_4 end 16 pin of the microprocessor U1 is connected with the VOUT2_EN end 12 pin of the energy management chip U3, the DIO_5 end 22 pin of the microprocessor U1 is connected with the No. 4 interface of the interface P1, the DIO_6 end 23 pin of the microprocessor U1 is connected with the No. 3 interface of the interface P1, the DIO_7 end 24 pin of the microprocessor U1 is connected with the No. 2 interface of the interface P1, the No. 1 interface of the interface P1 is grounded, and the No. 5 interface of the interface P1 is connected with the VOUT2 end 5 pin of the energy management chip U3.

The transmitting antenna circuit comprises an inductor L1, an inductor L2, a capacitor C7, a capacitor C8, a capacitor C9 and a transmitting antenna J1; the RF_N end 2 pin of the microprocessor U1 is connected with one end of an inductor L2, the other end of the inductor L2 is respectively connected with the RF_Pend 1 pin of the microprocessor U1, one end of a capacitor C8 and one end of the inductor L1, the other end of the inductor L1 is respectively connected with one end of a capacitor C7 and one end of a capacitor C9, the other end of the capacitor C7 is connected with the No. 1 port of a transmitting antenna J1, the No. 2 interface of the transmitting antenna J1, the No. 3 interface of the transmitting antenna J1, the No. 4 interface of the transmitting antenna J1 and the No. 5 interface of the transmitting antenna J1 are respectively connected with the other end of a capacitor C8 and the other end of the capacitor C9 and grounded.

The crystal oscillator circuit comprises a capacitor C11, a capacitor C12, a capacitor C17, a capacitor C18, a crystal oscillator Y1 and a crystal oscillator Y2; the X24M_N end 30 pin of the microprocessor U1 is respectively connected with one end of the crystal oscillator Y1 and one end of the capacitor C11, the X24M_P end 31 pin of the microprocessor U1 is respectively connected with the other end of the crystal oscillator Y1 and one end of the capacitor C12, the other end of the capacitor C11 is connected with the other end of the capacitor C12 and grounded, the X32K_Q1 end 5 pin of the microprocessor U1 is respectively connected with one end of the crystal oscillator Y2 and one end of the capacitor C18, the X32K_Q2 end 6 pin of the microprocessor U1 is respectively connected with the other end of the crystal oscillator Y2 and one end of the capacitor C17, and the other end of the capacitor C18 is respectively connected with the other end of the capacitor C17 and the GND end 16 pin of the energy management chip U3 and grounded.

The reset circuit comprises a capacitor C6 and a resistor R1; the nRESET end 21 pin of the microprocessor U1 is respectively connected with one end of a capacitor C6 and one end of a resistor R1, the other end of the capacitor C6 is grounded, and the other end of the resistor R1 is connected with the VDDS end 27 pin of the microprocessor U1, the VDDS2 end 11 pin of the microprocessor U1, the VDDS_DCDC end 19 pin of the microprocessor U1 and a first power supply filter circuit.

The first power supply filter circuit comprises a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, a capacitor C5 and an inductor FL1; the other end of the resistor R1, the pin VDDS end 27 of the microprocessor U1, the pin VDDS2 end 11 of the microprocessor U1, and the pin vdds_dcdc end 19 of the microprocessor U1 are respectively connected to one end of the capacitor C1, one end of the capacitor C2, one end of the capacitor C3, one end of the capacitor C4, one end of the capacitor C5, and one end of the inductor FL1, the other end of the capacitor C2, the other end of the capacitor C3, the other end of the capacitor C4, and the other end of the capacitor C5 are respectively grounded, and the other end of the inductor FL1 is connected to a fourth power supply.

The second power supply filter circuit comprises a capacitor C13, a capacitor C14, a capacitor C15 and an inductor L3; the dcdc_sw terminal 18 of the microprocessor U1 is connected to one end of the inductor L3, and the other end of the inductor L3 is respectively connected to the vddr_rf terminal 32 of the microprocessor U1, the VDDR terminal 28 of the microprocessor U1, one end of the capacitor C13, one end of the capacitor C14, and one end of the capacitor C15, and the other end of the capacitor C13, the other end of the capacitor C14, and the other end of the capacitor C15 are respectively grounded.

In the present embodiment, the energy supply of the nodes is realized by the energy harvesting, energy management chip U3. The interface P2 is an access interface of an environmental energy collector such as a solar battery or a thermopile, and the collected environmental energy is converged into the chip through the step-up transformer T1 and the energy coupling capacitor to collect and manage the energy. The energy management chip U3 supplies power to the microprocessor U1 of the terminal node through a 4-pin output standard 3.3 volts. The LDO in the energy management chip U3 provides a voltage stabilizing output of 2.2 volts to supply power for the safety management chip U2.

The sensor module is provided with three I/O ports (wherein DIO_7 can be used as analog I/O for data transmission between the analog sensor and the microprocessor). Considering that many sensor modules do not have a sleep function, the 16-pin (DIO_4) output of the microprocessor U1 controls the Vout2 enabling end of the energy management chip U3 to control the 5-pin output of the energy management chip U3 to supply power for the sensor modules, and the processing mode can ensure that the sensor consumes electric energy when data acquisition is needed, so that the power consumption of the whole node is reduced to the greatest possible extent.

The microprocessor U1 is an economical, efficient ultra low power 2.4GHz RF device with very low active RF and MCU currents. Three I/O interfaces are configured to be connected with the sensor module, wherein DIO_7 is used as an analog port and a digital port for data acquisition and communication between different types of sensors and the microprocessor; the chip is internally provided with a unique ultra-low power consumption sensor controller which is very suitable for being connected with an external sensor and can be used for autonomously collecting analog and digital data under the condition that the rest part of the system is in a sleep mode; the microprocessor performs corresponding processing on the acquired data and then communicates with the coordinator through the antenna.

The safety management scheme consists of a microprocessor and a safety management chip U2. The security management chip U2 is an encryption engine identity verification device with a high-security key storage function based on hardware, can effectively prevent physical attack on the node itself, and can also prevent logic attack on data transmitted between the device and the system. The security chip communicates with the microprocessor by means of a single bus.

In this embodiment, the reset circuit is composed of a resistor and a capacitor, and is used to ensure that the microprocessor can be automatically reset when powered on. The second power supply filter circuit is composed of an inductor and a capacitor and is used for filtering ripple interference possibly occurring on a power supply rail of the microprocessor. The first power supply filter circuit is used for filtering possible ripple interference and is used for sharing VDDR. And the transmitting antenna circuit is used for ensuring that radio frequency signals are coupled to an antenna (50 OHM) and ensuring wireless receiving and transmitting of data. And the crystal oscillator circuit is used for providing a high-frequency clock signal of 24 MHz and a low-frequency clock signal of 32.768K for the microprocessor respectively. The interface P1 is a sensor interface of the node, and can be conveniently connected with an analog or digital sensor to realize a data acquisition function.

In combination with the embodiment, the environmental energy collector is connected to the node through the P2 interface by using collected environmental energy (including solar energy, heat energy, vibration kinetic energy and the like), the step-up transformer T1 is used for boosting the collected electric energy and sending the boosted electric energy to the energy management chip U3, and the energy management chip U3 is used for integrating and optimally managing the collected environmental energy. The energy management chip U3 outputs stable 3.3V voltage to supply power for the microprocessor U1 through a 3.3V voltage rail; meanwhile, the LDO in the energy management chip U3 also outputs 2.2V voltage to provide energy for the safety management chip U2. The microprocessor U1 starts the power supply of the sensor module in real time according to the requirement of the working mode, collects the data collected by the sensor, sorts, analyzes and packages the data, and transmits the data meeting the wireless transmission protocol to the antenna to realize communication with the zigbee coordinator. Before the microprocessor collects the sensor data for packing and uploading, the security management chip U2 and the microprocessor verify the digital signature and the secret key in a single bus mode, so that the identity verification of the node in the whole network is ensured, and the hardware security in the true sense is realized.

In addition, in this embodiment, the output voltage value of the pin Vout of the chip may be changed by modifying different connection modes of the pins vs1 and vs2 on the configuration of the chip U3, so as to achieve selection of different supply voltages. Deviations may occur in the configuration of the I/O ports of the chip of microprocessor U1. The method comprises the steps of adjusting the pin sequence of the U1 and the sensor interface P1 and the connection allocation of the I/O ports; I/O port allocation adjustment adopted by the communication realization of the U1 and the chip U2 is realized; u1 is connected with I/O allocation adjustment of the control Vout2_EN pin of the U3 chip.

The above is only a preferred embodiment of the present invention, and is not intended to limit the present invention, but various modifications and variations can be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. The hardware safety type Zigbee terminal based on environment energy supply is characterized by comprising: the system comprises a microprocessor U1, a safety management chip U2, an energy management chip U3, a transmitting antenna circuit, a capacitor C19, a capacitor C20, a capacitor C21, a capacitor C22, a capacitor C23, a capacitor C24, a capacitor Cin1, a step-up transformer T1 and an environmental energy collector access interface P2; the C1 end 13 pin of the energy management chip U3 is connected with one end of a capacitor C20, the C2 end 14 pin of the energy management chip U3 is connected with one end of a capacitor C22, the other end of the capacitor C20 and the other end of the capacitor C22 are respectively connected with one end of a step-up transformer T1, the other end of the step-up transformer T1 is respectively connected with the anode of a capacitor Cin1 and the No. 1 interface of an environment energy collector access interface P2, the cathode of the capacitor Cin1 is respectively connected with the No. 2 interface of the environment energy collector access interface P2, the VS2 end 10 pin of the energy management chip U3 and the GND end 9 pin of the energy management chip U3 and is grounded, the DIO_8end 25 pin of the microprocessor U1 is connected with the SDA end 5 pin of the safety management chip U2, the GND end 4 pin of the safety management chip U2 is connected with the GND end 1 pin of the energy management chip U3, one end of a capacitor C19, the negative electrode of a capacitor C23 and one end of a second power supply and is grounded, the VCC end 8 pin of the safety management chip U2 is connected with the first power supply, the other end of the capacitor C19 is respectively connected with the VAUX end 2 pin of the energy management chip U3 and the VS1 end 11 pin of the energy management chip U3, the other end of the second power supply is connected with the negative electrode of the capacitor C21, the positive electrode of the capacitor C21 is connected with the VSTORE end 3 pin of the energy management chip U3, the VOUT end 4 pin of the energy management chip U3 is respectively connected with the positive electrode of the capacitor C23 and a third power supply, and the RF_N end 2 pin of the microprocessor U1 and the RF_P end 1 pin of the microprocessor U1 are respectively connected with a transmitting antenna circuit;

the device also comprises a crystal oscillator circuit, a reset circuit, a first power supply filter circuit, a second power supply filter circuit, an interface P1 and a capacitor C10; the VDDS end 27 pin of the microprocessor U1, the VDDS2 end 11 pin of the microprocessor U1 and the VDDS_DCDC end 19 pin of the microprocessor U1 are respectively connected with a first power supply filter circuit and a reset circuit, the nRESET end 21 pin of the microprocessor U1 is connected with the reset circuit, the DCDC_SW end 18 pin of the microprocessor U1, the VDDR_RF end 32 pin of the microprocessor U1 and the VDDR end 28 pin of the microprocessor U1 are respectively connected with a second power supply filter circuit, the DCOUPL end 12 pin of the microprocessor U1 is connected with one end of a capacitor C10, the other end of the capacitor C10 is respectively connected with the VSS end 3 pin of the microprocessor U1, the VSS end 7 pin of the microprocessor U1, the VSS end 17 pin of the microprocessor U1, the VSS end 20 pin of the microprocessor U1, the VSS end 29 pin of the microprocessor U1 and the EGP end 33 pin of the microprocessor U1, the method comprises the steps that a pin X32K_Q1 end 5 of a microprocessor U1, a pin X32K_Q2 end 6 of the microprocessor U1, a pin X24M_N end 30 of the microprocessor U1 and a pin X24M_P end 31 of the microprocessor U1 are respectively connected with a crystal oscillator circuit, the crystal oscillator circuit is connected with a pin GND end 16 of an energy management chip U3, a pin VLD0 end 6 of the energy management chip U3 is connected with one end of a capacitor C24, a pin GND end 8 of the energy management chip U3 is connected with the other end of the capacitor C2, the pin DIO_4 end 16 of the microprocessor U1 is connected with a pin VOUT2_EN end 12 of the energy management chip U3, a pin DIO_5 end 22 of the microprocessor U1 is connected with a No. 4 interface of an interface P1, a pin DIO_6 end 23 of the microprocessor U1 is connected with a No. 3 interface of the interface P1, a pin DIO_7 end 24 of the microprocessor U1 is connected with a No. 2 interface of the interface P1, a No. 1 interface of the interface P1 is grounded, and a pin DIO_4 of the interface P1 is connected with a No. 5 interface of the energy management chip U3;

the transmitting antenna circuit comprises an inductor L1, an inductor L2, a capacitor C7, a capacitor C8, a capacitor C9 and a transmitting antenna J1; the RF_N end 2 pin of the microprocessor U1 is connected with one end of an inductor L2, the other end of the inductor L2 is respectively connected with the RF_Pend 1 pin of the microprocessor U1, one end of a capacitor C8 and one end of the inductor L1, the other end of the inductor L1 is respectively connected with one end of a capacitor C7 and one end of a capacitor C9, the other end of the capacitor C7 is connected with the No. 1 port of a transmitting antenna J1, the No. 2 interface of the transmitting antenna J1, the No. 3 interface of the transmitting antenna J1, the No. 4 interface of the transmitting antenna J1 and the No. 5 interface of the transmitting antenna J1 are respectively connected with the other end of a capacitor C8 and the other end of the capacitor C9 and grounded;

the crystal oscillator circuit comprises a capacitor C11, a capacitor C12, a capacitor C17, a capacitor C18, a crystal oscillator Y1 and a crystal oscillator Y2, wherein an X24M-N end 30 pin of a microprocessor U1 is respectively connected with one end of the crystal oscillator Y1 and one end of the capacitor C11, an X24M-P end 31 pin of the microprocessor U1 is respectively connected with the other end of the crystal oscillator Y1 and one end of the capacitor C12, the other end of the capacitor C11 is connected with the other end of the capacitor C12 and grounded, an X32K-Q1 end 5 pin of the microprocessor U1 is respectively connected with one end of the crystal oscillator Y2 and one end of the capacitor C18, an X32K-Q2 end 6 pin of the microprocessor U1 is respectively connected with the other end of the crystal oscillator Y2 and one end of the capacitor C17, and the other end of the capacitor C18 is respectively connected with the other end of the capacitor C17 and a GND end 16 pin of an energy management chip U3;

the reset circuit comprises a capacitor C6 and a resistor R1; the nRESET end 21 pin of the microprocessor U1 is respectively connected with one end of a capacitor C6 and one end of a resistor R1, the other end of the capacitor C6 is grounded, and the other end of the resistor R1 is connected with the VDDS end 27 pin of the microprocessor U1, the VDDS2 end 11 pin of the microprocessor U1, the VDDS_DCDC end 19 pin of the microprocessor U1 and a first power supply filter circuit;

the first power supply filter circuit comprises a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, a capacitor C5 and an inductor FL1; the other end of the resistor R1, the pin of the VDDS end 27 of the microprocessor U1, the pin of the VDDS2 end 11 of the microprocessor U1 and the pin of the VDDS_DCDC end 19 of the microprocessor U1 are respectively connected with one end of the capacitor C1, one end of the capacitor C2, one end of the capacitor C3, one end of the capacitor C4, one end of the capacitor C5 and one end of the inductor FL1, the other end of the capacitor C2, the other end of the capacitor C3, the other end of the capacitor C4 and the other end of the capacitor C5 are respectively grounded, and the other end of the inductor FL1 is connected with a fourth power supply;