CN115412100A - Digital-to-analog converter integrating 2 - Google Patents
Digital-to-analog converter integrating 2 Download PDFInfo
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- CN115412100A CN115412100A CN202211067891.3A CN202211067891A CN115412100A CN 115412100 A CN115412100 A CN 115412100A CN 202211067891 A CN202211067891 A CN 202211067891A CN 115412100 A CN115412100 A CN 115412100A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
- H03M1/662—Multiplexed conversion systems
Abstract
The application discloses an integrated 2: a plurality of bit digital analog conversion units and differential signal input stage, every digital analog conversion brick unit includes: a current mirror comprising first and second NMOS transistors, both gates coupled to a bias voltage, and sources coupled to first and second nodes, respectively; third through sixth NMOS transistors, third and fourth NMOS transistors having drains coupled to the first node, fifth and sixth NMOS transistors having drains coupled to the second node, the gates of the third and fifth NMOS transistors are respectively coupled with the first pair of differential signals, and the gates of the fourth and sixth NMOS transistors are respectively coupled with the second pair of differential signals; the differential signal input stage includes first to eighth nand gates and first to fourth inverters. The present application addresses the clock speed requirements of the conventional 2.
Description
Technical Field
The present invention relates generally to the field of integrated circuit technology, and more particularly to a digital-to-analog converter integrated with a 2.
Background
In high-speed SerDes circuit applications based on digital-to-analog converter schemes, the performance of the last stage multiplexer directly affects the output signal linearity and the eye diagram quality of the digital-to-analog converter. Currently mainstream digital-to-analog converter scheme-based high-speed SerDes TX generally employs Half-speed architecture (Half Rate) and Quarter-speed architecture (Quarter Rate). The last set of multiplexers in the half-speed architecture, i.e., 2. With the increasing speed of SerDes applications, the speed requirements of a common 2. Here we propose a novel 2.
Disclosure of Invention
The invention aims to provide a digital-to-analog converter integrated with a 2.
The application discloses a digital-to-analog converter of integrated 2:
a plurality of bit digital to analog conversion units, each digital to analog conversion brick unit includes:
a current mirror comprising a first NMOS transistor and a second NMOS transistor, the gates of the first and second NMOS transistors each coupled to a bias voltage, the drains each coupled to a voltage source, the source of the first NMOS transistor coupled to a first node, the source of the second NMOS transistor coupled to a second node; and
third through sixth NMOS transistors, the drains of the third and fourth NMOS transistors each coupled to the first node, the drains of the fifth and sixth NMOS transistors each coupled to the second node, the gates of the third and fifth NMOS transistors each coupled to a first pair of differential signals, and the gates of the fourth and sixth NMOS transistors each coupled to a second pair of differential signals;
a differential signal input stage comprising first to eighth NAND-gates and first to fourth inverters, wherein outputs of the first and second NAND-gates are coupled to an input of the first inverter through a first switch and a second switch, respectively, outputs of the fifth and sixth NAND-gates are coupled to an input of the third inverter through a fifth switch and a sixth switch, respectively, outputs of the first and third inverters provide the first pair of differential signals, outputs of the third and fourth NAND-gates are coupled to an input of the third inverter through a third switch and a fourth switch, respectively, outputs of the seventh and eighth NAND-gates are coupled to an input of the fourth inverter through a seventh switch and an eighth switch, respectively, outputs of the second and fourth inverters provide the second pair of differential signals, respectively.
In a preferred embodiment, a first clock signal of four clock signals sequentially different in phase by 90 ° is coupled to one input of the fourth and eighth nand gates, a second clock signal is coupled to one input of the first and fifth nand gates, a third clock signal is coupled to one input of the third and seventh nand gates, and a fourth clock signal is coupled to one input of the second and sixth nand gates; sampling rising edges of the four clock signals respectively to obtain four pairs of differential clock sampling signals, wherein a first pair of differential clock sampling signals is coupled to the other input ends of the first NAND gate and the fifth NAND gate respectively, a second pair of differential clock sampling signals is coupled to the other input ends of the third NAND gate and the seventh NAND gate respectively, a third pair of differential clock sampling signals is coupled to the other input ends of the second NAND gate and the sixth NAND gate respectively, and a fourth pair of differential clock sampling signals is coupled to the other input ends of the fourth NAND gate and the eighth NAND gate respectively; the first switch and the fifth switch are controlled by the third path of clock signal, the second switch and the sixth switch are controlled by the first path of clock signal, the third switch and the seventh switch are controlled by the fourth clock signal, and the fourth switch and the eighth switch are controlled by the second path of clock signal.
In a preferred embodiment, the digital-to-analog converter further includes a first resistor and a second resistor, the first resistor is connected in series between the drain of the first NMOS transistor of each digital-to-analog brick unit and the power supply terminal, and the second resistor is connected in series between the drain of the second NMOS transistor of each digital-to-analog brick unit and the power supply terminal.
In a preferred embodiment, the digital-to-analog converter is a tailless current-steering digital-to-analog converter.
In a preferred embodiment, the first pair of differential signals and the second pair of differential signals are return-to-zero codes.
In a preferred embodiment, the digital-to-analog converter further includes: a bias voltage providing circuit, comprising: the drain and the gate of the seventh NMOS transistor are connected with the current source and provide the bias voltage to the gates of the first NMOS transistor and the second NMOS transistor, the source of the seventh NMOS transistor is connected with the drain of the eighth NMOS transistor, the gate of the eighth NMOS transistor is connected with a power supply end, and the source of the eighth NMOS transistor is connected with a ground end.
Compared with the prior art, the method has the following beneficial effects:
a novel tailless digital-to-analog converter (DAC) with two cascaded 2.
First, in the design of the 2.
Second, the output of the 2.
Third, the 2. A-B-A-B-A-B-A-B \8230realizesthe table tennis mode and the working principle.
Fourth, a conventional final stage multiplexer and digital-to-analog conversion is often accompanied by several stages of inverters INV. The integration of 2.
The present specification describes a number of technical features distributed throughout the various technical aspects, and if all possible combinations of technical features (i.e. technical aspects) of the present specification are listed, the description is made excessively long. In order to avoid this problem, the respective technical features disclosed in the above-mentioned summary of the invention of the present application, the respective technical features disclosed in the following embodiments and examples, and the respective technical features disclosed in the drawings may be freely combined with each other to constitute various new technical solutions (these technical solutions should all be considered as having been described in the present specification), unless such a combination of the technical features is technically impossible. For example, in one example, feature a + B + C is disclosed, in another example, feature a + B + D + E is disclosed, and features C and D are equivalent technical means that serve the same purpose, technically only one feature is used, but not both, and feature E may be technically combined with feature C, then the solution of a + B + C + D should not be considered as already described because the technology is not feasible, and the solution of a + B + C + E should be considered as already described.
Drawings
Fig. 1 is a circuit diagram of a digital-to-analog converter in an embodiment of the present application.
Fig. 2 is a circuit diagram of a differential signal input stage in one embodiment of the present application.
FIG. 3 is a timing diagram of a digital-to-analog converter according to an embodiment of the present application.
Detailed Description
In the following description, numerous technical details are set forth in order to provide a better understanding of the present application. However, it will be understood by those skilled in the art that the technical solutions claimed in the present application may be implemented without these technical details and with various changes and modifications based on the following embodiments.
To make the objects, technical solutions and advantages of the present application more clear, embodiments of the present application will be described in further detail below with reference to the accompanying drawings.
The application discloses a digital-to-analog converter of integrated 2: a plurality of bit digital-to-analog conversion units and a differential signal input stage, in one embodiment, the digital-to-analog converter DAC is a tailless current-steering digital-to-analog converter. Fig. 1 shows a novel tailless digital-to-analog converter (DAC) with two cascaded 2-Multiplexer (MUX) structures in one embodiment.
Each digital brick changing unit comprises: a current mirror, and third through sixth NMOS transistors. The current mirror includes a first NMOS transistor N1 and a second NMOS transistor N2, the gates of the first NMOS transistor N1 and the second NMOS transistor N2 are both coupled to the bias voltage VBS, the drains are both coupled to the voltage source, the source of the first NMOS transistor N1 is coupled to the first node T1, and the source of the second NMOS transistor N2 is coupled to the second node T2.
In one embodiment, the digital-to-analog converter further includes a first resistor R1 and a second resistor R2, the first resistor R1 is connected in series between the drain of the first NMOS transistor N1 of each digital-to-analog brick unit and the power supply terminal, and the second resistor R2 is connected in series between the drain of the second NMOS transistor N2 of each digital-to-analog brick unit and the power supply terminal.
Drains of the third and fourth NMOS transistors N3 and N4 are each coupled to the first node T1, drains of the fifth and sixth NMOS transistors N5 and N6 are each coupled to the second node T2, gates of the third and fifth NMOS transistors N3 and N5 are coupled to the first pair of differential signals a, ab, respectively, and gates of the fourth and sixth NMOS transistors N4 and N6 are coupled to the second pair of differential signals B, bb, respectively.
The digital-to-analog converter further includes: a bias voltage providing circuit, comprising: the current source I, the seventh NMOS transistor N7, the eighth NMOS transistor N8 and the capacitor C, wherein the drain electrode and the gate electrode of the seventh NMOS transistor N7 are connected with the current source I and provide a bias voltage VBS to the gate electrodes of the first NMOS transistor N1 and the second NMOS transistor N2, the source electrode of the seventh NMOS transistor N7 is connected with the drain electrode of the eighth NMOS transistor N8, the gate electrode of the eighth NMOS transistor N8 is connected with a power supply end, and the source electrode of the eighth NMOS transistor N8 is connected with a ground end. The capacitor C is connected to the gates of the first NMOS transistor N1 and the second NMOS transistor N2.
Fig. 2 shows a schematic diagram of a differential signal input stage in one embodiment. The differential signal input stage comprises a first NAND gate NAND1, a second NAND gate NAND2, a third NAND gate NAND3, a fourth NAND gate NAND4, a fifth NAND gate NAND5, a sixth NAND gate NAND6, a seventh NAND gate NAND7, an eighth NAND gate NAND8, a first inverter INV1, a second inverter INV2, a third inverter INV3 and a fourth inverter INV1. The outputs of the first NAND-gate NAND1 and the second NAND-gate NAND2 are coupled to the input of a first inverter INV1 via a first switch S1 and a second switch S2, respectively, the outputs of the fifth NAND-gate NAND5 and the sixth NAND-gate NAND6 are coupled to the input of a third inverter INV3 via a fifth switch S5 and a sixth switch S6, respectively, the outputs of the first inverter INV1 and the third inverter INV3 providing a first pair of differential signals a, ab, the outputs of the third NAND gate NAND3 and the fourth NAND gate NAND4 are coupled to the input of the third inverter INV3 through the third switch S3 and the fourth switch S4, respectively, the outputs of the seventh NAND gate NAND7 and the eighth NAND gate NAND8 are coupled to the input of the fourth inverter INV4 through the seventh switch S7 and the eighth switch S8, respectively, and the outputs of the second inverter INV2 and the fourth inverter INV4 provide the second pair of differential signals B, bb, respectively.
In one embodiment, a first clock signal Q1 of the four clock signals Q1/Q2/Q3/Q4 sequentially differing by 90 ° in phase is coupled to one input terminals of a fourth NAND gate NAND4 and an eighth NAND gate NAND8, a second clock signal Q2 is coupled to one input terminals of the first NAND gate NAND1 and a fifth NAND gate NAND5, a third clock signal Q3 is coupled to one input terminals of a third NAND gate NAND3 and a seventh NAND gate NAND7, and a fourth clock signal Q4 is coupled to one input terminals of the second NAND gate NAND2 and a sixth NAND gate NAND 6. Four pairs of differential clock sampling signals D1/D2/D3/D4/DB1/DB2/DB3/DB4 are obtained by sampling the rising edges of the four clock signals Q1/Q2/Q3/Q4 respectively. The first pair of differential clock sampling signals D1/DB1 is coupled to the other input of the first NAND-gate NAND1 and the fifth NAND-gate NAND, the second pair of differential clock sampling signals D2/DB2 is coupled to the other input of the third NAND-gate NAND3 and the seventh NAND-gate NAND7, the third pair of differential clock sampling signals D3/DB3 is coupled to the other input of the second NAND-gate NAND2 and the sixth NAND-gate NAND6, and the fourth pair of differential clock sampling signals D4/DB4 is coupled to the other input of the fourth NAND-gate NAND4 and the eighth NAND-gate NAND 8. The first switch S1 and the fifth switch S5 are controlled by a third clock signal Q3, the second switch S2 and the sixth switch S6 are controlled by a first clock signal Q1, the third switch S3 and the seventh switch S7 are controlled by a fourth clock signal Q4, and the fourth switch S4 and the eighth switch S8 are controlled by a second clock signal Q2. The present application addresses the clock speed requirements of the conventional 2.
The first pair of differential signals a, ab and the second pair of differential signals B, bb are return-to-zero (RZ) codes, effectively avoiding the effects of ISI.
Fig. 3 shows a timing diagram of the digital-to-analog converter in one embodiment. Suppose that the rising edge of Q1 produces data D1 and the rising edge of Q2 produces data D2, and so on. The output data a multiplexes the data D1 and D3. When Q1=0, Q2= Q3=1 (high potential) Q4=0, a = D1; when Q1=0, q2=0, Q3=1, Q4=1, a =0; when Q1=1, q2=0, Q3=0, Q4=1, a = D3; when Q1=1, q2=1, Q3=0, and Q4=0, a =0. The same applies to the multiplexing of data D2 and D3 by B.
The 2. A-B-A-B-A-B-A-B \8230realizesthe table tennis mode and the working principle. A conventional final stage multiplexer and digital-to-analog conversion is often accompanied by several stages of inverters INV. 2.
It is noted that, in the present patent application, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, the use of the verb "comprise a" to define an element does not exclude the presence of another, same element in a process, method, article, or apparatus that comprises the element. In the present patent application, if it is mentioned that a certain action is executed according to a certain element, it means that the action is executed according to at least the element, and two cases are included: performing the action based only on the element, and performing the action based on the element and other elements. The expression of a plurality of, a plurality of and the like includes 2, 2 and more than 2, more than 2 and more than 2.
This specification includes combinations of the various embodiments described herein. Separate references to embodiments (e.g., "one embodiment" or "some embodiments" or "a preferred embodiment") do not necessarily refer to the same embodiment; however, these embodiments are not mutually exclusive, unless indicated as mutually exclusive or as would be apparent to one of ordinary skill in the art. It should be noted that the term "or" is used in this specification in a non-exclusive sense unless the context clearly dictates otherwise.
All documents mentioned in this specification are to be considered as being incorporated in their entirety into the disclosure of the present application so as to be subject to modification as necessary. It should be understood that the above description is only for the preferred embodiment of the present disclosure, and is not intended to limit the scope of the present disclosure. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of one or more embodiments of the present disclosure should be included in the scope of protection of one or more embodiments of the present disclosure.
Claims (6)
1. A digital-to-analog converter incorporating a 2:
a plurality of bit digital to analog conversion units, each digital to analog conversion brick unit includes:
a current mirror comprising a first NMOS transistor and a second NMOS transistor, the gates of the first and second NMOS transistors each coupled to a bias voltage, the drains each coupled to a voltage source, the source of the first NMOS transistor coupled to a first node, the source of the second NMOS transistor coupled to a second node; and
third through sixth NMOS transistors, the drains of the third and fourth NMOS transistors each coupled to the first node, the drains of the fifth and sixth NMOS transistors each coupled to the second node, the gates of the third and fifth NMOS transistors each coupled to a first pair of differential signals, the gates of the fourth and sixth NMOS transistors each coupled to a second pair of differential signals;
a differential signal input stage comprising first to eighth NAND-gates and first to fourth inverters, wherein outputs of the first and second NAND-gates are coupled to an input of the first inverter through a first switch and a second switch, respectively, outputs of the fifth and sixth NAND-gates are coupled to an input of the third inverter through a fifth switch and a sixth switch, respectively, outputs of the first and third inverters provide the first pair of differential signals, outputs of the third and fourth NAND-gates are coupled to an input of the third inverter through a third switch and a fourth switch, respectively, outputs of the seventh and eighth NAND-gates are coupled to an input of the fourth inverter through a seventh switch and an eighth switch, respectively, outputs of the second and fourth inverters provide the second pair of differential signals, respectively.
2. The digital-to-analog converter of an integrated 2-multiplexer of claim 1, wherein a first clock signal of four clock signals sequentially 90 ° out of phase is coupled to one input of said fourth and eighth nand-gates, a second clock signal is coupled to one input of said first and fifth nand-gates, a third clock signal is coupled to one input of said third and seventh nand-gates, and a fourth clock signal is coupled to one input of said second and sixth nand-gates; sampling rising edges of the four clock signals respectively to obtain four pairs of differential clock sampling signals, wherein a first pair of differential clock sampling signals is coupled to the other input ends of the first NAND gate and the fifth NAND gate respectively, a second pair of differential clock sampling signals is coupled to the other input ends of the third NAND gate and the seventh NAND gate respectively, a third pair of differential clock sampling signals is coupled to the other input ends of the second NAND gate and the sixth NAND gate respectively, and a fourth pair of differential clock sampling signals is coupled to the other input ends of the fourth NAND gate and the eighth NAND gate respectively; the first switch and the fifth switch are controlled by the third path of clock signal, the second switch and the sixth switch are controlled by the first path of clock signal, the third switch and the seventh switch are controlled by the fourth clock signal, and the fourth switch and the eighth switch are controlled by the second path of clock signal.
3. The digital-to-analog converter of the integrated 2.
4. The digital-to-analog converter of the integrated 2.
5. The digital-to-analog converter of an integrated 2.
6. The digital-to-analog converter of an integrated 2: a bias voltage providing circuit, comprising: the drain and the gate of the seventh NMOS transistor are connected with the current source and provide the bias voltage to the gates of the first NMOS transistor and the second NMOS transistor, the source of the seventh NMOS transistor is connected with the drain of the eighth NMOS transistor, the gate of the eighth NMOS transistor is connected with a power supply end, and the source of the eighth NMOS transistor is connected with a ground end.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117220649A (en) * | 2023-11-07 | 2023-12-12 | 浙江大学 | Latch for high speed one-by-eight multiplexer |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117220649A (en) * | 2023-11-07 | 2023-12-12 | 浙江大学 | Latch for high speed one-by-eight multiplexer |
| CN117220649B (en) * | 2023-11-07 | 2024-04-16 | 浙江大学 | Latch for high speed one-by-eight multiplexer |
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