CN115410985A - Wafer dicing channel interconnect structure - Google Patents

Abstract

This application technical scheme provides a wafer cutting way interconnect structure, the wafer cutting way includes non-laser cutting district and is located the laser cutting district of non-laser cutting district both sides, the line structure includes: a top lead layer located on a main body portion of the non-laser-cutting region; the top conducting layer is positioned in the laser cutting area and the non-laser cutting areas on two sides of the top lead layer; the pad layer is positioned on the top layer lead layer and a non-laser cutting area and a laser cutting area which are arranged above the top layer conductive layer, wherein the top layer lead layer is directly connected with the pad layer, and a first passivation layer is further arranged between the top layer conductive layer and the pad layer. According to the technical scheme, the wafer cutting channel inner connecting line structure can obviously improve WAT electrical property under the condition that DED occurrence probability and severity are not influenced.

Description

Wafer dicing channel interconnection structure

Technical Field

The application relates to the field of wafer testing, in particular to a wafer cutting path internal connection structure.

Background

In the chip packaging process, laser groove processing (Laser groove processing) is performed to remove all circuit structure layers in a wafer dicing lane (wafer dicing lane) area to be cut, so as to provide a reserved operation space for a cutter during subsequent mechanical cutting and avoid damage of the cutter to the edge of a crystal grain.

Since the laser (laser) is used to rapidly burn in the scribe lane area, different structural layers, such as a test structure, a relatively open area, etc., may be caused to locally and finely burst, especially in the junction area of the scribe lane, and such burst is likely to occur in a passivation layer or a low dielectric constant (low k) layer, and if the range is too large or beyond control, there is a risk of Die Edge Delamination (DED).

Because the structural design of the cutting path occurs in the wafer manufacturing stage, the laser grooving process occurs in the packaging stage, the parameter and equipment conditions of each packaging factory are different, and meanwhile, because the laser cutting inevitably contacts the Test structure (Test key) under most conditions, the Test structure generally comprises a liner layer (Pad) and a Metal layer (Metal) at the lower layer, the design of the Metal has an important influence on the occurrence probability and severity of the DED problem, and the area of the Metal restricts the electrical performance of the wafer reliability Test (WAT).

Disclosure of Invention

The technical problem that this application will be solved provides a wafer cutting way inner connection structure, can show under the condition that does not influence DED's emergence probability and severity, and promote WAT electrical property.

In order to solve the above technical problem, the present application provides a wafer scribe line interconnect structure, the wafer scribe line includes non-laser cutting district and is located the laser cutting district of non-laser cutting district both sides, the line structure includes: a top lead layer located on a body portion of the non-laser-cut region; the top conducting layer is positioned in the laser cutting area and the non-laser cutting area on two sides of the top lead layer; the pad layer is positioned on the top layer lead layer and a non-laser cutting area and a laser cutting area which are arranged above the top layer conductive layer, wherein the top layer lead layer is directly connected with the pad layer, and a first passivation layer is further arranged between the top layer conductive layer and the pad layer.

In the embodiment of the present application, the laser scribe area is an area extending from the edge of the scribe line to the inside by a specific width.

In the embodiment of the present application, the width of the top lead layer in the direction perpendicular to the extending direction of the dicing streets is less than or equal to the width of the non-laser-scribe regions.

In the embodiment of the application, the width of the top lead layer in the direction perpendicular to the extending direction of the dicing streets is not more than 27 μm, and the width of the top lead layer in the direction parallel to the extending direction of the dicing streets is 50 μm to 100 μm.

In the embodiment of the present application, a contact surface between the top lead layer and the pad layer is circular or polygonal.

In an embodiment of the present application, the top conductive layer includes strip structures extending outward from edges of the top lead layer and arranged at intervals, and a ring structure connected to ends of the strip structures.

In an embodiment of the present application, a cross section of the ring structure is quadrilateral, wherein a first side and a second side perpendicular to an extending direction of the dicing street span the non-laser cutting area and the laser cutting area, and a third side and a fourth side parallel to the extending direction of the dicing street are located in the laser cutting area.

In the embodiment of the application, the length of the first side and the second side is 27-44 μm.

In this application embodiment, connect first limit with top layer lead wire layer the second limit with the stripe structure on top layer lead wire layer is located the non-laser cutting district connects the third limit with top layer lead wire layer the fourth edge with the stripe structure on top layer lead wire layer is located the laser cutting district.

In the embodiment of the present application, the number of the stripe structures located in the laser cutting area is less than the number of the stripe structures located in the non-laser cutting area.

In the embodiment of the present application, a dielectric layer is further included between adjacent stripe structures.

In an embodiment of the present invention, the scribe line interconnect structure further includes a second passivation layer on a surface of the pad layer above the first passivation layer.

In an embodiment of the present application, the material of the first passivation layer and the second passivation layer includes a silicon compound.

In an embodiment of the present application, the material of the pad layer includes aluminum.

Compared with the prior art, the wafer cutting channel internal connection structure has the following beneficial effects:

the wafer cutting way inner connection structure of the technical scheme of the application comprises a top layer lead layer and a top layer conducting layer, wherein the top layer lead layer is located at the main body part of a non-laser cutting area, the top layer lead layer is directly connected with a lining layer, the effective electric contact area of the WAT is increased, and the electric performance of the WAT is remarkably improved.

The top layer conducting layer includes certainly top layer lead layer edge outwards extends and interval arrangement's strip structures and connects the terminal ring structure of strip structures, wherein the strip structures of most are located non-laser cutting district, and the strip structures that only has a subtotal is located the laser cutting district, has further ensured that this application technical scheme's wafer cutting way in-connection line structure can not influence DED's emergence probability and severity.

The area of the backing layer covered by the passivation layer of the wafer cutting channel internal connection line structure is greatly reduced, the operation area of the backing layer is enlarged under the condition that the size of the backing layer is kept unchanged, and WAT is facilitated.

Drawings

The following drawings describe in detail exemplary embodiments disclosed in the present application. Wherein like reference numerals represent similar structures throughout the several views of the drawings. Those of ordinary skill in the art will understand that the present embodiments are non-limiting, exemplary embodiments and that the accompanying drawings are for illustrative and descriptive purposes only and are not intended to limit the scope of the present application, as other embodiments may equally fulfill the inventive intent of the present application. It should be understood that the figures are not drawn to scale. Wherein:

FIG. 1 is a schematic diagram of a top view of an interconnect structure in a wafer scribe line;

FIG. 2 isbase:Sub>A cross-sectional view taken at location A-A of FIG. 1;

FIG. 3 is a schematic diagram illustrating a top view of an interconnect structure of a dicing street according to an embodiment of the present application;

fig. 4 is a cross-sectional view at the position B-B in fig. 3.

Detailed Description

The following description is presented to enable one of ordinary skill in the art to make and use the present disclosure. Various localized modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present application. Thus, the present application is not limited to the embodiments shown, but is to be accorded the widest scope consistent with the claims.

In the current 28nm/14nm scribe line, in order to reduce the area of the top metal layer, the top metal layer is designed to be a grid shape, and the pad and the top metal layer are connected only through a few vias (via) on both sides. While such a design may improve the problem of DED in dicing, WAT is not favored due to the limited via contact area between the pad and the top metal layer.

Referring to fig. 1 and 2, fig. 1 isbase:Sub>A schematic top view ofbase:Sub>A wafer scribe line interconnect structure, and fig. 2 isbase:Sub>A cross-sectional view atbase:Sub>A-base:Sub>A position in fig. 1. The wafer dicing channel interconnection structure comprises a top metal layer 10, wherein a first passivation layer 20 is arranged on the surface of the top metal layer 10, a plurality of through holes 21 are formed on two sides of the first passivation layer 20, a liner layer 30 is formed on the surface of the first passivation layer 20 and in the through holes 21, and the top metal layer 10 is connected with the liner layer 30 in the through holes 21. The pad layer 30 has a through hole 41 therein, and a second passivation layer 40 is further included on a portion of the surface of the pad layer 30 and in the through hole 41. In order to make fig. 1 more clearly show the structure of the top metal layer, the structure above the top metal layer 10 in fig. 1 is removed, and the removed structure can be understood in conjunction with fig. 2. Since the bottom area of the through hole 21 is small, the contact area between the top metal layer 10 and the through hole 21 is small, which is not favorable for WAT. Meanwhile, the second passivation layer 40 covers a portion of the pad layer 30, so that the working area of the pad layer 30 is reduced, which is disadvantageous for the WAT.

In view of this, according to the technical solution of the present application, the density of the top metal layer is redistributed by improving the top metal layer below the pad layer, so that the area of the top metal layer located in the laser cutting region is smaller, thereby ensuring that the occurrence probability and the severity of the DED are not affected. Meanwhile, the area of the top metal layer of the non-laser cutting area is increased, and the WAT electrical property can be remarkably improved.

The embodiment of the application provides a wafer scribe line interconnect structure, a circuit connection structure of a device is provided below the wafer scribe line interconnect structure, and the circuit connection structure of the device is an existing structure and will not be described herein.

Referring to fig. 3 and 4, fig. 3 is a schematic top view of a scribe line interconnect structure according to an embodiment of the present invention, in order to clearly show the structures of the top lead layer and the top conductive layer according to an embodiment of the present invention, the structures above the top lead layer and the top conductive layer are removed, and the removed structure can be referred to fig. 4. Fig. 4 is a cross-sectional view at the position B-B in fig. 3. The dicing streets include non-laser dicing regions 110 and laser dicing regions 120. The laser scribe area 120 is an area extending from the edge of the scribe line to the inside by a specific width, which may be determined according to practical situations, for example, the specific width may be about 8.5 μm. The non-laser cutting regions 110 are located between the laser cutting regions 120, that is, the laser cutting regions 120 are located at two sides of the non-laser cutting regions 110. The laser dicing area 120 is adjacent to the die, and thus when the circuit structure in the laser dicing area 120 is diced, the die is easily damaged by the stress generated, so the design of the circuit structure in the laser dicing area 120 is very important.

The wiring structure of the embodiment of the present application includes a top lead layer 210 and a top conductive layer 220, wherein the top lead layer 210 is located on a main portion of the non-laser-cutting area 110 for connecting an internal circuit. The top conductive layer 220 is located in the laser cutting area 120 and the non-laser cutting area 110 on both sides of the top lead layer 110, and is used for conducting internal circuits. The top lead layer 210 and the top conductive layer 220 can be formed in the same process step, so the materials of the top lead layer 210 and the top conductive layer 220 can be the same, for example, the materials of the top lead layer 210 and the top conductive layer 220 are both metal, for example, the materials of the top lead layer 210 and the top conductive layer 220 can include copper, tungsten, etc.

The wiring structure further includes a pad layer 300, and the pad layer 300 is located in the non-laser-scribe region 110 and the laser-scribe region 120 above the top lead layer 210 and the top conductive layer 220. The material of the liner layer 300 may include aluminum. The top lead layer 210 and the pad layer 300 are directly connected, and a first passivation layer 400 is further included between the top conductive layer 220 and the pad layer 300. The first passivation layer 400 is used to isolate the pad layer 330 from the top conductive layer 220, so as to prevent the test result from being inaccurate due to leakage current in WAT. The material of the first passivation layer 400 may include a silicon compound, for example, the material of the first passivation layer 400 includes silicon dioxide. The test probe 500 is brought into contact with the surface of the backing layer 300 during testing.

Since the top lead layer 210 occupies the main portion of the non-laser cutting region 110, that is, the top lead layer 210 has a large area, and the bulk top lead layer 210 is connected to the pad layer 300, the electrical performance during testing can be significantly improved, and the problem of poor testing performance caused by the fact that the pad layer and the top metal layer are connected through a small number of through holes in the past is solved. At the same time, since the bulk top lead layer 210 is only located in the non-laser cutting region 110, the risk of DED is not increased.

The width of the top lead layer 210 in the direction perpendicular to the extending direction of the scribe lines (i.e., in the Y direction) is less than or equal to the width of the non-laser scribe region 110. In some embodiments, the width of the non-laser scribe region 110 is 27 μm, and the width of the top lead layer 210 in the direction perpendicular to the scribe line extending direction is not more than 27 μm, for example, the width of the top lead layer 210 in the direction perpendicular to the scribe line extending direction may be 5 μm, 10 μm, 15 μm, 20 μm, 21 μm, 22 μm, 23 μm, 24 μm, 25 μm, 26 μm, 27 μm, etc. Since the area of the top lead layer 210 affects the electrical performance during testing, the use cost of the material, and the size of the connection structure, the area of the top lead layer 210 is very important, and when the width of the top lead layer 210 perpendicular to the extending direction of the dicing streets is constant, the width of the top lead layer 210 in the extending direction parallel to the dicing streets (i.e. in the X direction) needs to be limited, so that the top lead layer 210 meets the requirements. In the embodiment of the present application, the top lead layer 210 has a width of 50 μm to 100 μm in a direction parallel to the extending direction of the dicing streets.

The contact surface between the top lead layer 210 and the pad layer 300 is circular or polygonal, for example, the cross-sectional shape of the top lead layer 210 may be square, rectangular, diamond, etc.

The top conductive layer 220 is not directly connected to the pad layer 300, so the area of the top conductive layer 220 does not affect the WAT electrical performance, and the top conductive layer 220 can be designed into a mesh structure to reduce the material cost. In the embodiment of the present invention, the top conductive layer 220 includes strip structures 221 extending outward from the edges of the top lead layer 210 and arranged at intervals, and a ring structure 222 connected to the ends of the strip structures 221. The width of the stripe structures 221 and the distance between adjacent stripe structures 221 are determined according to actual conditions.

In some embodiments, the ring structure 222 has a quadrilateral shape, wherein a first side L1 and a second side L1 perpendicular to the extending direction (i.e., X direction) of the dicing streets span the non-laser cutting area 110 and the laser cutting area 120, and a third side L3 and a fourth side L4 parallel to the extending direction (i.e., X direction) of the dicing streets are located in the laser cutting area 120. In some embodiments, the first side L1 and the second side L2 have a length dimension of 27 μm to 44 μm.

In the stripe structure 221, the first edge L1 and the top layer lead layer 210 are connected, the second edge L2 and the stripe structure 221 of the top layer lead layer 210 are located in the non-laser cutting area 110, and the third edge L3 and the top layer lead layer 210, the fourth edge L4 and the stripe structure 221 of the top layer lead layer 210 are connected and located in the laser cutting area 120. Meanwhile, the number of the stripe structures located in the laser cutting region 120 is less than the number of the stripe structures 221 located in the non-laser cutting region 110, that is, most of the stripe structures 221 are located in the non-laser cutting region 110, and only a small part of the stripe structures 221 are located in the laser cutting region 120, so that the occurrence probability and the severity of the DED are not affected.

In an actual wafer scribe line interconnect structure, a dielectric layer (not shown) is further included between adjacent stripe structures 221, which serves as a structural support. The material of the dielectric layer may include silicon oxide.

Referring to fig. 4, in some embodiments, the scribe-lane interconnect structure further includes a second passivation layer 600, and the second passivation layer 600 is located on the surface of the pad layer 300 above the first passivation layer 300. The material of the second passivation layer 600 may include a silicon compound, for example, the material of the second passivation layer 600 includes silicon dioxide. Comparing fig. 2 and fig. 4, the area of the Pad layer 300 covered by the second passivation layer 600 is greatly reduced, so that the area of the Pad Opening of the Pad layer 300 is increased under the condition that the dimension of the Pad layer 300 is kept unchanged, thereby further increasing the working area of the Pad layer 300.

To sum up, the wafer scribe line interconnect structure of the embodiment of the present application is through increasing the area of contact of backing layer and top metal layer to make the top metal layer and the part of backing layer contact, that is, the top lead layer is located the main part in the non-laser cutting area, and then significantly improve the WAT electrical performance, still can not influence the occurrence probability and the severity of DED simultaneously.

After reading this disclosure, those skilled in the art will appreciate that the foregoing disclosure may be presented by way of example only, and may not be limiting. Those skilled in the art will appreciate that the present application is intended to cover various reasonable variations, adaptations, and modifications of the embodiments described herein, although not explicitly described herein. Such alterations, modifications, and variations are intended to be within the spirit and scope of the exemplary embodiments of this application.

It is to be understood that the term "and/or" as used herein in this embodiment includes any and all combinations of one or more of the associated listed items. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present.

Similarly, it will be understood that when an element such as a layer, region or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. In contrast, the term "directly" means that there are no intervening elements. It will be further understood that the terms "comprises," "comprising," "includes" or "including," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It will also be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, a first element in some embodiments may be termed a second element in other embodiments without departing from the teachings of the present application. The same reference numerals or the same reference characters denote the same elements throughout the specification.

Further, the present specification describes example embodiments with reference to idealized example cross-sectional and/or plan and/or perspective views. Thus, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, example embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region shown as a rectangle will typically have rounded or curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the exemplary embodiments.

Claims (14)

1. The utility model provides a wafer dicing street interconnect structure, the wafer dicing street include non-laser cutting district and be located the laser cutting district of non-laser cutting district both sides, its characterized in that, the line structure includes:

a top lead layer located on a body portion of the non-laser-cut region;

the top conducting layer is positioned in the laser cutting area and the non-laser cutting area on two sides of the top lead layer;

the pad layer, be located top layer lead wire layer with non-laser cutting district and laser cutting district above the top layer conducting layer, wherein top layer lead wire layer with the pad layer direct connection, the top layer conducting layer with still include first passivation layer between the pad layer.

2. The wafer scribe line interconnect structure of claim 1, wherein the laser scribe area is an area extending from the edge of the wafer scribe line to an inner portion with a specific width.

3. The scribe line interconnect structure of claim 1, wherein the top lead layer has a width perpendicular to the direction of the scribe line that is less than or equal to the width of the non-laser scribe area.

4. The structure of claim 3, wherein the top lead layer has a width perpendicular to the extending direction of the dicing streets of not more than 27 μm, and the top lead layer has a width parallel to the extending direction of the dicing streets of 50 μm to 100 μm.

5. The wafer level interconnect structure of claim 1, wherein the top lead layer and the pad layer have circular or polygonal contact surfaces.

6. The structure of claim 1, wherein the top conductive layer comprises spaced apart stripe structures extending from edges of the top lead layer and ring structures connecting ends of the stripe structures.

7. The scribe line interconnect structure of claim 6, wherein the ring structure has a quadrilateral cross-section, wherein a first side and a second side perpendicular to the extending direction of the scribe line cross the non-laser scribe region and the laser scribe region, and a third side and a fourth side parallel to the extending direction of the scribe line are located in the laser scribe region.

8. The structure of claim 7, wherein the first side and the second side have a length of 27 μm to 44 μm.

9. The scribe line interconnect structure of claim 7, wherein the stripe structure connecting the first edge and the top lead layer, the second edge and the top lead layer is located in the non-laser scribe region, and the stripe structure connecting the third edge and the top lead layer, the fourth edge and the top lead layer is located in the laser scribe region.

10. The wafer level interconnect structure of claim 9, wherein the number of stripe structures in the laser scribe area is smaller than the number of stripe structures in the non-laser scribe area.

11. The wafer scribe line interconnect structure of claim 6 further comprising a dielectric layer between adjacent stripe structures.

12. The dicing street interconnect structure according to claim 1, further comprising a second passivation layer on a surface of the pad layer above the first passivation layer.

13. The wafer scribe line interconnect structure of claim 12 wherein the material of the first passivation layer and the second passivation layer comprises a silicon compound.

14. The wafer level interconnect structure of claim 1, wherein the material of the liner layer comprises aluminum.

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