CN115410913A - Improved method for etching passivation layer - Google Patents

Improved method for etching passivation layer Download PDF

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CN115410913A
CN115410913A CN202110592270.6A CN202110592270A CN115410913A CN 115410913 A CN115410913 A CN 115410913A CN 202110592270 A CN202110592270 A CN 202110592270A CN 115410913 A CN115410913 A CN 115410913A
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etching
layer
metal structure
passivation layer
radio frequency
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赵伟
任冬华
王长山
郝建英
赵兵
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CSMC Technologies Fab2 Co Ltd
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CSMC Technologies Fab2 Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers

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Abstract

The invention relates to an improved method for etching a passivation layer, which comprises the following steps: step A, obtaining a wafer structure; the wafer structure comprises a substrate, a metal structure on the substrate and a passivation layer covering the metal structure; b, forming an etching window by photoetching; step C, the passivation layer is etched through the etching window in a dry method with first radio frequency power, and the etching is stopped before the metal structure is etched; d, continuously performing dry etching downwards through the etching window by using second radio frequency power until the metal structure is etched; the second radio frequency power is less than the first radio frequency power. According to the invention, before the passivation layer is etched to the metal structure, the radio frequency power of dry etching is reduced, so that the plasma charge density when the plasma of the dry etching starts to contact the metal structure can be reduced, the plasma damage is improved, and abnormal starting voltage of the device caused by the plasma damage is avoided.

Description

Improved method for etching passivation layer
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to an improved method for etching a passivation layer.
Background
The etching of the passivation layer is a dry etching process in the manufacturing process of a semiconductor, a CVD method is used for covering silicon dioxide and silicon nitride media after a top aluminum pattern is formed, then a pattern is formed by using a photoetching technology, and the pattern is transferred onto a wafer by dry etching. The passivation etch may specifically utilize plasma techniques in combination with physical bombardment and chemical reactions to remove certain materials. During mass production, WAT (Wafer Acceptance Test) Vt (turn-on voltage) parameter anomalies occur sporadically, which are manifested as large within-Vt-chip uniformity.
When the WAT Vt parameter is out of specification, the chip can not be used normally, and scrap or yield loss is caused.
Disclosure of Invention
In order to solve the problem of abnormal turn-on voltage of the device, it is necessary to provide an improved method for etching the passivation layer.
An improved method of passivation layer etching, comprising: step A, obtaining a wafer structure; the wafer structure comprises a substrate, a metal structure on the substrate and a passivation layer covering the metal structure; b, forming an etching window by photoetching; step C, the passivation layer is etched through the etching window in a dry method through first radio frequency power, and the etching is stopped before the metal structure is etched; d, continuously performing dry etching downwards through the etching window by using second radio frequency power until the metal structure is etched; the second radio frequency power is less than the first radio frequency power.
According to the method for improving the passivation layer etching, before the passivation layer is etched to the metal structure, the radio frequency power of the dry etching is reduced, so that the plasma charge density when the plasma of the dry etching starts to contact the metal structure can be reduced, the plasma damage is improved, and the abnormal starting voltage of the device caused by the plasma damage is avoided.
In one embodiment, the second rf power is a power at which the plasma generated by the dry etching of step C does not cause plasma damage to the metal structure.
In one embodiment, the second rf power is 400W to 600W.
In one embodiment, the metal structure includes a conductive body and an auxiliary layer on the conductive body, the step D is stopped after etching to the auxiliary layer, and the step D further includes: and E, continuously performing dry etching to the conductive main body downwards through the etching window by using third radio frequency power, wherein the third radio frequency power is greater than the second radio frequency power.
In one embodiment, the first radio frequency power and the third radio frequency power are equal.
In one embodiment, the first rf power and the third rf power are 800W to 1500W.
In one embodiment, the conductive body comprises aluminum copper, and the auxiliary layer comprises a titanium layer and a titanium nitride layer over the titanium layer.
In one embodiment, the step D is stopped after etching to the titanium nitride layer.
In one embodiment, the passivation layer includes a silicon oxide layer and a silicon nitride layer on the silicon oxide layer.
In one embodiment, the silicon oxide layer comprises a silicon dioxide layer and the silicon nitride layer comprises a silicon nitride layer.
In one embodiment, the wafer structure obtained in step a further includes an etching stop layer disposed between the metal structure and the silicon oxide layer, where the etching stop layer is an insulating medium and is made of a material different from that of the silicon oxide layer; and the step C is etching to the etching stop layer.
In one embodiment, the method further comprises the step of detecting the spectral wavelength of the etching products of the step C and the step D; stopping etching when the characteristic spectrum wavelength concentration of the etching product of the etching stop layer is detected to be increased in the step C, and executing a step D; and D, stopping etching when the characteristic spectrum wavelength concentration of the etching product of the etching stop layer is detected to be reduced, and executing the step E.
In one of themIn one embodiment, the etch stop layer comprises silicon nitride; the step C is to detect the spectral wavelength
Figure BDA0003089686450000021
Stopping etching when the concentration of the silicon dioxide increases, and executing the step D; step D is to detect the spectral wavelength
Figure BDA0003089686450000022
Stops etching when the concentration of (c) decreases, and performs step E.
In one embodiment, step C and step D are dry etched in the same apparatus.
In one embodiment, the steps C, D and E are dry etched in the same equipment.
In one embodiment, the etching gas of step C and step D comprises CF 4 、CHF 3 、AR、SF 6 And N 2 。
In one embodiment, step B is to lithographically form an etch window for the contact hole.
In one embodiment, the metal structure is a top metal, and the wafer structure obtained in step a further includes a previous level of the top metal. The present application also provides another improved method of passivation layer etching, comprising: obtaining a wafer structure; the wafer structure comprises a substrate, a metal structure on the substrate and a passivation layer covering the metal structure; photoetching to form an etching window; dry etching the passivation layer through the etch window with a first radio frequency power, stopping before etching to the metal structure; and after the charge density of the plasma is reduced to the extent that the metal structure is not damaged by the plasma, continuing to perform dry etching downwards through the etching window until the metal structure is etched.
In one embodiment, the second rf power is 400W to 600W.
In one embodiment, the metal structure includes a conductive body and an auxiliary layer on the conductive body, the step D is stopped after etching to the auxiliary layer, and the step D further includes: and E, continuously performing dry etching to the conductive main body downwards through the etching window by using third radio frequency power, wherein the third radio frequency power is greater than the second radio frequency power.
In one embodiment, the first radio frequency power and the third radio frequency power are equal.
In one embodiment, the first rf power and the third rf power are 800W to 1500W.
In one embodiment, the conductive body comprises aluminum copper, and the auxiliary layer comprises a titanium layer and a titanium nitride layer over the titanium layer.
In one embodiment, step D is stopped after etching to the titanium nitride layer.
In one embodiment, the passivation layer includes a silicon oxide layer and a silicon nitride layer on the silicon oxide layer.
In one embodiment, the silicon oxide layer comprises a silicon dioxide layer and the silicon nitride layer comprises a silicon nitride layer.
In one embodiment, the wafer structure obtained in step a further includes an etching stop layer disposed between the metal structure and the silicon oxide layer, where the etching stop layer is an insulating medium and is made of a material different from that of the silicon oxide layer; and the step C is etching to the etching stop layer.
In one embodiment, the method further comprises the step of detecting the spectral wavelength of the etching products of the step C and the step D; stopping etching when the characteristic spectrum wavelength concentration of the etching product of the etching stop layer is detected to be increased in the step C, and executing a step D; and D, stopping etching when the characteristic spectrum wavelength concentration of the etching product of the etching stop layer is detected to be reduced, and executing the step E.
In one embodiment, the material of the etching stop layer comprises silicon nitride; the step C is to detect the spectral wavelength
Figure BDA0003089686450000041
Stopping etching when the concentration of the silicon dioxide increases, and executing the step D; step D is to detect the spectral wavelength
Figure BDA0003089686450000042
Stops etching when the concentration of (c) decreases, and performs step E.
In one embodiment, the step C and the step D are dry etched in the same equipment.
In one embodiment, the steps C, D and E are dry etched in the same equipment.
In one embodiment, the etching gas of step C and step D comprises CF 4 、CHF 3 、AR、SF 6 And N 2 。
In one embodiment, step B is to lithographically form an etch window for the contact hole.
In one embodiment, the metal structure is a top metal, and the wafer structure obtained in step a further includes a previous level of the top metal.
Drawings
For a better understanding of the description and/or illustration of embodiments and/or examples of those inventions disclosed herein, reference may be made to one or more of the drawings. The additional details or examples used to describe the figures should not be considered as limiting the scope of any of the disclosed inventions, the presently described embodiments and/or examples, and the presently understood best modes of these inventions.
FIG. 1 is a flow diagram of an improved method of passivation layer etching in one embodiment;
FIGS. 2 a-2 e are schematic cross-sectional views of a device during fabrication thereof using the method of FIG. 1 in one embodiment;
FIGS. 3 a-3 d are schematic cross-sectional views of a device during fabrication thereof using the method of FIG. 4 in one embodiment;
FIG. 4 is a flow chart of an improved method of passivation etch in another embodiment;
FIG. 5 is a graph comparing the turn-on voltage test results for a device made using the improved method of passivation layer etching of one embodiment with the WAT of a comparative example;
fig. 6 is a graph comparing the turn-on voltage test results for another example device made using the modified method of passivation layer etching with the WAT of the comparative example.
Detailed Description
To facilitate an understanding of the invention, the invention will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatially relative terms, such as "under," "below," "beneath," "under," "above," "over," and the like, may be used herein for convenience in describing the relationship of one element or feature to another element or feature illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the invention should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region shown as a rectangle will typically have rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted region. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present invention.
As used herein, the term semiconductor is used in the art to distinguish between P-type and N-type impurities, for example, to distinguish between doping concentrations, P + type represents P-type with heavy doping concentration, P-type represents P-type with medium doping concentration, P-type represents P-type with light doping concentration, N + type represents N-type with heavy doping concentration, N-type represents N-type with medium doping concentration, and N-type represents N-type with light doping concentration.
The inventor analyzes the test result of the large uniformity in the Vt chip, and finds that the abnormity can correspond to the etching cavities of the passivation layer one by one, the physical structure of the device has no obvious difference, and the inventor thinks that the abnormity is electrical abnormity caused by plasma damage.
The key factor of plasma damage is plasma imbalance in a local region, which is always present, and the following approaches are probably considered in the industry for plasma damage:
1. aiming at a product design end: a protection circuit is added into the new product, so that the plasma damage resistance of the chip is enhanced.
2. Aiming at the equipment end: the cavity is optimized, so that the plasma source is more stable and uniform.
3. Aiming at the process end: a gradual change process is introduced in the step of plasma initial generation, so that the plasma is prevented from being unstable and uneven due to sudden change.
The scheme 3 mainly considers the improvement of the instability/non-uniformity possibly generated in the plasma starting process, such as the process of raising the power from 0W to 2000W, and further dividing the process into a plurality of steps of raising the power from 0W to 500w, from 500w to 1000w, and from 1000w to 2000W. Or the pressure stabilization process may be divided into a plurality of step-wise changes. The core idea is to reduce the abrupt factor of the plasma process condition, and further reduce the possibility of plasma instability/non-uniformity.
In an attempt to address the plasma damage problem, the inventors have tried to reduce the abrupt change in plasma process conditions (gradual change in initial steps), but practice has proven ineffective. The reason analyzed is as follows: reducing abrupt changes in plasma process conditions is only applicable to the initial step and processes with large process variations, while the exemplary processes have no change in process conditions throughout the passivation layer etching process, so that plasma stability can only be enhanced by stepwise changes in the initial step, and experiments have found that no matter how the initial step is optimized, the electrical performance of WAT cannot be improved, indicating that plasma damage does not occur in the initial step.
Based on the above phenomenon, the present application considers improving the plasma damage effect of the entire passivation layer etching process in combination with the entire passivation layer etching process.
In order to improve the plasma damage effect of the whole passivation layer etching process, the application must pay attention to key points in the etching process, and the key points are mainly considered from the following aspects:
1. etching process conditions are as follows: exemplary processes are such that the process conditions remain consistent and unchanged from the beginning to the end of the etching process.
2. Corresponding equipment: an exemplary process is one in which the etching apparatus does not have any alarm messages from the beginning to the end of the etching process.
3. The material etched: the largest variation of the exemplary process throughout the etch process was found by analysis to be from insulating materials (silicon nitride and silicon dioxide) to conductive materials (titanium nitride and titanium and aluminum copper).
The process conditions and corresponding equipment are unchanged in the whole etching process, and the only change is that the etched material is changed. The inventor firstly confirms the effect of improving the plasma damage effect in the etching process by optimizing the process conditions, finally determines the process condition with the largest influence on the plasma as power through long-term experiments, and the most critical process point is at the moment of contact between the insulating material and the conductor material. The higher the power at this time, the more severe the plasma damage (the inventors used the strengthened sensitive product for plasma damage verification). The plasma is continuously present in the whole etching process of the passivation layer, and the plasma damage effect can be improved as long as the power is reduced before the metal layer is contacted in the etching process, so that the charge density in the plasma is reduced. The inventor designs a device structure convenient for mass production and fine control based on actual conditions, and a matched method for improving passivation layer etching.
FIG. 1 is a flow diagram of an improved method of passivation etch in one embodiment, including the steps of:
s110, obtaining the wafer structure.
Referring to fig. 2a, the wafer structure includes a substrate 210, a metal structure 220 on the substrate 210, and a passivation layer 230 covering the metal structure 220. Various device structures, such as active regions, well regions, contact regions, etc., may be formed in the substrate 210 as is known in the art. Other device structures, such as gates, dielectric layers, etc., may also be formed on substrate 210 as is known in the art. Metal structure 220 may be a top metal, such as a metal interconnect line; the substrate 210 and the substrate are formed with a layer before the top metal, i.e., a structure formed by a plurality of previous processes before the top metal. The substrate 210 may be at least one of the following materials: the semiconductor may be a multilayer structure of these semiconductors, or may be silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), or germanium-on-insulator (GeOI).
In the embodiment shown in fig. 2a, the passivation layer 230 includes a silicon oxide layer 232 and a silicon nitride layer 234 on the silicon oxide layer. Further, the silicon oxide layer 232 may be a silicon oxide layer, and the silicon nitride layer 234 may be a silicon nitride layer.
In one embodiment of the present application, the metal structure 220 includes a conductive body and an auxiliary layer on the conductive body. Further, the conductive body comprises aluminum copper, and the auxiliary layer comprises a titanium layer and a titanium nitride layer on the titanium layer.
And S120, forming an etching window by photoetching.
Referring to fig. 2b, a patterned photoresist layer 240 is lithographically formed on the passivation layer 230 to expose an etch window 241 of the passivation layer etch.
The photoresist layer 240 may be made of a common positive or negative resist material, and is patterned by exposure, development, etc. to expose the etching window 241.
In one embodiment of the present application, the etch window 241 is an etch window of a contact hole.
And S130, dry etching the passivation layer through the etching window by using first radio frequency power, and stopping before etching to the metal structure.
Referring to fig. 2c, the entire silicon nitride layer 234 and most of the silicon oxide layer 232 are etched away. In one embodiment of the present application, the etching of step S130 is performed using a time pattern (i.e., etching for a preset time period).
And S140, continuously performing dry etching downwards through the etching window by using second radio frequency power until the metal structure is etched.
In an embodiment of the present application, after the rf power of the dry etching apparatus used in step S130 is reduced, the product is continuously etched. Specifically, it is desirable that the second rf power is a power at which the plasma generated by the dry etching does not cause plasma damage to the metal structure 220. The inventors have experimentally confirmed that the probability of plasma damage is significantly changed when the power is between 800W and 1000W, and thus the rf power of the etcher cannot be too high when the metal structure 220 is exposed during the etching process. In one embodiment of the present application, the second rf power is 400W to 600W, and the first rf power is 800W to 1500W.
According to the method for improving the passivation layer etching, before the passivation layer is etched to the metal structure 220, the radio frequency power of the dry etching is reduced, so that the plasma charge density when the plasma of the dry etching starts to contact the metal structure can be reduced, the plasma damage is improved, and the abnormal starting voltage of the device caused by the plasma damage is avoided.
In one embodiment of the present application, step S140 is stopped after etching to the titanium nitride layer in the metal structure 220, see fig. 2d. Step S140 is followed by step S150: dry etching continues down through the etch window 241 at a third rf power to the aluminum-copper in the metal structure 220, see fig. 2e. The third radio frequency power is greater than the second radio frequency power. After step S140 is completed, etching is performed again with high power, which is beneficial to improving the selection ratio of the titanium nitride/titanium material and the barrier layer photoresist material in the etching process, and thus, the situation that the protected material below the photoresist is removed/damaged during etching due to excessive photoresist loss is avoided.
In one embodiment of the present application, the third rf power is 800W to 1500W. In one embodiment of the present application, the first radio frequency power and the third radio frequency power are equal. It is understood that step S150 and steps S130 and S140 are performed by using the same etching machine. In one embodiment of the present application, the passivation layer etching is performed using eMax equipment from AMAT corporation.
In one embodiment of the present application, the etching of step S140 uses an endpoint mode. In one embodiment of the present application, the etching of step S150 employs a time mode.
In one embodiment of the present application, the etching gases used in steps S130, S140 and S150 collectively include CF 4 、CHF 3 、AR、SF 6 And N 2 。
In one embodiment of the present application, the process conditions of steps S130, S140 and S150 are the same except for the RF power.
Using the optimized passivation layer etching process, the product slicing verification shows that when the old process generates plasma damage to affect the WAT Vt of the product, the new process conditions can effectively improve the phenomenon, as shown in fig. 5 and 6. This demonstrates that the above-described improved method of passivation layer etching can effectively improve the plasma damage effect of passivation layer etching. Based on this, it has been demonstrated that direct contact of the high power plasma to the metal structure 220 is the main factor causing plasma damage, and the conversion to low power before etching to the metal structure 220 is an effective method.
Fig. 4 is a flow chart of an improved method of passivation layer etching in another embodiment. In the embodiment, the etching stop layer is additionally arranged on the metal structure, so that the RF power of the dry etching can be more accurately controlled from a high time point to a low time point. The method of the embodiment shown in fig. 4 comprises the following steps:
s410, obtaining the wafer structure.
Referring to fig. 3a, the wafer structure includes a substrate 310, a metal structure 320 on the substrate 310, an etch stop layer 324 covering the metal structure 320, and a passivation layer 330 on the etch stop layer 324.
Various device structures known in the art, such as active regions, well regions, contact regions, etc., may be formed in the substrate 310, and other device structures known in the art, such as gates, dielectric layers, etc., may also be formed on the substrate 310. The substrate 310 may be at least one of the following materials: the semiconductor may be a multilayer structure of these semiconductors, or may be silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), or germanium-on-insulator (GeOI). The metal structure 320 may be a top metal, such as a metal interconnect line, etc.
In the embodiment shown in fig. 3a, the passivation layer 330 includes a silicon oxide layer 332 and a silicon nitride layer 334 on the silicon oxide layer. Further, the silicon oxide layer 332 may be a silicon oxide layer, and the silicon nitride layer 334 may be a silicon nitride layer.
The etch stop layer 324 is an insulating dielectric and needs to have a high etch selectivity with respect to the silicon oxide layer 332, and thus a material that can have a high etch selectivity with respect to the silicon oxide layer 332 is selected as the etch stop layer 324. In one embodiment of the present application, the etch stop layer 324 is a silicon nitride layer.
In one embodiment of the present application, the metal structure 320 includes a conductive body and an auxiliary layer on the conductive body. Further, the conductive body comprises aluminum copper, and the auxiliary layer comprises a titanium layer and a titanium nitride layer on the titanium layer.
And S420, forming an etching window by photoetching.
In one embodiment of the present application, etch window 341 is an etch window of a contact hole.
And S430, dry-etching the passivation layer through the etching window by using first radio frequency power, and stopping when the etching reaches the etching stop layer.
The high power etch is used to etch away the silicon oxide layer 332 and the silicon nitride layer 334 at the location of the etch window 341, stopping on the etch stop layer 324. Specifically, the spectral wavelength of the etching product is detected during the etching process, and the etching is stopped when the concentration of the characteristic spectral wavelength of the etching product of the etching stop layer 324 is detected to increase.
In one embodiment of the present application, the spectral signal of the silicon nitride layer 334 is filtered out during the etching process based on the actual etching process, and the detected spectral wavelength
Figure BDA0003089686450000111
Stopping the etching in step S430 when the concentration of (C) increases: (
Figure BDA0003089686450000112
Is a characteristic spectrum of the etching product CN when the etching stopper 324 is a silicon nitride layer).
S440, etching the etching stop layer through the etching window with a second radio frequency power until the metal structure is etched.
A transition is made to a low power etch, etching the etch stop layer 324. The etching is stopped when a decrease in the concentration of the characteristic spectral wavelength of the etching product of the etching stop layer 324 is detected. In one embodiment of the present application, the spectral wavelength is detected
Figure BDA0003089686450000113
Stops the etching in step S440 when the concentration of (a) decreases.
In another embodiment of the present application, the etching of step S440 is in a time mode. For a part of semiconductor products, it may occur that a characteristic spectrum signal is weak due to a product design problem, and etching may be performed at a fixed time.
In one embodiment of the present application, the second rf power is 400W to 600W, and the first rf power is 800W to 1500W.
In the method for improving the passivation layer etching, a thin etching stop layer 324 is additionally arranged, so that the etching rate is remarkably reduced when the etching stop layer 324 is etched by a dry method, the low RF power can be ensured to be switched before the etching is carried out on the metal structure 320, and the stable process control is realized.
In one embodiment of the present application, step S440 is stopped after etching to the titanium nitride layer in the metal structure 320, see fig. 3c. Step S450 is further included after step S440: dry etching continues down through the etch window 341 at a third rf power to the aluminum copper. Referring to fig. 3d, the corresponding over-etching amount is set based on actual product requirements, and the titanium and titanium nitride on the aluminum copper of the metal structure 320 are etched. The third radio frequency power is greater than the second radio frequency power. In one embodiment of the present application, the third rf power is 800W to 1500W. In one embodiment of the present application, the first radio frequency power and the third radio frequency power are equal. It is understood that step S450 and steps S430 and S440 are performed by using the same etching machine.
It should be understood that, although the steps in the flowcharts of the present application are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least a part of the steps in the flowchart of the present application may include a plurality of steps or a plurality of stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of performing the steps or the stages is not necessarily sequential, but may be performed alternately or alternately with other steps or at least a part of the steps or the stages in other steps.
In the description herein, references to the description of "some embodiments," "other embodiments," "desired embodiments," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, schematic depictions of the above terms do not necessarily refer to the same embodiment or example.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is specific and detailed, but not to be understood as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims (12)

1. An improved method of passivation layer etching, comprising:
step A, obtaining a wafer structure; the wafer structure comprises a substrate, a metal structure on the substrate and a passivation layer covering the metal structure;
b, forming an etching window by photoetching;
step C, the passivation layer is etched through the etching window in a dry method with first radio frequency power, and the etching is stopped before the metal structure is etched;
d, continuously performing dry etching downwards through the etching window by using second radio frequency power until the metal structure is etched; the second radio frequency power is less than the first radio frequency power.
2. The improved method for etching passivation layer as claimed in claim 1, wherein said second RF power is a power that does not cause plasma damage to said metal structure by the plasma generated by said dry etching of step C.
3. The improved method of passivation etching of claim 2 wherein said second rf power is 400W to 600W.
4. The improved method of passivation layer etching as claimed in claim 1, wherein said metal structure includes a conductive body and an auxiliary layer on the conductive body, said step D is stopped after etching to said auxiliary layer, said step D further comprising:
and E, continuously performing dry etching to the conductive main body downwards through the etching window by using third radio frequency power, wherein the third radio frequency power is greater than the second radio frequency power.
5. The improved method of passivation etching of claim 4, wherein said conductive body comprises aluminum copper, said auxiliary layer comprises a titanium layer and a titanium nitride layer over said titanium layer.
6. The improved method of etching a passivation layer of claim 4 or 5, wherein the passivation layer comprises a silicon oxide layer and a silicon nitride layer on the silicon oxide layer.
7. The improved method of etching a passivation layer of claim 6, wherein said silicon oxide layer comprises a silicon dioxide layer and said silicon nitride layer comprises a silicon nitride layer.
8. The improved method for etching the passivation layer according to claim 6, wherein the wafer structure obtained in step A further comprises an etching stop layer disposed between the metal structure and the silicon oxide layer, the etching stop layer being an insulating medium and being different from the silicon oxide layer in material;
and the step C is etching to the etching stop layer.
9. The improved method of passivation etching as claimed in claim 8, further comprising the step of detecting the spectral wavelength of the etching products of said steps C and D; stopping etching when the characteristic spectrum wavelength concentration of the etching product of the etching stop layer is detected to be increased in the step C, and executing a step D; and D, stopping etching when the characteristic spectrum wavelength concentration of the etching product of the etching stop layer is detected to be reduced, and executing the step E.
10. The improved method of passivation etching as claimed in claim 9, wherein said etch stop layer comprises silicon nitride; the step C is to detect the spectral wavelength
Figure FDA0003089686440000021
Stopping etching when the concentration of the silicon dioxide increases, and executing the step D; said step D is detecting the spectral wavelength
Figure FDA0003089686440000022
Stops etching when the concentration of (c) decreases, and performs step E.
11. The improved method for etching passivation layer as claimed in claim 1, wherein said metal structure is top metal, and said wafer structure obtained in step a further comprises a previous level of top metal.
12. An improved method of passivation layer etching, comprising:
obtaining a wafer structure; the wafer structure comprises a substrate, a metal structure on the substrate and a passivation layer covering the metal structure;
photoetching to form an etching window;
dry etching the passivation layer through the etch window with a first radio frequency power, stopping before etching to the metal structure;
and after the charge density of the plasma is reduced to the extent that the metal structure is not damaged by the plasma, continuing to perform dry etching downwards through the etching window until the metal structure is etched.
CN202110592270.6A 2021-05-28 2021-05-28 Improved method for etching passivation layer Pending CN115410913A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116047859A (en) * 2023-03-02 2023-05-02 广州新锐光掩模科技有限公司 Method for manufacturing photomask passivation layer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116047859A (en) * 2023-03-02 2023-05-02 广州新锐光掩模科技有限公司 Method for manufacturing photomask passivation layer

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