CN115408278A - Firmware loading abnormity detection method, device, equipment and storage medium - Google Patents
Firmware loading abnormity detection method, device, equipment and storage medium Download PDFInfo
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Abstract
The application discloses a firmware loading abnormity detection method, a firmware loading abnormity detection device, equipment and a storage medium, and relates to the technical field of firmware loading. The method is applied to a logic device which is respectively connected with a main chip and a firmware carrier, and comprises the following steps: monitoring a transmission signal of a loading link between the firmware carrier and the main chip; timing by utilizing an internal timer; the timer is used for timing the transmission time of the transmission signal and starting timing after the logic device is electrified; and judging whether the firmware loading of the main chip is abnormal or not according to the signal monitoring result, the timing result and a preset judgment rule. Therefore, a logic device is added between a firmware carrier for storing firmware and a main chip, and the transmission of a signal link is detected through the functions of signal detection, timing and the like of the logic device, so that whether the firmware is normal in the reading process is judged, and whether the firmware loading is abnormal is confirmed.
Description
Technical Field
The present invention relates to the field of firmware loading technologies, and in particular, to a method, an apparatus, a device, and a storage medium for detecting firmware loading anomalies.
Background
In a server type product, there are multiple IC chips (Integrated Circuit chips) that require specific firmware to be loaded for normal operation. In general, an EEPROM (Electrically Erasable Programmable read only memory) or a nor flash (non-volatile flash memory) is externally mounted on a chip as a storage medium of firmware. Whether the firmware can be loaded normally determines whether the corresponding chip and the whole server product can work normally. In the production and processing, firmware loading faults caused by firmware burning abnormity, material abnormity or hardware link abnormity occasionally occur, but the fault reason cannot be intuitively positioned by production line detection, so that the time cost of positioning and processing is increased.
The existing firmware detection scheme basically aims at the integrity verification of a firmware file, and checks whether the file is correct and completely usable or not by comparing specific fields in the firmware file and the like, so that abnormal scenes such as carrier chip abnormity of a storage medium of firmware on a board card and the like, firmware burning abnormity during processing, loading mode configuration error and the like cannot be covered, and the fault reason cannot be rapidly positioned when the chip cannot normally work due to the fact that the firmware file has no problem but the loading abnormity occurs.
Disclosure of Invention
In view of the above, an object of the present invention is to provide a method, an apparatus, a device and a medium for detecting a firmware loading exception, which can improve the capability of detecting a firmware loading exception. The specific scheme is as follows:
in a first aspect, the present application discloses a method for detecting a firmware loading exception, which is applied to a logic device connected to a main chip and a firmware carrier, and includes:
monitoring a transmission signal of a loading link between the firmware carrier and the main chip;
timing by utilizing an internal timer; the timer is used for timing the transmission time of the transmission signal and starting timing after the logic device is electrified;
and judging whether the firmware loading of the main chip is abnormal or not according to the signal monitoring result, the timing result and a preset judgment rule.
Optionally, the determining whether the firmware loading of the main chip is abnormal according to the signal monitoring result, the timing result and the preset determination rule includes:
if the transmission signal is not monitored and the transmission signal is not monitored in the first preset time after the logic device is powered on, judging that the firmware loading of the main chip is abnormal.
Optionally, the determining whether the firmware loading of the main chip is abnormal according to the signal monitoring result, the timing result and the preset determination rule includes:
if the transmission signal is monitored, determining a transmission time length obtained by timing the transmission time of the transmission signal;
and judging whether the difference value between the transmission time length and the preset firmware loading time length is within a preset time length range, and judging whether the firmware loading of the main chip is abnormal according to a judgment result.
Optionally, the determining whether the firmware loading of the main chip is abnormal according to the determination result includes:
if the difference value between the transmission time length and the preset firmware loading time length is out of the preset time length range, judging that the firmware loading of the main chip is abnormal;
and if the difference value between the transmission time length and the preset firmware loading time length is within the preset time length range, judging that the firmware loading of the main chip is not abnormal.
Optionally, the logic device is connected to any one or more of the indicator light, the buzzer and the substrate management controller, and after determining whether the firmware loading of the main chip is abnormal according to the signal monitoring result, the timing result and the preset determination rule, the method further includes:
if the judgment result shows that the firmware loading of the main chip is abnormal, sending a signal to any one or more of the indicator light, the buzzer and the substrate management controller; and the substrate management controller is used for displaying alarm information on the user interface after receiving the signal.
Optionally, the determining whether the firmware loading of the main chip is abnormal according to the signal monitoring result, the timing result and a preset determination rule includes:
judging whether each loading link between the firmware carrier and the main chip is abnormal or not according to a signal monitoring result, a timing result and a preset judgment rule;
and if any one of the loading links is abnormal, judging that the firmware loading of the main chip is abnormal.
In a second aspect, the present application discloses a firmware loading exception detection apparatus, including:
the monitoring module is used for monitoring a transmission signal of a loading link between the firmware carrier and the main chip;
the timing module is used for timing by utilizing an internal timer; the timer is used for timing the transmission time of the transmission signal and starting timing after the logic device is electrified;
and the abnormity judgment module is used for judging whether the firmware loading of the main chip is abnormal or not according to the signal monitoring result, the timing result and a preset judgment rule.
In a third aspect, the present application discloses an electronic device, comprising:
a memory for storing a computer program;
and the processor is used for executing the computer program to realize the firmware loading abnormity detection method.
In a fourth aspect, the present application discloses a computer readable storage medium for storing a computer program; wherein the computer program when executed by the processor implements the firmware load exception detection method described above.
In the present application, a transmission signal of a load link between the firmware carrier and the main chip is monitored; timing by utilizing an internal timer; the timer is used for timing the transmission time of the transmission signal and starting timing after the logic device is electrified; and judging whether the firmware loading of the main chip is abnormal or not according to the signal monitoring result, the timing result and a preset judgment rule. Therefore, a logic device is added between a firmware carrier for storing the firmware and a main chip, the transmission of a signal link is detected through the functions of signal detection, timing and the like of the logic device, and whether the firmware is normal in the reading process is judged, so that whether the firmware loading is abnormal is confirmed, and the firmware loading abnormity detection capability is improved. The problem that the chip cannot work normally due to the fact that the firmware is not loaded normally because of abnormal scenes such as abnormal chip of carriers such as firmware carriers, abnormal firmware burning during processing, wrong loading mode configuration and the like can be solved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a flowchart of a firmware loading exception detection method provided in the present application;
FIG. 2 is a block diagram of a specific firmware loading exception detection system according to the present application;
fig. 3 is a flowchart of a specific firmware loading exception detection method provided in the present application;
fig. 4 is a schematic structural diagram of a firmware loading exception detection apparatus according to the present application;
fig. 5 is a structural diagram of a firmware loading exception detection system according to the present application;
fig. 6 is a block diagram of an electronic device provided in the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all the embodiments. All other embodiments, which can be obtained by a person skilled in the art without making any creative effort based on the embodiments in the present invention, belong to the protection scope of the present invention.
In the prior art, basically aiming at the integrity verification of a firmware file, whether the file is correct and completely usable is checked by methods such as comparison of specific fields in the firmware file, abnormal scenes such as carrier chip abnormity of a storage medium of firmware on a board card and the like, firmware burning abnormity during processing, loading mode configuration error and the like cannot be covered, and therefore when the firmware file has no problem and the chip cannot normally work due to loading abnormity, the fault reason cannot be quickly located. In order to overcome the technical problems, the application provides a firmware loading abnormity detection method which can improve the firmware loading abnormity detection capability and solve the problem that the chip cannot work normally due to the fact that the firmware is not loaded normally due to abnormal scenes such as abnormal chip loading of carriers such as firmware carriers, abnormal firmware burning during processing, loading mode configuration errors and the like.
The embodiment of the application discloses a firmware loading exception detection method, which is applied to a logic device respectively connected with a main chip and a firmware carrier, and as shown in fig. 1, the method can comprise the following steps:
step S11: monitoring a transmission signal of a load link between the firmware carrier and the main chip.
In this embodiment, a transmission signal of a load link between the firmware carrier and the main chip is monitored by a logic device located between the main chip and the firmware carrier. The firmware carrier is a carrier for storing firmware, and may be an EEPROM or a norflash. The Logic Device may be a CPLD (Complex Programmable Logic Device), or other devices with the same function, such as a Micro Controller Unit (MCU). That is, the topology is realized by hardware, and on the signal transmission link between the Host (Host) chip and the firmware carrier chip, a CPLD or other similar logic device is responsible for signal transmission and detection, so as to realize the transmission and detection of the firmware loading link signal.
Step S12: timing by utilizing an internal timer; the timer is used for timing the transmission time of the transmission signal and starting timing after the logic device is powered on.
In this embodiment, an internal timer of the logic device is used for timing, where the timer may be used for timing the transmission time of the transmission signal, that is, starting timing after the transmission signal is detected until the transmission signal disappears, that is, recording the duration of continuous existence of the transmission signal. The timer can also be used for starting timing after the logic device is electrified, namely the timer starts timing after the logic device is electrified, and can also meet other requirements for timing and simultaneously execute a plurality of timing tasks.
Step S13: and judging whether the firmware loading of the main chip is abnormal or not according to the signal monitoring result, the timing result and a preset judgment rule.
In this embodiment, it is finally determined whether the firmware loading of the main chip is abnormal according to the signal monitoring result, the timing result, and the preset determination rule. The preset judgment rule is determined according to a firmware loading rule, that is, whether the firmware loading of the main chip is abnormal is judged according to a signal monitoring result, a timing result and a common firmware loading rule.
Therefore, the firmware loading abnormity detection method applied to the server fills the blank that the existing firmware detection scheme is only basically directed at the firmware file, but can not detect abnormal states such as a hardware link state, whether the firmware storage chip is reversed, whether the firmware is burned or not and the like, detects the firmware loading abnormity in time, is convenient for developers to quickly position whether the firmware loading abnormity exists or not when the main chip works abnormally, and also position whether the burning abnormity exists or not when the board card is processed, the chip is reversed or not and the like, improves the problem positioning efficiency and the production reliability, and saves the labor and the time cost.
In this embodiment, the determining whether the firmware loading of the main chip is abnormal according to the signal monitoring result, the timing result, and the preset determination rule may include: judging whether each loading link between the firmware carrier and the main chip is abnormal or not according to a signal monitoring result, a timing result and a preset judgment rule; and if any one of the loading links is abnormal, judging that the firmware loading of the main chip is abnormal. It can be understood that a loading link between the main chip and the firmware carrier may be an SPI (Serial Peripheral Interface), and thus there may be two types of links, namely a one-line link or a four-line link.
In this embodiment, the logic device is connected to any one or more of the indicator light, the buzzer and the substrate management controller, and after determining whether the firmware loading of the main chip is abnormal according to the signal monitoring result, the timing result and the preset determination rule, the method may further include: if the judgment result is that the firmware loading of the main chip is abnormal, sending a signal to any one or more of the indicator light, the buzzer and the substrate management controller; and the substrate management controller is used for displaying alarm information on the user interface after receiving the signal. In the embodiment, when the loading is abnormal, an alarm is given to inform an operator or a user to detect and repair the fault in time, so that when the user or a development tester finds that the chip is abnormal in function, whether the chip is abnormal in firmware loading can be quickly positioned. The specific alarm modes can comprise a warning light, a warning sound, a user interface display and the like.
For example, as shown in fig. 2, a specific structure diagram of a firmware loading exception detection system is disclosed, in the aspect of hardware connection, a logic device is arranged between a firmware carrier and a main chip, and the logic device detects an external power access (AC ON) and a power button (Powerbutton), and connects an indicator Light (LED), a Buzzer (Buzzer), and a Baseboard Management Controller (BMC). The main chips are some chips on the board card, and the loading condition of the chips is mainly monitored in the implementation; the firmware carrier is a chip for storing firmware, and the main chip loads the required firmware from the chip; a logic device: the intermediate link between the main chip and the firmware carrier chip is responsible for transmitting and detecting firmware loading signals, judging whether loading is normal or not, and giving an alarm according to a judgment result; after judging that the firmware is loaded abnormally, the logic device controls an alarm indicator lamp to light up and a buzzer to sound; the logic device may also notify the BMC after determining that the firmware is abnormally loaded, and the BMC may display corresponding warning information in a UI (user interface).
For chips needing to load firmware, a main chip is generally connected with carrier chips such as an EEPROM/Flash and the like through buses such as an SPI. In the embodiment, a CPLD or a similar logic device is added between the Host chip and the EEPROM/Flash, so that signal transmission firstly passes through the CPLD and then is transmitted to the Host chip; the CPLD can judge whether a signal is transmitted on a transmission link or not, and starts to monitor signal transmission on the link by taking a power-on or power-on signal as a starting point; after the CPLD judges that the loading fails, the CPLD can inform the BMC, and the BMC displays corresponding warning information on the webpage UI, such as prompting a user that a certain chip fails to load firmware.
As can be seen from the above, in this embodiment, a transmission signal of a loading link between the firmware carrier and the main chip is monitored; timing by utilizing an internal timer; the timer is used for timing the transmission time of the transmission signal and starting timing after the logic device is electrified; and judging whether the firmware loading of the main chip is abnormal or not according to the signal monitoring result, the timing result and a preset judgment rule. Therefore, a logic device is added between a firmware carrier for storing the firmware and a main chip, the transmission of a signal link is detected through the functions of signal detection, timing and the like of the logic device, whether the firmware is normal in the reading process is judged, and whether the firmware loading is abnormal is confirmed. The problem that chips cannot work normally due to the fact that the firmware is not loaded normally due to abnormal scenes such as abnormal chip carriers of firmware carriers and the like, abnormal firmware burning during processing, wrong loading mode configuration and the like can be solved.
The embodiment of the application discloses a specific firmware loading exception detection method, which is applied to a logic device respectively connected with a main chip and a firmware carrier, and as shown in fig. 3, the method may include the following steps:
step S21: monitoring a transmission signal of a load link between the firmware carrier and the main chip.
Step S22: timing by utilizing an internal timer; the timer is used for timing the transmission time of the transmission signal and starting timing after the logic device is powered on.
Step S23: if the transmission signal is not monitored and the transmission signal is not monitored in a first preset time after the logic device is electrified, judging that the firmware loading of the main chip is abnormal.
In this embodiment, if the logic device does not monitor the transmission signal between the firmware carrier and the main chip within the first preset time after being powered on, it is determined that the firmware loading of the main chip is abnormal. It can be understood that the firmware content is stored in the firmware carrier, and the firmware loading is usually performed on the main chip when the firmware carrier is used, so that after the firmware carrier is powered on and used, if the transmission signal is not monitored in a preset time period, it can be considered that the firmware loading may be abnormal.
Step S24: and if the transmission signal is monitored, determining a transmission time length obtained by timing the transmission time of the transmission signal.
In this embodiment, if the logic device monitors a transmission signal between the firmware carrier and the main chip after being powered on, the transmission duration of the transmission signal, that is, the duration from the appearance to the disappearance of the signal, is determined according to the timing of the timer on the existence duration of the transmission signal.
Step S25: and judging whether the difference value between the transmission time length and the preset firmware loading time length is within a preset time length range, and judging whether the firmware loading of the main chip is abnormal according to a judgment result.
In this embodiment, after the transmission duration is determined, whether a difference between the transmission duration and the preset firmware loading duration is within a preset duration range is determined, and whether the firmware loading of the main chip is abnormal is determined according to a determination result. It can be understood that the firmware loading duration is usually within a certain range, so the preset firmware loading duration is configured in advance, and if a transmission signal is detected, the start of firmware loading is represented; the preset time length range is a preset error range, so that whether the firmware loading is abnormal or not can be judged by comparing whether the difference value between the transmission time length and the preset firmware loading time length is within the preset error range or not.
In this embodiment, the determining whether the firmware loading of the main chip is abnormal according to the determination result may include: if the difference value between the transmission time length and the preset firmware loading time length is out of the preset time length range, judging that the firmware loading of the main chip is abnormal; and if the difference value between the transmission time length and the preset firmware loading time length is within the preset time length range, judging that the firmware loading of the main chip is not abnormal. Namely, if the difference between the transmission time length and the preset firmware loading time length is within the preset error range, it is determined that the firmware loading of the main chip is abnormal, and if the difference between the transmission time length and the preset firmware loading time length is outside the preset error range, it is determined that the firmware loading of the main chip is abnormal. Therefore, the condition that the firmware loading caused by the fault is finished in advance and the complete firmware loading is not completed can be screened out, and the condition that the firmware loading caused by the fault is blocked and the firmware loading can not be completed completely.
That is to say, in the embodiment, the preset firmware loading time length is configured to be tA by utilizing the characteristic that the chip loading firmware generally has a specific time length. The logic device uses an internal Timer (Timer) to calculate whether a signal is transmitted on a link after power-on/power-on and the time length of the signal transmission. Then, according to the result, the firmware loading is roughly divided into the following scenes:
and if no signal transmission exists and no signal transmission is detected after a certain time after power-on/power-on, the load is determined to be overtime and the link is abnormal. In the scene, the logic device controls the alarm indicator light to be lightened, the buzzer rings, and a user is informed to check whether the hardware link, the firmware carrier placement or the firmware burning is abnormal or not;
if signal transmission exists and the signal transmission duration is basically consistent with tA, the link is judged to be normal, the alarm indicator lamp is not on, and the buzzer does not sound;
if signal transmission exists, but after the time length of tA, the signal transmission is still detected after a certain time, the loading is judged to be overtime, and the link is abnormal. Under the scene, the logic device controls the alarm indicator lamp to light up, the buzzer rings, and the user is informed to check whether the hardware link, the firmware carrier placement or the firmware burning is abnormal or not.
In addition, in this embodiment, the method for detecting a firmware loading exception further includes: acquiring firmware information corresponding to the firmware in the firmware carrier, judging whether the firmware information is consistent with information in a preset firmware information base, and judging whether the firmware loading of the main chip is abnormal according to a judgment result. That is, in addition to the detection logic of timeout determination, other determination logic may be used as appropriate, for example, when the firmware information is less, the determination may be made by determining whether the firmware code pattern is consistent with the normal firmware code pattern in the preset firmware information base.
For the specific processes of step S21 and step S22, reference may be made to corresponding contents disclosed in the foregoing embodiments, and details are not repeated herein.
As can be seen, the internal timer is used for timing in the embodiment; the timer is used for timing the transmission time of the transmission signal and starting timing after the logic device is powered on. If the transmission signal is not monitored and the transmission signal is not monitored in a first preset time after the logic device is electrified, judging that the firmware loading of the main chip is abnormal. And if the transmission signal is monitored, determining the transmission time length obtained by timing the transmission time of the transmission signal. And judging whether the difference value between the transmission time length and the preset firmware loading time length is within a preset time length range or not, and judging whether the firmware loading of the main chip is abnormal or not according to a judgment result.
Therefore, by utilizing the rule that the firmware is loaded in the duration, the firmware content is stored in the firmware carrier, and the firmware loading is usually performed on the main chip when the firmware carrier is used, so that after the firmware carrier is electrified and used, if the transmission signal is not monitored in the preset time period, the firmware loading can be considered to be abnormal. If the logic device monitors a transmission signal between the firmware carrier and the main chip after being electrified, determining the transmission time length of the transmission signal according to the timing of the timer on the existence time length of the transmission signal, namely the time length from the appearance of the signal to the disappearance of the signal, wherein the preset firmware loading time length is configured in advance because the firmware loading time length is usually within a certain range, and if the transmission signal is detected, the representation starts to load the firmware; the preset time range is a preset error range, so that whether the firmware loading is abnormal can be judged by comparing whether the difference value between the transmission time and the preset firmware loading time is within the preset error range.
Correspondingly, an embodiment of the present application further discloses a firmware loading exception detection apparatus, as shown in fig. 4, the apparatus includes:
a monitoring module 11, configured to monitor a transmission signal of a loading link between the firmware carrier and the main chip;
a timing module 12 for timing with an internal timer; the timer is used for timing the transmission time of the transmission signal and starting timing after the logic device is electrified;
and the abnormity judgment module 13 is used for judging whether the firmware loading of the main chip is abnormal according to the signal monitoring result, the timing result and a preset judgment rule.
In this embodiment, a transmission signal of a load link between the firmware carrier and the main chip is monitored; timing by utilizing an internal timer; the timer is used for timing the transmission time of the transmission signal and starting timing after the logic device is electrified; and judging whether the firmware loading of the main chip is abnormal or not according to the signal monitoring result, the timing result and a preset judgment rule. Therefore, a logic device is added between a firmware carrier for storing the firmware and a main chip, the transmission of a signal link is detected through the functions of signal detection, timing and the like of the logic device, whether the firmware is normal in the reading process is judged, and whether the firmware loading is abnormal is confirmed. The problem that the chip cannot work normally due to the fact that the firmware is not loaded normally because of abnormal scenes such as abnormal chip of carriers such as firmware carriers, abnormal firmware burning during processing, wrong loading mode configuration and the like can be solved.
In some specific embodiments, the abnormality determining module 13 may specifically include:
and the abnormality determination unit is used for determining that the firmware loading of the main chip is abnormal if the transmission signal is not monitored and the transmission signal is not monitored in a first preset time after the logic device is powered on.
In some specific embodiments, the abnormality determining module 13 may specifically include:
a transmission duration determining unit, configured to determine, if the transmission signal is monitored, a transmission duration obtained by timing a transmission time of the transmission signal;
and the abnormity judgment unit is used for judging whether the difference value between the transmission time length and the preset firmware loading time length is within a preset time length range or not and judging whether the firmware loading of the main chip is abnormal or not according to a judgment result.
In some specific embodiments, the abnormality determining unit may specifically include:
the first judging unit is used for judging that the firmware loading of the main chip is abnormal if the difference value between the transmission time length and the preset firmware loading time length is out of the preset time length range;
and the second judging unit is used for judging that the firmware loading of the main chip is not abnormal if the difference value between the transmission time length and the preset firmware loading time length is within the preset time length range.
In some embodiments, the rule that the firmware is loaded in the duration is used, the firmware content is stored in the firmware carrier, and the firmware loading is usually performed on the main chip when the firmware carrier is used, so that when the transmission signal is not monitored in the preset time period after the firmware carrier is powered on and used, it can be considered that the firmware loading may be abnormal. If the logic device monitors a transmission signal between the firmware carrier and the main chip after being electrified, determining the transmission time length of the transmission signal according to the timing of the timer on the existence time length of the transmission signal, namely the time length from the appearance of the signal to the disappearance of the signal, wherein the preset firmware loading time length is configured in advance because the firmware loading time length is usually within a certain range, and if the transmission signal is detected, the representation starts to load the firmware; the preset time length range is a preset error range, so that whether the firmware loading is abnormal or not can be judged by comparing whether the difference value between the transmission time length and the preset firmware loading time length is within the preset error range or not.
In some specific embodiments, the logic device is connected to any one or more of an indicator light, a buzzer and a baseboard management controller, and the firmware loading abnormality detection apparatus further includes:
the alarm unit is used for sending a signal to any one or more of the indicator light, the buzzer and the substrate management controller if the judgment result shows that the firmware loading of the main chip is abnormal; the baseboard management controller is used for displaying alarm information on the user interface after receiving the signal.
In some embodiments, the logic device detects the power access and power-on button connected externally, and connects the indicator light, the buzzer and the baseboard management controller. The main chips are some chips on the board card, and the loading condition of the chips is mainly monitored in the implementation; the firmware carrier is a chip for storing firmware, and the main chip loads the required firmware from the chip; a logic device: the intermediate link between the main chip and the firmware carrier chip is responsible for transmitting and detecting firmware loading signals, judging whether the loading is normal or not, and giving an alarm according to a judgment result; after judging that the firmware is loaded abnormally, the logic device controls an alarm indicator lamp to light up and a buzzer to sound; the logic device can also inform the baseboard management controller after judging that the firmware is abnormally loaded, and the baseboard management controller can display corresponding warning information in a user interface.
In some specific embodiments, the abnormality determining module 13 may specifically include:
the link abnormity judging unit is used for judging whether each loading link between the firmware carrier and the main chip is abnormal or not according to a signal monitoring result, a timing result and a preset judging rule;
and the firmware loading abnormity judging unit is used for judging that the firmware loading of the main chip is abnormal if any one of the loading links is abnormal.
Correspondingly, an embodiment of the present application further discloses a firmware loading exception detection system, as shown in fig. 5, the system includes: the system comprises a main chip, a logic device and a firmware carrier, wherein the logic device is respectively connected with the main chip and the firmware carrier and is used for monitoring a transmission signal of a loading link between the firmware carrier and the main chip; timing by utilizing an internal timer; the timer is used for timing the transmission time of the transmission signal and starting timing after the logic device is electrified; and judging whether the firmware loading of the main chip is abnormal or not according to the signal monitoring result, the timing result and a preset judgment rule. And implementing the relevant steps in the firmware loading exception detection method disclosed by any one of the foregoing embodiments. The main chip is some chips needing to load firmware on the board card, and the implementation mainly monitors the loading condition of the chips; the firmware carrier is a chip for storing firmware, and the main chip loads the required firmware from the chip.
Further, the embodiment of the present application also discloses an electronic device, which is shown in fig. 6, and the content in the drawing cannot be considered as any limitation to the application scope.
Fig. 6 is a schematic structural diagram of an electronic device 20 according to an embodiment of the present disclosure. The electronic device 20 may specifically include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input output interface 25, and a communication bus 26. The memory 22 is configured to store a computer program, and the computer program is loaded and executed by the processor 21 to implement relevant steps in the firmware loading exception detection method disclosed in any of the foregoing embodiments.
In this embodiment, the power supply 23 is configured to provide a working voltage for each hardware device on the electronic device 20; the communication interface 24 can create a data transmission channel between the electronic device 20 and an external device, and a communication protocol followed by the communication interface is any communication protocol applicable to the technical solution of the present application, and is not specifically limited herein; the input/output interface 25 is configured to obtain external input data or output data to the outside, and a specific interface type thereof may be selected according to specific application requirements, which is not specifically limited herein.
In addition, the storage 22 is used as a carrier for resource storage, and may be a read-only memory, a random access memory, a magnetic disk or an optical disk, etc., and the resources stored thereon include an operating system 221, a computer program 222, data 223 including timing results, etc., and the storage may be a transient storage or a permanent storage.
The operating system 221 is used for managing and controlling each hardware device and the computer program 222 on the electronic device 20, so as to realize the operation and processing of the mass data 223 in the memory 22 by the processor 21, and may be Windows Server, netware, unix, linux, and the like. The computer program 222 may further include a computer program that can be used to perform other specific tasks in addition to the computer program that can be used to perform the firmware loading abnormality detection method disclosed in any of the foregoing embodiments and executed by the electronic device 20.
Further, an embodiment of the present application further discloses a computer storage medium, where computer-executable instructions are stored in the computer storage medium, and when the computer-executable instructions are loaded and executed by a processor, the steps of the firmware loading anomaly detection method disclosed in any of the foregoing embodiments are implemented.
In the present specification, the embodiments are described in a progressive manner, and each embodiment focuses on differences from other embodiments, and the same or similar parts between the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.
The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in Random Access Memory (RAM), memory, read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrases "comprising a," "8230," "8230," or "comprising" does not exclude the presence of additional like elements in a process, method, article, or apparatus that comprises the element.
The firmware loading exception detection method, apparatus, device and medium provided by the present invention are described in detail above, and a specific example is applied in the present document to explain the principle and the implementation of the present invention, and the description of the above embodiment is only used to help understanding the method and the core idea of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
Claims (10)
1. A firmware loading abnormity detection method is characterized in that the method is applied to a logic device which is respectively connected with a main chip and a firmware carrier, and comprises the following steps:
monitoring a transmission signal of a loading link between the firmware carrier and the main chip;
timing by utilizing an internal timer; the timer is used for timing the transmission time of the transmission signal and starting timing after the logic device is electrified;
and judging whether the firmware loading of the main chip is abnormal or not according to the signal monitoring result, the timing result and a preset judgment rule.
2. The method for detecting the firmware loading exception according to claim 1, wherein the determining whether the firmware loading of the main chip has the exception according to the signal monitoring result, the timing result and the preset determination rule comprises:
if the transmission signal is not monitored and the transmission signal is not monitored in the first preset time after the logic device is powered on, judging that the firmware loading of the main chip is abnormal.
3. The method for detecting the firmware loading exception according to claim 1, wherein the determining whether the firmware loading of the main chip has the exception according to the signal monitoring result, the timing result and the preset determination rule comprises:
if the transmission signal is monitored, determining a transmission time length obtained by timing the transmission time of the transmission signal;
and judging whether the difference value between the transmission time length and the preset firmware loading time length is within a preset time length range, and judging whether the firmware loading of the main chip is abnormal according to a judgment result.
4. The method for detecting the firmware loading exception according to claim 3, wherein the determining whether the firmware loading of the main chip has the exception according to the determination result includes:
if the difference value between the transmission time length and the preset firmware loading time length is out of the preset time length range, judging that the firmware loading of the main chip is abnormal;
and if the difference value between the transmission time length and the preset firmware loading time length is within the preset time length range, judging that the firmware loading of the main chip is not abnormal.
5. The firmware loading anomaly detection method according to claim 1, wherein the logic device is connected to any one or more of an indicator light, a buzzer and a baseboard management controller, and after determining whether the firmware loading of the main chip is anomalous according to the signal monitoring result, the timing result and the preset determination rule, the method further comprises:
if the judgment result shows that the firmware loading of the main chip is abnormal, sending a signal to any one or more of the indicator light, the buzzer and the substrate management controller; the baseboard management controller is used for displaying alarm information on the user interface after receiving the signal.
6. The method for detecting firmware loading exception according to any one of claims 1 to 5, wherein the determining whether the firmware loading of the main chip is abnormal according to the signal monitoring result, the timing result and a preset determination rule includes:
judging whether each loading link between the firmware carrier and the main chip is abnormal or not according to a signal monitoring result, a timing result and a preset judgment rule;
and if any one of the loading links is abnormal, judging that the firmware loading of the main chip is abnormal.
7. A firmware loading abnormity detection device is characterized in that the device is applied to a logic device which is respectively connected with a main chip and a firmware carrier, and comprises:
the monitoring module is used for monitoring a transmission signal of a loading link between the firmware carrier and the main chip;
the timing module is used for timing by utilizing an internal timer; the timer is used for timing the transmission time of the transmission signal and starting timing after the logic device is electrified;
and the abnormity judgment module is used for judging whether the firmware loading of the main chip is abnormal or not according to the signal monitoring result, the timing result and a preset judgment rule.
8. A firmware loading abnormity detection system is characterized by comprising a main chip, a logic device and a firmware carrier; the logic device is respectively connected with the main chip and the firmware carrier;
the logic device is used for monitoring a transmission signal of a loading link between the firmware carrier and the main chip; timing by utilizing an internal timer; the timer is used for timing the transmission time of the transmission signal and starting timing after the logic device is electrified; and judging whether the firmware loading of the main chip is abnormal or not according to the signal monitoring result, the timing result and a preset judgment rule.
9. An electronic device, comprising:
a memory for storing a computer program;
a processor for executing the computer program to implement the firmware load exception detection method of any of claims 1 to 6.
10. A computer-readable storage medium for storing a computer program; wherein the computer program, when executed by the processor, implements the firmware load exception detection method of any of claims 1 to 6.
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| CN202211041924.7A CN115408278A (en) | 2022-08-29 | 2022-08-29 | Firmware loading abnormity detection method, device, equipment and storage medium |
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| CN202211041924.7A CN115408278A (en) | 2022-08-29 | 2022-08-29 | Firmware loading abnormity detection method, device, equipment and storage medium |
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| CN202211041924.7A Pending CN115408278A (en) | 2022-08-29 | 2022-08-29 | Firmware loading abnormity detection method, device, equipment and storage medium |
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