CN115407149A - Subway train inversion control unit detection circuit - Google Patents

Subway train inversion control unit detection circuit Download PDF

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Publication number
CN115407149A
CN115407149A CN202211031024.4A CN202211031024A CN115407149A CN 115407149 A CN115407149 A CN 115407149A CN 202211031024 A CN202211031024 A CN 202211031024A CN 115407149 A CN115407149 A CN 115407149A
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pin
resistor
capacitor
contactor
triode
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CN115407149B (en
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黄慧建
胡超
马剑
陈鹏
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Nanjing Rail Transit Systems Co ltd
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Nanjing Rail Transit Systems Co ltd
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01K—MEASURING TEMPERATURE; MEASURING QUANTITY OF HEAT; THERMALLY-SENSITIVE ELEMENTS NOT OTHERWISE PROVIDED FOR
    • G01K13/00—Thermometers specially adapted for specific purposes
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/25—Arrangements for measuring currents or voltages or for indicating presence or sign thereof using digital measurement techniques

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Abstract

The invention discloses a subway train inversion control unit detection circuit, which comprises: the device comprises a power circuit, a current detection circuit, a voltage detection circuit, a contactor detection circuit, an optical fiber receiving circuit, a drive plate detection circuit and a temperature detection circuit; the invention can meet the requirements of self-checking, function simulation and fault recurrence of the inversion control unit; in addition, a protection function and an indication function are designed in the detection circuit, so that the whole function is more comprehensive.

Description

Subway train inversion control unit detection circuit
Technical Field
The invention belongs to the technical field of subway train inverters, and particularly relates to a detection circuit of a subway train inversion control unit.
Background
After many years of subway construction in China, the holding capacity of the subway vehicles is greatly increased, a huge stock market is formed, and the holding capacity of the subway vehicles with huge scales can bring a large amount of maintenance and updating requirements of the rail parts. In urban subway traffic, core equipment of a subway train is a traction inverter box which converts 1500V direct current into alternating voltage with adjustable amplitude and frequency to drive an asynchronous squirrel cage motor on the train and provide power for the train to run. The inversion control unit is a main control unit in the traction inverter box and is responsible for traction/brake control, pulse mode generation, space vector pulse width modulation control, inverter protection, speed measurement, relay control, torque control, voltage and current control, communication and the like.
With the improvement of the maintenance technology of the traction inverter, the maintenance content is expanded from the maintenance of the traction inverter and the drive plate to the maintenance of the inversion control unit, but the detection means of the inversion control unit by subway operation companies is deficient, and the detection can only be carried out by adopting a loading method, so that the detection mode not only increases the workload of the locomotive and has potential safety hazards, but also influences the normal operation of the train. Therefore, an inversion control unit detector is urgently needed, which can realize offline detection of an inversion control unit and can analyze, judge and reproduce fault points of a fault inversion control unit.
Disclosure of Invention
In view of the above-mentioned deficiencies of the prior art, an object of the present invention is to provide a detection circuit for an inversion control unit of a subway train, so as to meet the requirement of offline detection of the inversion control unit of the existing subway train. The detection circuit can realize the simulation of sampling values of power supplies and voltage and current of different voltage grades, the action of a relay, the detection of the feedback of a driving plate, the simulation of temperature and the receiving of trigger pulses, an interface is completely matched with an inversion control unit, and the voltage, the current and the temperature of different grades can be simulated by adjusting parameters of components.
In order to achieve the purpose, the technical scheme adopted by the invention is as follows:
the invention relates to a detection circuit of an inversion control unit of a subway train, which comprises the following components: the device comprises a power circuit, a current detection circuit, a voltage detection circuit, a contactor detection circuit, an optical fiber receiving circuit, a drive plate detection circuit and a temperature detection circuit; wherein the content of the first and second substances,
the power supply circuit is used for carrying out grading control on input +/-24V direct current, providing +/-24V voltage for the inversion control unit, the contactor detection circuit and the drive plate detection circuit, providing +/-12V and +/-6V voltage for the current detection circuit and the optical fiber receiving circuit, and providing +/-15V voltage for the voltage detection circuit;
the current detection circuit is used for simulating and detecting U-phase and V-phase current sampling values of the positive electrode and the negative electrode of the input end of the traction inverter and the output end of the traction inverter, so that the current sampling values of the positive electrode and the negative electrode of the input end are equal, the U-phase and V-phase current sampling values of the output end are the same in size and opposite in direction, and the switching frequencies of the currents are the same; the sampled current is sent to an inversion control unit;
the voltage detection circuit is used for simulating and detecting a DC1500V voltage sampling value at the input end of the traction box and a bus voltage sampling value after the pre-charging contactor or the main contactor is closed after the high-speed circuit breaker is closed, and the sampled voltage is sent to the inversion control unit;
the contactor detection circuit is used for simulating the action of a relay in the traction box; the inverter control unit receives an action instruction sent by the inverter control unit and feeds back the action condition to the inverter control unit; simultaneously controlling the input of the voltage detection circuit and the indicator light loop;
the optical fiber receiving circuit is used for receiving the three-phase full-bridge trigger pulse and the chopping trigger pulse generated by the inversion control unit and carrying out level conversion; the three-phase full-bridge trigger pulse is sent to a current detection circuit; the chopping trigger pulse is sent to the voltage detection circuit and used for simulating the action of the chopping loop;
the drive plate detection circuit is used for simulating a drive plate feedback circuit, judging whether the drive plate fails or not and providing +24V voltage for the drive plate;
and the temperature detection circuit is used for simulating the temperatures of a three-phase full bridge, a chopper loop and the environment in the inverter.
Further, the power supply circuit includes: a +/-24V grading control circuit, a low-dropout linear voltage stabilizing circuit and a +/-15V voltage circuit; wherein the content of the first and second substances,
the ± 24V hierarchical control circuit includes: a main power supply interface JP1, diodes D8 and D9, switches S3 and S4, relays K5 and K6, and an ICU power supply interface J5; pin 1 of the main power interface JP1 is connected to pin 1 of the switch S3 and pin 4 of the relay K5, respectively; pins 2 and 3 of the main power interface JP1 are connected and then respectively connected with pin 1 of the diode D8 and pin 16 of the relay K5 and connected with GND; the 4 pins of the main power interface JP1 are connected with the 13 pins of the relay K5; a pin 1 of the relay K5 is connected with a pin 2 of the switch S3; the pin 8 of the relay K5, the pin 1 of the switch S4 and the pin 4 of the relay K6 are connected, and the connection position is defined as VCC +/+24V; a pin 9 of the relay K5 is connected with a pin 13 of the relay K6, and the connection position is defined as VCC-/-24V; a pin 2 of the diode D9 is respectively connected with a pin 1 of the relay K6 and a pin 2 of the switch S4; a pin 8 of the relay K6 is respectively connected with a pin A1 and a pin B1 of an ICU power interface J5, and the connection position is defined as ICU-VCC +/+24V; a pin 9 of the relay K6 is respectively connected with a pin A2 and a pin B2 of an ICU power interface J5, and the connection position is defined as ICU-VCC-/-24V; a pin 1 of the diode D9, a pin 16 of the relay K6 and pins A3 and B3 of the ICU power interface J5 are connected with GND; the +/-24V power supply is transmitted to an inversion control unit through an ICU power interface J5;
the low dropout linear voltage regulator circuit comprises: the current sensor interface U7, the voltage stabilization chips U6, U8, U9 and U11, the light emitting diodes DS3 and DS5, the capacitors C15, C16, C17, C18, C19, C20, C25, C26, C27, C28, C29 and C30, and the resistors R18, R20, R22 and R26; a pin A3 of the current sensor interface U7 is connected with a pin 1 of the resistor R18 and receives +24V voltage provided by the inversion control unit; a pin 2 of the resistor R18 is respectively connected with a pin 1 of the capacitor C19, a pin 1 of the capacitor C17 and a pin 1 of the voltage stabilizing chip U6; the 3 pins of the voltage stabilizing chip U6 are output terminals, the output voltage is +12V, which is defined as VCC +/+12V here, and the output voltages are respectively connected to the 1 pin of the capacitor C18, the 1 pin of the resistor R20, the 1 pin of the capacitor C15, the 1 pin of the capacitor C16, and the 1 pin of the voltage stabilizing chip U8; pin 2 of the resistor R20 is connected with pin 1 of the light emitting diode DS 3; a pin 3 of the voltage stabilizing chip U8 is an output end, the output voltage is +6V, defined as VCC +/+6V here, and the output voltage is connected with a pin 2 of the capacitor C16; a pin B3 of the current sensor interface U7 is connected with a pin 1 of the resistor R26 and receives-24V voltage provided by the inversion control unit; the pin 2 of the resistor R26 is respectively connected with the pin 2 of the capacitor C27, the pin 2 of the capacitor C25 and the pin 2 of the voltage stabilizing chip U11; the pin 3 of the voltage stabilizing chip U11 is an output terminal, the output voltage is-12V, which is defined as VCC-/-12V, and is connected to the pin 2 of the capacitor C26, the pin 2 of the light emitting diode DS5, the pin 2 of the capacitor C28, the pin 2 of the capacitor C29, the pin 2 of the capacitor C30, and the pin 2 of the voltage stabilizing chip U9, respectively; pin 2 of the resistor R22 is connected with pin 1 of the light emitting diode DS 5; the pin 3 of the voltage stabilizing chip U9 is an output end, the output voltage is-6V, and VCC-/-6V is defined here, and is connected with the pin 1 of the capacitor C30; a pin 2 of a capacitor C19, a pin 2 of a capacitor C17, a pin 2 of a voltage stabilizing chip U6, a pin 2 of a capacitor C18, a pin 2 of a light emitting diode DS3, a pin 2 of a capacitor C20, a pin 2 of a capacitor C15, a pin 2 of a voltage stabilizing chip U8, a pin 1 of a capacitor C27, a pin 1 of a capacitor C25, a pin 1 of a voltage stabilizing chip U11, a pin 1 of a capacitor C26, a pin 1 of a resistor R22, a pin 1 of a capacitor C28, a pin 1 of a capacitor C29 and a pin 1 of a voltage stabilizing chip U9 are all connected with GND; a pin A2 of the current sensor interface U7 outputs a V-phase sampling current (VC), a pin A3 is connected with a pin +24V and a pin A5 output by the inversion control unit and outputs a direct-current positive sampling current (PC), a pin B2 outputs a U-phase sampling current (UC), and a pin B3 is connected with a pin-24V and a pin B5 output by the inversion control unit and outputs a direct-current negative sampling current (NC);
the ± 15V voltage circuit includes: a voltage detection interface J1, capacitors C9, C10, C13 and C14 and resistors R9 and R17; a pin A2 of the voltage detection interface J1 is respectively connected with a pin 2 of the capacitor C10 and a pin 1 of the resistor R9; a pin 2 of the resistor R9 is connected with a pin 2 of the capacitor C9, and the connection position is defined as VCC +/+15V; pin A3 of the voltage detection interface J1 is respectively connected with pin 2 of the capacitor C14 and pin 1 of the resistor R17; a pin 2 of the resistor R17 is connected with a pin 2 of the capacitor C13, and the connection position is defined as VCC-/-15V; pin 1 of the capacitor C10, pin 1 of the capacitor C9, pin 1 of the capacitor C14 and pin 1 of the capacitor C13 are all connected with GND.
Furthermore, the ICU power interface J5 is a connector of 178323-3.
Furthermore, the current sensor interface U7 is a connector of model 178326-3.
Further, the model of the voltage stabilization chip U6 is MC7812BD.
Further, the model of the voltage stabilizing chip U8 is MC7906CD.
Further, the model of the voltage stabilization chip U11 is MC7912BD.
Further, the model of the voltage stabilization chip U9 is MC7806BD.
Further, the voltage detection interface J1 is a connector with the model number of 178323-3.
Further, the current detection circuit includes: the three-phase full-bridge type three-phase power supply comprises a three-phase full-bridge analog circuit, a transformer circuit, a U-phase current conditioning circuit, a V-phase current conditioning circuit, a positive electrode current conditioning circuit and a negative electrode current conditioning circuit; wherein the content of the first and second substances,
the three-phase full-bridge analog circuit comprises: MOSFETs V10, V11, V12, V13, V14, V15 and capacitor C37; the 2 feet of the capacitor C37 are respectively connected with the source S of the source S, MOSFETV11 of the MOSFET V10 and the source S of the source S, MOSFETV of the MOSFET V10 and VCC +/+12V; a pin 1 of the capacitor C37 is respectively connected with a source S of the MOSFET V13, a source S of S, MOSFETV of the MOSFET V14 and VCC-/-12V; after being connected with a drain D of a drain D, MOSFETV of the MOSFETV10, the drain D is connected with a pin 1 of the pulse transformer T1; the drain D of the drain D, MOSFETV14 of the MOSFET V11 is connected with the pin 1 of the pulse transformer T3; the drain D of the drain D, MOSFETV of the MOSFET V12 is connected with the pin 1 of the pulse transformer T2;
the transformer circuit includes: pulse transformers T1, T2, T3, capacitors C33, C36, C39, and resistors R33, R38, R41; the pin 4 of the pulse transformer T1, the pin 4 of the pulse transformer T2 and the pin 4 of the pulse transformer T3 are connected; the pin 8 of the pulse transformer T1 is respectively connected with the pin 1 of the resistor R33 and the pin 1 of the capacitor C33, and then is connected with the pin 3 of the operational amplifier U12A; the pin 8 of the pulse transformer T2 is connected with the pin 1 of the resistor R38 and the pin 1 of the capacitor C36; a pin 8 of the pulse transformer T3 is respectively connected with a pin 1 of the resistor R41 and a pin 1 of the capacitor C39, and then is connected with a pin 3 of the operational amplifier U13A; a pin 5 of the pulse transformer T1, a pin 5 of the pulse transformer T2, a pin 5 of the pulse transformer T3, a pin 2 of the resistor R33, a pin 2 of the capacitor C33, a pin 2 of the resistor R38, a pin 2 of the capacitor C36, a pin 2 of the resistor R41 and a pin 2 of the capacitor C39 are all connected with GND;
the U-phase current conditioning circuit comprises: an operational amplifier U12, triodes V6, V7, V8 and V9, a diode D6, capacitors C32, C34 and C35, and resistors R29, R30, R31, R32, R34, R35, R36 and R37; the operational amplifier U12 comprises an operational amplifier U12A and an operational amplifier U12B; a pin 2 of the operational amplifier U12A is respectively connected with a pin 2 of the resistor R35 and a pin 2 of the resistor R36; after the pin 1 of the resistor R35 is connected with the pin 1 of the resistor R29, the pin is connected with the emitter E of the triode V6 and the emitter E of the triode V7; a pin 1 of the operational amplifier U12A is respectively connected with a base B of the triode V6 and a base B of the triode V7; the pin 2 of the resistor R29, the pin 2 of the resistor R30, the pin 2 of the resistor R34 and the pin 2 of the capacitor C34 are connected; a pin 5 of the operational amplifier U12B is connected with a pin 1 of the resistor R30; a pin 6 of the operational amplifier U12B is respectively connected with a pin 2 of the resistor R37 and a pin 1 of the resistor R31, and then is connected with an emitter E of the triode V8 and an emitter E of the triode V9; the pin 7 of the operational amplifier U12B is respectively connected with the base B of the triode V8 and the base B of the triode V9; the pin 2 of the resistor R31, the pin 2 of the resistor R32 and the pin 2 of the diode D6 are connected; after connecting pin 1 of the resistor R32 and pin 1 of the diode D6, connecting the two pins with pin B2 of the current sensor interface U7; the pin 8 of the operational amplifier U12A, the pin 2 of the capacitor C32, the collector C of the triode V6 and the collector C of the triode V8 are all connected with VCC +/+12V; a pin 4 of the operational amplifier U12A, a pin 2 of the capacitor C35, a collector C of the triode V7 and a collector C of the triode V9 are all connected with VCC-/-12V; pin 1 of the capacitor C32, pin 1 of the capacitor C34, pin 1 of the capacitor C35, pin 1 of the resistor R34, pin 1 of the resistor R36 and pin 1 of the resistor R37 are all connected with GND;
the V-phase current conditioning circuit includes: an operational amplifier U13, triodes V16, V17, V18 and V19, a diode D7, capacitors C38, C40 and C41, and resistors R42, R43, R44, R45, R46, R50, R51 and R52; the operational amplifier U13 comprises an operational amplifier U13A and an operational amplifier U13B; a pin 2 of the operational amplifier U13A is respectively connected with a pin 2 of the resistor R50 and a pin 2 of the resistor R51; after the pin 1 of the resistor R50 is connected with the pin 1 of the resistor R42, the resistor R is connected with an emitter E of the triode V16 and an emitter E of the triode V17; a pin 1 of the operational amplifier U13A is respectively connected with a base B of the triode V16 and a base B of the triode V17; the pin 2 of the resistor R42, the pin 2 of the resistor R43, the pin 2 of the resistor R46 and the pin 2 of the capacitor C40 are connected; a pin 5 of the operational amplifier U13B is connected with a pin 1 of the resistor R43; the pin 6 of the operational amplifier U13B is respectively connected with the pin 2 of the resistor R52 and the pin 1 of the resistor R44, and then is connected with the emitter E of the triode V18 and the emitter E of the triode V19; the pin 7 of the operational amplifier U13B is respectively connected with the base B of the triode V18 and the base B of the triode V19; the pin 2 of the resistor R44, the pin 2 of the resistor R45 and the pin 2 of the diode D7 are connected; the resistor R45 is connected with a pin 1 of the diode D7 and then connected with a pin A2 of the current sensor interface U7; the pin 8 of the operational amplifier U13A, the pin 2 of the capacitor C38, the collector C of the triode V16 and the collector C of the triode V18 are all connected with VCC +/+12V; a pin 4 of the operational amplifier U13A, a pin 2 of the capacitor C41, a collector C of the triode V17 and a collector C of the triode V19 are all connected with VCC-/-12V; pin 1 of the capacitor C38, pin 1 of the capacitor C40, pin 1 of the capacitor C41, pin 1 of the resistor R46, pin 1 of the resistor R51 and pin 1 of the resistor R52 are all connected with GND;
the positive electrode current conditioning circuit comprises: an operational amplifier U5, a triode V3, capacitors C12, C21 and C22 and resistors R15, R19 and R21; pin 2 of the resistor R15 is connected with pin 1 of the resistor R19; a pin 2 of the resistor R19 is connected with a pin 1 of the capacitor C21 and then connected with a pin 3 of the operational amplifier U5; a pin 2 of the operational amplifier U5 is connected with a pin 1 of the resistor R21 and then connected with an emitter E of the triode V3; a pin 6 of the operational amplifier U5 is connected with a base B of the triode V3; pin 2 of the resistor R21 is connected with pin A5 of the current sensor interface U7; a pin 7 of the operational amplifier U5, a pin 1 of the capacitor C12, a pin 1 of the resistor R15 and a collector C of the triode V3 are all connected with VCC +/+12V; the 4 pin of the operational amplifier U5 and the 1 pin of the capacitor C22 are both connected with VCC-/-12V; the pin 2 of the capacitor C12, the pin 2 of the capacitor C21, the pin 2 of the capacitor C22 and the pin 3 of the resistor R19 are all connected with GND;
the negative current conditioning circuit comprises: an operational amplifier U10, a triode V4, capacitors C23, C24 and C31 and resistors R24, R25 and R27; pin 1 of the resistor R27 is connected with pin 3 of the resistor R24; a pin 2 of the resistor R24 is connected with a pin 2 of the capacitor C24, and then is connected with a pin 3 of the operational amplifier U10; a pin 2 of the operational amplifier U10 is connected with a pin 1 of the resistor R25 and then connected with an emitter E of the triode V4; a pin 6 of the operational amplifier U10 is connected with a base electrode B of the triode V4; pin 2 of the resistor R25 is connected with pin B5 of the current sensor interface U7; a pin 7 of the operational amplifier U10 and a pin 1 of the capacitor C23 are both connected with VCC +/+12V; a pin 4 of the operational amplifier U10, a pin 1 of the capacitor C31, a pin 2 of the resistor R27 and a collector C of the triode V4 are all connected with VCC-/-12V; pin 2 of the capacitor C23, pin 2 of the capacitor C31, pin 1 of the capacitor C24 and pin 1 of the resistor R24 are all connected with GND.
Furthermore, the MOSFETs V11, V12, V13, V14, V15 and V16 are all NPN type, and the model is IRFZ34.
Further, the model number of the operational amplifier U12 is TL082ID; the triodes V6 and V8 are NPN triodes with the model number of BC817, and the triodes V7 and V9 are PNP triodes with the model number of BC807; and the U-phase current is amplified in two stages and then sent to an inversion control unit.
Further, the model number of the operational amplifier U13 is TL082ID; the triodes V16 and V18 are NPN triodes, and the model is BC817; the triodes V17 and V19 are PNP triodes with the model number of BC807; and the V-phase current is amplified in two stages and then sent to an inversion control unit.
Further, the operational amplifier U5 is model TL081ID; the triode V3 is an NPN triode with the model number of BC817; the positive electrode current is amplified by a single stage and then sent to an inversion control unit.
Further, the operational amplifier U10 is of model TL081ID; the triode V4 is a PNP triode with the model number of BC807; the negative current is amplified by a single stage and then sent to an inversion control unit.
Further, the voltage detection circuit includes: a DC1500V voltage sampling circuit and a bus voltage sampling circuit;
the DC1500V voltage sampling circuit includes: the circuit comprises an operational amplifier U3, a triode V5, a switch S1, capacitors C3, C4 and C5, and resistors R5, R6 and R7; a pin 2 of the switch S1 is connected with VCC +/+24V; pin 1 of the switch S1 is connected with pin 1 of the resistor R5; after being connected with the pin 2 of the resistor R5, the pin 2 of the resistor R6 and the pin 2 of the capacitor C4, the two pins are connected with the pin 3 of the operational amplifier U3; a pin 2 of the operational amplifier U3 and a pin 2 of the resistor R7 are connected with an emitter E of the triode V5 and then connected with a pin A1 of the voltage detection interface J1; a pin 6 of the operational amplifier U3 is connected with a base B of the triode V5; a pin 7 of the operational amplifier U3 and a pin 2 of the capacitor C3 are both connected with VCC +/+15V; the 4 pin of the operational amplifier U3 and the 2 pin of the capacitor C5 are both connected with VCC-/-15V; pin 1 of the capacitor C3, pin 1 of the capacitor C4, pin 1 of the capacitor C5, pin 1 of the resistor R6 and pin 1 of the resistor R7 are all connected with GND;
the bus voltage sampling circuit includes: an operational amplifier U4, triodes V1 and V2, a diode D2, capacitors C6, C7, C8 and C11, and resistors R8, R11, R12, R13 and R14; the operational amplifier U4 comprises an operational amplifier U4A and an operational amplifier U4B; after being connected with the pin 2 of the resistor R8, the pin 2 of the resistor R12 and the pin 2 of the capacitor C7, the three-pin-connected operational amplifier is connected with the pin 3 of the operational amplifier U4A; after the pin 2 of the operational amplifier U4A, the pin 2 of the resistor R11 and the pin 2 of the resistor R13 are connected, the operational amplifier U is connected with an emitter E of the triode V1; a pin 1 of the operational amplifier U4A is connected with a base electrode B of the triode V1; pin 1 of the resistor R11 is connected with pin 1 of the diode D2; a pin 2 of the diode D2 is connected with a pin 2 of the capacitor C8 and then connected with a pin 5 of the operational amplifier U4B; a pin 6 of the operational amplifier U4B is respectively connected with a pin 2 of the resistor R14 and an emitter E of the triode V2, and then is connected with a pin B1 of the voltage detection interface J1; the pin 7 of the operational amplifier U4B is connected with the base B of the triode V2; the pin 8 of the operational amplifier U4A, the pin 2 of the capacitor C6, the collector C of the triode V1 and the collector C of the triode V2 are connected with VCC +/+15V; the pin 4 of the operational amplifier U4A and the pin 2 of the capacitor C11 are both connected with VCC-/-15V; pin 1 of capacitor C6, pin 1 of capacitor C7, pin 1 of capacitor C8, pin 1 of capacitor C11, pin 1 of resistor R12, pin 1 of resistor R13 and pin 1 of resistor R14 are all connected with GND.
Further, the operational amplifier U3 is TL081ID; the triode V5 is an NPN triode with the model number BC817; the DC1500V voltage is sampled and amplified in a single stage and then sent to an inversion control unit.
Further, the model number of the operational amplifier U4 is TL082ID; the triodes V1 and V2 are NPN triodes, and the model is BC817; and the bus voltage is amplified in two stages by sampling and then is sent to an inversion control unit.
Further, the contactor detection circuit includes: the system comprises a bypass contactor loop, a fan contactor loop, a pre-charging contactor loop, a main contactor loop and an emergency braking simulation loop; wherein the content of the first and second substances,
the bypass contactor circuit includes: the contactor comprises a contactor interface J2, a contactor K3, a diode D1, a light emitting diode DS4 and a resistor R23; the pin A3 of the contactor interface J2 is connected with the pin 1 of the contactor K3 and the pin 1 of the diode D1 respectively; the A4 pin of the contactor interface J2 is respectively connected with the 13 pin and the 16 pin of the contactor K3 and the 2 pin of the diode D1; the 4 feet of the contactor K3 are connected with VCC +/+24V; the pin 9 of the contactor K3 is connected with the pin B3 of the contactor interface J2; a pin 8 of the contactor K3 is connected with a pin 2 of the resistor R23; pin 1 of the resistor R23 is connected with pin 1 of the light emitting diode DS 4; pin 2 of the light emitting diode DS4 is connected with GND;
the fan contactor loop includes: the contactor comprises a contactor interface J2, a contactor K4, a diode D3, a light emitting diode DS6 and a resistor R28; the A5 pin of the contactor interface J2 is connected with the 1 pin of the contactor K4 and the 1 pin of the diode D3 respectively; a pin A6 of the contactor interface J2 is respectively connected with a pin 13 and a pin 16 of the contactor K4 and a pin 2 of the diode D3; the 4 feet of the contactor K4 are connected with VCC +/+24V; the pin 9 of the contactor K4 is connected with the pin B6 of the contactor interface J2; the pin 8 of the contactor K4 is connected with the pin 2 of the R28; pin 1 of the resistor R28 is connected with pin 1 of the light emitting diode DS 6; pin 2 of the light emitting diode DS6 is connected with GND;
the pre-charging contactor circuit includes: the device comprises a contactor interface J2, a contactor K2, a diode D4, a light emitting diode DS2 and a resistor R16; the pin A7 of the contactor interface J2 is respectively connected with the pin 1 of the contactor K2 and the pin 1 of the diode D4; a pin A8 of the contactor interface J2 is respectively connected with a pin 13 and a pin 16 of the contactor K2 and a pin 2 of the diode D4; the 4 pins of the contactor K2 are connected with VCC +/+24V; a pin 11 of the contactor K2 is connected with a pin B7 of a contactor interface J2; pin 9 of the contactor K2 is connected with pin 2 of the resistor R16; pin 1 of the resistor R16 is connected with pin 1 of the light emitting diode DS 2; pin 2 of the light emitting diode DS2 is connected with GND; the pin 8 of the contactor K2 is connected with the pin 8 of the contactor K1 and then connected with the pin 1 of the resistor R8;
the main contactor circuit includes: the contactor comprises a contactor interface J2, a contactor K1, a diode D5, a light emitting diode DS1 and a resistor R10; the A9 pin of the contactor interface J2 is respectively connected with the 1 pin of the contactor K1 and the 1 pin of the diode D5; a pin A10 of the contactor interface J2 is respectively connected with a pin 13 and a pin 16 of the contactor K1 and a pin 2 of the diode D5; the 4 pins of the contactor K1 are connected with VCC +/+24V; the pin 11 of the contactor K1 is connected with the pin B9 of the contactor interface J2; a pin 9 of the contactor K1 is connected with a pin 2 of the resistor R10; pin 1 of the resistor R10 is connected with pin 1 of the light emitting diode DS 1; pin 2 of the light emitting diode DS1 is connected with GND;
the emergency braking simulation circuit comprises: a contactor interface J2 and a switch S2; the A2 pin of the contactor interface J2 is connected with the 1 pin of the switch S2; pin B1 of contactor interface J2 is connected to pin 2 of switch S2.
Further, the type of the contactor interface J2 is 178328-3.
Furthermore, the types of the contactors K1, K2, K3 and K4 are G5V-2.
Further, the optical fiber receiving circuit includes: a main loop trigger pulse circuit and a chopping trigger pulse circuit; wherein the content of the first and second substances,
the main loop trigger pulse circuit includes: the optical fiber receivers U14, U15, U16, U17, U18 and U19, the triodes V20, V21 and V22, the capacitors C42, C43, C44, C45, C46 and C47, the resistors R53, R54, R55, R56, R57, R58, R59, R60, R61, R62, R63, R64, R65, R66, R67, R68, R69 and R70;
the 3 pins of the optical fiber receiver U14, the 1 pin of the capacitor C42 and the 1 pin of the resistor R53 are connected with VCC +/+12V; the pin 2 of the optical fiber receiver U14 and the pin 2 of the capacitor C42 are both connected with VCC +/+6V; pin 1 of the optical fiber receiver U14 is connected with pin 1 of the resistor R56 and pin 2 of the resistor R53 respectively; the pin 2 of the resistor R56 is connected with the grid G of the MOSFET V10;
a pin 3 of the optical fiber receiver U15, a pin 1 of the capacitor C43, a pin 1 of the resistor R54 and an emitter E of the triode V20 are all connected with VCC-/-6V; a pin 2 of the optical fiber receiver U15, a pin 2 of the capacitor C43 and a pin 2 of the resistor R58 are connected with VCC-/-12V; pin 1 of the optical fiber receiver U15 is connected with pin 1 of the resistor R57; after the pin 2 of the resistor R54 is connected with the pin 2 of the resistor R57, the base B of the triode V20 is connected; a collector C of the triode V20 is respectively connected with a pin 1 of the resistor R55 and a pin 1 of the resistor R58; pin 2 of the resistor R55 is connected with a grid G of the MOSFET V13;
the 3 pins of the optical fiber receiver U16, the 1 pin of the capacitor C44 and the 1 pin of the resistor R59 are all connected with VCC +/+12V; a pin 2 of the optical fiber receiver U16 and a pin 2 of the capacitor C44 are both connected with VCC +/+6V; pin 1 of the optical fiber receiver U16 is connected with pin 1 of the resistor R62 and pin 2 of the resistor R59 respectively; a pin 2 of the resistor R62 is connected with a grid G of the MOSFET V11;
a pin 3 of the optical fiber receiver U17, a pin 1 of the capacitor C45, a pin 1 of the resistor R60 and an emitter E of the triode V21 are all connected with VCC-/-6V; the pin 2 of the optical fiber receiver U17, the pin 2 of the capacitor C45 and the pin 2 of the resistor R64 are all connected with VCC-/-12V; pin 1 of the optical fiber receiver U17 is connected with pin 1 of the resistor R63; after the pin 2 of the resistor R60 is connected with the pin 2 of the resistor R63, the base B of the triode V21 is connected; a collector C of the triode V21 is respectively connected with a pin 1 of the resistor R61 and a pin 1 of the resistor R64; pin 2 of the resistor R61 is connected with a grid G of the MOSFET V14;
the 3 pins of the optical fiber receiver U18, the 1 pin of the capacitor C47 and the 1 pin of the resistor R65 are all connected with VCC +/+12V; a pin 2 of the optical fiber receiver U18 and a pin 2 of the capacitor C47 are both connected with VCC +/+6V; pin 1 of the optical fiber receiver U18 is connected with pin 1 of the resistor R69 and pin 2 of the resistor R65 respectively; the pin 2 of the resistor R69 is connected with a grid G of the MOSFET V12;
a pin 3 of the optical fiber receiver U19, a pin 1 of the capacitor C46, a pin 1 of the resistor R66 and an emitter E of the triode V22 are all connected with VCC-/-6V; pin 2 of the optical fiber receiver U19, pin 2 of the capacitor C46 and pin 2 of the resistor R68 are all connected with VCC-/-12V; pin 1 of the optical fiber receiver U19 is connected with pin 1 of the resistor R70; after the pin 2 of the resistor R66 is connected with the pin 2 of the resistor R70, the base B of the triode V22 is connected; a collector C of the triode V22 is respectively connected with a pin 1 of the resistor R67 and a pin 1 of the resistor R68; a pin 2 of the resistor R67 is connected with a grid G of the MOSFET V15;
the chopping trigger pulse circuit comprises: the device comprises optical fiber receivers U1 and U2, triodes V23 and V24, capacitors C1 and C2, and resistors R1, R2, R3 and R4;
the 3 pins of the optical fiber receiver U1, the 1 pin of the capacitor C1 and the 1 pin of the resistor R1 are all connected with VCC +/+6V; the pin 2 of the optical fiber receiver U1, the pin 2 of the capacitor C1 and the emitter E of the triode V23 are all connected with GND; a pin 1 of the optical fiber receiver U1 is respectively connected with a pin 2 of the resistor R1 and a base B of the triode V23; a collector C of the triode V23 is connected with a pin 1 of the resistor R2; a pin 2 of the resistor R2 is connected with a pin 5 of the operational amplifier U4B;
the 3 pins of the optical fiber receiver U2, the 1 pin of the capacitor C2 and the 1 pin of the resistor R3 are all connected with VCC +/+6V; a pin 2 of the optical fiber receiver U2, a pin 2 of the capacitor C2 and an emitter E of the triode V24 are all connected with GND; a pin 1 of the optical fiber receiver U2 is respectively connected with a pin 2 of the resistor R3 and a base B of the triode V24; a collector C of the triode V24 is connected with a pin 1 of the resistor R4; and a pin 2 of the resistor R4 is connected with a pin 5 of the operational amplifier U4B.
Furthermore, the models of the optical fiber receivers U14, U15, U16, U17, U18 and U19 are R-2532Z, and the models of the triodes V20, V21 and V22 are PNP triodes and BC807.
Furthermore, the models of the optical fiber receivers U1 and U2 are R-2532Z, and the models of the triodes V23 and V24 are NPN triodes BC817.
Further, the drive board detection circuit includes: a contactor interface J3, a switch S5, light emitting diodes DS7 and DS8 and resistors R39 and R40; wherein, the first and the second end of the pipe are connected with each other,
pin B2 of the contactor interface J3 is connected with pin 1 of the switch S5; pin 2 of the switch S5 is connected with pin 2 of the resistor R39; a pin 1 of the resistor R39 is connected with ICU-VCC +/+24V; a pin A1 of the contactor interface J3 is connected with a pin 1 of a light-emitting diode DS 7; pin 2 of the light emitting diode DS7 is connected with pin 1 of the resistor R40; pin 2 of the resistor R40 is connected with pin A2 of the contactor interface J3; a pin A3 of the contactor interface J3 is connected with a pin 1 of a light-emitting diode DS 8; pin 2 of the light emitting diode DS8 is connected to GND.
Further, the type of the contactor interface J3 is 178141-3.
Further, the temperature detection circuit includes: contactor interface J4 and PT100 resistors R47, R48, R49; wherein the content of the first and second substances,
the pin A1 of the contactor interface J4 is connected with the pin 2 of the resistor R47; pin 1 of the resistor R47 is connected with pin B1 of the contactor interface J4; pin A2 of the contactor interface J4 is connected with pin 2 of the resistor R48; pin 1 of the resistor R48 is connected with pin B2 of the contactor interface J4; pin A3 of the contactor interface J4 is connected with pin 2 of the resistor R49; pin 1 of resistor R49 is connected to pin B3 of contactor interface J4.
Further, the type of the contactor interface J4 is 178323-3.
The invention has the beneficial effects that:
the detection circuit of the subway train inversion control unit has the characteristics of good matching property, strong expansibility, low power consumption, simplicity in operation and the like, and can meet the requirements of self-checking, function simulation and fault recurrence of the inversion control unit; in addition, the detection circuit is provided with a protection function (overcurrent protection, relay coil protection) and an indication function (power indication, relay on-off indication and drive plate indication), so that the whole function is more comprehensive.
The invention greatly meets the requirements of offline detection, function simulation, fault reproduction and the like of the inversion control unit of the current subway train, improves the maintenance efficiency of the train traction box and reduces the difficulty of daily maintenance.
The invention adopts a modular design idea, realizes the construction of circuits with the same function by using discrete elements, and has the characteristics of high reliability, low cost and strong applicability.
Drawings
FIG. 1 is a diagram of the design architecture of the circuit of the present invention;
FIG. 2a is a schematic diagram of a + -24V hierarchical control circuit;
FIG. 2b is a schematic diagram of a low dropout linear voltage regulator circuit;
FIG. 2c is a schematic diagram of a + -15V voltage circuit;
FIG. 3a is a schematic diagram of a three-phase full-bridge analog circuit;
FIG. 3b is a schematic diagram of a transformer circuit;
FIG. 3c is a schematic diagram of a U-phase current conditioning circuit;
FIG. 3d is a schematic diagram of a V-phase current conditioning circuit;
FIG. 3e is a schematic diagram of a positive current conditioning circuit;
FIG. 3f is a schematic diagram of a negative current conditioning circuit;
FIG. 4a is a schematic diagram of a DC1500V voltage sampling circuit;
FIG. 4b is a schematic diagram of a bus voltage sampling circuit;
FIG. 5 is a schematic diagram of a contactor detection circuit;
FIG. 6a is a schematic diagram of a main loop trigger pulse circuit;
FIG. 6b is a schematic diagram of a chopping trigger pulse circuit;
FIG. 7 is a schematic diagram of a drive board detection circuit;
fig. 8 is a schematic diagram of a temperature detection circuit.
Detailed Description
In order to facilitate understanding of those skilled in the art, the present invention will be further described with reference to the following examples and drawings, which are not intended to limit the present invention.
Referring to fig. 1, the present invention provides a detection circuit for an inversion control unit of a subway train, including: the device comprises a power circuit, a current detection circuit, a voltage detection circuit, a contactor detection circuit, an optical fiber receiving circuit, a drive plate detection circuit and a temperature detection circuit; wherein the content of the first and second substances,
the power supply circuit is used for carrying out grading control on input +/-24V direct current, providing +/-24V voltage for the inversion control unit, the contactor detection circuit and the drive plate detection circuit, providing +/-12V and +/-6V voltage for the current detection circuit and the optical fiber receiving circuit, and providing +/-15V voltage for the voltage detection circuit;
wherein the power supply circuit includes: a +/-24V grading control circuit, a low-dropout linear voltage stabilizing circuit and a +/-15V voltage circuit; wherein the content of the first and second substances,
referring to fig. 2a, the ± 24V hierarchical control circuit includes: a main power supply interface JP1, diodes D8 and D9, switches S3 and S4, relays K5 and K6, and an ICU power supply interface J5; pin 1 of the main power interface JP1 is connected to pin 1 of the switch S3 and pin 4 of the relay K5, respectively; pins 2 and 3 of the main power interface JP1 are connected and then respectively connected with pin 1 of the diode D8 and pin 16 of the relay K5 and connected with GND; the 4 pins of the main power interface JP1 are connected with the 13 pins of the relay K5; a pin 1 of the relay K5 is connected with a pin 2 of the switch S3; the pin 8 of the relay K5, the pin 1 of the switch S4 and the pin 4 of the relay K6 are connected, and the connection position is defined as VCC +/+24V; a pin 9 of the relay K5 is connected with a pin 13 of the relay K6, and the connection position is defined as VCC-/-24V; a pin 2 of the diode D9 is respectively connected with a pin 1 of the relay K6 and a pin 2 of the switch S4; a pin 8 of the relay K6 is respectively connected with a pin A1 and a pin B1 of an ICU power interface J5, and the connection position is defined as ICU-VCC +/+24V; a pin 9 of the relay K6 is respectively connected with a pin A2 and a pin B2 of an ICU power interface J5, and the connection position is defined as ICU-VCC-/-24V; a pin 1 of the diode D9, a pin 16 of the relay K6 and pins A3 and B3 of the ICU power interface J5 are connected with GND; the +/-24V power supply is sent to an inversion control unit through an ICU power supply interface J5;
referring to FIG. 2b, the low dropout linear voltage regulator circuit comprises: the current sensor interface U7, the voltage stabilization chips U6, U8, U9 and U11, the light emitting diodes DS3 and DS5, the capacitors C15, C16, C17, C18, C19, C20, C25, C26, C27, C28, C29 and C30, and the resistors R18, R20, R22 and R26; a pin A3 of the current sensor interface U7 is connected with a pin 1 of the resistor R18 and receives +24V voltage provided by the inversion control unit; a pin 2 of the resistor R18 is respectively connected with a pin 1 of the capacitor C19, a pin 1 of the capacitor C17 and a pin 1 of the voltage stabilizing chip U6; the pin 3 of the voltage stabilizing chip U6 is an output terminal, the output voltage is +12V, which is defined as VCC +/+12V, and is connected to the pin 1 of the capacitor C18, the pin 1 of the resistor R20, the pin 1 of the capacitor C15, the pin 1 of the capacitor C16, and the pin 1 of the voltage stabilizing chip U8, respectively; pin 2 of the resistor R20 is connected with pin 1 of the light emitting diode DS 3; a pin 3 of the voltage stabilizing chip U8 is an output end, the output voltage is +6V, defined as VCC +/+6V here, and the output voltage is connected with a pin 2 of the capacitor C16; a pin B3 of the current sensor interface U7 is connected with a pin 1 of the resistor R26 and receives-24V voltage provided by the inversion control unit; the pin 2 of the resistor R26 is respectively connected with the pin 2 of the capacitor C27, the pin 2 of the capacitor C25 and the pin 2 of the voltage stabilizing chip U11; the pin 3 of the voltage stabilizing chip U11 is an output terminal, the output voltage is-12V, which is defined as VCC-/-12V, and is connected to the pin 2 of the capacitor C26, the pin 2 of the light emitting diode DS5, the pin 2 of the capacitor C28, the pin 2 of the capacitor C29, the pin 2 of the capacitor C30, and the pin 2 of the voltage stabilizing chip U9, respectively; pin 2 of the resistor R22 is connected with pin 1 of the light-emitting diode DS 5; the pin 3 of the voltage stabilizing chip U9 is an output end, the output voltage is-6V, and VCC-/-6V is defined here, and is connected with the pin 1 of the capacitor C30; a pin 2 of a capacitor C19, a pin 2 of a capacitor C17, a pin 2 of a voltage stabilizing chip U6, a pin 2 of a capacitor C18, a pin 2 of a light emitting diode DS3, a pin 2 of a capacitor C20, a pin 2 of a capacitor C15, a pin 2 of a voltage stabilizing chip U8, a pin 1 of a capacitor C27, a pin 1 of a capacitor C25, a pin 1 of a voltage stabilizing chip U11, a pin 1 of a capacitor C26, a pin 1 of a resistor R22, a pin 1 of a capacitor C28, a pin 1 of a capacitor C29 and a pin 1 of a voltage stabilizing chip U9 are all connected with GND; a pin A2 of a current sensor interface U7 outputs V-phase sampling current (VC), a pin A3 is connected with +24V and +24V output by an inversion control unit, a pin A5 outputs direct-current positive sampling current (PC), a pin B2 outputs U-phase sampling current (UC), and a pin B3 is connected with-24V and-B5 output by the inversion control unit and outputs direct-current negative sampling current (NC);
referring to fig. 2c, the ± 15V voltage circuit includes: a voltage detection interface J1, capacitors C9, C10, C13 and C14 and resistors R9 and R17; a pin A2 of the voltage detection interface J1 is respectively connected with a pin 2 of a capacitor C10 and a pin 1 of a resistor R9; a pin 2 of the resistor R9 is connected with a pin 2 of the capacitor C9, and the connection position is defined as VCC +/+15V; pin A3 of the voltage detection interface J1 is respectively connected with pin 2 of the capacitor C14 and pin 1 of the resistor R17; a pin 2 of the resistor R17 is connected with a pin 2 of the capacitor C13, and the connection position is defined as VCC-/-15V; pin 1 of the capacitor C10, pin 1 of the capacitor C9, pin 1 of the capacitor C14 and pin 1 of the capacitor C13 are all connected with GND.
In a specific example, the ICU power interface J5 is a connector of 178323-3.
In a specific example, the current sensor interface U7 is a connector of model 178326-3.
In a specific example, the model of the voltage regulator chip U6 is MC7812BD.
In a specific example, the model of the voltage stabilization chip U8 is MC7906CD.
In a specific example, the model of the voltage regulation chip U11 is MC7912BD.
In a specific example, the model of the regulator chip U9 is MC7806BD.
In a specific example, the voltage detection interface J1 is a connector of model 178323-3.
The current detection circuit is used for simulating and detecting U-phase and V-phase current sampling values of the positive electrode and the negative electrode of the input end of the traction inverter and the output end of the traction inverter, so that the current sampling values of the positive electrode and the negative electrode of the input end are equal, the U-phase and V-phase current sampling values of the output end are the same in size and opposite in direction, and the switching frequencies of the currents are the same; the sampled current is sent to an inversion control unit;
wherein the current detection circuit includes: the three-phase full-bridge type three-phase power supply comprises a three-phase full-bridge analog circuit, a transformer circuit, a U-phase current conditioning circuit, a V-phase current conditioning circuit, a positive electrode current conditioning circuit and a negative electrode current conditioning circuit; wherein the content of the first and second substances,
referring to fig. 3a, the three-phase full-bridge analog circuit comprises: MOSFETs V10, V11, V12, V13, V14, V15 and capacitor C37; the 2 feet of the capacitor C37 are respectively connected with the source S of the source S, MOSFETV11 of the MOSFET V10 and the source S of the source S, MOSFETV of the MOSFET V10 and VCC +/+12V; a pin 1 of the capacitor C37 is respectively connected with a source S of the MOSFET V13, a source S of S, MOSFETV of the MOSFET V14 and VCC-/-12V; the drain electrode D of the drain electrode D, MOSFETV of the MOSFET V10 is connected with the pin 1 of the pulse transformer T1; the drain D of the drain D, MOSFETV14 of the MOSFET V11 is connected with the pin 1 of the pulse transformer T3; the drain D of the drain D, MOSFETV of the MOSFET V12 is connected with the pin 1 of the pulse transformer T2;
referring to fig. 3b, the transformer circuit comprises: pulse transformers T1, T2, T3, capacitors C33, C36, C39, and resistors R33, R38, R41; the pin 4 of the pulse transformer T1, the pin 4 of the pulse transformer T2 and the pin 4 of the pulse transformer T3 are connected; the pin 8 of the pulse transformer T1 is respectively connected with the pin 1 of the resistor R33 and the pin 1 of the capacitor C33, and then is connected with the pin 3 of the operational amplifier U12A; the pin 8 of the pulse transformer T2 is connected with the pin 1 of the resistor R38 and the pin 1 of the capacitor C36; a pin 8 of the pulse transformer T3 is respectively connected with a pin 1 of the resistor R41 and a pin 1 of the capacitor C39, and then is connected with a pin 3 of the operational amplifier U13A; a pin 5 of the pulse transformer T1, a pin 5 of the pulse transformer T2, a pin 5 of the pulse transformer T3, a pin 2 of the resistor R33, a pin 2 of the capacitor C33, a pin 2 of the resistor R38, a pin 2 of the capacitor C36, a pin 2 of the resistor R41 and a pin 2 of the capacitor C39 are all connected with GND;
referring to fig. 3c, the U-phase current conditioning circuit includes: an operational amplifier U12, triodes V6, V7, V8 and V9, a diode D6, capacitors C32, C34 and C35, and resistors R29, R30, R31, R32, R34, R35, R36 and R37; the operational amplifier U12 comprises an operational amplifier U12A and an operational amplifier U12B; a pin 2 of the operational amplifier U12A is respectively connected with a pin 2 of the resistor R35 and a pin 2 of the resistor R36; after the pin 1 of the resistor R35 is connected with the pin 1 of the resistor R29, the pin is connected with the emitter E of the triode V6 and the emitter E of the triode V7; a pin 1 of the operational amplifier U12A is respectively connected with a base B of the triode V6 and a base B of the triode V7; the pin 2 of the resistor R29, the pin 2 of the resistor R30, the pin 2 of the resistor R34 and the pin 2 of the capacitor C34 are connected; a pin 5 of the operational amplifier U12B is connected with a pin 1 of the resistor R30; a pin 6 of the operational amplifier U12B is respectively connected with a pin 2 of the resistor R37 and a pin 1 of the resistor R31, and then is connected with an emitter E of the triode V8 and an emitter E of the triode V9; the pin 7 of the operational amplifier U12B is respectively connected with the base B of the triode V8 and the base B of the triode V9; the pin 2 of the resistor R31, the pin 2 of the resistor R32 and the pin 2 of the diode D6 are connected; after connecting pin 1 of the resistor R32 and pin 1 of the diode D6, connecting the two pins with pin B2 of the current sensor interface U7; the pin 8 of the operational amplifier U12A, the pin 2 of the capacitor C32, the collector C of the triode V6 and the collector C of the triode V8 are all connected with VCC +/+12V; a pin 4 of the operational amplifier U12A, a pin 2 of the capacitor C35, a collector C of the triode V7 and a collector C of the triode V9 are all connected with VCC-/-12V; pin 1 of the capacitor C32, pin 1 of the capacitor C34, pin 1 of the capacitor C35, pin 1 of the resistor R34, pin 1 of the resistor R36 and pin 1 of the resistor R37 are all connected with GND;
referring to fig. 3d, the V-phase current conditioning circuit includes: an operational amplifier U13, triodes V16, V17, V18 and V19, a diode D7, capacitors C38, C40 and C41, and resistors R42, R43, R44, R45, R46, R50, R51 and R52; the operational amplifier U13 comprises an operational amplifier U13A and an operational amplifier U13B; a pin 2 of the operational amplifier U13A is respectively connected with a pin 2 of the resistor R50 and a pin 2 of the resistor R51; after the pin 1 of the resistor R50 is connected with the pin 1 of the resistor R42, the pin is connected with an emitter E of the triode V16 and an emitter E of the triode V17; a pin 1 of the operational amplifier U13A is respectively connected with a base B of the triode V16 and a base B of the triode V17; the pin 2 of the resistor R42, the pin 2 of the resistor R43, the pin 2 of the resistor R46 and the pin 2 of the capacitor C40 are connected; a pin 5 of the operational amplifier U13B is connected with a pin 1 of the resistor R43; the pin 6 of the operational amplifier U13B is respectively connected with the pin 2 of the resistor R52 and the pin 1 of the resistor R44, and then is connected with the emitter E of the triode V18 and the emitter E of the triode V19; the pin 7 of the operational amplifier U13B is respectively connected with the base B of the triode V18 and the base B of the triode V19; the pin 2 of the resistor R44, the pin 2 of the resistor R45 and the pin 2 of the diode D7 are connected; the resistor R45 is connected with a pin 1 of the diode D7 and then connected with a pin A2 of the current sensor interface U7; the pin 8 of the operational amplifier U13A, the pin 2 of the capacitor C38, the collector C of the triode V16 and the collector C of the triode V18 are all connected with VCC +/+12V; a pin 4 of the operational amplifier U13A, a pin 2 of the capacitor C41, a collector C of the triode V17 and a collector C of the triode V19 are all connected with VCC-/-12V; pin 1 of the capacitor C38, pin 1 of the capacitor C40, pin 1 of the capacitor C41, pin 1 of the resistor R46, pin 1 of the resistor R51 and pin 1 of the resistor R52 are all connected with GND;
referring to fig. 3e, the positive current conditioning circuit comprises: an operational amplifier U5, a triode V3, capacitors C12, C21 and C22 and resistors R15, R19 and R21; pin 2 of the resistor R15 is connected with pin 1 of the resistor R19; a pin 2 of the resistor R19 is connected with a pin 1 of the capacitor C21, and then is connected with a pin 3 of the operational amplifier U5; a pin 2 of the operational amplifier U5 is connected with a pin 1 of the resistor R21 and then connected with an emitter E of the triode V3; a pin 6 of the operational amplifier U5 is connected with a base B of the triode V3; pin 2 of the resistor R21 is connected with pin A5 of the current sensor interface U7; a pin 7 of the operational amplifier U5, a pin 1 of the capacitor C12, a pin 1 of the resistor R15 and a collector C of the triode V3 are all connected with VCC +/+12V; the pin 4 of the operational amplifier U5 and the pin 1 of the capacitor C22 are both connected with VCC-/-12V; the pin 2 of the capacitor C12, the pin 2 of the capacitor C21, the pin 2 of the capacitor C22 and the pin 3 of the resistor R19 are all connected with GND; wherein the resistor R19 is an adjustable resistor.
Referring to fig. 3f, the negative current conditioning circuit comprises: an operational amplifier U10, a triode V4, capacitors C23, C24 and C31 and resistors R24, R25 and R27; pin 1 of the resistor R27 is connected with pin 3 of the resistor R24; a pin 2 of the resistor R24 is connected with a pin 2 of the capacitor C24, and then is connected with a pin 3 of the operational amplifier U10; a pin 2 of the operational amplifier U10 is connected with a pin 1 of the resistor R25 and then connected with an emitter E of the triode V4; a pin 6 of the operational amplifier U10 is connected with a base electrode B of the triode V4; pin 2 of the resistor R25 is connected with pin B5 of the current sensor interface U7; the pin 7 of the operational amplifier U10 and the pin 1 of the capacitor C23 are both connected with VCC +/+12V; a pin 4 of the operational amplifier U10, a pin 1 of the capacitor C31, a pin 2 of the resistor R27 and a collector C of the triode V4 are all connected with VCC-/-12V; the pin 2 of the capacitor C23, the pin 2 of the capacitor C31, the pin 1 of the capacitor C24 and the pin 1 of the resistor R24 are all connected with GND; wherein the resistor R24 is an adjustable resistor.
In a specific example, the mosfets V11, V12, V13, V14, V15 and V16 are all NPN type, and the model is IRFZ34.
In a specific example, the operational amplifier U12 has a model number TL082ID; the triodes V6 and V8 are NPN triodes with the model number of BC817, and the triodes V7 and V9 are PNP triodes with the model number of BC807; and the U-phase current is amplified in two stages and then sent to an inversion control unit.
In a specific example, the model number of the operational amplifier U13 is TL082ID; the triodes V16 and V18 are NPN triodes, and the model is BC817; the triodes V17 and V19 are PNP triodes with the model number of BC807; and the V-phase current is amplified in two stages and then is sent to an inversion control unit.
In a specific example, the operational amplifier U5 is model TL081ID; the triode V3 is an NPN triode with the model number of BC817; the positive electrode current is amplified by a single stage and then sent to an inversion control unit.
In a specific example, the operational amplifier U10 is model TL081ID; the triode V4 is a PNP triode with the model number of BC807; the negative current is amplified by a single stage and then sent to an inversion control unit.
The voltage detection circuit is used for simulating and detecting a DC1500V voltage sampling value at the input end of the traction box and a bus voltage sampling value after the pre-charging contactor or the main contactor is closed after the high-speed circuit breaker is closed, and the sampled voltage is sent to the inversion control unit;
wherein the voltage detection circuit includes: a DC1500V voltage sampling circuit and a bus voltage sampling circuit;
referring to fig. 4a, the DC1500V voltage sampling circuit includes: the circuit comprises an operational amplifier U3, a triode V5, a switch S1, capacitors C3, C4 and C5 and resistors R5, R6 and R7; a pin 2 of the switch S1 is connected with VCC +/+24V; pin 1 of the switch S1 is connected with pin 1 of the resistor R5; after being connected with the pin 2 of the resistor R5, the pin 2 of the resistor R6 and the pin 2 of the capacitor C4, the resistor R is connected with the pin 3 of the operational amplifier U3; a pin 2 of the operational amplifier U3 and a pin 2 of the resistor R7 are connected with an emitter E of the triode V5 and then connected with a pin A1 of the voltage detection interface J1; a pin 6 of the operational amplifier U3 is connected with a base B of the triode V5; a pin 7 of the operational amplifier U3 and a pin 2 of the capacitor C3 are both connected with VCC +/+15V; the pin 4 of the operational amplifier U3 and the pin 2 of the capacitor C5 are both connected with VCC-/-15V; pin 1 of the capacitor C3, pin 1 of the capacitor C4, pin 1 of the capacitor C5, pin 1 of the resistor R6 and pin 1 of the resistor R7 are all connected with GND;
referring to fig. 4b, the bus voltage sampling circuit includes: an operational amplifier U4, triodes V1 and V2, a diode D2, capacitors C6, C7, C8 and C11, and resistors R8, R11, R12, R13 and R14; the operational amplifier U4 comprises an operational amplifier U4A and an operational amplifier U4B; after being connected with the pin 2 of the resistor R8, the pin 2 of the resistor R12 and the pin 2 of the capacitor C7, the three-pin-connected operational amplifier is connected with the pin 3 of the operational amplifier U4A; after the pin 2 of the operational amplifier U4A, the pin 2 of the resistor R11 and the pin 2 of the resistor R13 are connected, the operational amplifier U4A is connected with the emitter E of the triode V1; a pin 1 of the operational amplifier U4A is connected with a base B of the triode V1; pin 1 of the resistor R11 is connected with pin 1 of the diode D2; a pin 2 of the diode D2 is connected with a pin 2 of the capacitor C8 and then connected with a pin 5 of the operational amplifier U4B; a pin 6 of the operational amplifier U4B is respectively connected with a pin 2 of the resistor R14 and an emitter E of the triode V2, and then is connected with a pin B1 of the voltage detection interface J1; the pin 7 of the operational amplifier U4B is connected with the base B of the triode V2; a pin 8 of the operational amplifier U4A, a pin 2 of the capacitor C6, a collector C of the triode V1 and a collector C of the triode V2 are all connected with VCC +/+15V; the pin 4 of the operational amplifier U4A and the pin 2 of the capacitor C11 are both connected with VCC-/-15V; pin 1 of capacitor C6, pin 1 of capacitor C7, pin 1 of capacitor C8, pin 1 of capacitor C11, pin 1 of resistor R12, pin 1 of resistor R13 and pin 1 of resistor R14 are all connected with GND.
In a specific example, the operational amplifier U3 is model TL081ID; the triode V5 is an NPN triode with the model number BC817; the DC1500V voltage is sampled and amplified in a single stage and then sent to an inversion control unit.
In a specific example, the model U4 of the operational amplifier is TL082ID; the triodes V1 and V2 are NPN triodes, and the model is BC817; and the bus voltage is amplified in two stages by sampling and then sent to an inversion control unit.
Referring to fig. 5, the contactor detection circuit is used for simulating the action of a relay in a traction box; the inverter receives an action instruction sent by an inverter control unit and feeds back an action condition to the inverter control unit; simultaneously controlling the input of the voltage detection circuit and the indicator light loop;
wherein, the contactor detection circuit includes: the system comprises a bypass contactor loop, a fan contactor loop, a pre-charging contactor loop, a main contactor loop and an emergency braking simulation loop; wherein the content of the first and second substances,
the bypass contactor loop includes: the contactor comprises a contactor interface J2, a contactor K3, a diode D1, a light emitting diode DS4 and a resistor R23; the pin A3 of the contactor interface J2 is respectively connected with the pin 1 of the contactor K3 and the pin 1 of the diode D1; the A4 pin of the contactor interface J2 is respectively connected with the 13 pin and the 16 pin of the contactor K3 and the 2 pin of the diode D1; the 4 feet of the contactor K3 are connected with VCC +/+24V; the pin 9 of the contactor K3 is connected with the pin B3 of the contactor interface J2; the pin 8 of the contactor K3 is connected with the pin 2 of the resistor R23; pin 1 of the resistor R23 is connected with pin 1 of the light-emitting diode DS 4; pin 2 of the light emitting diode DS4 is connected with GND;
the fan contactor loop includes: the contactor comprises a contactor interface J2, a contactor K4, a diode D3, a light emitting diode DS6 and a resistor R28; the A5 pin of the contactor interface J2 is connected with the 1 pin of the contactor K4 and the 1 pin of the diode D3 respectively; the A6 pin of the contactor interface J2 is respectively connected with the 13 pin and the 16 pin of the contactor K4 and the 2 pin of the diode D3; the 4 pins of the contactor K4 are connected with VCC +/+24V; a pin 9 of the contactor K4 is connected with a pin B6 of the contactor interface J2; pin 8 of the contactor K4 is connected with pin 2 of the R28; pin 1 of the resistor R28 is connected with pin 1 of the light emitting diode DS 6; pin 2 of the light emitting diode DS6 is connected with GND;
the pre-charge contactor circuit includes: the contactor comprises a contactor interface J2, a contactor K2, a diode D4, a light emitting diode DS2 and a resistor R16; the pin A7 of the contactor interface J2 is respectively connected with the pin 1 of the contactor K2 and the pin 1 of the diode D4; the A8 pin of the contactor interface J2 is respectively connected with the 13 pin and the 16 pin of the contactor K2 and the 2 pin of the diode D4; the 4 pins of the contactor K2 are connected with VCC +/+24V; the pin 11 of the contactor K2 is connected with the pin B7 of the contactor interface J2; pin 9 of the contactor K2 is connected with pin 2 of the resistor R16; pin 1 of the resistor R16 is connected with pin 1 of the light emitting diode DS 2; pin 2 of the light emitting diode DS2 is connected with GND; after the pin 8 of the contactor K2 is connected with the pin 8 of the contactor K1, the pin is connected with the pin 1 of the resistor R8;
the main contactor circuit includes: the contactor comprises a contactor interface J2, a contactor K1, a diode D5, a light emitting diode DS1 and a resistor R10; a pin A9 of the contactor interface J2 is respectively connected with a pin 1 of the contactor K1 and a pin 1 of the diode D5; the A10 pin of the contactor interface J2 is respectively connected with the 13 pin and the 16 pin of the contactor K1 and the 2 pin of the diode D5; the 4 pins of the contactor K1 are connected with VCC +/+24V; the pin 11 of the contactor K1 is connected with the pin B9 of the contactor interface J2; a pin 9 of the contactor K1 is connected with a pin 2 of the resistor R10; pin 1 of the resistor R10 is connected with pin 1 of the light emitting diode DS 1; the pin 2 of the light-emitting diode DS1 is connected with GND;
the emergency braking simulation circuit comprises: a contactor interface J2 and a switch S2; the A2 pin of the contactor interface J2 is connected with the 1 pin of the switch S2; pin B1 of contactor interface J2 is connected to pin 2 of switch S2.
In a specific example, the type of the contactor interface J2 is 178328-3.
In a specific example, the types of the contactors K1, K2, K3 and K4 are G5V-2.
The optical fiber receiving circuit is used for receiving the three-phase full-bridge trigger pulse and the chopping trigger pulse generated by the inversion control unit and converting the level; the three-phase full-bridge trigger pulse is sent to the current detection circuit; the chopping trigger pulse is sent to the voltage detection circuit and used for simulating the action of the chopping loop;
wherein, the optical fiber receiving circuit includes: a main loop trigger pulse circuit and a chopping trigger pulse circuit; wherein the content of the first and second substances,
referring to fig. 6a, the main loop trigger pulse circuit includes: the optical fiber receivers U14, U15, U16, U17, U18 and U19, the triodes V20, V21 and V22, the capacitors C42, C43, C44, C45, C46 and C47, the resistors R53, R54, R55, R56, R57, R58, R59, R60, R61, R62, R63, R64, R65, R66, R67, R68, R69 and R70;
the 3 pins of the optical fiber receiver U14, the 1 pin of the capacitor C42 and the 1 pin of the resistor R53 are connected with VCC +/+12V; the pin 2 of the optical fiber receiver U14 and the pin 2 of the capacitor C42 are both connected with VCC +/+6V; pin 1 of the optical fiber receiver U14 is connected with pin 1 of the resistor R56 and pin 2 of the resistor R53 respectively; the pin 2 of the resistor R56 is connected with the grid G of the MOSFET V10;
a pin 3 of the optical fiber receiver U15, a pin 1 of the capacitor C43, a pin 1 of the resistor R54 and an emitter E of the triode V20 are all connected with VCC-/-6V; a pin 2 of the optical fiber receiver U15, a pin 2 of the capacitor C43 and a pin 2 of the resistor R58 are connected with VCC-/-12V; pin 1 of the optical fiber receiver U15 is connected with pin 1 of the resistor R57; after the pin 2 of the resistor R54 is connected with the pin 2 of the resistor R57, the base B of the triode V20 is connected; a collector C of the triode V20 is respectively connected with a pin 1 of the resistor R55 and a pin 1 of the resistor R58; pin 2 of the resistor R55 is connected with a grid G of the MOSFET V13;
the 3 pins of the optical fiber receiver U16, the 1 pin of the capacitor C44 and the 1 pin of the resistor R59 are all connected with VCC +/+12V; the pin 2 of the optical fiber receiver U16 and the pin 2 of the capacitor C44 are both connected with VCC +/+6V; pin 1 of the optical fiber receiver U16 is connected with pin 1 of the resistor R62 and pin 2 of the resistor R59 respectively; pin 2 of the resistor R62 is connected with the grid G of the MOSFET V11;
a pin 3 of the optical fiber receiver U17, a pin 1 of the capacitor C45, a pin 1 of the resistor R60 and an emitter E of the triode V21 are all connected with VCC-/-6V; the pin 2 of the optical fiber receiver U17, the pin 2 of the capacitor C45 and the pin 2 of the resistor R64 are all connected with VCC-/-12V; pin 1 of the optical fiber receiver U17 is connected with pin 1 of the resistor R63; after the pin 2 of the resistor R60 is connected with the pin 2 of the resistor R63, the base B of the triode V21 is connected; a collector C of the triode V21 is respectively connected with a pin 1 of the resistor R61 and a pin 1 of the resistor R64; pin 2 of the resistor R61 is connected with a grid G of the MOSFET V14;
the 3 pins of the optical fiber receiver U18, the 1 pin of the capacitor C47 and the 1 pin of the resistor R65 are all connected with VCC +/+12V; a pin 2 of the optical fiber receiver U18 and a pin 2 of the capacitor C47 are both connected with VCC +/+6V; pin 1 of the optical fiber receiver U18 is connected with pin 1 of the resistor R69 and pin 2 of the resistor R65 respectively; the pin 2 of the resistor R69 is connected with a grid G of the MOSFET V12;
a pin 3 of the optical fiber receiver U19, a pin 1 of the capacitor C46, a pin 1 of the resistor R66 and an emitter E of the triode V22 are all connected with VCC-/-6V; pin 2 of the optical fiber receiver U19, pin 2 of the capacitor C46 and pin 2 of the resistor R68 are all connected with VCC-/-12V; pin 1 of the optical fiber receiver U19 is connected with pin 1 of the resistor R70; after the pin 2 of the resistor R66 is connected with the pin 2 of the resistor R70, the base B of the triode V22 is connected; a collector C of the triode V22 is respectively connected with a pin 1 of the resistor R67 and a pin 1 of the resistor R68; a pin 2 of the resistor R67 is connected with a grid G of the MOSFET V15;
referring to fig. 6b, the chopping trigger pulse circuit includes: the optical fiber receiver comprises optical fiber receivers U1 and U2, triodes V23 and V24, capacitors C1 and C2, and resistors R1, R2, R3 and R4;
the 3 pins of the optical fiber receiver U1, the 1 pin of the capacitor C1 and the 1 pin of the resistor R1 are all connected with VCC +/+6V; the pin 2 of the optical fiber receiver U1, the pin 2 of the capacitor C1 and the emitter E of the triode V23 are all connected with GND; a pin 1 of the optical fiber receiver U1 is respectively connected with a pin 2 of the resistor R1 and a base B of the triode V23; a collector C of the triode V23 is connected with a pin 1 of the resistor R2; the pin 2 of the resistor R2 is connected with the pin 2 of the diode D2;
the 3 pins of the optical fiber receiver U2, the 1 pin of the capacitor C2 and the 1 pin of the resistor R3 are all connected with VCC +/+6V; a pin 2 of the optical fiber receiver U2, a pin 2 of the capacitor C2 and an emitter E of the triode V24 are all connected with GND; a pin 1 of the optical fiber receiver U2 is respectively connected with a pin 2 of the resistor R3 and a base B of the triode V24; a collector C of the triode V24 is connected with a pin 1 of the resistor R4; pin 2 of the resistor R4 is connected to pin 2 of the diode D2.
In a specific example, the optical fiber receivers U14, U15, U16, U17, U18, and U19 are of the type R-2532Z, and the triodes V20, V21, and V22 are PNP triodes of the type BC807.
In a specific example, the optical fiber receivers U1 and U2 are R-2532Z, and the triodes V23 and V24 are NPN triodes, and BC817.
The drive plate detection circuit is used for simulating a drive plate feedback circuit, judging whether the drive plate has a fault or not and providing +24V voltage for the drive plate;
as shown in fig. 7, the driving board detection circuit includes: a contactor interface J3, a switch S5, light emitting diodes DS7 and DS8 and resistors R39 and R40; wherein the content of the first and second substances,
pin B2 of the contactor interface J3 is connected with pin 1 of the switch S5; pin 2 of the switch S5 is connected with pin 2 of the resistor R39; a pin 1 of the resistor R39 is connected with ICU-VCC +/+24V; the pin A1 of the contactor interface J3 is connected with the pin 1 of the light emitting diode DS 7; pin 2 of the light-emitting diode DS7 is connected with pin 1 of the resistor R40; pin 2 of the resistor R40 is connected with pin A2 of the contactor interface J3; a pin A3 of the contactor interface J3 is connected with a pin 1 of a light-emitting diode DS 8; pin 2 of the light emitting diode DS8 is connected to GND.
In a specific example, the type of the contactor interface J3 is 178141-3.
And the temperature detection circuit is used for simulating the temperatures of a three-phase full bridge, a chopper loop and the environment in the inverter.
As shown in fig. 8, the temperature detection circuit includes: contactor interface J4 and PT100 resistors R47, R48, R49; wherein the content of the first and second substances,
the pin A1 of the contactor interface J4 is connected with the pin 2 of the resistor R47; pin 1 of the resistor R47 is connected with pin B1 of the contactor interface J4; pin A2 of the contactor interface J4 is connected with pin 2 of the resistor R48; pin 1 of the resistor R48 is connected with pin B2 of the contactor interface J4; pin A3 of the contactor interface J4 is connected with pin 2 of the resistor R49; pin 1 of resistor R49 is connected to pin B3 of contactor interface J4.
In a specific example, the type of the contactor interface J4 is 178323-3.
In the invention, an inversion control unit is correspondingly connected with the detection circuit of the invention through a connector, and the inversion control unit starts self-detection after receiving a self-detection instruction.
The power circuit provides power for the detection circuit and the inversion control unit, wherein +/-24V and +/-15V are generated in the inversion control unit and are supplied to the current detection circuit, the voltage detection circuit and the optical fiber receiving circuit; the inversion control unit controls a relay K2 in the contactor detection circuit to act, the pre-charging of the analog capacitor is carried out, a voltage sampling value obtained by the voltage detection circuit is sent to the inversion control unit through the connector, after the pre-charging is finished, the electric appliance K2 is switched off, and the relay K1 acts; the optical fiber receiving circuit receives the trigger pulse generated by the inversion control unit, carries out level conversion and then directly drives the MOSFET, and the inversion current is respectively sent to the U-phase and V-phase current detection circuits through the transformer and is sent to the inversion control unit through the connector after being conditioned; direct current positive and negative pole currents at the input end of the traction inverter are directly controlled by an adjustable resistor and are sent to an inversion control unit through a connector after being conditioned; the relays K3 and K4 respectively simulate a bypass and a fan loop, complete relay actions after receiving control instructions and simultaneously feed back the control instructions to the inversion control unit; the switch S2 simulates the emergency condition of the train, and the inversion control unit immediately stops the output of the traction box after the switch S is closed; s5 in the drive plate detection circuit is used for simulating a drive plate feedback circuit, an indicator lamp DS8 is on when the drive plate fails, and an indicator lamp DS7 detects whether a power supply of the drive plate is normal or not; and the temperature detection circuit is used for simulating the temperatures of a three-phase full bridge, a chopper loop and the environment in the inverter.
While the invention has been described in connection with what is presently considered to be the most practical and preferred embodiment, it is to be understood that the invention is not to be limited to the disclosed embodiment, but on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims (8)

1. The utility model provides a subway train contravariant control unit detection circuitry which characterized in that includes: the device comprises a power circuit, a current detection circuit, a voltage detection circuit, a contactor detection circuit, an optical fiber receiving circuit, a drive plate detection circuit and a temperature detection circuit;
the power circuit is used for carrying out classification control on the input +/-24V direct current, providing +/-24V voltage for the inversion control unit, the contactor detection circuit and the drive plate detection circuit, providing +/-12V and +/-6V voltage for the current detection circuit and the optical fiber receiving circuit, and providing +/-15V voltage for the voltage detection circuit;
the current detection circuit is used for simulating and detecting U-phase and V-phase current sampling values of the positive electrode and the negative electrode of the input end of the traction inverter and the output end of the traction inverter, so that the current sampling values of the positive electrode and the negative electrode of the input end are equal, the U-phase and V-phase current sampling values of the output end are the same in size and opposite in direction, and the switching frequencies of the currents are the same; the sampled current is sent to an inversion control unit;
the voltage detection circuit is used for simulating and detecting a DC1500V voltage sampling value at the input end of the traction box and a bus voltage sampling value after the pre-charging contactor or the main contactor is closed after the high-speed circuit breaker is closed, and the sampled voltage is sent to the inversion control unit;
the contactor detection circuit is used for simulating the action of a relay in the traction box; the inverter receives an action instruction sent by an inverter control unit and feeds back an action condition to the inverter control unit; simultaneously controlling the input of the voltage detection circuit and the indicator light loop;
the optical fiber receiving circuit is used for receiving the three-phase full-bridge trigger pulse and the chopping trigger pulse generated by the inversion control unit and carrying out level conversion; the three-phase full-bridge trigger pulse is sent to the current detection circuit; the chopping trigger pulse is sent to the voltage detection circuit and used for simulating the action of the chopping loop;
the drive plate detection circuit is used for simulating a drive plate feedback circuit, judging whether the drive plate has a fault or not and providing +24V voltage for the drive plate;
and the temperature detection circuit is used for simulating the temperatures of a three-phase full bridge, a chopper loop and the environment in the inverter.
2. The subway train inverter control unit detection circuit as claimed in claim 1, wherein said power circuit comprises: a +/-24V grading control circuit, a low-dropout linear voltage stabilizing circuit and a +/-15V voltage circuit;
the ± 24V hierarchical control circuit includes: a main power supply interface JP1, diodes D8 and D9, switches S3 and S4, relays K5 and K6, and an ICU power supply interface J5; pin 1 of the main power supply interface JP1 is connected with pin 1 of the switch S3 and pin 4 of the relay K5 respectively; pins 2 and 3 of the main power interface JP1 are connected and then respectively connected with pin 1 of the diode D8 and pin 16 of the relay K5 and connected with GND; the 4 pins of the main power interface JP1 are connected with the 13 pins of the relay K5; a pin 1 of the relay K5 is connected with a pin 2 of the switch S3; the 8 pin of the relay K5, the 1 pin of the switch S4 and the 4 pin of the relay K6 are connected, and the connection position is defined as VCC +/+24V; a pin 9 of the relay K5 is connected with a pin 13 of the relay K6, and the connection position is defined as VCC-/-24V; a pin 2 of the diode D9 is respectively connected with a pin 1 of the relay K6 and a pin 2 of the switch S4; the 8 pins of the relay K6 are respectively connected with the A1 pin and the B1 pin of the ICU power interface J5, and the connection position is defined as ICU-VCC +/+24V; a pin 9 of the relay K6 is respectively connected with a pin A2 and a pin B2 of an ICU power interface J5, and the connection position is defined as ICU-VCC-/-24V; a pin 1 of the diode D9, a pin 16 of the relay K6 and pins A3 and B3 of the ICU power interface J5 are connected with GND; the +/-24V power supply is transmitted to an inversion control unit through an ICU power interface J5;
the low dropout linear voltage regulator circuit comprises: the current sensor interface U7, the voltage stabilizing chips U6, U8, U9 and U11, the light emitting diodes DS3 and DS5, the capacitors C15, C16, C17, C18, C19, C20, C25, C26, C27, C28, C29 and C30 and the resistors R18, R20, R22 and R26; a pin A3 of the current sensor interface U7 is connected with a pin 1 of the resistor R18 and receives +24V voltage provided by the inversion control unit; a pin 2 of the resistor R18 is respectively connected with a pin 1 of the capacitor C19, a pin 1 of the capacitor C17 and a pin 1 of the voltage stabilizing chip U6; the pin 3 of the voltage stabilizing chip U6 is an output terminal, the output voltage is +12V, which is defined as VCC +/+12V, and is connected to the pin 1 of the capacitor C18, the pin 1 of the resistor R20, the pin 1 of the capacitor C15, the pin 1 of the capacitor C16, and the pin 1 of the voltage stabilizing chip U8, respectively; pin 2 of the resistor R20 is connected with pin 1 of the light-emitting diode DS 3; a pin 3 of the voltage stabilizing chip U8 is an output terminal, and the output voltage is +6V, which is defined as VCC +/+6V here, and is connected to a pin 2 of the capacitor C16; a pin B3 of the current sensor interface U7 is connected with a pin 1 of the resistor R26 and receives-24V voltage provided by the inversion control unit; the pin 2 of the resistor R26 is respectively connected with the pin 2 of the capacitor C27, the pin 2 of the capacitor C25 and the pin 2 of the voltage stabilizing chip U11; the pin 3 of the voltage stabilizing chip U11 is an output terminal, the output voltage is-12V, which is defined as VCC-/-12V, and is connected to the pin 2 of the capacitor C26, the pin 2 of the light emitting diode DS5, the pin 2 of the capacitor C28, the pin 2 of the capacitor C29, the pin 2 of the capacitor C30, and the pin 2 of the voltage stabilizing chip U9, respectively; pin 2 of the resistor R22 is connected with pin 1 of the light emitting diode DS 5; the pin 3 of the voltage stabilizing chip U9 is an output end, the output voltage is-6V, and VCC-/-6V is defined here, and is connected with the pin 1 of the capacitor C30; a pin 2 of a capacitor C19, a pin 2 of a capacitor C17, a pin 2 of a voltage stabilizing chip U6, a pin 2 of a capacitor C18, a pin 2 of a light emitting diode DS3, a pin 2 of a capacitor C20, a pin 2 of a capacitor C15, a pin 2 of a voltage stabilizing chip U8, a pin 1 of a capacitor C27, a pin 1 of a capacitor C25, a pin 1 of a voltage stabilizing chip U11, a pin 1 of a capacitor C26, a pin 1 of a resistor R22, a pin 1 of a capacitor C28, a pin 1 of a capacitor C29 and a pin 1 of a voltage stabilizing chip U9 are all connected with GND; a2 pin of a current sensor interface U7 outputs V-phase sampling current, A3 pin is connected with +24V and A5 pins output by an inversion control unit and outputs direct current positive sampling current, B2 pin outputs U-phase sampling current, B3 pin is connected with-24V and B5 pins output by the inversion control unit and outputs direct current negative sampling current;
the ± 15V voltage circuit includes: a voltage detection interface J1, capacitors C9, C10, C13 and C14 and resistors R9 and R17; a pin A2 of the voltage detection interface J1 is respectively connected with a pin 2 of the capacitor C10 and a pin 1 of the resistor R9; a pin 2 of the resistor R9 is connected with a pin 2 of the capacitor C9, and the connection position is defined as VCC +/+15V; a pin A3 of the voltage detection interface J1 is respectively connected with a pin 2 of the capacitor C14 and a pin 1 of the resistor R17; pin 2 of the resistor R17 is connected with pin 2 of the capacitor C13, and the connection position is defined as VCC-/-15V; pin 1 of the capacitor C10, pin 1 of the capacitor C9, pin 1 of the capacitor C14 and pin 1 of the capacitor C13 are all connected with GND.
3. The subway train inverter control unit detection circuit as claimed in claim 2, wherein said current detection circuit comprises: the three-phase full-bridge type three-phase power supply comprises a three-phase full-bridge analog circuit, a transformer circuit, a U-phase current conditioning circuit, a V-phase current conditioning circuit, a positive electrode current conditioning circuit and a negative electrode current conditioning circuit;
the three-phase full-bridge analog circuit comprises: MOSFETs V10, V11, V12, V13, V14, V15 and capacitor C37; the 2 feet of the capacitor C37 are respectively connected with a source S of a source S, MOSFETV of a source S, MOSFETV11 of the MOSFET V10 and VCC +/+12V; a pin 1 of the capacitor C37 is respectively connected with a source S of the MOSFET V13, a source S of S, MOSFETV of the MOSFET V14 and VCC-/-12V; after being connected with a drain D of a drain D, MOSFETV of the MOSFETV10, the drain D is connected with a pin 1 of the pulse transformer T1; the drain D of the drain D, MOSFETV14 of the MOSFET V11 is connected with the pin 1 of the pulse transformer T3; the drain D of the drain D, MOSFETV of the MOSFET V12 is connected with the pin 1 of the pulse transformer T2;
the transformer circuit includes: pulse transformers T1, T2, T3, capacitors C33, C36, C39, and resistors R33, R38, R41; the pin 4 of the pulse transformer T1, the pin 4 of the pulse transformer T2 and the pin 4 of the pulse transformer T3 are connected; the pin 8 of the pulse transformer T1 is respectively connected with the pin 1 of the resistor R33 and the pin 1 of the capacitor C33, and then is connected with the pin 3 of the operational amplifier U12A; the pin 8 of the pulse transformer T2 is connected with the pin 1 of the resistor R38 and the pin 1 of the capacitor C36; a pin 8 of the pulse transformer T3 is respectively connected with a pin 1 of the resistor R41 and a pin 1 of the capacitor C39, and then is connected with a pin 3 of the operational amplifier U13A; a pin 5 of the pulse transformer T1, a pin 5 of the pulse transformer T2, a pin 5 of the pulse transformer T3, a pin 2 of the resistor R33, a pin 2 of the capacitor C33, a pin 2 of the resistor R38, a pin 2 of the capacitor C36, a pin 2 of the resistor R41 and a pin 2 of the capacitor C39 are all connected with GND;
the U-phase current conditioning circuit comprises: an operational amplifier U12, triodes V6, V7, V8 and V9, a diode D6, capacitors C32, C34 and C35, and resistors R29, R30, R31, R32, R34, R35, R36 and R37; the operational amplifier U12 comprises an operational amplifier U12A and an operational amplifier U12B; a pin 2 of the operational amplifier U12A is respectively connected with a pin 2 of the resistor R35 and a pin 2 of the resistor R36; after the pin 1 of the resistor R35 is connected with the pin 1 of the resistor R29, the pin is connected with the emitter E of the triode V6 and the emitter E of the triode V7; a pin 1 of the operational amplifier U12A is respectively connected with a base B of the triode V6 and a base B of the triode V7; the pin 2 of the resistor R29, the pin 2 of the resistor R30, the pin 2 of the resistor R34 and the pin 2 of the capacitor C34 are connected; a pin 5 of the operational amplifier U12B is connected with a pin 1 of the resistor R30; a pin 6 of the operational amplifier U12B is respectively connected with a pin 2 of the resistor R37 and a pin 1 of the resistor R31, and then is connected with an emitter E of the triode V8 and an emitter E of the triode V9; a pin 7 of the operational amplifier U12B is respectively connected with a base B of the triode V8 and a base B of the triode V9; the pin 2 of the resistor R31, the pin 2 of the resistor R32 and the pin 2 of the diode D6 are connected; after connecting pin 1 of the resistor R32 and pin 1 of the diode D6, connecting the resistor R with pin B2 of the current sensor interface U7; the pin 8 of the operational amplifier U12A, the pin 2 of the capacitor C32, the collector C of the triode V6 and the collector C of the triode V8 are all connected with VCC +/+12V; a pin 4 of the operational amplifier U12A, a pin 2 of the capacitor C35, a collector C of the triode V7 and a collector C of the triode V9 are all connected with VCC-/-12V; pin 1 of the capacitor C32, pin 1 of the capacitor C34, pin 1 of the capacitor C35, pin 1 of the resistor R34, pin 1 of the resistor R36 and pin 1 of the resistor R37 are all connected with GND;
the V-phase current conditioning circuit includes: an operational amplifier U13, triodes V16, V17, V18 and V19, a diode D7, capacitors C38, C40 and C41, and resistors R42, R43, R44, R45, R46, R50, R51 and R52; the operational amplifier U13 comprises an operational amplifier U13A and an operational amplifier U13B; a pin 2 of the operational amplifier U13A is respectively connected with a pin 2 of the resistor R50 and a pin 2 of the resistor R51; after the pin 1 of the resistor R50 is connected with the pin 1 of the resistor R42, the pin is connected with an emitter E of the triode V16 and an emitter E of the triode V17; a pin 1 of the operational amplifier U13A is respectively connected with a base B of the triode V16 and a base B of the triode V17; the pin 2 of the resistor R42, the pin 2 of the resistor R43, the pin 2 of the resistor R46 and the pin 2 of the capacitor C40 are connected; a pin 5 of the operational amplifier U13B is connected with a pin 1 of the resistor R43; the pin 6 of the operational amplifier U13B is respectively connected with the pin 2 of the resistor R52 and the pin 1 of the resistor R44, and then is connected with the emitter E of the triode V18 and the emitter E of the triode V19; the pin 7 of the operational amplifier U13B is respectively connected with the base B of the triode V18 and the base B of the triode V19; the pin 2 of the resistor R44, the pin 2 of the resistor R45 and the pin 2 of the diode D7 are connected; the resistor R45 is connected with a pin 1 of the diode D7 and then connected with a pin A2 of the current sensor interface U7; the pin 8 of the operational amplifier U13A, the pin 2 of the capacitor C38, the collector C of the triode V16 and the collector C of the triode V18 are all connected with VCC +/+12V; a pin 4 of the operational amplifier U13A, a pin 2 of the capacitor C41, a collector C of the triode V17 and a collector C of the triode V19 are all connected with VCC-/-12V; pin 1 of the capacitor C38, pin 1 of the capacitor C40, pin 1 of the capacitor C41, pin 1 of the resistor R46, pin 1 of the resistor R51 and pin 1 of the resistor R52 are all connected with GND;
the positive electrode current conditioning circuit comprises: an operational amplifier U5, a triode V3, capacitors C12, C21 and C22 and resistors R15, R19 and R21; pin 2 of the resistor R15 is connected with pin 1 of the resistor R19; a pin 2 of the resistor R19 is connected with a pin 1 of the capacitor C21, and then is connected with a pin 3 of the operational amplifier U5; a pin 2 of the operational amplifier U5 is connected with a pin 1 of the resistor R21 and then connected with an emitter E of the triode V3; a pin 6 of the operational amplifier U5 is connected with a base B of the triode V3; pin 2 of the resistor R21 is connected with pin A5 of the current sensor interface U7; a pin 7 of the operational amplifier U5, a pin 1 of the capacitor C12, a pin 1 of the resistor R15 and a collector C of the triode V3 are all connected with VCC +/+12V; the pin 4 of the operational amplifier U5 and the pin 1 of the capacitor C22 are both connected with VCC-/-12V; the pin 2 of the capacitor C12, the pin 2 of the capacitor C21, the pin 2 of the capacitor C22 and the pin 3 of the resistor R19 are all connected with GND;
the negative current conditioning circuit comprises: an operational amplifier U10, a triode V4, capacitors C23, C24 and C31 and resistors R24, R25 and R27; pin 1 of the resistor R27 is connected with pin 3 of the resistor R24; a pin 2 of the resistor R24 is connected with a pin 2 of the capacitor C24, and then is connected with a pin 3 of the operational amplifier U10; a pin 2 of the operational amplifier U10 is connected with a pin 1 of the resistor R25 and then connected with an emitter E of the triode V4; a pin 6 of the operational amplifier U10 is connected with a base B of the triode V4; pin 2 of the resistor R25 is connected with pin B5 of the current sensor interface U7; the pin 7 of the operational amplifier U10 and the pin 1 of the capacitor C23 are both connected with VCC +/+12V; a pin 4 of the operational amplifier U10, a pin 1 of the capacitor C31, a pin 2 of the resistor R27 and a collector C of the triode V4 are all connected with VCC-/-12V; pin 2 of the capacitor C23, pin 2 of the capacitor C31, pin 1 of the capacitor C24 and pin 1 of the resistor R24 are all connected with GND.
4. The subway train inverter control unit detection circuit as claimed in claim 3, wherein said voltage detection circuit comprises: a DC1500V voltage sampling circuit and a bus voltage sampling circuit;
the DC1500V voltage sampling circuit comprises: the circuit comprises an operational amplifier U3, a triode V5, a switch S1, capacitors C3, C4 and C5 and resistors R5, R6 and R7; a pin 2 of the switch S1 is connected with VCC +/+24V; pin 1 of the switch S1 is connected with pin 1 of the resistor R5; after being connected with the pin 2 of the resistor R5, the pin 2 of the resistor R6 and the pin 2 of the capacitor C4, the resistor R is connected with the pin 3 of the operational amplifier U3; a pin 2 of the operational amplifier U3 and a pin 2 of the resistor R7 are connected with an emitter E of the triode V5 and then connected with a pin A1 of the voltage detection interface J1; a pin 6 of the operational amplifier U3 is connected with a base B of the triode V5; a pin 7 of the operational amplifier U3 and a pin 2 of the capacitor C3 are both connected with VCC +/+15V; the 4 pin of the operational amplifier U3 and the 2 pin of the capacitor C5 are both connected with VCC-/-15V; pin 1 of the capacitor C3, pin 1 of the capacitor C4, pin 1 of the capacitor C5, pin 1 of the resistor R6 and pin 1 of the resistor R7 are all connected with GND;
the bus voltage sampling circuit includes: an operational amplifier U4, triodes V1 and V2, a diode D2, capacitors C6, C7, C8 and C11, and resistors R8, R11, R12, R13 and R14; the operational amplifier U4 comprises an operational amplifier U4A and an operational amplifier U4B; after being connected with the pin 2 of the resistor R8, the pin 2 of the resistor R12 and the pin 2 of the capacitor C7, the three-pin-connected operational amplifier is connected with the pin 3 of the operational amplifier U4A; after the pin 2 of the operational amplifier U4A, the pin 2 of the resistor R11 and the pin 2 of the resistor R13 are connected, the operational amplifier U is connected with an emitter E of the triode V1; a pin 1 of the operational amplifier U4A is connected with a base B of the triode V1; pin 1 of the resistor R11 is connected with pin 1 of the diode D2; a pin 2 of the diode D2 is connected with a pin 2 of the capacitor C8, and then is connected with a pin 5 of the operational amplifier U4B; a pin 6 of the operational amplifier U4B is respectively connected with a pin 2 of the resistor R14 and an emitter E of the triode V2, and then is connected with a pin B1 of the voltage detection interface J1; the pin 7 of the operational amplifier U4B is connected with the base B of the triode V2; a pin 8 of the operational amplifier U4A, a pin 2 of the capacitor C6, a collector C of the triode V1 and a collector C of the triode V2 are all connected with VCC +/+15V; the 4 pin of the operational amplifier U4A and the 2 pin of the capacitor C11 are both connected with VCC-/-15V; pin 1 of capacitor C6, pin 1 of capacitor C7, pin 1 of capacitor C8, pin 1 of capacitor C11, pin 1 of resistor R12, pin 1 of resistor R13 and pin 1 of resistor R14 are all connected with GND.
5. The subway train inverter control unit detection circuit as claimed in claim 4, wherein said contactor detection circuit comprises: the system comprises a bypass contactor loop, a fan contactor loop, a pre-charging contactor loop, a main contactor loop and an emergency braking simulation loop;
the bypass contactor circuit includes: the contactor comprises a contactor interface J2, a contactor K3, a diode D1, a light emitting diode DS4 and a resistor R23; the pin A3 of the contactor interface J2 is connected with the pin 1 of the contactor K3 and the pin 1 of the diode D1 respectively; the A4 pin of the contactor interface J2 is respectively connected with the 13 pin and the 16 pin of the contactor K3 and the 2 pin of the diode D1; the 4 feet of the contactor K3 are connected with VCC +/+24V; a pin 9 of the contactor K3 is connected with a pin B3 of the contactor interface J2; the pin 8 of the contactor K3 is connected with the pin 2 of the resistor R23; pin 1 of the resistor R23 is connected with pin 1 of the light emitting diode DS 4; pin 2 of the light emitting diode DS4 is connected with GND;
the fan contactor loop includes: the contactor comprises a contactor interface J2, a contactor K4, a diode D3, a light emitting diode DS6 and a resistor R28; the A5 pin of the contactor interface J2 is connected with the 1 pin of the contactor K4 and the 1 pin of the diode D3 respectively; the A6 pin of the contactor interface J2 is respectively connected with the 13 pin and the 16 pin of the contactor K4 and the 2 pin of the diode D3; the 4 pins of the contactor K4 are connected with VCC +/+24V; a pin 9 of the contactor K4 is connected with a pin B6 of the contactor interface J2; the pin 8 of the contactor K4 is connected with the pin 2 of the R28; pin 1 of the resistor R28 is connected with pin 1 of the light emitting diode DS 6; pin 2 of the light emitting diode DS6 is connected with GND;
the pre-charge contactor circuit includes: the contactor comprises a contactor interface J2, a contactor K2, a diode D4, a light emitting diode DS2 and a resistor R16; the pin A7 of the contactor interface J2 is respectively connected with the pin 1 of the contactor K2 and the pin 1 of the diode D4; the A8 pin of the contactor interface J2 is respectively connected with the 13 pin and the 16 pin of the contactor K2 and the 2 pin of the diode D4; the 4 pins of the contactor K2 are connected with VCC +/+24V; the pin 11 of the contactor K2 is connected with the pin B7 of the contactor interface J2; pin 9 of the contactor K2 is connected with pin 2 of the resistor R16; pin 1 of the resistor R16 is connected with pin 1 of the light emitting diode DS 2; pin 2 of the light emitting diode DS2 is connected with GND; after the pin 8 of the contactor K2 is connected with the pin 8 of the contactor K1, the pin is connected with the pin 1 of the resistor R8;
the main contactor circuit includes: the contactor comprises a contactor interface J2, a contactor K1, a diode D5, a light emitting diode DS1 and a resistor R10; the A9 pin of the contactor interface J2 is respectively connected with the 1 pin of the contactor K1 and the 1 pin of the diode D5; the A10 pin of the contactor interface J2 is respectively connected with the 13 pin and the 16 pin of the contactor K1 and the 2 pin of the diode D5; the 4 pins of the contactor K1 are connected with VCC +/+24V; a pin 11 of the contactor K1 is connected with a pin B9 of a contactor interface J2; a pin 9 of the contactor K1 is connected with a pin 2 of the resistor R10; pin 1 of the resistor R10 is connected with pin 1 of the light emitting diode DS 1; the pin 2 of the light-emitting diode DS1 is connected with GND;
the emergency braking simulation circuit comprises: a contactor interface J2 and a switch S2; the A2 pin of the contactor interface J2 is connected with the 1 pin of the switch S2; pin B1 of contactor interface J2 is connected to pin 2 of switch S2.
6. The subway train inverter control unit detection circuit as claimed in claim 5, wherein said optical fiber receiving circuit comprises: a main loop trigger pulse circuit and a chopping trigger pulse circuit;
the main loop trigger pulse circuit includes: the optical fiber receivers U14, U15, U16, U17, U18 and U19, the triodes V20, V21 and V22, the capacitors C42, C43, C44, C45, C46 and C47, the resistors R53, R54, R55, R56, R57, R58, R59, R60, R61, R62, R63, R64, R65, R66, R67, R68, R69 and R70;
the 3 pins of the optical fiber receiver U14, the 1 pin of the capacitor C42 and the 1 pin of the resistor R53 are connected with VCC +/+12V; the pin 2 of the optical fiber receiver U14 and the pin 2 of the capacitor C42 are both connected with VCC +/+6V; pin 1 of the optical fiber receiver U14 is connected with pin 1 of the resistor R56 and pin 2 of the resistor R53 respectively; the pin 2 of the resistor R56 is connected with the grid G of the MOSFET V10;
a pin 3 of the optical fiber receiver U15, a pin 1 of the capacitor C43, a pin 1 of the resistor R54 and an emitter E of the triode V20 are all connected with VCC-/-6V; the pin 2 of the optical fiber receiver U15, the pin 2 of the capacitor C43 and the pin 2 of the resistor R58 are all connected with VCC-/-12V; pin 1 of the optical fiber receiver U15 is connected with pin 1 of the resistor R57; pin 2 of the resistor R54 is connected with pin 2 of the resistor R57, and then is connected with the base B of the triode V20; a collector C of the triode V20 is respectively connected with a pin 1 of the resistor R55 and a pin 1 of the resistor R58; pin 2 of the resistor R55 is connected with a grid G of the MOSFET V13;
the 3 pins of the optical fiber receiver U16, the 1 pin of the capacitor C44 and the 1 pin of the resistor R59 are all connected with VCC +/+12V; the pin 2 of the optical fiber receiver U16 and the pin 2 of the capacitor C44 are both connected with VCC +/+6V; pin 1 of the optical fiber receiver U16 is connected with pin 1 of the resistor R62 and pin 2 of the resistor R59 respectively; pin 2 of the resistor R62 is connected with the grid G of the MOSFET V11;
a pin 3 of the optical fiber receiver U17, a pin 1 of the capacitor C45, a pin 1 of the resistor R60 and an emitter E of the triode V21 are all connected with VCC-/-6V; the pin 2 of the optical fiber receiver U17, the pin 2 of the capacitor C45 and the pin 2 of the resistor R64 are all connected with VCC-/-12V; pin 1 of the optical fiber receiver U17 is connected with pin 1 of the resistor R63; after the pin 2 of the resistor R60 is connected with the pin 2 of the resistor R63, the base B of the triode V21 is connected; a collector C of the triode V21 is respectively connected with a pin 1 of the resistor R61 and a pin 1 of the resistor R64; pin 2 of the resistor R61 is connected with a grid G of the MOSFET V14;
the 3 pins of the optical fiber receiver U18, the 1 pin of the capacitor C47 and the 1 pin of the resistor R65 are all connected with VCC +/+12V; the pin 2 of the optical fiber receiver U18 and the pin 2 of the capacitor C47 are both connected with VCC +/+6V; pin 1 of the optical fiber receiver U18 is connected with pin 1 of the resistor R69 and pin 2 of the resistor R65 respectively; the pin 2 of the resistor R69 is connected with a grid G of the MOSFET V12;
a pin 3 of the optical fiber receiver U19, a pin 1 of the capacitor C46, a pin 1 of the resistor R66 and an emitter E of the triode V22 are all connected with VCC-/-6V; pin 2 of the optical fiber receiver U19, pin 2 of the capacitor C46 and pin 2 of the resistor R68 are all connected with VCC-/-12V; pin 1 of the optical fiber receiver U19 is connected with pin 1 of the resistor R70; after the pin 2 of the resistor R66 is connected with the pin 2 of the resistor R70, the base B of the triode V22 is connected; a collector C of the triode V22 is respectively connected with a pin 1 of the resistor R67 and a pin 1 of the resistor R68; a pin 2 of the resistor R67 is connected with a grid G of the MOSFET V15;
the chopping trigger pulse circuit comprises: the optical fiber receiver comprises optical fiber receivers U1 and U2, triodes V23 and V24, capacitors C1 and C2, and resistors R1, R2, R3 and R4;
the 3 pins of the optical fiber receiver U1, the 1 pin of the capacitor C1 and the 1 pin of the resistor R1 are all connected with VCC +/+6V; the pin 2 of the optical fiber receiver U1, the pin 2 of the capacitor C1 and the emitter E of the triode V23 are all connected with GND; a pin 1 of the optical fiber receiver U1 is respectively connected with a pin 2 of the resistor R1 and a base B of the triode V23; a collector C of the triode V23 is connected with a pin 1 of the resistor R2; a pin 2 of the resistor R2 is connected with a pin 5 of the operational amplifier U4B;
the 3 pins of the optical fiber receiver U2, the 1 pin of the capacitor C2 and the 1 pin of the resistor R3 are all connected with VCC +/+6V; a pin 2 of the optical fiber receiver U2, a pin 2 of the capacitor C2 and an emitter E of the triode V24 are all connected with GND; a pin 1 of the optical fiber receiver U2 is respectively connected with a pin 2 of the resistor R3 and a base B of the triode V24; a collector C of the triode V24 is connected with a pin 1 of the resistor R4; and a pin 2 of the resistor R4 is connected with a pin 5 of the operational amplifier U4B.
7. The subway train inverter control unit detection circuit as claimed in claim 6, wherein said drive board detection circuit comprises: a contactor interface J3, a switch S5, light emitting diodes DS7 and DS8 and resistors R39 and R40;
pin B2 of the contactor interface J3 is connected with pin 1 of the switch S5; pin 2 of the switch S5 is connected with pin 2 of the resistor R39; a pin 1 of the resistor R39 is connected with ICU-VCC +/+24V; the pin A1 of the contactor interface J3 is connected with the pin 1 of the light emitting diode DS 7; pin 2 of the light-emitting diode DS7 is connected with pin 1 of the resistor R40; pin 2 of the resistor R40 is connected with pin A2 of the contactor interface J3; the pin A3 of the contactor interface J3 is connected with the pin 1 of the light-emitting diode DS 8; pin 2 of the light emitting diode DS8 is connected to GND.
8. The subway train inverter control unit detection circuit as claimed in claim 7, wherein said temperature detection circuit comprises: contactor interface J4 and PT100 resistors R47, R48, R49;
a pin A1 of the contactor interface J4 is connected with a pin 2 of the resistor R47; pin 1 of the resistor R47 is connected with pin B1 of the contactor interface J4; pin A2 of the contactor interface J4 is connected with pin 2 of the resistor R48; pin 1 of the resistor R48 is connected with pin B2 of the contactor interface J4; pin A3 of the contactor interface J4 is connected with pin 2 of the resistor R49; pin 1 of resistor R49 is connected to pin B3 of contactor interface J4.
CN202211031024.4A 2022-08-26 2022-08-26 Subway train inversion control unit detection circuit Active CN115407149B (en)

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CN107422278A (en) * 2017-07-17 2017-12-01 南京轨道交通系统工程有限公司 Subway train traction invertor high pressure belt load testing platform
CN112526264A (en) * 2020-11-26 2021-03-19 苏州市万松电气有限公司 Single-phase inverter detection system
CN112731190A (en) * 2020-12-04 2021-04-30 南京轨道交通系统工程有限公司 Universal tester and method applied to subway train inverter module

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103683313A (en) * 2012-09-13 2014-03-26 武汉金天新能源科技有限公司 Photovoltaic inverter employing hybrid type power device
CN103929102A (en) * 2013-04-17 2014-07-16 济南田中工贸有限公司 Variable-frequency input inversion type direct-current motor driving controller
CN103956952A (en) * 2013-04-17 2014-07-30 济南田中工贸有限公司 Vector frequency conversion controller of synchronization frequency conversion type alternating current motor
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