CN115398543A

CN115398543A - Programming dual ended memory devices and erasing method and apparatus

Info

Publication number: CN115398543A
Application number: CN202180006564.4A
Authority: CN
Inventors: H·纳扎里安; 桑·阮
Original assignee: Xinyuan Semiconductor Shanghai Co ltd
Current assignee: Xinyuan Semiconductor Shanghai Co ltd
Priority date: 2021-03-19
Filing date: 2021-03-19
Publication date: 2022-11-25
Also published as: WO2022197307A1

Abstract

A method of performing an erase or program operation on dual-ended memory devices includes initiating an erase cycle or program cycle of the dual-ended memory devices of a first plurality of dual-ended memory devices at substantially the same time, monitoring an erase detect or program detect condition of each of the dual-ended memory devices, and prior to detecting the erase detect or program detect condition of all of the dual-ended memory devices, the method includes detecting an erase detect or program detect condition of a first dual-ended memory device of the first plurality of dual-ended memory devices, and initiating an erase cycle or program of a second dual-ended memory device of a second plurality of dual-ended memory devices in response to detecting the erase detect or program detect condition of the first dual-ended memory device.

Description

Method and apparatus for programming and erasing dual-ended memory devices

Technical Field

Embodiments of the present disclosure relate to dual ended memory devices and methods. For example, embodiments relate to methods and apparatus for bulk program or erase operations for resistive random access memory devices in dual ended memory devices.

Background

Resistive switching memories represent a recent innovation in the field of integrated circuit technology. While most resistive switching memory technologies are in a development phase, the inventors have addressed various technical concepts of resistive switching memories, and these technical concepts are in one or more verification phases to prove or disprove the relevant theory or technique. The inventors believe that the resistance-switching memory technology shows convincing evidence that it has substantial advantages over competing technologies in the semiconductor electronics industry.

The inventors believe that a resistance-switching memory cell can be configured to include multiple states having different resistance values that can be measured. For example, for a single bit cell, a resistance-switching memory cell may be configured to exist in a relatively low resistance state or to exist in a relatively high resistance state. The multi-bit cells may have other states of resistance that are different from each other and from the relatively low resistance state and the relatively high resistance state. The different resistance states of the resistance-switching memory cell can be associated with logical information states to perform a digital memory operation. Thus, the inventors believe that many such arrays of memory cells can provide digital memory storage of many bits.

The inventors have successfully put the resistance-switching memory into one or the other resistance state in response to external conditions. Thus, with transistors, applying or removing external conditions can be used to program or de-program (e.g., erase) the memory. Further, depending on the physical make-up and electrical arrangement, a resistance-switching memory cell can typically remain programmed or unprogrammed. Depending on the characteristics of the memory cell device, maintaining the state may require other conditions to be met (e.g., there is a minimum operating voltage, there is a minimum operating temperature, etc.), or the conditions are not met.

The inventors have proposed some solutions to the practical application of resistance switching techniques to memory applications of electronic devices. For example, resistive switching elements are generally considered in theory as viable alternatives to, at least in part, metal Oxide Semiconductor (MOS) type memory transistors for electronically storing digital information. The model of resistance-switching memory devices offers some potential technical advantages over non-volatile FLASH MOS type transistors.

In view of the foregoing, the assignee of the present disclosure is directed to continued development of practical applications of resistance switching techniques.

Disclosure of Invention

The following presents a simplified summary of the disclosure in order to provide a basic understanding of some aspects described herein. This summary is not an extensive overview of the disclosure. It is neither intended to identify key or critical elements of the disclosure nor to delineate the scope of the invention. Its sole purpose is to present some concepts of the disclosure in a simplified form as a prelude to the more detailed description that is presented later.

Some embodiments relate to filament-based resistive random access (ReRAM) devices being developed by the assignee. Other embodiments may also be applied to other types of two-terminal devices, such as oxygen-vacancy memories, phase-change memories, magnetic memories, etc. In various embodiments, the erased state is associated with the high resistance state and the programmed state is associated with the low resistance state by convention, although other conventions are also within the scope of the present disclosure. When a read voltage or current is applied to the ReRAM device, the erased state of the ReRAM device is determined with a small current detected (e.g., relative to a preset threshold), and the programmed state of the ReRAM is determined with a large current detected (e.g., also relative to a threshold).

According to one aspect, a method of performing an erase or program operation on a dual-ended memory device is described. A technique includes initiating an erase cycle or a program cycle of dual-ended memory devices of a first batch of dual-ended memory devices substantially simultaneously, and monitoring an erase detect or program detect condition of each dual-ended memory device. In various embodiments, substantially simultaneous in connection with electronic memory operations may be defined as, for example, the simultaneous application of power signals, the initiation of power signals during the same clock cycle or during adjacent clock cycles of controlling current or voltage circuits to effect memory operations on a two-terminal memory device, and the like. One process includes, prior to detecting an erase detect or program detect condition for all dual-ended memory devices: detecting an erase detection or program detection condition of a first dual-ended memory device of the first plurality of dual-ended memory devices, and initiating an erase cycle or programming of a second dual-ended memory device of the second plurality of dual-ended memory devices in response to detecting the erase detection or program detection condition of the first dual-ended memory device.

According to another aspect, a semiconductor device is described. An apparatus includes a first batch of dual-ended storage devices and a second batch of dual-ended storage devices. A system may include: a state adjustment enabling portion connected to the first plurality of two-terminal memory devices and the second plurality of two-terminal memory devices, wherein the state adjustment enabling portion is configured to substantially enable each of the two-terminal memory devices in the first plurality of two-terminal memory devices to enter a predetermined state, wherein the predetermined state is selected from the group consisting of an erased state and a programmed state; and a detection section connected to the first plurality of dual-ended storage devices and the status adjustment enabling section, wherein the detection section is configured to simultaneously detect whether an adjustment success condition occurs for each of the dual-ended storage devices in the first plurality of dual-ended storage devices. In various embodiments, the state adjustment enabling portion is further configured to enable the first dual-ended storage devices of the second batch of dual-ended storage devices to enter the predetermined state in response to detecting that the adjustment success condition occurs for the second dual-ended storage devices of the first batch of dual-ended storage devices and prior to detecting the adjustment success conditions for all dual-ended storage devices of the first batch of dual-ended storage devices.

The following description and the annexed drawings set forth certain illustrative aspects of the specification. These aspects are indicative, however, of but a few of the various ways in which the principles of the specification may be employed. Other advantages and novel features of the specification will become apparent from the following detailed description of the specification when considered in conjunction with the drawings.

Drawings

Many aspects, embodiments, objects, and advantages of the present invention will become apparent from the following detailed description when considered in conjunction with the accompanying drawings in which like reference characters refer to like parts throughout. In this specification, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. However, it is understood that certain aspects of the disclosure may be practiced without these specific details or with other methods, components, materials, etc. In other instances, well-known structures and devices are shown in block diagram form in order to facilitate describing the present disclosure;

FIG. 1 illustrates an example circuit diagram of an array of two-terminal memory devices used to implement aspects of the present disclosure in an embodiment;

FIG. 2 depicts an example block diagram of a memory operation circuit for operating a block of memory cells in accordance with a further embodiment;

FIG. 3 illustrates a block diagram of storage operation drivers operating asynchronously with respect to other drivers in an embodiment;

FIG. 4 depicts a diagram of possible programming cycles of an asynchronous driver operating on a dual ended block of memory cells in a further embodiment;

FIG. 5 shows a timing diagram of signals for a plurality of two-terminal memory cells that contribute to improved operating time in other embodiments;

FIG. 6 depicts a schematic diagram of an example multiplexer used to connect operational drivers to different subsets of memory blocks in one or more embodiments;

FIG. 7 illustrates a flow chart of an example method for programming or erasing a block of memory cells in accordance with a disclosed embodiment;

FIG. 8 illustrates a flow diagram of an example method for implementing storage operations on a dual-ended storage device in accordance with further embodiments;

FIG. 9 illustrates a block diagram of an example electronic operating environment, in accordance with certain embodiments presented herein;

FIG. 10 depicts a block diagram of an example computing environment for implementing one or more disclosed embodiments of the present disclosure.

Detailed Description

As the name implies, a two-terminal memory device has two terminals or electrodes. Here, the terms "electrode" and "terminal" may be used interchangeably. Typically, the first electrode of a two-terminal memory is referred to as a "top electrode" (TE) and the second electrode of the two-terminal memory is referred to as a "bottom electrode" (BE), but it should BE understood that the electrodes of the two-terminal memory device may BE arranged according to any suitable arrangement, including horizontally with the components of the memory cells (substantially) side-by-side rather than overlapping each other. Located between the TE and BE of a two-terminal memory device is typically an interface layer, sometimes also referred to as a switching layer, a resistance-switching medium (RSM), or a resistance-switching layer (RSL). When incorporated into RSM, a two-terminal memory device may be referred to as a (two-terminal) resistance-switching device. Embodiments of the present disclosure provide a two-terminal resistance-switching device connected to multiple components at one of two terminals, forming a three-terminal non-volatile memory cell.

In general, the composition of a memory cell may vary from device to device with different components selected to achieve desired characteristics (e.g., volatile/non-volatile, on/off current ratio, switching time, read time, memory endurance, program/erase cycles, etc.). One example of a filament-based device may include: a conductive layer, such as a metal, metal alloy, metal nitride (e.g., including TiN, taN, tiW, or other suitable metal compound); an optional interfacial layer (e.g., a doped p-type (or n-type) silicon (Si) bearing layer (e.g., p-type or n-type Si bearing layer, p-type or n-type polysilicon, p-type or n-type poly SiGe, etc.)); a resistance-switching layer (RSL) and an active metal-containing layer capable of being ionized. Under appropriate conditions, the active metal-containing layer can provide the RSL with filament-forming ions. In these embodiments, the conductive filament (e.g., formed of ions) may be electrically conductive through at least a subset of the RSLs, and the resistance of the filament-based device may be determined, for example, by a tunneling resistance between the filament and the conductive layer. A memory cell having this characteristic can be described as a filament-based device.

The RSL, which may also be referred to in the art as a Resistance Switching Medium (RSM), may include, for example, an undoped amorphous Si-containing layer, a semiconductor layer having intrinsic properties, silicon nitride (e.g., siN, si) ₃ N ₄ 、SiN _x Etc.), a sub-oxide of Si (e.g., siO _x Where x has a value between 0.1 and 2), a silicon nitride, a metal oxide, a metal nitride, a non-stoichiometricSilicon compounds in amounts, and the like. Other examples of materials suitable for RSL may include Si _x Ge _y O _z (where x, y and z are each suitably positive numbers), silicon oxide (e.g., siO _N Where N is a suitable positive number), silicon oxynitride, undoped amorphous Si (a-Si), amorphous SiGe (a-SiGe), taO _B (where B is a suitable positive number), hfO _C (wherein C is a suitable positive number), tiO _D (wherein D is an appropriate number), al ₂ O _E (where E is a suitable positive number), etc., nitrides (e.g., alN, siN), or suitable combinations thereof.

In some embodiments, an RSL used as part of a non-volatile memory device (non-volatile RSL) may include a relatively large number (e.g., compared to volatile selector devices) of material voids or defects to trap neutral metal particles (at least at low voltages) within the RSL. A large number of voids or defects may facilitate the formation of a stable structure of thick, neutral metal particles. In such a configuration, these trapped particles may hold the non-volatile memory device in a low resistance state in the absence of an external stimulus (e.g., a power source), thereby enabling non-volatile operation. In other embodiments, the RSL employed by the volatile selector device (volatile RSL) may have very few material voids or defects. The conductive filaments formed in such RSLs can be very thin due to few voids/defects of the trapped particles and are unstable without a suitably high external stimulus (e.g., electric field, voltage, current, joule heat, or a suitable combination thereof). Furthermore, particles with high surface energy and good diffusivity within the RSL can be selected. This results in conductive filaments that can be formed quickly in response to a suitable stimulus, but also easily deformed, for example in response to an external stimulus falling below the deformation level. Note that the volatile RSL and the conductive filament for the selector device may have different electrical characteristics from the conductive filament and the nonvolatile RSL for the nonvolatile memory device. For example, the selector means RSL may have a higher material resistance and may have a higher on/off current ratio, etc.

Active metal-containing layers for filament-based memory cellsTo include: silver (Ag), gold (Au), titanium (Ti), titanium nitride (TiN) or other suitable titanium compounds, nickel (Ni), copper (Cu), aluminum (Al), chromium (Cr), tantalum (Ta), iron (Fe), manganese (Mn), tungsten (W), vanadium (V), cobalt (Co), platinum (Pt), hafnium (Hf), and palladium (Pd). In some aspects of the present disclosure, other suitable conductive materials as well as compounds, nitrides, oxides, alloys, or combinations of the foregoing or similar materials may be used for the active-containing metal layer. Further, in at least one embodiment, the active metal-containing layer can employ a non-stoichiometric compound, such as a non-stoichiometric metal oxide or metal nitride (e.g., alO) _x 、AlN _x 、CuO _x 、CuN _x 、AgO _x 、AgN _x Etc., where x is a suitably positive number 0<x<2, may have different values for different non-stoichiometric compounds) or other suitable metal compounds.

In one or more embodiments, the disclosed filament resistance-switching device may include an active metal layer comprising a metal selected from the group consisting of TiN _x 、TaN _x 、AlN _x 、CuN _x 、WN _x And AgN _x A metal nitride of the group, wherein x is a positive number. In a further embodiment, the active metal layer may include a material selected from the group consisting of TiO _x 、TaO _x 、AlO _x 、CuO _x 、WO _x And AgO _x A metal oxide of the group. In yet another or more embodiments, the active metal layer may include a material selected from the group consisting of TiO _a N _b 、AlO _a N _b 、CuO _a N _b 、WO _a N _b And AgO _a N _b A metal oxynitride of the group consisting of wherein a and b are positive numbers. The disclosed filament resistance-switching device may further include a switching layer comprising a switching material selected from the group consisting of: siO 2 _y 、AlN _y 、TiO _y 、TaO _y 、AlO _y 、CuO _y 、TiN _x 、TiN _y 、TaN _x 、TaN _y 、SiO _x 、SiN _y 、AlN _x 、CuN _x 、CuN _y 、AgN _x 、AgN _y 、TiO _x 、TaO _x 、AlO _x 、CuO _x 、AgO _x And AgO _y Wherein x and y are positive numbers, and y is greater than x. Various combinations of the above are contemplated and considered within the scope of embodiments of the present invention.

In one example, a filament resistivity-switching device is disclosed that includes a particle donor layer (e.g., an active metal-containing layer) that includes a metal compound and a resistivity-switching layer. In an alternative embodiment of this example, the particle donor layer comprises a metal nitride: MN (Mobile node) _x E.g. AgN _x 、TiN _x 、AlN _x And the resistivity-switching layer includes a metal nitride: MN (Mobile node) _y E.g. AgO _y 、TiO _y 、AlO _y Etc., where y and x are positive numbers, and in some cases y is greater than x. In an alternative embodiment of this example, the particle donor layer comprises a metal oxide: MO (metal oxide semiconductor) _x E.g. AgO _x 、TiO _x 、AlO _x And the like, the resistivity-switching layer includes a metal oxide: MO (metal oxide semiconductor) _y E.g. AgO _y 、TiO _y 、AlO _y Etc., where y and x are positive numbers, and in some cases y is greater than x. In yet another alternative embodiment, the metal compound of the particle donor layer is MN _x (e.g., agN) _x 、TiN _x 、AlN _x Etc.) and the resistivity-switching layer is selected from the group consisting of MO _y (e.g., agO) _y 、TiO _y 、AlO _y ) Etc.) and SiO _y Groups wherein x and y are generally non-stoichiometric values, or vice versa in yet another embodiment.

As used herein, variables x, a, b, etc., representing values or ratios of one element relative to another (or other) element in a compound can have different values applicable to the respective compounds, and are not intended to represent the same or similar values or ratios between compounds. Some details regarding embodiments of the present disclosure similar to the examples described above may be found in the following U.S. patent applications, which are assigned to the assignee of the present patent application: application No. 11/875,541 filed on 10/19/2007 and application No. 12/575,921 filed on 10/8/2009, and application No. 14/588,185 filed on 12/31/2014, assigned to the assignee of the present patent application. Each of the foregoing patent applications is individually incorporated by reference in its entirety and herein for all purposes.

It should be understood that various embodiments herein may utilize various memory cell technologies having different physical characteristics. For example, different resistance-switching memory cell technologies may have different discrete programmable resistances, different associated program/erase voltages, and other differentiating characteristics. For example, embodiments of the present disclosure may employ a bipolar switching device that exhibits a first switching response (e.g., programming to one of a set of program states) to an electrical signal of a first polarity and a second switching response (e.g., erasing to an erased state) to an electrical signal of a second polarity. A bipolar switching device, for example, is in contrast to a unipolar device that exhibits both a first switching response (e.g., programming) and a second switching response (e.g., erasing) in response to electrical signals having the same polarity and different magnitudes.

In various embodiments, the filament-based resistance-switching device may operate in a bipolar manner, behaving differently in response to external stimuli of different polarity (or direction, energy flow, energy source orientation, etc.). As an illustrative example, for a volatile filament-based selector device, in response to a first polarity stimulus exceeding a first threshold voltage (or set of voltages), the filament selector device may change from a first resistance state to a second resistance state. Further, the filament selector device may change from the first state to a third state in response to a second polarity excitation exceeding a second threshold voltage. In some embodiments, the third state may be substantially the same as the first state, have the same or similar measurable intrinsic properties (e.g., conductivity, etc.), have the same or similar threshold excitation amplitude (albeit of opposite polarity or direction), and so on. In other embodiments, the third state may differ from the second state in measurable characteristics (e.g., a conductivity value responsive to a reverse polarity as compared to a forward polarity) or in a threshold stimulus associated with switching out of the first state (e.g., a magnitude of a positive voltage required to switch to the second state as compared to a magnitude of a negative voltage required to switch to the third state).

For bipolar operation of the non-volatile filament-based memory cell, a conductive path or filament is formed through the non-volatile RSL in response to application of a suitable programming voltage to the memory cell. In particular, upon application of a programming voltage, metal ions are generated from the active metal-containing layer and migrate into the non-volatile RSL layer. The metal ions may occupy voids or defect sites within the non-volatile RSL layer. In some embodiments, after removing the bias voltage, the metal ions become neutral metal particles and remain trapped in voids or defects of the non-volatile RSL layer. When enough particles are trapped, a filament is formed and the memory cell switches from a relatively high resistance state to a relatively low resistance state. More specifically, the trapped metal particles provide a conductive path or filament through the non-volatile RSL layer, and the resistance is typically determined by the tunneling resistance through the non-volatile RSL layer. In some resistance-switching devices, an erase process may be performed to at least partially deform the conductive filament to return the memory cell from a low-resistance state to a high-resistance state. More specifically, upon application of an erase bias voltage, metal particles trapped in voids or defects of the non-volatile RSL become mobile ions and migrate back towards the active metal layer. In the context of memory, such state changes may be associated with various states of the binary bit. For an array of multiple memory cells, a word, byte, page, block, etc. of memory cells may be programmed or erased to represent a zero or one of the binary information, and the binary information is stored by effectively retaining these states for a period of time. In various embodiments, multiple levels of information (e.g., multiple bits) may be stored in such a memory cell.

It will be understood by those of ordinary skill in the art or by the background provided herein that when the various aspects and embodiments herein do not specify a particular memory cell technology or program/erase voltage, it is intended that these aspects and embodiments incorporate any suitable memory cell technology and be adapted for program/erase voltage operation of the memory cell technology. It should be further understood that embodiments including alternative memory cell technologies or signal level variations are considered within the scope of the present disclosure when circuit modifications known to those of ordinary skill in the art or changes to the operating signal level known to those of ordinary skill in the art are required to replace different memory cell technologies.

As described above, application of a programming voltage (also referred to as a "programming pulse") to one of the electrodes of a two-terminal memory results in the formation of a conductive filament in an interface layer (e.g., RSL). By convention and as generally described herein, the TE receives the programming pulses and the BE is grounded (or held at a lower voltage or opposite polarity than the programming pulses), but this is not intended to limit all embodiments. Conversely, applying an "erase pulse" to one of the electrodes (typically a pulse of opposite polarity to the program pulse or a pulse applied to the opposite electrode from the program pulse) may disrupt the continuity of the filament, for example by driving the metal particles or other material forming the filament back to the active metal source. The characteristics of such a conductive filament and its presence or absence affect the electrical characteristics of a two-terminal memory cell, e.g., decreasing resistance and/or increasing conductance between the two terminals when the conductive filament is present, and vice versa when not present.

After a program or erase pulse, a read pulse may be asserted. The read pulse is typically lower in amplitude than the program or erase pulse and is typically insufficient to affect the conductive filament and/or change the state of the two-terminal memory cell. By applying a read pulse to one of the electrodes of a two-terminal memory, a measured current (e.g., ion) when compared to a predetermined threshold current may indicate the conductive state of the two-terminal memory cell. The threshold current may be preset based on an expected current value for the two-terminal memory device in different states (e.g., a high resistance state current; a corresponding current for one or more low resistance states, etc.), as appropriate for a given two-terminal memory technology. For example, when a conductive filament has been formed (e.g., in response to application of a programming pulse), the conductance of the cell is greater than would otherwise be the case, and the current (e.g., ion) reading measured in response to the read pulse will be greater. On the other hand, when the conductive filament is removed (e.g., in response to applying an erase pulse), the resistance of the cell is higher because the interface layer has a relatively higher resistance, so the conductance of the cell is lower and the current measured in response to the read pulse (e.g., ioff) reading will be lower. Conventionally, when a conductive filament is formed, the memory cell is said to be in an "on state" with high conductance. When the conductive filament is not present, the memory cell is said to be in an "off state". Memory cells in either an on state or an off state may be logically mapped to binary values, e.g., "1" and "0". It should be understood that the convention used herein in connection with the state of a cell or related logical binary mapping is not intended to be limiting, and that other conventions, including the reverse convention, may be employed in connection with the present disclosure. The techniques detailed herein are described and illustrated in connection with Single Level Cell (SLC) memory, but it should be understood that the disclosed techniques may also be used with multi-level cell (MLC) memory, where a single memory cell may retain a set of measurably different states representing multi-bit information.

Digital information may be stored in such devices by mapping the digital information to the nonvolatile resistance state of a two-terminal memory cell. Electronic devices comprising many such double-ended memory cells can also store large amounts of data. The high density array is configured to contain as many memory cells as possible for a given chip space area, thereby maximizing the data storage capacity of the memory chip or system-on-chip device.

For two-terminal memories (e.g., crossbar arrays) formed at intersections of metal lines within a wafer, the inventors of the present disclosure have recognized two general conventions for arranging memory cells. The first convention is a 1T1R memory array, in which each memory cell is isolated from the electrical effects (e.g., current flow, including leakage path current) of surrounding circuitry by an associated transistor. The second convention is a 1TnR memory array (n is a positive number greater than 1) in which a group of multiple memory cells is isolated from the electrical effects of surrounding circuitry by one (or more) transistors. In a 1T1R environment, individual memory cells may be configured with high current rejection between memory cells, significantly reducing the leakage path current of the 1T1R memory array.

An example mechanism for interfacing a 1T1R memory array is provided. The first terminal of the two-terminal resistive memory device may be connected to a drain of the transistor. A second terminal of the two-terminal resistive memory device may be connected to a bit line of the 1T1R memory array. The source of the transistor is grounded or used as a source for an erase or program signal depending on the erase/program conditions of the memory array.

Examples of memory architectures for improved programming or erasing of dual-ended memory devices

Some embodiments of the present disclosure include increasing read or erase bandwidth by implementing asynchronous program or erase operations on multiple two-terminal (e.g., resistive random access) memory devices (ReRAM devices). In some embodiments, the program or erase operations are applied to ReRAM devices from a group of ReRAM devices at substantially the same time, but the inventors have recognized that in some cases these operations may actually be completed at different times. In one example, an erase operation is driven simultaneously by a single charge pump to multiple (e.g., 16) ReRAM devices, but some (e.g., 2) ReRAM devices may be programmed faster than the rest of the ReRAM devices. Accordingly, embodiments of the present disclosure are provided to begin programming or erasing operations of other (e.g., another 2) ReRAM devices in another set of such apparatuses, rather than waiting until the programming or erasing operations of the remaining (e.g., 14) ReRAM devices are complete. As an example of the foregoing, for the first ReRAM device and the second ReRAM device, the erase operation begins at about the same time (e.g., simultaneously, within a common clock cycle, within adjacent clock cycles, etc.); completing an erase operation of the first ReRAM device; then, before the erase operation of the second ReRAM device is completed, an erase operation of a third ReRAM device is started; next, completing the erase operation of the second ReRAM device before the erase operation of the third ReRAM device is completed; subsequently, before the erase operation of the third ReRAM device is completed, an erase operation of a fourth ReRAM device is started; and so on. As can be seen from the above, because the program or erase operations for the ReRAM device are completed at different times, embodiments may begin performing additional program or erase operations without waiting for the slower program or erase operations to complete.

In other embodiments of the present disclosure, multiple ReRAM devices may be subjected to erase or program operations by reducing the verify cycle after erase or program detection. More specifically, in an initial embodiment of the present disclosure, during a typical erase cycle, the amount of current is detected and the erase flag is set when the current drops below a programmed or predetermined low level (e.g., 0.5 microamperes (ua), 0.3ua, or 0.1ua or any other suitable level for a high resistance state for a given two-terminal memory technology). In the event that the erase flag is not detected, another erase pulse is provided (or, in some embodiments, the erase pulse is maintained or continued) while the current is monitored; with the erase flag set, the ReRAM device is considered erased and the erase pulse terminates. In some embodiments, after detecting the erase flag, a verification process (read operation) is performed to verify that the ReRAM device has been erased, and if the verification process is successful, the ReRAM device is considered erased (e.g., verified as erased).

In various embodiments related to programming ReRAM devices, during a typical programming cycle, the amount of current is detected and a program flag is set when the current is above a programmed or predetermined high level (e.g., 1.0ua, 1.3ua, or 1.5ua, or any other suitable level for a low resistance state (or one of a set of low resistance states) for a given two-terminal memory technology. In the event that the magnitude of the programming current is not detected, another programming pulse is provided (or the programming cycle is maintained or continued) while the current is monitored; with the program flag set, the ReRAM device is considered to have been programmed, and the programming pulse terminates. In some embodiments, after detecting the program flag, a verification process (read operation) is performed to verify that the ReRAM device has been programmed, and if the verification process is successful, the ReRAM device is considered to be programmed (e.g., verified as programmed).

In various embodiments, the verify process is considered to be longer in time (e.g., 1us to 5 us), and in some cases may be as long as half the duration of an erase pulse (e.g., 2us to 10 us) or a program pulse (e.g., 2us to 10 us), so some embodiments of the present disclosure provide the foregoing verify process to greatly reduce the time of the erase or program process. This is especially important where multiple ReRAM devices are to be programmed or erased at one time. In various embodiments, after detecting the erase flag or the program flag, the erase or program pulse is terminated (e.g., the erase or program is not verified by the read step), and then the ReRAM device is considered erased or programmed.

Other embodiments of the present disclosure include increasing the ability to detect when a ReRAM device is erased. As described above, in embodiments, to detect whether a ReRAM device is erased, a verify operation (e.g., read operation, read voltage) is applied to the ReRAM device. If properly erased, the typical erased state current flowing through a ReRAM device is on the order of 50nA to 200nA in various embodiments. In some embodiments, reliable sensing of the small current may be achieved, at least to some extent, by separating the small current from background noise. Sensing time after the ReRAM device is actually erased is relatively long because background noise from other parts of the chip often creates interference. In other words, the noise forces the erase cycle to extend longer than would otherwise be required.

In various embodiments, to reduce the effects of noise and reduce the amount of time of an erase cycle, the present disclosure is provided to bias the current flowing through the ReRAM with a bias current (e.g., a background current) and then compare the combined bias current to a threshold current. More specifically, in some embodiments, the current (e.g., about 50nA to erase a cell to about 200nA to program a cell) is biased (e.g., 1uA to 3 uA) by a bias current (e.g., 1uA to 3 uA), and the combined bias current (e.g., about 1.05uA to erase a cell to about 1.20uA to program a cell) is sensed compared to a threshold current (e.g., about 1.12 uA). In this example, a cell is considered erased if the combined bias current is less than about 1.12uA (e.g., about 1.05uA for erasing a cell), and is considered programmed if the combined bias current is greater than 1.12uA (e.g., about 1.20uA for programming a cell). With such embodiments, it is believed that it is possible to determine when a ReRAM device is erased more quickly than before. In other embodiments, other bias currents, threshold currents, etc. may be used.

Embodiments of the present disclosure may include using one, two, or all three of the above techniques, as well as other techniques, to erase and program multiple ReRAM devices.

Referring now to the drawings, FIG. 1 illustrates a diagram of an example array 100 of dual-ended memory devices for implementing one or more embodiments of the present disclosure. In an embodiment, the array 100 may represent a single double-ended memory block, where a double-ended memory block is defined having a first set of bit lines 102 intersecting a second set of word lines 104 and source lines 106, and memory cells 120 at (schematic) intersections of the bit lines 102 and the source lines 106. The number of bit lines 102 in a block may be conventionally set, with an absolute minimum of no less than 1 bit line, but in practice there will be multiple bit lines 102 per block (e.g., 8 bit lines, 32 bit lines, 128 bit lines, 256 bit lines, or any suitable number therebetween, or more). Rather, the blocks are merely convenient descriptors of a default number of bit lines 102, word lines 104, and source lines 106, which may vary in respective numbers according to one or more embodiments disclosed herein. For illustrative purposes, array 100 includes X bit lines (where X is a suitable integer greater than 1), where bit lines 102 are collectively referred to as bit lines BL ₀ 、BL ₁ 、BL ₂ 、BL ₃ 、BL ₄ 、BL ₅ 、…BL _X 。

The two-terminal memory cells 120 included in the array 100 are arranged in rows 110 connected to a common word line 104 and source line 106. For example, row 110 is connected to WL ₀ And SL ₀ And another row (e.g., nth row, where N is a suitable integer greater than 1) is connected to WL _N And SL _N As shown in the figure.

Each two-terminal memory cell 120 includes a resistance-switching device (represented by a resistance symbol) electrically connected in series with a transistor device (represented by a transistor symbol). The top electrode 122 of the memory cell 120 is coupled to one of the bit lines 102 (e.g., BL) _X ) A common node, and the bottom electrode 124 of the memory cell 120 and one of the source lines 106(e.g., WL) ₀ ) The nodes are shared. Further, the first terminal of the resistance switching device is connected to the second terminal of the transistor consisting of TE 122 and BL _X A common node, and a second terminal of the resistance-switching device is connected to a drain (or source, depending on convention) of the transistor device.

To apply a programming signal to memory cells 120 in a given row 110, an activation signal (e.g., a high voltage, such as 2.5 volts, or any other suitable voltage for activating transistor devices selected for transistor devices of memory cells 120 suitable for a selected transistor technology) is applied to the WL ₀ . The gate node is electrically connected to WL ₀ The transistor device of (a) is activated to cause current to flow between the source node and the drain node of the transistor. A second terminal of the resistance-switching device of memory cell 120 is electrically connected to SL upon activation of the associated transistor device ₀ . By in BL _X And SL ₀ An operating voltage (or current, electric field, or other suitable stimulus) is applied to perform an associated memory operation on memory cell 120. Examples of operations include read operations, write operations, and erase operations, each with appropriate voltages or voltage ranges, pulse durations, peak current values, etc. to implement these storage operations. For some resistive random access memory devices, suitable voltage ranges for read, write, and erase operations may be, for example, 0.5V to 1.5V, 2V to 3V, -2V to-3V, respectively, but those of ordinary skill in the art will appreciate that such voltage/voltage ranges will vary depending on the two-terminal technology suitable for selection for memory cell 120.

In the embodiment, at WL ₀ Connecting a high voltage to BL when activated _X And connects a low voltage (e.g., zero volts, ground voltage, or other suitable low voltage) to SL ₀ Memory cell 120 is programmed to a low resistance state. On the contrary, at WL ₀ Connect a low voltage (e.g., zero volts, ground voltage, etc.) to the BL when activated _X And connecting a high voltage to the SL ₀ Memory cell 120 is erased to a high resistance state. The memory cell 120 may be programmed or erased by connecting a medium read voltage (e.g., so small as not to program or erase) to the BL _X Connect a low voltageTo SL ₀ And connecting the activation voltage to the WL ₀ To implement a read operation.

In some embodiments, the source driver may be used to provide suitable storage operation voltages or currents with suitable pulse durations to achieve these storage operations (e.g., see fig. 2 and 3 and fig. 6 below). The source drivers may be connected to the various bit lines of the array 100 using any suitable multiplexer known in the art or known to those skilled in the art from the context provided herein (e.g., see fig. 6 below). In some embodiments, the sensing circuit may be connected to the bit line during a storage operation. In the case of a program or erase operation, the sense circuitry may be configured to respond to detecting a pass through the BL _X And an erase operation applied to memory cell 120, or may be set in response to detecting a pass through BL _X And the program operation applied to the memory cell 120. In an embodiment, a single bit may represent both an erase flag and a program flag, and if set (or reset, depending on convention) the bit is an erase bit, then reset (or set, depending on convention) the bit is a program bit. In other embodiments, separate bits may be provided for the erase flag and the program flag.

In a further embodiment, the source driver may repeat the storage operation if the program or erase bit is not set by the sensing circuit during a predetermined pulse time for the storage operation. As an illustrative example, if an erase operation is initiated and the sense circuit does not set the erase flag before the predetermined pulse time expires, the source driver may repeat the erase operation for a given memory cell. As an alternative embodiment, the source driver may not have a predetermined pulse time and may be configured to maintain the erase operation until the sensing circuit sets the erase flag, and in response thereto (e.g., in a subsequent clock cycle, or upon receiving an erase flag set signal, etc.), the source driver may terminate the erase operation. In yet another embodiment, a combination of the foregoing may be programmed into the source driver. For example, the source driver may perform an erase operation within a predetermined pulse time, and the erase operation is terminated in response to the setting of the erase flag (in one embodiment, before the end of the pulse time). Subsequent pulse time erase operations may be performed until the erase flag is set.

In alternative or additional embodiments of the present disclosure, the source driver may be configured to verify a program or erase flag. When the program or erase flag is set, the source driver terminates the program or erase operation (as applicable). A read operation may then be initiated, and flow through the BL coupled to memory cell 120 may be initiated as described herein _X Is compared to the appropriate current magnitude for the program operation or erase operation. As an illustrative example, if BL is measured _X Is greater than about 1.0ua (or other value suitable for a given two-terminal technology, or greater than one of a set of values for MLC two-terminal memory cells), then memory cell 120 is determined to be in a programmed state and the program flag is verified. As another example, if BL is measured _X Less than about 0.5ua (or other suitable value given a two-terminal technology), the memory cell 120 is determined to be in an erased state and the erase flag is verified. In at least some embodiments, in response to the setting of the program flag or the erase flag, the source driver can abort the verification of the program or erase and continue the reading of subsequent bit lines (and memory cells).

Referring now to FIG. 2, there is illustrated a block diagram of a memory device 200 that can operate in conjunction with one or more of the disclosed embodiments. Memory device 200 includes multiple BLOCKs of dual ended memory cells, including BLOCK ₁ 202A、BLOCK ₂ 202B to BLOCK _Z 202C (collectively, memory blocks 202A-202C). Memory blocks 202A-202C each include X bit lines. It should be understood that each block need not have the same number X of bit lines, and one or more blocks may have different integers of bit lines (e.g., Y, where Y is a suitable number greater than zero). As shown, the memory BLOCK ₁ 202A includes a first set of X bit lines: BL1<0:X>208A. Also, BLOCK ₂ 202B includes a second set of X bit lines: BL2<0:X>208B, up to BLOCK _Z 202C includes the ZGroup X bit lines: BLZ<0:X>208C (collectively referred to as bit lines 208A-208C).

Each row of memory cells is defined by an associated word line WL ₀ 、…WL _N And (4) activating. Once activated, a voltage or current may be applied to the memory cells of a given memory block 202A-202C. The memory device 200 includes a source driver: DRIVER ₁ 240A、DRIVER ₂ 240B、…DRIVER _Z 240C (collectively referred to as source drivers 240A-240C) for applying signals to bit lines of the bit lines 208A-208C. The source drivers 240A-240C are connected to the individual bit lines 208A through a multiplexer 230. In one embodiment, multiplexers 230 are configured to connect each source driver 240A-240C to only the bit lines of the associated memory block 202A-202C. However, in some embodiments, the multiplexer 230 may be configured to connect the source driver 240A (or 240B, or 240C) to any of the memory blocks 202A-202C.

A charge pump 250 is provided to power the source drivers 240A-240C. In addition, the charge pump 250 may provide power to selected word line/source line pairs through the decoder 220. Charge pump 250 feeds selected word lines (e.g., WL) through decoder 220 ₀ ) Applying a high signal 220 ₀ To activate the connection to the associated source line (e.g., SL) ₀ ) The memory cell of (1). Low signal 220 _N Is applied to unselected word lines (e.g., WL) _N ) To deactivate the memory cell connected to the deactivated word line.

The storage operation is implemented by the storage apparatus 200 by: the selected word line (e.g., WL0, etc.) is activated, and a signal is applied across the selected bit line and the source line (e.g., SL0, etc.) associated with the selected bit line. In various embodiments, the source drivers 240A-240C may initiate storage operations for multiple memory cells in a respective memory block 202A-202C at substantially the same time (e.g., simultaneously, in a common clock cycle, in adjacent clock cycles, or other suitable convention). As defined herein, the plurality of memory cells is implemented by memory cells of the same bit line order in different memory blocks 202A-202C. In other words, the zero level bit line of each memory block (including: BL 1) _<0> 210A、BL2 _<0> 210B、…BLZ _<0> 210C (collectively, zero level bit lines 210A-210C)) are included in the first batch of memory cells. As shown in FIG. 2, the first plurality of memory cells includes

memory cells

212A, 212B, … C (collectively referred to as a plurality of memory cells 212A-212C). The second group of memory cells includes a primary bit line (BL 1) in each memory block 202A-202C _<1> 、BL2 _<1> 、…BLZ _<1> ) The third group of memory cells includes the secondary bit lines (BL 1) in each of the memory blocks 202A-202C _<2> 、BL2 _<2> 、…BLZ _<2> ) Those of (a) and so on.

To improve the erase time of a block of memory cells, the source drivers 240A-240C may be configured to initiate memory operations on a first plurality of memory cells 212A-212C simultaneously, but may independently perform memory operations on subsequent memory cells of the associated memory block 202A-202C. In other words, a given source driver 240A begins a bulk erase (or program) operation of memory BLOCKs 202A-202C simultaneously with source drivers 240B and 240C, but may continue to BLOCK independently of the progress of source drivers 240B and 240C ₁ The subsequent bit lines of 202A operate and vice versa. This may improve bulk operation time because the delay of one source driver (e.g., 240B) erasing or programming a given memory cell does not delay the progress of subsequent memory cells on subsequent bit lines of other source drivers (e.g., 240A, 240C). Conversely, upon detecting a completion event (e.g., setting a program flag or an erase flag, optionally in conjunction with a read verify operation), a source driver (e.g., 240A) may be connected to a subsequent bit line (e.g., from BL 1) using multiplexer 230 _<0> To BL1 _<1> ). In at least one embodiment, the source driver completes a given memory BLOCK (e.g., BLOCK) ₁ 202A) All bit lines (e.g., BL 1) _<0:X> ) The source driver may be connected to different memory BLOCKs (e.g., BLOCK) ₂ 202B、BLOCK _Z 202C) To further reduce the overall time of bulk erase (or program) operations.

Referring now to FIG. 3, a storage device 300 configured to perform storage operations on storage units of different batches of storage units as provided herein is illustrated. In one or more embodiments, the storage device 300 can be substantially similar to the storage device 200 of FIG. 2, supra. Thus, as shown, memory device 300 may include source drivers 240A-240C, multiplexer 230, memory blocks 202A-202C and bit lines 208A-208C as described above, as well as other components of memory device 200 not specifically depicted in FIG. 3.

Bulk storage operations of memory device 300 are shown, i.e., different source drivers 240A-240C at a start time t ₀ After a time t _a And (c) performing operation on different batches of storage units, wherein a is an integer greater than 0. To WL ₀ Providing an activation signal to activate the connection to the WL ₀ All of the transistors of (1). Applying appropriate signals to the source lines SL ₀ To be connected to SL ₀ The memory cells of (a) are programmed (e.g., low signal) or erased (e.g., high signal). Source driver 1240A is still coupled to memory cells in the zeroth group of bit lines, specifically to BL1 _<0> 210, the memory cell 312A operates. At the same time, source driver 2240B has proceeded to connect memory cells in the second set of bit lines, in particular to BL2 _<2> 210B, and the source driver 240C has proceeded to connect to the memory cells in the first group, in particular to BLZ _<1> 210C, the memory cell 312Z operates. As shown in memory device 200, the long operation time of memory cell 312A does not delay the pair of BLOCK by source driver 2240B ₂ 202B without delaying the operation of the source driver 202C on BLOCK _Z 202C. By configuring the source drivers 240A-240C to continue on to subsequent groups of bit lines (e.g., from BLZ) independently of the other source drivers 240A-240C _<0> To BLZ _<1> Etc.), the impact of longer operation times on a given memory cell can be minimized due to bulk erase or bulk program operations, thereby increasing the overall speed of such operations.

FIG. 4 illustrates an example pulse time diagram 400 for a memory block according to other embodiments of the present disclosure. Pulse time diagram 400 plots current on the vertical axis and time on the horizontal axis. In addition, FIG. 4 provides a respective pulse time diagram for each of the blocks 202A-202C.

Each pulse has a time for a successful program or erase operation of a given memory cell within the associated memory block. For BLOCK ₁ 202A, a number of pulse times are shown depending on the time it takes for a memory cell to complete a program or erase operation (e.g., as determined by setting an erase flag or program flag, optionally in conjunction with a read/verify operation). At a first pulse time t ₀ 422 to the first memory cell (from BLOCK) ₁ 202A, from the left side of the figure) for programming. In one embodiment, the pulse time t ₀ 422 may be a default or minimum pulse time. In other embodiments, a default pulse time (e.g., 20 nanoseconds, or other suitable value associated with an average, medium value, typical value, etc. of the program or erase time for a given type of dual ended memory technology employed by the memory cell) may be provided, which may be shortened when a program or erase event is detected. In other words, in the latter embodiment, the initial time may be a default time, but without a minimum pulse time.

If the storage operation is not completed on a given memory cell at the end of the pulse time, additional pulses may be implemented until the sensing circuit detects that the memory cell completed the storage operation. In an alternative embodiment, the initial pulse time may be maintained until the completion of the storage operation is detected. BLOCK ₁ The second memory cell (from the left side of the figure) requires a ratio t ₀ 422 pulse time long t ₂ 424 pulse times to complete the memory operation. Still other memory locations relate to t ₁ 426 pulse time to complete the memory operation, where t ₂ >t ₁ >t ₀ . In contrast, BLOCK ₂ 202B are all default t ₀ Pulse time 422, and BLOCK _Z 202C has a few t ₁ 426 pulse time, but not t ₂ 424 pulse time.

Because the source drivers 240A-240C are configured to continue operating on subsequent bit lines (and memory cells) independently of the other source drivers 240A-240C, at a given time T ₁ 450, each memory block 202A-240C may complete a different number of memory cells. For BLOCK ₁ 202A, fourteenth memory cell 412A (counting the number of completed pulses) at time T ₁ 250 is completed, and for BLOCK ₂ 202B, the seventeenth memory cell 412B has completed. For BLOCK _Z 202C, fifteenth memory cell 412Z at time T ₁ Completed before 250.

According to one or more embodiments, the source drivers 240A-240C may be connected to different blocks when the operations for all the memory cells of a given block are completed. In some embodiments, the source driver 240B may operate on the memory block 202A that another source driver 240A is currently operating to complete the memory block 202A more quickly. In other embodiments, source driver 240B may point to a memory block (not depicted) to which no source driver is currently assigned.

FIG. 5 depicts an example timing diagram 500 for a storage operation for multiple storage devices in a disclosed embodiment. According to further embodiments of the present disclosure, timing diagram 500 facilitates reducing program/erase operation times for a plurality of memory devices. For example, where the precharge time 504 (increasing the signal, e.g., before a set of memory operations begin) and the ramp down time 508 (decreasing the signal, e.g., after a set of memory operations) have durations comparable to the state change time 506, applying the state change signal to the plurality of memory devices within the state change time 506 may significantly reduce the program/erase durations of the plurality of memory devices.

As an illustrative example, consider a 1.6us precharge time 504, a 1.6us state change time 506, and a 1.6us ramp down time 508. Given all of these times, 3 × 1.6us or 4.8us is required to initiate and complete a store operation on a single memory cell. However, some two-terminal memory technologies may program or erase for a fraction of this time (e.g., as an example of some resistive random access memories)E.g., an erase time of about 20 ns). However, for

fixed times

504, 506, 508, the operating speed of the dual-ended memory is not achieved by operation of the circuit. However, for a bulk operation when programming or erasing a plurality of memory cells in the state change time 506, the average operation time per cell can be significantly reduced. During a state change time 506, an operating signal is applied to a first bit line/top electrode (BL/TE) ₁ ) 520 and then to a second BL/TE ₂ 522, third BL/TE ₃ 524, and so on until the Z-th BL/TE _Z 526 as shown. For example, if the average operation time is 20ns, a cell number equal to 1.6us (1600 ns)/20 ns, or 80 memory cells, can be completed. Completing 80 memory cells within the same 4.6us can significantly reduce the operating time per cell from 4.6us per cell to 57.5ns per cell.

In the embodiment of FIG. 5, the pulse times are modular with a default time t ₀ 422 and a multiple (e.g., two times) of a default time, e.g., t ₁ 426. Other embodiments within the scope of the present disclosure will not have a modularized time, such as when a pulse period is terminated in response to detecting a memory operation (e.g., at the next clock period, such as 10ns for 100Mhz clock, 2ns for 500mhz clock, or a high speed clock or faster). A new memory cell may be targeted after the pulse time expires (e.g., at a suitable subsequent clock cycle).

Fig. 6 shows an example schematic diagram of a multiplexer 600 in accordance with one or more other embodiments of the present disclosure. Multiplexer 600 may be configured to selectively connect source drivers (e.g., source drivers 240A-240C) to bit lines of a memory block. Multiplexer 600 depicts a first set of bit lines BL of a single memory block _<0> 602、BL _<1> 604、BL _<2> 606、…BL _<Z> 608, collectively referred to as bit lines 602-608. However, it should be understood that the multiplexer may also incorporate bit lines (e.g., bit line BL 2) for multiple memory blocks<0:X>208B、BLZ<0:X>208C, and other bit lines not described herein).

Driver switches 610 are provided to connect source drivers to bit lines of bit lines 602-608. In some embodiments, multiple source drivers may be connected to any of the bit lines 602-608 (e.g., through a driver multiplexer (not depicted)). However, in other embodiments, each source driver may be connected to only the bit lines of a single memory block.

In various embodiments, sensing circuitry 618 for sensing current on one or more bit lines 602-608 is provided to determine when a storage operation is complete. For example, the sensing circuit 618 may compare the current flowing in the bit line to a current threshold and identify a change in current that is suitable to exceed the current threshold. For a programming operation, sensing circuit 618 may detect an increase in current through the bit line above a current threshold and set a program flag to notify an associated source driver of the detected programming event. For an erase operation, the sense circuit 618 may detect that the current flowing through the bit line has dropped below a current threshold and set an erase flag to notify the associated source driver of the detected erase event. The sense circuit 618 may be connected to a selected bit line through a sense contact 614.

In alternative or other embodiments, multiplexer 600 may include a bias signal to provide a bias to the current detected by sensing circuit 618. The bias signal 616 can be configured to have a magnitude suitable for reducing the effects of noise on the sensing circuit 618 when detecting current in the bit lines 602-608. In this case, sensing circuit 618 compares the current to a threshold current that includes a constant bias current. As an illustrative example, the current may be biased between about 1 microampere (uA) and about 3uA, or any other suitable value. In this example, a 1uA bias current is used, adding a constant 1uA to the threshold current used by sensing circuit 618. Where the current flowing through average/typical, etc. to erase a cell is about 50nA and the current flowing through average/typical, etc. to program a cell is about 200nA, the baseline current threshold that measurably distinguishes between erasing and programming a cell may be, for example, 120nA. When added to the 1uA bias current, sense circuit 618 will detect a current on bit lines 602-608 that is higher or lower than 1.12uA to distinguish between erasing and programming of a cell. This bias current will help mitigate the effects of low signal noise in the electronic device, improving the accuracy of the sensing circuit 618.

The figures included herein are described with respect to interaction between a number of memory cells, memory cell components, memory arrays, or memory architectures. It will be appreciated that such a diagram may include those memory cells, components, arrays, and architectures specified therein, a portion of the specified memory cells/components/arrays/architectures, or suitable alternative or additional memory cells/components/arrays/architectures. The sub-components may also be implemented to be electrically connected to other sub-components, rather than being included in a parent architecture. Also, according to other embodiments, the various components may be implemented in a combined architecture. For example, in one embodiment, source drivers 240A-240C may be implemented as subcomponents of a single voltage/current driver. In addition, some disclosed embodiments may be implemented as part of other disclosed embodiments, where appropriate.

Still further, one or more of the disclosed processes may be combined into a single process that provides aggregate functionality. For example, a program or erase process may include a read/verify process and vice versa to program/erase semiconductor cells and verify completion of the programming/erasing through a single process. Further, it should be understood that the various rows of the multiple cell memory architecture can be grouped (e.g., multiple rows erased simultaneously) or erased individually. Further, it should be understood that multiple memory cells on a particular row may be grouped (e.g., multiple memory cells read/programmed simultaneously) or read or programmed individually. The components of the disclosed architecture may also interact with one or more other components not specifically described herein but known by those of skill in the art or made apparent by the context provided herein.

In view of the example diagrams described herein, processing methodologies that may be implemented in accordance with the present disclosure may be better appreciated with reference to the flow diagrams of fig. 7 and 8. While, for purposes of simplicity of explanation, the methodologies of fig. 7 and 8 are shown and described as a series of blocks, it is to be understood and appreciated that the claimed subject matter is not limited by the order of the blocks, as some blocks may occur in different orders or concurrently with other blocks from what is depicted and described herein. Moreover, not all illustrated blocks may be required to implement the methodologies described herein, and in some embodiments, additional method steps not described, but known to one of ordinary skill in the art or through the context provided herein, may be incorporated into the described methodologies. Moreover, it should be further appreciated that the methodologies disclosed herein are capable of being stored on an article of manufacture to facilitate transporting and transferring such methodologies to electronic devices. The term article of manufacture, as used, is intended to encompass a computer program accessible from any computer-readable device, device or storage medium combined with a carrier.

Referring now to fig. 7, depicted is a flow diagram of an example method 700 of performing an erase or program operation on a dual ended memory device in accordance with a further embodiment of the present disclosure. The method 700 may include, at 702, substantially simultaneously initiating an erase cycle or a program cycle of dual-ended memory devices of a first batch of dual-ended memory devices. In an embodiment, the first batch of two-terminal memory devices may include memory cells on respective zeroth bit lines in different blocks of the two-terminal memory devices. The method 700 may include, at 704, monitoring an erase detection or program detection condition of each dual-ended memory device in the first batch of dual-ended memory devices. Additionally, the method 700 may include, at 706, detecting an erase detection or program detection condition of a first dual-ended storage device of the first batch of dual-ended storage devices prior to detecting the erase detection or program detection condition of all dual-ended storage devices of the first batch of dual-ended storage devices. Additionally, the method 700 may include, at 708, initiating an erase cycle or a program cycle of a second dual-ended memory device of a second batch of dual-ended memory devices prior to detecting an erase detect or a program detect condition of all dual-ended memory devices of the first batch of dual-ended memory devices. The subsequent erase cycle or program cycle may be in response to detecting an erase detection or program detection condition of the first dual-sided memory device. As described herein, the second population of two-terminal memory devices may include memory devices on corresponding primary bit lines of different blocks of the two-terminal memory devices.

In a further embodiment, prior to detecting the erase detection or program detection condition of all of the dual-ended memory devices, the method 700 may further include detecting an erase detection or program detection condition of a third dual-ended memory device of the first batch of dual-ended memory devices. Additionally, the method 700 may include initiating an erase cycle or a program cycle of a fourth dual-ended memory device of the second population of dual-ended memory devices in response to detecting an erase detect or a program detect condition of the third dual-ended memory device.

In still further embodiments, detecting an erase detection or a program detection condition of a first dual-ended storage device of the first batch of dual-ended storage devices may include performing a verification cycle on the first dual-ended storage device to determine a success condition or to determine a lack of success condition. Further, in other embodiments, an erase cycle or a program cycle of a second dual-ended storage device of the second set of dual-ended storage devices is initiated in response to detecting an erase detection or a program detection condition of the first dual-ended storage device and determining a successful condition.

In an alternative or additional embodiment of the method 700, an erase cycle or a program cycle of a second dual-ended storage device of the second set of dual-ended storage devices is initiated substantially without a verify cycle of a first dual-ended storage device of the first set of dual-ended storage devices. According to such embodiments, the verification period may be selected from the group consisting of an erase verification period and a program verification period.

In a further embodiment, detecting an erase detection or program detection condition of a first dual-ended storage device of the first population of dual-ended storage devices includes receiving a current associated with the first dual-ended storage device. In the latter embodiment, method 700 may also include biasing the current by a current offset to form a bias current and comparing the bias current to a current threshold to detect an erase detection or program detection condition. Still further, detecting an erase detection or program detection condition in response to the sensed current may include detecting as an erase detection condition when the sensed current is less than a current threshold. Alternatively, detecting an erase detection or program detection condition in response to the sensed current may include detecting a program detection condition when the sensed current is greater than a current threshold.

In yet another embodiment, the two-terminal memory device includes a resistive random access (ReRAM) device. In such embodiments, monitoring the erase detect or program detect condition of each dual-ended memory device may include monitoring the erase detect or program detect condition of each ReRAM device.

In yet another embodiment, the two-terminal memory device is selected from the group consisting of a phase change memory, a metal oxide memory, a silicon sub-oxide memory, a chalcogenide memory, a magnetic memory, a carbon nanotube memory, and a filament-based memory. In other embodiments, after detecting the erase detection or program detection condition of the last dual-ended memory device of the first plurality of dual-ended memory devices, the method 700 may include initiating an erase cycle or program cycle of a third dual-ended memory device of the second plurality of dual-ended memory devices in response to detecting the erase detection or program detection condition of the last dual-ended memory device of the first plurality of dual-ended memory devices. In at least one disclosed embodiment, the number of dual-ended storage devices of the first batch of dual-ended storage devices is in a range of 8 to 32.

Fig. 8 depicts a flow diagram of an example method 800 for implementing additional aspects of the present disclosure. Method 800 may include, at 802, initiating a state change operation of memory cells connected to a first set of bit lines in a respective memory block of a two-terminal memory. The method 800 may include, step 804, initiating a state change detection of memory cells on a first set of bit lines. Further, the method 800 may include, at 806, detecting a change of state of a memory cell in the first block of memory cells, and the method 800 may include, at 808, connecting a power supply of the first memory block to a bit line of the first memory block belonging to the second group of bit lines of the respective memory block. Method 800 may include, at 810, detecting a change in state of other memory cells in a memory block associated with the other memory cells. The method 800 may include, at 812, connecting a power supply for the associated memory block to a subsequent bit line in a subsequent set of bit lines within the associated memory block. At 814, it is determined whether all storage devices of the storage block have successfully changed state. If so, method 800 may end at 816. Otherwise, method 800 returns to 810.

Examples of operating environments

In order to provide a background for the various aspects of the present disclosure, FIG. 9 and the following discussion are intended to provide a brief, general description of a suitable environment in which the various aspects of the present disclosure can be implemented or processed. Although the technical solutions have been described above in the general context of semiconductor architectures and process methods for operating arrays of two-terminal memory devices, those skilled in the art will recognize that the present disclosure may also be implemented in conjunction with other architectures or process methods. Moreover, those skilled in the art will appreciate that the disclosed processes may be practiced with processing systems or computer processors, which may include single-processor or multi-processor computer systems, minicomputers, mainframe computers, as well as personal computers, hand-held computing devices (e.g., PDAs, telephones, watches), microprocessor-based or programmable consumer or industrial electronics, and the like, alone or in combination with a host computer. The illustrated aspects may also be practiced in distributed computing environments where tasks are performed by remote processing devices that are linked through a communications network. However, some, if not all, aspects of the claimed innovation may be implemented on stand-alone electronic devices, such as memory cards, flash memory modules, removable memory (e.g., CF card, USB memory stick, SD card, micro SD card), and so forth. In a distributed computing environment, program modules may be located in both local and remote memory storage modules or devices.

FIG. 9 illustrates a block diagram of an example of the operation of a storage array 902 of a multi-block storage cell array and a control environment 900 in accordance with aspects of the present disclosure. In at least one aspect of the present disclosure, the memory array 902 may include a memory selected from a variety of memory cell technologies. In at least one embodiment, the memory array 902 may comprise dual-ended memory technology arranged in a compact two-dimensional or three-dimensional architecture. Suitable two-terminal memory technologies may include resistive switching memory, conductive bridge memory, phase change memory, organic memory, magnetoresistive memory, and the like, or suitable combinations of the foregoing. In yet another embodiment, the memory array 902 may be configured to operate in accordance with bulk program or erase operations provided herein.

The column controller 906 and the sense amplifiers 908 can be formed adjacent to the memory array 902. Further, column controller 906 may be configured to activate (or identify for activation) a subset of bit lines of memory array 902. Column controller 906 may utilize the control signals provided by reference and control signal generator 918 to activate and operate the corresponding bit lines in the subset of bit lines to which appropriate program, erase, or read voltages are applied. The inactive bit lines may be held at an inhibit voltage (also applied by reference and control signal generator 918) to mitigate or avoid bit disturb effects on these inactive bit lines.

Further, the operating and control environment 900 may include a row controller 904. The row controller 904 may be formed adjacent to and electrically connected to word lines (and source lines, in some embodiments) of the memory array 902. In addition, using control signals in the reference and control signal generator 918, the row controller 904 can select a particular row of memory cells with an appropriate select voltage. In addition, row controller 904 can perform program, erase, or read operations by applying appropriate voltages on selected word lines (and source lines). Similar to the column controller 906, the row controller 904 can apply an inhibit voltage to the inactive word lines (source lines) to mitigate or avoid bit-disturb (bit-disturb) effects on the inactive word lines (source lines).

The sense amplifiers 908 can read data from or write data to activated memory cells of the memory array 902 selected by the column control 906 and the row control 904. Data read from the memory array 902 may be provided to an input/output buffer 912. Likewise, data to be written to memory array 902 may be received from input/output buffer 912 and written to an active memory cell of memory array 902.

The clock source 910 may provide corresponding clock pulses to facilitate the timing of read, write, and program operations by the row 904 and column 906 controllers. Clock source 910 may be responsive to reception by operating and control environment 900 the external or internal command further facilitates the selection of a word line or bit line. Input/output buffer 912 may include command and address inputs and bidirectional data inputs and outputs. Instructions are provided via command and address inputs and data to be written to the memory array 902 and read from the memory array 902 are transferred via bidirectional data inputs and outputs to facilitate connection to an external host device, such as a computer or other processing device (not shown, but see, e.g., computer 1002 of fig. 10, described below).

Input/output buffer 912 may be configured to receive write data, receive erase instructions, receive status or maintenance instructions, output read data, output status information, and receive address data and command data and address data for the corresponding instructions. The address data may be transferred to the row controller 904 and the column controller 906 via the address register 914. In addition, input data is transmitted to the memory array 902 via a signal input line between the sense amplifier 908 and the input/output buffer 912, and output data is received from the memory array 902 via a signal output line from the sense amplifier 908 to the input/output buffer 912. Input data may be received from the host device, and output data may be transmitted to the host device via the I/O bus.

Commands received from the host device may be provided to a command interface 916. The command interface 916 may be configured to receive an external control signal from a host device and determine whether data input to the input/output buffer 912 is write data, a command, or an address. The input command may be transmitted to state machine 920.

State machine 920 may be configured to manage programming and reprogramming of storage array 902 (as well as other storage groups of a multi-group storage array). The instructions provided to state machine 920 are implemented according to a control logic configuration that enables state machine 920 to manage the reading, writing, erasing, data input, data output, and other functions associated with memory cell array 902. In some aspects, state machine 920 is capable of sending and receiving acknowledgements or negative acknowledgements regarding successful receipt or execution of various commands. In further embodiments, state machine 920 may decode and implement state-related commands, decode and implement configuration commands, and so forth.

To perform read, write, erase, input, output, etc., functions, state machine 920 may control clock source 908 or reference and control signal generator 918. Control of the clock source 908 may cause the output pulses to be configured to facilitate the row controller 904 and the column controller 906 to perform particular functions. The output pulse may be transmitted to a selected bit line, e.g., by column controller 906, or to a word line, e.g., by row controller 904.

With reference to FIG. 10, a suitable environment 1000 for implementing various aspects of the claimed subject matter includes a computer 1002. The computer 1002 includes a processing unit 1004, a system memory 1010, a codec 1014, and a system bus 1008. The system bus 1008 couples system components including, but not limited to, the system memory 1010 to the processing unit 1004. The processing unit 1004 can be any of various available processors. Dual microprocessors and other multiprocessor architectures also can be employed as the processing unit 1004.

The system bus 1008 can be any of several types of bus structure(s) including the memory bus or memory controller, a peripheral bus or external bus, and/or a local bus using any variety of available bus architectures including, but not limited to, industry Standard Architecture (ISA), micro-channel architecture (MSA), extended ISA (EISA), intelligent Drive Electronics (IDE), VESA Local Bus (VLB), peripheral Component Interconnect (PCI), card bus, universal Serial Bus (USB), advanced Graphics Port (AGP), personal computer memory card international association bus (PCMCIA), firewire (IEEE 1394), and Small Computer System Interface (SCSI)).

The system memory 1010 includes volatile memory 1010A and non-volatile memory 1010B. The basic input/output system (BIOS), containing the basic routines to transfer information between elements within the computer 1002, such as during start-up, is stored in nonvolatile memory 1010B. Further, in accordance with the present invention, codec 1014 may include at least one of an encoder or a decoder, where at least one of the encoder or decoder may include hardware, software, or a combination of hardware and software. Although the codec 1014 is depicted as a separate component, the codec 1014 may be included within the non-volatile memory 1010B. By way of illustration, and not limitation, nonvolatile memory 1010B can include Read Only Memory (ROM), programmable ROM (PROM), electrically Programmable ROM (EPROM), electrically Erasable Programmable ROM (EEPROM), or flash memory, two terminal memory, and the like. Volatile memory 1010A includes Random Access Memory (RAM), which acts as external cache memory. According to this aspect, the volatile memory may store write operation retry logic (not shown in fig. 10) or the like. By way of illustration and not limitation, RAM may take many forms, such as Static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), and Enhanced SDRAM (ESDRAM).

The computer 1002 may also include removable/non-removable, volatile/nonvolatile computer storage media. FIG. 10 illustrates, for example a disk storage 1006. Disk storage 1006 includes, but is not limited to, the following devices: a magnetic disk drive, a Solid State Drive (SSD), a floppy disk drive, a tape drive, a Jaz drive, a Zip drive, a LS-100 drive, a flash memory card, or a memory stick. In addition, disk storage 1006 can include storage media separately or in combination with other storage media including, but not limited to, an optical disk Drive such as a compact disk read only memory (CD-ROM), CD recordable Drive (CD-R Drive), CD rewritable Drive (CD-RW Drive) or a digital versatile disk ROM Drive (DVD-ROM). To facilitate connection of the disk storage devices 1006 to the system bus 1008, a removable or non-removable interface is typically used such as storage interface 1012. It is to be appreciated that the storage device 1006 can store information related to a user. This information may be stored or provided to a server or application running on the user device. In one embodiment, the user may be informed (e.g., via output device 1032) of the type of information stored to disk storage 1006 or transmitted to the server or application. The user may be provided with an opportunity to opt-in or opt-out (e.g., via input from input device 1042) of collecting and/or sharing such information with a server or application.

It is to be appreciated that fig. 10 describes software that acts as an intermediary between users and the basic computer resources described in suitable operating environment 1000. Such software includes an operating system 1006A. Operating system 1006A, which can be stored on disk storage 1006, acts to control and allocate resources of the computer system 1002. Application programs 1006C take advantage of the management of resources by operating system 1006A through program modules 1006D, as well as program data 1006D stored either in system memory 1010 or on disk storage 1006, such as start/close transaction tables, etc. It is to be appreciated that the claimed subject matter can be implemented with various operating systems or combinations of operating systems.

A user enters commands or information into the computer 1002 through input device(s) 1042. Input devices 1042 include, but are not limited to, a pointing device such as a mouse, trackball, stylus, touch pad, keyboard, microphone, joystick, game pad, satellite dish, scanner, TV tuner card, digital camera, digital video camera, web camera, and the like. These and other input devices connect to the processing unit 1004 through the system bus 1008 via input port 1040. Input ports 1040 include, for example, a serial port, a parallel port, a game port, and a Universal Serial Bus (USB). Output devices 1032 use some ports of the same type as input devices 1042. Thus, for example, a USB port may be used to provide input to computer 1002 and to output information from computer 1002 to an output device 1032. Output adapter 1030 is provided to illustrate that there are some output devices 1032 like monitors, speakers, and printers, among other output devices 1032, which require special adapters. The output adapters 1030 include, by way of illustration and not limitation, video and sound cards that provide a means of connection between the output device 1032 and the system bus 1008. It should be noted that other devices and/or systems of devices provide both input and output capabilities such as remote computer 1038.

The computer 1002 may operate in a networked environment using logical connections to one or more remote computers, such as a remote computer 1024. The remote computer 1024 can be a personal computer, a server, a router, a network PC, a workstation, a microprocessor based appliance, a peer device, a smart phone, a tablet computer or other network node, and typically includes many of the elements described relative to the computer 1002. For purposes of brevity, remote computer(s) 1024 illustrates only the storage device 1026. Remote computer 1024 is logically connected to computer 1002 through a network 1022 and then connected via communication interface 1020. Network 1022 includes wired or wireless communication networks such as Local Area Networks (LANs) and Wide Area Networks (WANs), as well as cellular networks. LAN technologies include Fiber Distributed Data Interface (FDDI), copper Distributed Data Interface (CDDI), ethernet, token ring, and the like. WAN technologies include, but are not limited to, point-to-point links, circuit switching networks like Integrated Services Digital Networks (ISDN) and variations thereon, packet switching networks, and Digital Subscriber Lines (DSL).

Communication interface 1020 refers to the hardware/software employed to connect the network 1022 to the bus 1008. While communication interface 1020 is shown for illustrative clarity inside computer 1002, it can also be external to computer 1002. The hardware/software necessary for connection to the network 1022 includes, for exemplary purposes only, internal and external technologies such as, modems including regular telephone grade modems, cable modems and DSL modems, ISDN adapters, and wired and wireless ethernet cards, hubs, and routers.

The illustrated aspects of the disclosure may also be practiced in distributed computing environments where certain tasks are performed by remote processing devices that are linked through a communications network. In a distributed computing environment, program modules or stored information, instructions or the like may be located in local or remote memory storage devices.

Further, it should be understood that the various components described herein may include circuitry that may include components and circuit elements of appropriate values in order to implement embodiments of the present disclosure. Further, it is understood that many different components may be implemented on one or more IC chips. For example, in one embodiment, a set of components may be implemented in a single IC chip. In other embodiments, one or more of the respective components are fabricated or implemented on separate IC chips.

With respect to the various functions performed by the above described components, architectures, circuits, processes, and the like, the terms (including a reference to a "means") used to describe such components are intended to correspond, unless otherwise indicated, to any component which performs the specified function of the described component (e.g., a functional equivalent), even though not structurally equivalent to the disclosed structure which performs the function in the herein illustrated exemplary aspects of the embodiments. In this regard, it will also be recognized that the embodiments include a system as well as a computer-readable medium having computer-executable instructions for performing the acts and/or events of the various processes.

In addition, while a particular feature may have been disclosed with respect to only one of several implementations, such feature may be combined with one or more other features of the other implementations as may be desired and advantageous for any given or particular application. Furthermore, to the extent that the terms "includes" and "including" and variations thereof are used in either the detailed description or the claims, such terms are intended to be inclusive in a manner similar to the term "comprising".

As used in this application, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or". That is, unless specified otherwise, or clear from context, "X employs a or B" is intended to mean any of the natural inclusive permutations. That is, if X employs A; x is B; or X employs both A and B, then "X employs A or B" satisfies any of the foregoing conditions. In addition, the articles "a" and "an" as used in this application and the appended claims should generally be construed to mean "one or more" unless specified otherwise or clear from context to be directed to a singular form.

Further embodiments may be envisioned by one of ordinary skill in the art after reading this disclosure. For example, in various embodiments, an erase operation may be initiated for multiple ReRAM devices (e.g., 16, 32, etc.) simultaneously.

In other embodiments, combinations or sub-combinations of the above disclosed embodiments may be advantageously made. The block diagrams and flow charts of the architecture are grouped for ease of understanding. However, it should be understood that combinations of blocks, additions of new blocks, rearrangements of blocks, and the like are contemplated in alternative embodiments of the present disclosure.

It is also understood that the examples and embodiments described herein are for illustrative purposes only and that various modifications or changes in light thereof will be suggested to persons skilled in the art and are to be included within the spirit and purview of this application and scope of the appended claims.

Claims

1. A method of performing an erase operation or a program operation on a dual-ended memory device, comprising:

starting an erase cycle or a program cycle of the dual-ended memory devices of the first batch of dual-ended memory devices;

monitoring an erase detection condition or a program detection condition of each dual-ended memory device; and

before detecting an erase detection condition or a program detection condition of all dual-ended memory devices, the method includes:

detecting an erase detection condition or a program detection condition of a first dual-ended memory device of the first plurality of dual-ended memory devices; and

an erase cycle or a program cycle of a second dual-ended storage device of the second set of dual-ended storage devices is initiated in response to detecting an erase detect condition or a program detect condition of the first dual-ended storage device.

2. The method of claim 1, wherein prior to detecting an erase detection condition or a program detection condition of all dual-ended memory devices, the method comprises:

detecting an erase detection condition or a program detection condition of a third dual-ended memory device of the first plurality of dual-ended memory devices; and

in response to detecting an erase detect condition or a program detect condition of the third dual-ended memory device, initiating an erase cycle or a program cycle of a fourth dual-ended memory device of the second plurality of dual-ended memory devices.

3. The method of claim 1, wherein after detecting an erase detection condition or a program detection condition of the first dual-ended storage device of the first batch of dual-ended storage devices, the method comprises performing a verification cycle on the first dual-ended storage device to determine a successful condition or to determine a lack of successful condition, and

wherein an erase cycle or a program cycle of the second dual-ended storage devices of the second set of dual-ended storage devices is initiated in response to detecting an erase detection condition or a program detection condition of the first dual-ended storage devices and determining the success condition.

4. The method of claim 1, wherein an erase cycle or a program cycle of the second dual-ended storage devices of the second population of dual-ended storage devices is initiated substantially without a verify cycle of the first dual-ended storage devices of the first population of dual-ended storage devices.

5. The method of claim 4, wherein the verify cycle is selected from the group consisting of an erase verify cycle and a program verify cycle.

6. The method of claim 1, wherein detecting an erase detection condition or a program detection condition of the first dual-ended storage devices of the first batch of dual-ended storage devices comprises:

receiving a current associated with the first dual-ended storage device;

biasing a current by a current offset to form a bias current;

the bias current is compared to a current threshold to detect an erase detection condition or a program detection condition.

7. The method of claim 6, wherein detecting an erase detection condition or a program detection condition in response to the sensed current comprises:

detecting an erase detection condition when the sensed current is less than the current threshold; or

A program detect condition is detected when the sensed current is greater than the current threshold.

8. The method of claim 1, wherein the two-terminal memory device comprises a resistive random access device (ReRAM device); and is

Wherein monitoring an erase detect condition or a program detect condition of each two-terminal memory device comprises monitoring an erase detect condition or a program detect condition of each of the ReRAM devices.

9. The method of claim 1, wherein the two-terminal memory device is selected from the group consisting of a phase change memory, a metal oxide memory, a silicon sub-oxide memory, a chalcogenide memory, a magnetic memory, a carbon nanotube memory, and a filament-based memory.

10. The method of claim 1, wherein after detecting an erase detection condition or a program detection condition of a last dual-ended memory device of the first batch of dual-ended memory devices, the method comprises:

in response to detecting an erase detection condition or a program detection condition of the last one of the first plurality of dual-ended memory devices, initiating an erase cycle or a program cycle of a third one of the second plurality of dual-ended memory devices, and

wherein the number of dual-ended storage devices of the first batch of dual-ended storage devices is in the range of 8 to 32.

11. A semiconductor device, comprising:

a first batch of dual-ended storage devices;

a second set of dual-ended storage devices;

a state adjustment enabling portion connected to the first and second batches of dual-ended memory devices, wherein the state adjustment enabling portion is configured to enable each dual-ended memory device in the first batch of dual-ended memory devices to enter a predetermined state, wherein the predetermined state is selected from the group consisting of an erased state and a programmed state;

a detection section connected to the first batch of dual-ended storage devices and the status adjustment enabling section, wherein the detection section is configured to detect an adjustment success condition for a dual-ended storage device of the first batch of dual-ended storage devices;

wherein the state adjustment enabling section is further configured to enable entering the first dual-ended storage device of the second batch of dual-ended storage devices into the predetermined state in response to detecting an adjustment success condition for the second dual-ended storage device of the first batch of dual-ended storage devices and prior to detecting an adjustment success condition for all dual-ended storage devices of the first batch of dual-ended storage devices.

12. The semiconductor device of claim 11, wherein the state adjustment enabling section is further configured to enable a third dual-ended storage device of the second batch of dual-ended storage devices to enter the predetermined state in response to detecting an adjustment success condition for a fourth dual-ended storage device of the first batch of dual-ended storage devices and prior to detecting adjustment success conditions for all dual-ended storage devices of the first batch of dual-ended storage devices.

13. The semiconductor device of claim 11, further comprising:

a verification section connected to the first batch of dual-ended storage devices, the second batch of dual-ended storage devices, the state adjustment enabling section, and the detection section, wherein the verification section is configured to verify that each of the dual-ended storage devices in the first batch of dual-ended storage devices reaches the predetermined state,

wherein the state adjustment enabling section is further configured to enable the first dual-ended storage devices of the second batch of dual-ended storage devices to enter a predetermined state in response to detecting an adjustment success condition of the second dual-ended storage devices of the first batch of dual-ended storage devices and in response to the verifying section verifying that the second dual-ended storage devices reach the predetermined state.

14. The semiconductor device of claim 11, wherein the state adjustment enabling portion is configured to enable the first two-terminal memory devices of the second plurality of two-terminal memory devices to enter the predetermined state without substantially verifying the predetermined state.

15. The semiconductor device of claim 14, wherein a verify cycle associated with the verifying of the predetermined state is selected from the group consisting of an erase verify cycle and a program verify cycle.

16. The semiconductor device according to claim 11, wherein the detection section comprises:

a first input configured to receive a current associated with the second dual-terminal storage device;

a bias circuit connected to the first input and configured to bias a current by a current offset to form a bias current;

a comparator connected to the bias circuit and configured to compare the bias current to a threshold current to determine a sensed current; and

a detector circuit connected to the comparator and configured to determine an adjustment success condition in response to the sensed current.

17. The semiconductor device of claim 16, wherein the detector circuit is configured to determine an adjustment success condition when the sensed current is less than a first threshold current, or

Wherein the detector circuit is configured to determine an adjustment success condition when the sensed current is greater than a second threshold current.

18. The semiconductor device of claim 11, wherein the first batch of two-terminal memory devices comprises resistive random access devices (ReRAM devices).

19. The semiconductor device of claim 11, wherein the first batch of two-terminal memory devices is selected from the group consisting of phase change memory, metal oxide memory, silicon sub-oxide memory, chalcogenide memory, magnetic memory, carbon nanotube memory, and filament-based memory.

20. The semiconductor device of claim 11, wherein the number of two-terminal memory devices in the first batch of two-terminal memory devices is in a range of 8 to 32.