CN115985381A - Capacitance measurement and apparatus for resistive switching memory devices - Google Patents
Capacitance measurement and apparatus for resistive switching memory devices Download PDFInfo
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Abstract
A semiconductor device, comprising: a two-terminal memory device characterized by a programming voltage range and a first capacitance, wherein the two-terminal memory device is coupled in parallel between ground and a first common node; a first capacitor having a second capacitance, coupled between ground and a second common node; a voltage source configured to provide an input voltage below a programming voltage range; a first operational amplifier comprising an inverting input, a non-inverting input, and an output, wherein the non-inverting input is coupled to the first voltage source, wherein the inverting input is coupled to the third common node, and wherein the output is coupled to the fourth common node; a first resistance means coupled between the third common node and the fourth common node, and wherein the first common node is coupled to the second common node and the third common node.
Description
Cross Reference to Related Applications
This patent application claims the benefit of U.S. provisional application No.62/888000 entitled "RERAM CAPACITANCE MEASUREMENT AND APPARATUS" filed on 2019, 8, 16, which is hereby incorporated by reference in its entirety AND for all purposes.
Documents incorporated by reference
U.S. patent application Ser. No.14/588185, filed on 31.12.2014, entitled "SELECTOR DEVICE FOR TWO-TERMINAL MEMORY", U.S. patent application Ser. No.14/717185, filed on 20.5.5.2015, entitled "NON-VOLATILE MEMORY SWITCHING O TERMINAL DEVICE AND A MOS TRANSISTOR", U.S. patent application Ser. No. 15/71717104, filed on 10.3.10.2015, entitled "SELECTOR-BASED NON-VOLATILE CELL manufactures ILUTZIZING IC-FOUNDRY COMPATIBLE PROCESSES", U.S. patent application Ser. No.15/066504, filed on 30.6.30.2015, entitled "SENGA NON-VOLATILE MEMORIZATION SELECTING INC" and U.S. patent application Ser. No. 20131/3214, filed on 31.6.31.7.A.A.S. NANOLATILE MEMORAL OF THE INVENTION, and incorporated by reference to this application Ser. No. 5.S. 5.3, and No. 325932.A, incorporated herein by reference, each.
Technical Field
Embodiments of the present disclosure relate to electronic memory structures; for example, various embodiments disclose apparatus and methods for measuring capacitance of an electronic memory device.
Background
The inventors have recognized a variety of solid-state memory architectures for modern electronic memories and computing devices. Tight control of the processes used to manufacture modern solid-state memory structures is important to create a properly functioning memory structure and to achieve tight consistency among multiple devices.
In various embodiments, the inventors of the present disclosure desire to minimize the impact of variations in the semiconductor manufacturing process. Process variations may differ between multiple semiconductor wafers produced by one process or between dies within a single wafer or both. These process variations, in turn, may result in performance variations for the memory structure on a given die. Performance variations outside of the acceptable manufacturing range are typically considered bad parts and discarded. This reduction in the acceptable yield of parts increases the indirect cost of the overall process. While some performance variations are small enough to remain within the target operating specification, they still adversely affect memory performance over time.
In view of the foregoing, the inventors desire new mechanisms to mitigate the effects of process variations that overcome the current challenges of dealing with existing memory structures in the art.
Disclosure of Invention
The following presents a simplified summary of the disclosure in order to provide a basic understanding of some aspects described herein. This summary is not an extensive overview of the disclosed subject matter. It is intended to neither identify key or critical elements of the disclosure nor delineate the scope of the innovation. Its sole purpose is to present some concepts of the disclosed subject matter in a simplified form as a prelude to the more detailed description that is presented later.
Various embodiments of the present invention relate to the fabrication of semiconductor two-terminal memory devices including arrays of non-volatile ReRAM memories currently being developed by Crossbar, inc. Further embodiments relate to the fabrication of semiconductor memory devices including volatile two-terminal resistive switching devices, such as selector devices (e.g., for example)
Selector device), also developed by Crossbar, inc. Further embodiments relate to the manufacture of semiconductor memory devices comprising one or more arrays of very high speed non-volatile memory devices, which accordingly comprise transistors, selector devices and optionally capacitors. Other embodiments relate to the fabrication of other two terminal memory devices, such as wire-like memory devices, magnetoresistive memory devices, phase change memory devices, carbon nanotube memory devices, conductive bridge memory devices, silicon sub-oxide memory devices, metal oxide memory devices, and the like.
In various types of two-terminal memory devices, and for more advanced semiconductor processing nodes, variations in the thickness of the memory layer can affect the operation of the memory device and peripheral circuits. Due to process variations, the memory layer thickness may differ between two-terminal memory devices within the same die, and between different dies across a wafer. Different thicknesses of the memory layers can have an effect on the characteristics of a two-terminal memory, such as programming, reading, and erasing voltages; program, read and erase speeds; program, read and erase features, and the like.
In some cases, differences in memory layer thickness can be compensated for by setting trim values and other parameters during program, read, or erase cycles. In other cases, the memory layer thickness may be too far out of specification to compensate for trim values, and such devices may be considered defective die. In either case, the ability to accurately measure these memory layer thickness variations during manufacturing can significantly improve the quality control of the manufacturing process, identify devices that are operating within acceptable ranges, identify appropriate trim values to facilitate proper operation from wafer to wafer and die to die, and generally optimize manufacturing costs.
Because electrical characteristics of a memory layer (e.g., programming, reading, and erasing conditions) may vary according to variations in a thickness of the memory layer, various implementations relate to efficient and effective mechanisms for determining the thickness of a memory layer of a two-terminal memory device. In some embodiments, the thickness can be measured directly from a cross-sectional image of the device. However, this technique is expensive and impractical on a production line. In other embodiments, the thickness may be determined indirectly by measuring the parasitic capacitance of the layers. In some embodiments, parasitic capacitance may be measured by connecting electronic equipment external to the die or wafer to electrical connection points on the surface of the die/wafer. These embodiments may be cumbersome and error prone if the contact points on the die/wafer surface are small, or may consume excessive die/wafer surface area if the contact is made large. These are also impractical on a production line. Furthermore, different portions of a memory layer or layers may not be selectively accessible through external contact points. Therefore, there is a need for indirect measurement of memory layer thickness within a semiconductor die or wafer, particularly in modern high volume production environments that facilitate accurate and repeatable measurements.
Some disclosed embodiments provide an on-die circuit that can be selectively connected to different sets of two-terminal resistive switching devices to measure the parasitic capacitance of the resistive switching devices from within the die itself. In some embodiments, the circuitry may be integrated within or between peripheral circuitry that controls access to an array of resistive switching devices (see, e.g., fig. 12, below), may be fabricated at least partially on a substrate of a die, at least partially within a memory layer of the die or other portion of the die, or a suitable combination of the foregoing. In one or more embodiments, the circuit may be a resistance-capacitance (RC) circuit that outputs a frequency that varies according to a parasitic capacitance of a resistive switching device coupled to the RC circuit. In further embodiments, the present disclosure may provide multiple on-die circuits on a die to measure different portions of a memory array. In other embodiments, the present disclosure may provide multiple circuits on different dies of a wafer to test memory layer uniformity across different portions of the wafer.
In an embodiment, the present disclosure provides a semiconductor device. The semiconductor device may include a first plurality of two-terminal memory devices, wherein each of the two-terminal memory devices is characterized by a programming voltage within a programming voltage range, wherein the first plurality of two-terminal memory devices is associated with a first capacitance, and wherein the first plurality of two-terminal memory devices is selectively coupled in parallel between ground and a first common node. Further, the semiconductor device may include: a first capacitor coupled between ground and a second common node, wherein the first capacitor is characterized by a second capacitance; and a first voltage source configured to provide a first input voltage, wherein the first input voltage is smaller than the programming voltage range. Additionally, the semiconductor device may include a first operational amplifier including an inverting input, a non-inverting input, and an output, wherein the non-inverting input is coupled to the first voltage source, wherein the inverting input is coupled to the third common node, and wherein the output is coupled to the fourth common node. Further, the semiconductor device may include a first resistance device coupled between a third common node and a fourth common node, wherein the first common node is coupled to the second common node and the third common node.
Further embodiments of the present disclosure provide a method for operating a semiconductor device. The method may include closing the first switch and coupling a first plurality of two-terminal memory devices to an inverting input of the first operational amplifier, wherein each two-terminal memory device of the first plurality of two-terminal memory devices is characterized by a programming voltage within a first programming voltage range, wherein the first capacitor is coupled between the inverting input of the first operational amplifier and ground, and wherein the first resistance device is coupled between the inverting input of the first operational amplifier and an output of the first operational amplifier. In addition to the above, the method may include providing a first input voltage to the non-inverting input of the first operational amplifier with a first voltage source, wherein the first input voltage is less than a minimum programming voltage in a first programming voltage range. The method may also include outputting a first signal with a first operational amplifier, wherein the first signal is characterized by a first oscillation frequency, wherein the first oscillation frequency is responsive to a first capacitance associated with the first plurality of two-terminal memory devices. Additionally, the method may include measuring a frequency value of the first oscillation frequency and storing an indicator associated with the first oscillation frequency measurement in the memory.
The following description and the annexed drawings set forth certain illustrative aspects of the specification. These aspects are indicative, however, of but a few of the various ways in which the principles of the specification may be employed. Other advantages and novel features of the specification will become apparent from the following detailed description of the specification when considered in conjunction with the drawings.
Drawings
Various aspects, embodiments, objects, and advantages of the present invention will become apparent from the following detailed description when considered in conjunction with the accompanying drawings in which like reference characters refer to like parts throughout. In the description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. It is understood, however, that certain aspects of the present disclosure may be practiced without these specific details or with other methods, components, materials, etc. In other instances, well-known structures and devices are shown in block diagram form in order to facilitate describing the present disclosure;
FIG. 1 depicts a schematic diagram of an example circuit for determining capacitance of one or more Resistive Switching Devices (RSDs) in a disclosed embodiment;
FIG. 2 shows a schematic diagram of an example circuit for providing a frequency output proportional to a capacitance of a switching device coupled to the circuit;
FIG. 3 depicts a disclosed embodiment for determining the capacitance of a non-volatile RSD;
FIG. 4 illustrates a disclosed embodiment for determining capacitance of a volatile RSD;
FIG. 5 depicts an embodiment for determining the capacitance of a memory cell having a volatile RSD in series with a non-volatile RSD;
FIG. 6 illustrates an embodiment for determining the capacitance of a plurality of RSDs or a memory cell comprised of volatile and non-volatile RSDs;
FIG. 7 depicts an embodiment for determining a relationship between the frequency of an RC circuit and the average capacitance of a set of RSDs coupled to the RC circuit;
FIG. 8 illustrates a flow chart of an example method for determining capacitance of a plurality of two-terminal memory devices of a memory array;
FIG. 9 depicts a flow diagram of an example method for adjusting trim values of a memory array using on-die capacitance determinations for memory devices of the array;
FIG. 10 depicts a flowchart of an example method for determining memory layer uniformity across multiple dies of a wafer in some disclosed embodiments;
FIG. 11 shows a flow diagram of an example method for determining a range of memory layer characteristics across a single die in further embodiments;
FIG. 12 depicts a block diagram of an example electronic operating environment, in accordance with certain embodiments of the present disclosure;
FIG. 13 illustrates a block diagram of an example computing environment for implementing one or more of the disclosed embodiments presented herein.
Detailed Description
As the name implies, a two-terminal resistive switching device has two terminals or electrodes. Herein, the terms "electrode" and "terminal" are used interchangeably; in addition, the two-terminal resistive switching device includes a non-volatile two-terminal memory device and a volatile two-terminal switching device. Typically, the first electrode of the two-terminal resistive switching device is referred to as a "top electrode" (TE) and the second electrode of the two-terminal resistive switching device is referred to as a "bottom electrode" (BE), but it should BE understood that the electrodes of the two-terminal resistive switching device may BE arranged in any suitable arrangement, including horizontally, where the components of the memory cell are (substantially) side-by-side rather than overlapping one another. Between the TE and BE of a two-terminal resistive switching device is typically an interface layer, sometimes also referred to as a switching layer, a Resistive Switching Medium (RSM), or a Resistive Switching Layer (RSL); however, such devices are not limited to these layers, and one or more barrier layers, adhesion layers, ion conducting layers, seed layers, etc., as disclosed herein, in any publications incorporated by reference, or as generally understood and used in the art, may BE included between or near one or more of the TE, BE, or interface layers consistent with the proper operation of such devices. Various embodiments of the present disclosure provide an array of memory devices including circuitry fabricated on a die having an array of memory devices for determining capacitance of one or more two-terminal resistive switching devices of the array. An architecture is also provided to control and operate an array of memory devices.
In general, the composition of memory cells can vary for devices having different components selected to achieve desired characteristics (e.g., volatile/non-volatile, on/off current ratios, switching times, read times, memory endurance, program/erase cycles, etc.). One example of a thread-based device may include: a conductive layer, such as a metal, metal alloy, metal nitride, (e.g., including TiN, taN, tiW, or other suitable metal compound); an optional interface layer (e.g., a doped p-type (or n-type) silicon (Si) carrier layer (e.g., p-type or n-type Si carrier layer, p-type or n-type polysilicon, p-type or n-type poly SiGe, etc.)); a Resistive Switching Layer (RSL); and an active metal-containing layer capable of being ionized. Under appropriate conditions, the active metal-containing layer can provide filament-forming ions to the RSL. In such embodiments, the conductive filament (e.g., formed of ions) may facilitate conductivity through at least a subset of the RSL, and, as one example, the resistance of the filament-based device may be determined by the tunneling resistance between the filament and the conductive layer. Memory cells having such characteristics may be described as being thread-based devices.
RSLs (which may also be referred to in the art as Resistive Switching Media (RSM)) may include, for example: undoped amorphous Si-containing layer, semiconductor layer having intrinsic characteristics, silicon nitride (e.g. SiN, si) 3 N 4 、SiN x Etc.), silicon sub-oxides (e.g., siO) x Where x has a value between 0.1 and 2), silicon nitride, metal oxides, metal nitrides, non-stoichiometric silicon compounds, and the like. Other examples of materials suitable for RSL may include Si X Ge Y O Z (where x, y and z are correspondingly appropriate positive numbers), silicon oxide (e.g., siO N Where N is a suitably positive number), silicon oxynitride, undoped amorphous silicon (a-Si), amorphous SiGe (a-SiGe), taO B (wherein B is an appropriate positive number), hfO C (wherein C is an appropriate positive number), tiO D (wherein D is an appropriate number), al 2 O E (where E is an appropriate positive number), or the like, nitrides (e.g., alN, siN), or appropriate combinations thereof.
In some implementations, an RSL used as part of a non-volatile memory device (non-volatile RSL) may include a relatively large number (e.g., compared to a volatile selector device) of material voids or defects to trap neutral metal particles (at least at low voltages) within the RSL. The large number of voids or defects may promote the formation of a thick, stable neutral metal particle structure. In such a structure, these trapped particles can hold the non-volatile memory device in a low resistance state in the absence of an external stimulus (e.g., power), thereby enabling non-volatile operation. In other embodiments, the RSL for a volatile selector device (volatile RSL) may have very few material voids or defects for trapping particles. The conductive filaments formed in such RSLs can be very thin (e.g., one to a few particles wide depending on the field strength, particle material or RSL material, or suitable combinations of the above) and unstable in the absence of a suitably high external stimulus (e.g., electric field, voltage, current, joule heating, or suitable combinations thereof) due to few voids/defects that trap particles. Furthermore, the particles can be selected to have a high surface energy and good diffusivity within the RSL. This results in a conductive filament that can be formed quickly in response to an appropriate stimulus, but that is also easily deformed, for example, in response to an external stimulus that drops below a magnitude of deformation (which may be lower than a magnitude of formation of an external stimulus associated with forming a volatile conductive filament, for example, in response to a current flowing through the selector device; see U.S. patent application No.14/755998, incorporated by reference above). Note that the volatile RSL and the conductive filament for the selector device may have different electrical characteristics than the conductive filament and the non-volatile RSL for the non-volatile memory device. For example, the selector means RSL may have a higher material resistance and may have a higher on/off current ratio, etc.
The active metal-containing layer for the thread-based memory cell may include, among others: silver (Ag), gold (Au), titanium (Ti), titanium nitride (TiN), or other suitable compounds of titanium, nickel (Ni), copper (Cu), aluminum (Al), chromium (Cr), tantalum (Ta), iron (Fe), manganese (Mn), tungsten (W), vanadium (V), cobalt (Co), platinum (Pt), hafnium (Hf), and palladium (Pd). In some aspects of the present disclosure, other suitable conductive materials as well as compounds, nitrides, oxides, alloys, or combinations of the foregoing or similar materials may be used for the active metal-containing layer. Further, in at least one embodiment, non-stoichiometric compounds such as non-stoichiometric metal oxides or metal nitrides (e.g., alO) x 、AlNx、CuOx、CuNx、AgOx、AgNx, etc., where x is a suitable positive number 0 < x < 2, which may have different values for different non-stoichiometric compounds) or other suitable metal compounds may be used for the active metal-containing layer.
In one or more embodiments, the disclosed wire resistive switching devices may include an active metal layer comprising a metal nitride selected from the group consisting of: tiNx, taNx, alNx, cuNx, WNx, and AgNx, where x is a positive number. In further embodiments, the active metal layer may include a metal oxide selected from the group consisting of: tiOx, taOx, alOx, cuOx, WOx, and AgOx. In yet another or more embodiments, the active metal layer may include a metal oxynitride selected from the group consisting of: tiOaNb, alOaNb, cuOaNb, WOaNb, and AgOaNb, wherein a and b are positive numbers. The disclosed filamentary resistive switching devices may also include a switching layer comprising a switching material selected from the group consisting of: siOy, alNy, tiOy, taOy, alOy, cuOy, tiNx, tiNy, taNx, taNy, siOx, siNy, alNx, cuNx, cuNy, agNx, agNy, tiOx, taOx, alOx, cuOx, agOx, and AgOy, wherein x and y are positive numbers, and y is greater than x. Various combinations of the above are contemplated and considered to be within the scope of embodiments of the present invention.
In one example, the disclosed filamentary resistive switching devices include a particle donor layer (e.g., an active metal-containing layer) that includes a metal compound and a resistive switching layer. In an alternative embodiment of this example, the particle donor layer comprises a metal nitride: MNx, such as AgNx, tiNx, alNx, etc., and the resistive-switching layer comprises a metal nitride: MNy, such as AgOy, tiOy, alOy, and the like, where y and x are positive numbers, and in some cases y is greater than x. In an alternative embodiment of this example, the particle donor layer comprises a metal oxide: MOx, such as AgOx, tiOx, alOx, etc., and the resistive switching layer includes a metal oxide: MOy, such as AgOy, tiOy, alOy, and the like, where y and x are positive numbers, and in some cases y is greater than x. In yet another alternative, the metal compound of the particle donor layer is MNx (e.g., agNx, tiNx, alNx, etc.) and the resistive switching layer is selected from the group consisting of MOy (e.g., agOx, tiOx, alOx, etc.) and SiOy, where x and y are typically non-stoichiometric values, or vice versa in yet another embodiment.
As used herein, variables x, a, b, etc., representing values or ratios of one element relative to another (or other) element in a compound can have different values that apply to the corresponding compound, and are not intended to represent the same or similar values or ratios in the compound. Some details regarding embodiments of the present disclosure similar to the examples described above may be found in the following U.S. patent applications, assigned to the assignee of the present patent application: application nos. 11/875541 filed on 10/19/2007 and 12/575921 filed on 10/8/2009; each of the foregoing patent applications, except those incorporated by reference elsewhere herein, is incorporated by reference herein in its respective entirety and for all purposes.
It should be understood that various embodiments herein may utilize a variety of memory cell technologies having different physical characteristics. For example, different resistive switching memory cell technologies may have different discrete programmable resistances, different associated program/erase voltages, and other differentiating characteristics. For example, various embodiments of the present disclosure may employ a bipolar switching device that exhibits a first switching response to an electrical signal of a first polarity (e.g., programming to one of a set of programmed states) and a second switching response to an electrical signal having a second polarity (e.g., erasing to an erased state). For example, a bipolar switching device is in contrast to a unipolar device that exhibits both a first switching response (e.g., programming) and a second switching response (e.g., erasing) in response to electrical signals having the same polarity and different magnitudes.
In various embodiments, the wire-based resistive switching devices may operate in a bipolar manner to behave differently in response to external stimuli of different polarities (or directions, energy flows, energy source orientations, etc.). For volatile filament-based selector devices, as an illustrative example, in response to a first polarity stimulus exceeding a first threshold voltage (or set of voltages), the filament-based selector device may change from a first resistance state to a second resistance state. Further, the filament selector device may change from the first state to a third state in response to a second polarity stimulus exceeding a second threshold voltage. In some embodiments, the third state may be substantially the same as the first state, have the same or similar measurably different characteristics (e.g., conductivity, etc.), have the same or similar threshold stimulation amplitude (although opposite polarity or direction)), and so forth. In other embodiments, the third state may differ from the second state in measurable characteristics (e.g., different conductivity values in response to reverse polarity as compared to forward polarity) or in threshold stimulation associated with an overshoot of the first state (e.g., different magnitude of positive voltage required to transition to the second state as compared to magnitude of negative voltage required to transition to the third state).
For bipolar operation of a non-volatile, wire-based memory cell, a conductive path or filament is formed through the non-volatile RSL in response to an appropriate programming voltage applied across the memory cell. In particular, upon application of a programming voltage, metal ions are generated from the active metal-containing layer and migrate into the non-volatile RSL layer. The metal ions may occupy voids or defect sites within the non-volatile RSL layer. In some embodiments, after removing the bias voltage, the metal ions become neutral metal particles and remain trapped in voids or defects of the non-volatile RSL layer. When enough particles are trapped, a filament is formed and the memory cell switches from a relatively high resistance state to a relatively low resistance state. More specifically, the trapped metal particles provide a conductive path or filament through the non-volatile RSL layer, and the resistance is typically determined by the tunneling resistance through the non-volatile RSL layer. In some resistive switching devices, an erase process may be performed to deform the conductive filament to at least partially return the memory cell from a low resistance state to a high resistance state. More specifically, upon application of an erase bias voltage, metal particles trapped in voids or defects of the non-volatile RSL become mobile ions and migrate back towards the active metal layer. In the context of memory, such state changes may be associated with the respective states of the binary bits. For an array of multiple memory cells, one or more words, one or more bytes, one or more pages, one or more blocks, etc. of memory cells may be programmed or erased to represent a zero or one in the binary information, and the binary information is effectively stored by retaining these states over time. In various embodiments, multiple levels of information (e.g., multiple bits) may be stored in such memory cells.
Without specifying a particular memory cell technology or program/erase voltage for the various aspects and embodiments herein, these aspects and embodiments are intended to be combined with any suitable memory cell technology and operated by a program/erase voltage suitable for that technology, as would be known to one of ordinary skill in the art or made known to one of ordinary skill by the context provided herein. It should also be understood that implementations or signal level variations including substituted memory cell technologies are considered to be within the scope of the present disclosure in the event that replacement of a different memory cell technology would require circuit modifications known to those of ordinary skill in the art or changes in operating signal levels known to such skilled persons.
As described above, application of a programming voltage (also referred to as a "programming pulse") to one of the electrodes of a two-terminal memory may cause a conductive filament to form in an interface layer (e.g., RSL). By convention, and as generally described herein, the TE receives the programming pulse and the BE is grounded (or held at a lower voltage or opposite polarity than the programming pulse), but this is not intended to limit all embodiments. Conversely, applying an "erase pulse" to one of the electrodes (typically a pulse of opposite polarity to the program pulse or an electrode opposite the program pulse) may disrupt the continuity of the filament, for example, by driving metal particles or other materials forming the filament back to the active metal source. The characteristics of such a conductive filament, and its presence or absence, affect the electrical characteristics of a two-terminal memory cell, such as, for example, decreasing the resistance between the two terminals and/or increasing the conductance between the two terminals when the conductive filament is present as compared to when the conductive filament is not present.
After a program or erase pulse, it can be a read pulse. The read pulse is typically lower in amplitude than the program or erase pulse and is typically insufficient to affect the conductive filament and/or change the state of the two-terminal memory cell. By applying a read pulse to one of the electrodes of the two-terminal memory, the measured current (e.g., ion) may indicate the conductive state of the two-terminal memory cell when compared to a predetermined threshold current. The threshold current may be preset based on an expected current value for the two-terminal memory device for a given two-terminal memory technology at different states (e.g., high resistance state current; corresponding current for one or more low resistance states, etc.). For example, when a conductive filament has been formed (e.g., in response to application of a programming pulse), the conductance of the cell is greater than would otherwise be the case, and the measured current (e.g., ion) reading in response to the reading pulse will be greater. On the other hand, when the conductive filament is removed (e.g., in response to applying an erase pulse), the resistance of the cell is higher because the interface layer has a relatively higher resistance, so the conductance of the cell is lower, and the measured current (e.g., ioff) reading in response to the read pulse will be smaller. Conventionally, when a conductive filament is formed, the memory cell is said to be in an "on state" with high conductance. When the conductive filament is not present, the memory cell is said to be in an "off state". Memory cells in either an on state or an off state may be logically mapped to binary values such as, for example, "1" and "0". It should be understood that the convention used herein that is associated with the state of a cell or associated logical binary mapping is not intended to be limiting, as other conventions, including the reverse convention, may be used in connection with the disclosed subject matter. The techniques detailed herein are described and illustrated in connection with Single Level Cell (SLC) memory, but it should be understood that the disclosed techniques may also be used with multi-level cell (MLC) memory where a single memory cell may retain a set of measurably different states representing multi-bit information.
Digital information may be stored in such devices by mapping the digital information to the non-volatile resistance state of the two-terminal memory cell. Electronic devices comprising many of these two-terminal memory cells can also store large amounts of data. The high density array is configured to include as many memory cells as possible for a given chip space area, thereby maximizing the data storage capacity of the memory chip or system-on-chip device.
For two-terminal memories (e.g., crossbar arrays) formed at intersections of metal lines within a wafer, the inventors of the present disclosure have recognized two general conventions for arranging memory cells. The first convention is a 1T1R memory array, in which each memory cell is isolated from the electrical effects (e.g., current flow, including leakage path current) of surrounding circuitry by an associated transistor. The second convention is a 1TnR memory array (n is a positive number greater than 1) in which multiple memory cell groups are isolated from the electrical effects of surrounding circuitry by one (or more) transistors. In the 1T1R background, individual memory cells may be configured with high current rejection between memory cells, thereby significantly reducing leakage path current of the 1T1R memory array.
One example mechanism for connecting a 1T1R memory array includes a first terminal of a two-terminal resistive memory device connected to a drain of a transistor. A second terminal of the two-terminal resistive memory device may be connected to a bit line of the 1T1R memory array. Depending on the erase/program conditions of the memory array, the source of the transistor is grounded or used as a source of an erase or program signal. Another example mechanism involves a three-terminal memory including a transistor coupled to a volatile two-terminal resistive switching device. A first terminal of the volatile RSD is connected to the gate of the transistor and a second terminal of the volatile RSD is connected to a voltage source. Volatile RSDs allow charge to accumulate at the gate of a transistor when activated, and can trap the accumulated charge at the transistor gate when deactivated. Other Resistive Switching Device (RSD) circuits may be used within the scope of the present disclosure.
Fig. 1 shows an example of a circuit 100 according to various embodiments of the present invention. Such circuitry, or suitable variations thereof, may be included in a semiconductor die incorporating two-terminal memory cells. In some embodiments, such circuitry may be included in one die on a semiconductor wafer, multiple dies on a semiconductor wafer, or all of the dies on a semiconductor wafer. The circuit 100 may be configured to selectively connect to one or more Resistive Switching Devices (RSDs) 114 on a given die to determine the capacitance of the RSD. From the capacitance determination, characteristics of the memory layer in which the RSD is formed may be estimated or inferred. Typically, the RSD114 is a two-terminal resistive switching device, but a three-terminal RSD114 incorporating a volatile selector RSD and a transistor (and optional capacitor) may also be well utilized.
FIG. 1 shows an operational amplifier 104 (OPAMP) having an inverting input 102A (-), a non-inverting input 102B (+) and an output 106 (out). Resistor R1 110 is connected between output 106 and inverting input 102A of operational amplifier 104. In addition, capacitor C1116 is connected between inverting input 102A and ground. In an embodiment, the terminals of capacitor 116 and resistor 110 are connected to respective nodes, which are in turn connected to inverting input 102A. In at least one embodiment, these respective nodes may all be a single common node 112, as shown.
Inverting input 102A may also be connected at its first terminal to RSD114. In an embodiment, the two-terminal RSD114 may include a plurality of RSDs respectively connected in parallel between the common node 112 and ground. In another embodiment, the (two-terminal) RSD114 may be selectively connected and disconnected from the common node 112 and the circuit 100 (e.g., by a switch, multiplexer, or other suitable electrical connection; see fig. 2, below). Still further, the non-inverting input 102B may be connected to a voltage source Vref, which may be configured to provide a selected voltage, voltage amplitude, voltage waveform, etc. to the non-inverting input 102B. The output 106, if the operational amplifier 104 is additionally coupled to a (frequency) divider, such as a divide by an N-way divider circuit (— N-/N; where N is a suitable positive number).
As described above, RSD114 is coupled at one terminal (or terminals) thereof to inverting input 102A (e.g., through common node 112). RSD114 is coupled to inverting input 102A to mimic capacitor C RSD May be in a non-conductive state. For nanoscale RSD technologies, the capacitance of a single RSD may be very small. For reasonable accuracy in determining the capacitance value of RSD114, the capacitance of RSD114 should be within the order of magnitude of C1116 (or any suitable value or range therebetween), and preferably within the range of about 1/3 to about 3 times the magnitude of C1116, or any suitable range or value therebetween. However, a stated value is within the meaning of the term "about" as used herein, unless the context clearly dictates otherwise, a variation within the range of one tenth to a few tenths of the stated voltage (e.g., the range of 0.1 volts, 0.2 volts, 0.3 volts, 0.1 volts-0.5 volts, or an appropriate value between the two) or a few percent of the stated value (e.g., 1% -25%, 5-20%, 1-15%, 5-15%, or any appropriate value therebetween, or any appropriate range of percentages therebetween). It is to be understood that terms of "about," or other terms of degree, as used herein are intended to refer to the changes, ranges, or values specified herein, or those reasonably understood by one of ordinary skill, to provide the same or similar functions and operations as a given component of a device, component or element of a device, or method or step thereof described. Thus, the term of degree generally refers to a value or range that one of ordinary skill in the art would understand to facilitate operation of the various embodiments described.
In order to achieve a capacitance C in the desired range RSD Multiple RSDs 114 may be connected in parallel to add their respective capacitances to a larger combination C RSD . Where the two-terminal RSD114 includes multiple resistive switching devices, the devices may be connected in parallel at respective first terminals (e.g., at the common node 112) and grounded at their second terminals. In the case of a three terminal RSD114 comprising a volatile selector and a transistor (and optional capacitor), the first terminal of the volatile selector is selectively connected to the inverting input 102A, and its second terminal is connected to the gate of the transistor. A plurality of such three-terminal RSDs 114 may be connected in parallel at their respective volatile selector first terminals.
At each locationIn one embodiment, any suitable number of RSDs 114 may be used in parallel combinations, such as 10,000 to 20,000; 20,000 to 60,000, etc., or any suitable range of values therebetween. Since each resistive switching device has a small capacitance, by coupling a large number of devices in parallel, the small capacitances add up until shown as C RSD The larger RSD capacitance.
In operation, the voltage source provides a voltage Vref that is lower than the programming voltage (or range of lower programming voltages) of the RSD114. In this way, the voltage applied to the two terminal memory device should not affect the programmed state of the resistive switching device. In some implementations, the programming voltage of a non-volatile two-terminal memory device is approximately 1 volt, for example, so the applied Vref should be less than 1 volt, such as 0.2 volts, 0.4 volts, 0.6 volts, 0.8 volts, etc., or any suitable value or range of values therebetween. Further, vref is not limited by this example, and other voltages less than the switching voltage of RSD114 may be used. Thus, vref may have: a value or range of values (e.g., 0.2-1.0 volts or any suitable value or range therebetween) for a non-volatile two-terminal resistance random access memory (ReRAM); different values/ranges of values for non-volatile phase change, magnetoresistive, conductive bridging, or other suitable non-volatile memory; another value/range of values for the volatile two-terminal selector device (e.g., 0.1 volts-1.0 volts, or any suitable value or range therebetween); and another value/range of values of the non-volatile three-terminal RSD comprising a volatile two-terminal selector device (and optional capacitor) coupled to the gate of the transistor.
In response to the application of Vref, circuit 100 will begin to oscillate or "ring" and the output of operational amplifier 104 at output node 106 will oscillate at a detectable frequency. This oscillation is a result of the time delay in the rise of the voltage between non-inverting input 102B and inverting input 102A, and R (of resistor 110) of RC circuit 100 (of capacitor C) 1 116+C RSD 114) is proportional to C. When the voltage Vref of the non-inverting input 102B is higher than the inverting input 102A, the output of the operational amplifier 104 increases; when the voltage of the inverting input 102A is higher than Vref at the non-inverting input 102B, the operational amplifierIs inverted and lowered. The RC circuit 100 provides a delay that facilitates summing the operational amplifier output with a capacitance: c 1 And C RSD Proportional detectable frequency oscillations.
In some embodiments, the voltage source may adjust Vref to a different voltage, below the minimum programming voltage within the appropriate programming voltage range associated with RSD114. For example, where the programming voltage of the RSD114 ranges between about 1.2 volts to about 1.5 volts, vref may be set to a different voltage that is at least less than 1.2 volts or lower. In some embodiments, different values of Vref may cause operational amplifier 104 to oscillate at different frequencies. In other embodiments, the operational amplifier 104 may oscillate around the same oscillation frequency with different applied Vref voltages.
In other embodiments, a frequency divider 107 is provided. In at least one example, divider 107 may be a counter circuit, but the disclosure is not limited by this particular example. The frequency divider 7 may be configured to reduce the output of the operational amplifier 104 to a smaller frequency. In some embodiments, divider 7 may be configured (e.g., pre-fabricated) for a fixed frequency reduction factor (e.g., 20x, 50x, 100x, 1000x reduction, etc.) or may be programmed (e.g., post-fabricated) to one of a set of programmable frequency reduction values. Thus, as one example, divider 7 may be configured to provide a reduced frequency in MHz at divider output 108 in response to the original output in GHz of operational amplifier 104 at output 106. As another example, frequency divider 7 may receive a signal at a MHz frequency at output 106 and output a signal at a KHz frequency at output 108, and so on.
Based on the measured or otherwise determined oscillation frequency, trim values of the memory array may be adjusted for proper operation. Such trim values may relate to programming, reading or erasing: voltage, current, cycle period, cycle step, voltage or current ramp value or ramp/ramp rate, or the like, or a suitable combination of the foregoing. For example, the program, read and erase cycles may include applying different pulse widths having different amplitudesOne or more voltage pulses of different pulse-to-pulse relationships (e.g., ramp up, ramp down, ramp up rate, ramp down rate, etc.), different overall timing of cycles, different current limits, etc. In at least some disclosed embodiments, one, more, or all of these parameters may be modified by the trim values described above. As a non-limiting illustrative example, in response to a lower relative oscillation frequency, a higher C may be inferred RSD Indicating that the memory layer is relatively thick. The trim value associated with the programming time of the RSD114 may be increased to compensate for the thicker memory layer. For higher relative oscillation frequencies, the opposite is true, indicating that the memory layer is relatively thin.
The trim values and the circuitry for adjusting the trim values are typically included in on-die (non-volatile, etc.) memory. In some embodiments, a die incorporating embodiments of the present disclosure may be placed on a test apparatus or the like, and the oscillation frequency determined by the test apparatus. The trim value may then be programmed by a register embedded within the die using the test device. In other embodiments, the die may include additional circuitry (not depicted) that may automatically determine an appropriate trim value based on the measured oscillation frequency at output 108 and a programmed capacitance value associated with the measured oscillation frequency. Measured oscillation frequency and C RSD May be stored in a memory (not depicted, but see fig. 12 and 13 below) as a look-up table, database, or other suitable data management structure.
In various embodiments, the relationship between the oscillation frequency at output 108 and the thickness of the memory layer, as well as appropriate trimming values, may be determined at least in part from experimental data. These relationships may then be stored on the die in some embodiments, or on the test device in other embodiments, and accessed in response to determining the oscillation frequency. These relationships may then be used to set the trim value of the RSD114 at production, for example, in a production plant or test facility.
In other embodiments, circuit 100 may be replicated in a subset of dies on a semiconductor wafer. In such embodiments, the oscillation frequency of the RSD in one die on the wafer, e.g., at the 12 o 'clock position die on the wafer, may be compared to the oscillation frequencies determined for other die on the wafer, e.g., at the 6 o' clock, 3 o 'clock, 9 o' clock, etc. position die on the wafer. If the oscillation frequencies are substantially similar, this may indicate a uniform memory layer thickness across the wafer. Conversely, if the oscillation frequencies are different, this may indicate non-uniformity in the memory layer thickness across the wafer. In some cases, non-uniformities may be compensated for by setting trim values on die determined to have memory layer thicknesses outside of a target value or range of values to achieve a target RSD performance. However, in other cases, the difference may be outside of an acceptable correction range, and such a die may be identified as defective. The large difference in memory layer thickness can be used to indicate a problem with the manufacturing process (e.g., material deposition non-uniformity) and thus can be used for diagnostics and process corrections are needed.
Fig. 2 illustrates an embodiment of an RC circuit 100 for determining capacitance of one or more resistive switching devices within a die of a semiconductor device in a further embodiment. The RC circuit 200 may include an operational amplifier 104 having inverting and non-inverting inputs (e.g., as described above for fig. 1) and an output 106. The output 106 may be input to an optional divider circuit 107, but the divider circuit 107 is not necessary in all embodiments. The resistor 110 is coupled between the output 106 of the operational amplifier 104 and a common node 224 connected to the inverting input of the operational amplifier 104. Further, the capacitance may be connected to the second common node 222 and ground, as shown. In an embodiment, the second common node 222 and the common node 224 may be the same electrical node. One or more RSDs may be selectively connected to the second common node 222, the common node 224, or both, through a switching circuit 230. The switching circuitry 230 may be embodied by a switch, multiplexer, or other suitable mechanism for selectively connecting the first plurality of RSDs 114 with a node (e.g., common node 224, second common node 222, … …), selectively disconnecting the first plurality of RSDs 114 from a node, and selectively connecting or disconnecting the second plurality of RSDs (not depicted) from a node.
As known to those of ordinary skill in the art, although fig. 2 shows a single capacitor C coupled to the third common node 220 RSD But a capacitance C RSD May be the sum of (first) multiple RSDs 114 connected in parallel. It should be understood that the capacitance C RSD May vary as different pluralities of RSDs (not depicted) are connected to the third common node 220, including different RSDs, different numbers of RSDs, etc. Furthermore, in some embodiments, the connection to the third common node 220 may be fixed within the memory array at the time of manufacture (e.g., the first plurality of RSDs may all be coupled to a common bit line, word line, source line, etc. at the time of manufacture). However, in alternative embodiments, the (first) plurality of RSDs 114 connected to the third common node 220 may instead be selectively provided by a multiplexer or other switching circuitry configured to selectively connect respective subsets of RSDs of the memory array to the third common node 220. Other embodiments not specifically shown or described herein but known to those of ordinary skill in the art or reasonably conveyed by the context provided herein are considered to be within the scope of the present disclosure.
An output is generated at an output node 108 in response to a voltage Vref applied at a non-inverting input of the operational amplifier 104 of the RC circuit 104. The output oscillates with an amplitude 210 and has a period 212 defining the oscillation frequency. The amplitude 210 may be controlled by the voltage value of Vref. Because the output (e.g., output 106) is provided by resistor 110 at node 224, vref is selected to maintain amplitude 210 at a voltage that is less than the programming voltage associated with the plurality of RSDs 114 (or less than the minimum programming voltage in the range of programming voltages). This prevents bit disturbance of memory devices associated with the multiple RSDs 114 (see, e.g., fig. 3 and 4, below). In some embodiments, vref may be selected to measure a capacitance of a two-terminal non-volatile memory component of an RSD that includes a two-terminal volatile selector device electrically in series with the two-terminal non-volatile memory component (e.g., see fig. 5 below). In such embodiments, vref may be selected to have a magnitude large enough to activate the selector device components of the RSD(s) 114, but small enough to prevent programming or erasing of the two-terminal non-volatile memory components of the RSD(s) 114.
As shown in FIG. 2, the output frequency produced at output node 108 is equal to 1/period 212 and is ANDed (C) RSD +C 1 ) Is in direct proportion. Thus, C RSD And an output frequency-C 1 Is in direct proportion. Thus, by measuring the frequency and subtracting C 1 To determine C RSD . In the case where a single RSD114 is coupled to the third common node 220, C RSD Is the capacitance value of a single RSD114. In the case where multiple RSDs 114 are coupled to a third common node 220, C RSD Representing the sum of the capacitances of the plurality of RSDs 114. By dividing by the number of RSDs in the plurality of RSDs 114, the average capacitance for each RSD may be determined.
FIG. 3 illustrates a schematic diagram of an example circuit 300 including shunt capacitances in further disclosed embodiments. The parallel capacitor comprises a capacitor having a known capacitance C 1 In electrical parallel with one or more two-terminal non-volatile RSDs 302. The one or more two-terminal non-volatile RSDs 302 may include a single RSD having a first terminal connected to the node 220 and a second terminal connected to ground. Alternatively, the two-terminal non-volatile RSD 302 may include a plurality of two-terminal non-volatile resistive switching memory devices having respective first terminals connected in parallel at the common node 220 and second terminals connected to ground. The switching device 230 may electrically couple the first terminal to the node 222 and the capacitor C 1 116 are connected in parallel.
The current-voltage response 320 of the two-terminal non-volatile RSD 302 is also shown (but not necessarily to scale). To measure the capacitance of the two-terminal non-volatile RSD 302, the device should be in an erased (high resistance) state. To prevent the RSD 302 from programming to a low resistance state, the voltage across the RSD 302 should remain less than the programming voltage amplitude (or a range of possible programming voltage amplitudes associated with the RSD 302 (e.g., 1.2 to 1).7 volts) is applied (e.g.,<1.2 volts) small). V P Example programming voltage magnitudes associated with changing the RSD 302 from a high resistance state (mimicking capacitance) to a low resistance state (mimicking resistance) are shown. For example, by maintaining the voltage across the RSD 302 at V P Hereinafter, the (average) capacitance of the RSD 302 may be determined as described herein.
FIG. 4 illustrates a schematic diagram of an example circuit 400 including shunt capacitances in other disclosed embodiments. The parallel capacitor comprises a capacitor having a known capacitance C 1 Electrically in parallel with one or more two-terminal volatile RSDs 402. In an embodiment, the one or more two-terminal volatile RSDs 402 may be two-terminal volatile selector devices. In some embodiments, RSD402 may be a single RSD having a first terminal connected to node 220 and a second terminal connected to ground. Alternatively, the RSD402 may include a plurality of two-terminal volatile RSDs having respective first terminals connected in parallel at the common node 220 and second terminals connected to ground. The switching device 230 may electrically couple the first terminal to the node 222 and the capacitor C 1 116 are connected in parallel.
A current-voltage response 420 of the two-terminal volatile RSD402 is shown. The depicted current-voltage response 420 corresponds to (but is not necessarily to scale) that was developed by the assignee of the present patent application
A selector device. To measure the capacitance of the two-terminal volatile RSD402, the device should be in an inactive (high resistance) state, corresponding to a positive switching voltage as shown: v S Negative switching voltage: -V S The voltage value in between. Starting from 0 volts and increasing the applied voltage to less than V S (or-V) S ) Prevents the volatile RSD402 from switching to a low resistance state. For example, the voltage across the RSD 302 should be kept at a higher than switching voltage magnitude (e.g.,<1.0 volts) or a minimum switching voltage magnitude (e.g.,<0.8 volts) of small amplitude. For example,by maintaining the voltage across the volatile RSD402 at-V S To V S In between, the (average) capacitance of the RSD402 may be determined as described herein.
Fig. 5 illustrates a diagram of an example circuit 500 including shunt capacitances in other disclosed embodiments. The parallel capacitor comprises a capacitor having a known capacitance C 1 In electrical parallel with one or more memory cells 502, 504. The first memory cell 502 may include a two-terminal memory cell 502 including a two-terminal volatile switching device electrically connected in series with a two-terminal non-volatile memory device. The current-voltage response (but not necessarily to scale) of the two-terminal memory cell 502 is provided at 520. In another embodiment, the second memory cell 502 may include a three-terminal memory cell 504, which may include a two-terminal volatile switching device connected at one terminal to the gate of a CMOS transistor. In either embodiment, the memory cells 502, 504 may be a single two-terminal memory cell 502 having a first terminal connected to the node 220 and a second terminal connected to ground or a single three-terminal memory cell 504 having a two-terminal selector device with a first selector terminal connected to the node 220 and a second selector terminal connected to the gate of the CMOS transistor. Alternatively, the RSD 502 may include a plurality of memory cells 502, 504 having respective first terminals connected in parallel at the common node 220 and second terminals connected to ground or to respective gates of respective CMOS transistors.
For memory cell 502, in some embodiments, the capacitance of the combined volatile selector and non-volatile memory device of memory cell 502 may be measured, or the capacitance of a two-terminal non-volatile memory device that does not include a two-terminal volatile selector device may be measured. In the first case, vref remains below the switching voltage amplitude V S or-V S To maintain the selector device in a high resistance state. In this manner, volatile selector devices and non-volatile memory devices may be measured as described hereinThe capacitance of the series combination of (a). In other embodiments, vref may be increased to V S The programming voltage V is maintained at P Hereinafter, to measure the capacitance of a memory device that does not include a selector device. For memory cell 504, the capacitance of the volatile selector device of memory cell 504 may be adjusted by maintaining Vref at the switching voltage magnitude V S or-V S The following is simply measured to keep the selector means in a high resistance state.
Fig. 6 illustrates an embodiment 600 in which a plurality of resistive switching devices 610 are electrically coupled in parallel to measure a combined capacitance of the plurality of resistive switching devices 610. As shown, each two-terminal RSD 602 is connected in parallel with each other and to a capacitor C 1 116. In various embodiments, the number of resistive switching devices 610 may be: about 10, about 100, about 1000, about 10000, about 20000, about 60000 or more; may be in the range of about 10 to about 100, in the range of about 100 to about 1000, in the range of about 1000 to about 10000, in the range of about 10000 to about 20000, in the range of about 20000 to about 60000 or greater; or may be any suitable number between those explicitly identified or may be any suitable range of values between those explicitly identified.
FIG. 7 illustrates an alternative embodiment 700 for characterizing capacitance of a memory device array. A set of Vref voltages may be applied to a plurality of memory devices, producing a range of capacitance measurements according to the RC measurement circuit described herein. The capacitance 704 and frequency 702 used for such measurements are shown in fig. 7. The best fit frequency versus capacitance 706 may be plotted to characterize the memory devices of the array.
The schematic diagrams included herein are described with respect to interaction between a number of memory devices, memory device components, memory arrays, or electronic circuits. It will be understood that such schematic diagrams may include those memory devices, components, arrays, and circuits specified therein, some of the specified memory devices/components/arrays/circuits, or suitable alternative or additional memory devices/components/arrays/circuits. Sub-components of a circuit or memory device may also be implemented as electrically connected to other sub-components rather than included in a parent circuit, where appropriate. Likewise, according to other embodiments, the various components may be implemented in a combined architecture. Moreover, some disclosed embodiments can be implemented as part of other disclosed embodiments, where appropriate.
Still further, one or more of the disclosed processes may be combined into a single process that provides aggregate functionality. For example, a program or erase process may include a read/verify process, or vice versa, to facilitate programming/erasing memory cells and verifying completion of programming/erasing by a single process. Further, it should be understood that rows of multiple memory device architectures may be erased in groups (e.g., multiple rows simultaneously) or individually. Further, it should be understood that multiple memory cells on a particular row may be read or programmed in groups (e.g., multiple memory cells are read/programmed at the same time) or individually. The components of the disclosed architecture may also interact with one or more other components not specifically described herein but known to those of ordinary skill in the art or reasonably apparent from the context provided herein.
Referring to fig. 8, an example flow diagram of a method 800 for characterizing a memory array of semiconductor dies in the additional disclosed embodiments is depicted. At 802, method 800 may include closing a first switch and coupling a first plurality of two-terminal memory devices to an inverting input of a first operational amplifier, wherein each of the first plurality of two-terminal memory devices is characterized by a programming voltage within a first programming voltage range. In an embodiment, the first capacitor may be coupled between the inverting input of the first operational amplifier and ground, and the first resistance device may be coupled between the inverting input of the first operational amplifier and the output of the first operational amplifier. In response to closing the first switch, the first capacitor and the first resistance device may be electrically parallel to the first plurality of two-terminal memory devices.
At 804, the method 800 may include providing a first input voltage to a non-inverting input of a first operational amplifier with a first voltage source, wherein the first input voltage is less than a minimum programming voltage in a first voltage range. At 806, the method 800 may include outputting a first signal with a first operational amplifier, wherein the first signal is characterized by a first oscillation frequency, wherein the first oscillation frequency is responsive to a first capacitance associated with the first plurality of two-terminal memory devices.
At 808, method 800 may include measuring a frequency value of the first oscillation frequency. At 810, method 800 may include storing an indicator associated with the first oscillation frequency measurement in a memory.
In an embodiment, a first plurality of two-terminal memory devices, a first switch, a first operational amplifier, a first capacitor, a first resistance device, and a first voltage source are formed within a first die of a plurality of dies formed on a semiconductor device. In further embodiments, a second die of the plurality of dies includes a second plurality of two-terminal memory devices, a second switch, a second operational amplifier, a second capacitor, a second resistance device, and a second voltage source. In such embodiments, the method 800 may further include closing a second switch and coupling a second plurality of two-terminal memory devices to the inverting input of the second operational amplifier, wherein each of the second plurality of two-terminal memory devices is characterized by a second programming voltage within a second programming voltage range. Further, in various embodiments, a second capacitor may be coupled between the inverting input of the second operational amplifier and ground, and a second resistance device may be coupled between the inverting input of the second operational amplifier and the output of the second operational amplifier. In further embodiments, the method 800 may include providing a second input voltage to the non-inverting input of the second operational amplifier using a second voltage source, wherein the second input voltage is less than a minimum programming voltage in a second range of programming voltages. Further, the method 800 may include outputting a second signal with a second operational amplifier, wherein the second signal is characterized by a second oscillation frequency, wherein the second oscillation frequency is responsive to a second capacitance associated with a second plurality of two-terminal memory devices. Still further, the method 800 may include measuring a second frequency value of the second oscillation frequency and storing a second indicator associated with the second oscillation frequency in the second memory. In another embodiment, the method 800 may include: when a difference between a frequency value of the first oscillation frequency and a second oscillation frequency value of the second oscillation frequency is within a predetermined frequency range, a passing condition of the semiconductor wafer is determined.
In an alternative or additional embodiment, the method 800 may include providing a second input voltage to the non-inverting input of the first operational amplifier using the first voltage source, wherein the second input voltage is less than a minimum programming voltage in the first programming voltage range. Further, the method 800 may include outputting a second signal with the first operational amplifier, wherein the second signal is characterized by a second oscillation frequency, wherein the second oscillation frequency is responsive to a first capacitance associated with the first plurality of two-terminal memory devices. In various embodiments, the method 800 may further include measuring a second frequency value of the second oscillation frequency and storing a second indicator associated with the second oscillation frequency in the memory.
In an embodiment, the method 800 may further include determining a pass condition of the first plurality of two-terminal memory devices when a difference between the first oscillation frequency and the second oscillation frequency is within a predetermined frequency range. For example, the difference between the first input voltage and the second input voltage may be less than 0.5 volts.
According to other embodiments, method 800 may include modifying the trim value in response to an indicator associated with the first oscillation frequency and storing the trim value in memory. In at least one such embodiment, the trim value may be associated with a parameter associated with the first plurality of two-terminal memory devices, wherein the parameter is selected from the group consisting of: read parameters, write parameters, and erase parameters. In at least one embodiment, the number of two-terminal memory devices in the first plurality of two-terminal memory devices is in a range of 20,000 to 60,000. In other embodiments, outputting the first signal with the first operational amplifier may additionally include outputting a second signal with the first operational amplifier, wherein the second signal is characterized by a second oscillation frequency and dividing the second oscillation frequency with a frequency divider to determine the first oscillation frequency.
Referring to FIG. 9, a method 900 for characterizing a resistive switching device of a memory array in various embodiments is depicted. At 902, the method 900 may include selectively connecting one or more two-terminal resistive switching devices of a memory array to an RC oscillator circuit formed in the same die as the memory array. At 904, method 900 may include providing a first voltage to an input of an RC oscillator circuit that is less than a minimum switching voltage associated with a two-terminal resistive switching device. Further, at 906, the method 900 may include measuring a first oscillation frequency output from the RC oscillator circuit, and at 908, the method 900 may include determining an average capacitance of the one or more two-terminal resistive switching devices from the oscillation frequency output. At 910, method 900 may include determining a trim value for a trim parameter of a memory array based at least in part on the average capacitance.
FIG. 10 depicts a method 1000 for measuring memory device characteristics, in accordance with an alternative or additional embodiment of the present disclosure. At 1002, the method 1000 may include selectively connecting a first plurality of two-terminal resistive switching devices of a memory array to an RC oscillator circuit formed in a first die of a semiconductor wafer with the memory array. At 1004, method 1000 may include providing a first voltage to an input of an RC oscillator circuit that is less than a minimum switching voltage associated with a first set of devices. In addition to the above, at 1006, method 1000 may include measuring a first oscillation frequency output from an RC oscillator circuit.
At 1008, the method 1000 may include selectively connecting a second plurality of two-terminal resistive switching devices of the memory array to a second RC oscillator circuit formed in the first die. Further, at 1010, the method 1000 may include providing a second voltage to the input of the second RC oscillator circuit that is less than a minimum switching voltage of the second plurality of devices. At 1012, method 1000 may include measuring a second oscillation frequency output from the second RC oscillator circuit, and at 1014, method 1000 may include determining a difference of the first oscillation frequency and the second oscillation frequency. Still further, at 1016, the method 1000 may include determining whether a pass condition is satisfied. In an embodiment, the pass condition may be that a difference between the first oscillation frequency and the second oscillation frequency is less than a target value (or range of values). The target values may be set based on characteristics of the first and second plurality of devices, characteristics of the first and second dies, characteristics of the semiconductor wafer, etc., or an appropriate combination of the foregoing. In response to the pass condition being satisfied, method 1000 may proceed to 1018 and pass the wafer. In response to a pass condition failure, the method 1000 proceeds to 1020 and the wafer is rejected.
Fig. 11 illustrates a flow diagram of an example method 1100 in accordance with alternative or additional embodiments of the present disclosure. At 1102, the method 1100 may include selectively connecting a first plurality of two-terminal resistive switching devices of a memory array to an RC oscillator circuit formed with the memory array in a single die of a semiconductor device. At 1104, method 1100 may include providing a first voltage to an input of an RC oscillator circuit that is less than a minimum switching voltage associated with a first set of devices. At 1106, method 1100 may include measuring a first oscillation frequency output from the RC oscillator circuit, and at 1108, method 1100 may include providing a second voltage less than a minimum switching voltage to an input of the RC oscillator circuit.
At 1110, method 1100 may include measuring a second oscillation frequency output from the RC oscillator circuit. Further, at 1114, the method 1100 can include determining a difference of the first oscillation frequency and the second oscillation frequency. At 1116, the method 1100 may include determining whether a pass condition of the die has been met. In an embodiment, the passing condition may be whether a difference between the first oscillation frequency and the second oscillation frequency is less than a target value. In response to the pass condition being met, the method 1100 may proceed to 1118 and the die may pass. In response to the pass condition failing, the method 1100 may proceed to 1120 and the die may be rejected.
Example operating Environment
In order to provide a background for the various aspects of the disclosed subject matter, FIG. 12 and the following discussion are intended to provide a brief, general description of a suitable environment in which the various aspects of the disclosed subject matter can be implemented or processed. While the present subject matter has been described above in the general context of semiconductor architectures and process methods for fabricating, operating, or characterizing arrays of two-terminal memory devices, those skilled in the art will recognize that the present disclosure may also be implemented in combination with other architectures or process methods. Further, those skilled in the art will appreciate that the disclosed processes may be practiced with a processing system or computer processor, alone or in combination with a host computer that may include: single-processor or multiprocessor computer systems, minicomputers, mainframe computers, as well as personal computers, hand-held computing devices (e.g., PDAs, telephones, watches), microprocessor-based or programmable consumer or industrial electronics, and the like. The illustrated aspects may also be practiced in distributed computing environments where tasks are performed by remote processing devices that are linked through a communications network. However, some, if not all, aspects of the claimed innovation may be practiced on stand-alone electronic devices, such as memory cards, flash memory modules, removable memories (e.g., CF cards, USB memory sticks, SD cards, microSD cards), and so forth. In a distributed computing environment, program modules may be located in both local and remote memory storage modules or devices.
FIG. 12 illustrates a block diagram of an example operating and control environment 1200 for a memory array 1202 of a multi-block memory cell array in accordance with aspects of the present disclosure. In at least one aspect of the present disclosure, memory array 1202 can include memory selected from a variety of memory cell technologies. In at least one implementation, the memory array 1202 can include two-terminal memory technology arranged in a compact two-dimensional or three-dimensional architecture. Suitable two-terminal memory technologies may include resistive switching memory, conductive bridge memory, phase change memory, organic memory, magnetoresistive memory, and the like, or suitable combinations of the foregoing. In yet another embodiment, memory array 1202 may be configured to characterize the thickness of the memory layers in which memory array 1202 is formed, as described herein.
Further, the operating and control environment 1200 may include a row controller 1204. The row controller 1204 may be formed adjacent to and electrically connected with word lines (and in some embodiments source lines) of the memory array 1202. In addition, using the control signals of the reference and control signal generator 1218, the row controller 1204 can select a particular row with the appropriate select voltage for the memory cells. In addition, the row controller 1204 may facilitate program, erase, or read operations by applying appropriate voltages at selected word lines (and source lines). Similar to the column controller 1206, the row controller 1204 may apply an inhibit voltage to the inactive word lines (source lines) to mitigate or avoid bit disturb effects on the inactive word lines (source lines).
The clock source 1210 may provide respective clock pulses to facilitate timing of read, write, and program operations by the row controller 1204 and the column controller 1206. The clock source 1210 may also facilitate selection of a word line or bit line in response to external or internal commands received by the operating and control environment 1200. Input and input/output buffers 1212 may include command and address inputs, as well as bidirectional data inputs and outputs. Instructions are provided by command and address inputs, and data to be written to memory array 1202 and data read from memory array 1202 are transferred on bidirectional data inputs and outputs, facilitating a connection to an external host device such as a computer or other processing apparatus (not depicted, but see, e.g., computer 1302 of fig. 13, below).
Input and input/output buffer 1212 may be configured to receive write data, receive erase instructions, receive status or maintenance instructions, output read data, output status information, and receive address data and command data and address data for the corresponding instructions. Address data may be transferred to row controller 1204 and column controller 1206 through address registers 1214. In addition, input data is transmitted to the memory array 1202 via a signal input line between the sense amplifier 1208 and the input and output buffer 1212, and output data is received from the memory array 1202 via a signal output line from the sense amplifier 1208 to the input and output buffer 1212. Input data may be received from a host device and output data may be passed to the host device via an I/O bus.
In an embodiment, an RC circuit 100 for determining capacitances of a subset of a memory array 1202 is provided. The RC circuit 100 is formed on a die having an operating and control environment 1200. In various embodiments, the RC circuit 100 may be fabricated within or in a suitable combination of input/output buffers 1212, address registers 1214, column controls 1206, row controls 1204, sense amplifiers 1208, or reference and control signal generator 1218, or other suitable components. In another embodiment, the RC circuit 100 may be fabricated separately from the foregoing components, with independent connections to the memory array 1202 and input/output buffers 1212 for receiving and responding to commands, as shown.
Commands received from a host device may be provided to command interface 1216. The command interface 1216 may be configured to receive an external control signal from a host device and determine whether data input to the input and input/output buffer 1212 is write data, a command, or an address. The input commands may be communicated to a state machine 1220.
The state machine 1220 may be configured to manage programming and reprogramming of the memory array 1202 (as well as other memory banks of a multi-bank memory array). The instructions provided to the state machine 1220 are implemented according to a control logic configuration, enabling the state machine 1220 to manage reads, writes, erases, data inputs, data outputs, and other functions associated with the memory array 1202. In some aspects, the state machine 1220 may send and receive acknowledgements and negative acknowledgements regarding successful receipt or execution of various commands. In further embodiments, state machine 1220 may decode and implement state-related commands, decode and implement configuration commands, and the like.
To perform read, write, erase, input, output, etc. functions, state machine 1220 may control clock source 1210 or reference and control signal generator 1218. Control of the clock source 1210 may cause the output pulses to be configured to facilitate the row controller 1204 and the column controller 1206 to perform particular functions. The output pulse may be transmitted to a selected bit line, for example, next to the column controller 1206, or a word line, for example, next to the row controller 1204.
With reference to FIG. 13, a suitable environment 1300 for implementing various aspects of the claimed subject matter includes a computer 1302. The computer 1302 includes a processing unit 1304, a system memory 1310, a codec 1314, and a system bus 1308. The system bus 1308 couples system components including, but not limited to, the system memory 1310 to the processing unit 1304. The processing unit 1304 can be any of various available processors. Dual microprocessors and other multiprocessor architectures also can be employed as the processing unit 1304.
The system bus 1308 can be any of several types of bus structure(s) including a memory bus or memory controller, a peripheral bus or external bus, and/or a local bus using any of a variety of available bus architectures, including, but not limited to: industry Standard Architecture (ISA), micro-channel architecture (MSA), extended ISA (EISA), intelligent Drive Electronics (IDE), VESA Local Bus (VLB), peripheral Component Interconnect (PCI), card bus, universal Serial Bus (USB), advanced Graphics Port (AGP), personal computer memory card International Association bus (PCMCIA), firewire (IEEE 1394), and Small Computer Systems Interface (SCSI).
The system memory 1310 includes volatile memory 1310A and non-volatile memory 1310B. The basic input/output system (BIOS), containing the basic routines to transfer information between elements within the computer 1302, such as during start-up, is stored in nonvolatile memory 1310B. Further, in accordance with the subject innovation, codec 1314 may include at least one of an encoder or a decoder, where the at least one of an encoder or decoder may be comprised of hardware, software, or a combination of hardware and software. Although codec 1314 is depicted as a separate component, codec 1314 may be included within non-volatile memory 1310B. By way of illustration, and not limitation, nonvolatile memory 1310B can include Read Only Memory (ROM), programmable ROM (PROM), electrically Programmable ROM (EPROM), electrically Erasable Programmable ROM (EEPROM), or flash memory, two terminal memory, and the like. Volatile memory 1310A includes Random Access Memory (RAM), which acts as external cache memory. According to the present aspect, the volatile memory may store write operation retry logic (not shown in fig. 13) or the like. By way of illustration and not limitation, RAM comes in many forms, such as Static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double Data Rate SDRAM (DDRSDRAM), and Enhanced SDRAM (ESDRAM).
It is to be appreciated that fig. 13 describes software that acts as an intermediary between users and the basic computer resources described in the suitable operating environment 1300. Such software includes an operating system 1306A. Operating system 1306A, which can be stored on disk storage 1306, acts to control and allocate resources of the computer system 1302. Application 1306C takes advantage of the management of resources by operating system 1306A through programming modules 1306D and programming data 1306D stored in system memory 1310 or on disk storage 1306, such as a launch/close transaction table. It is to be appreciated that the claimed subject matter can be implemented with various operating systems or combinations of operating systems.
A user enters commands or information into the computer 1302 through input device(s) 1342. Input devices 1342 include, but are not limited to, a pointing device such as a mouse, trackball, stylus, touch pad, keyboard, microphone, joystick, game pad, satellite dish, scanner, TV tuner card, digital camera, digital video camera, web camera, and the like. These and other input devices connect to the processing unit 1304 through the system bus 1308 via input port 1340. Input ports 1340 include, for example: serial ports, parallel ports, game ports, and Universal Serial Bus (USB). The output device 1332 uses some of the same type of ports as the input device 1342. Thus, for example, a USB port may be used to provide input to computer 1302 and to output information from computer 1302 to an output device 1332. Output adapter 1330 is provided to illustrate that there are some output devices 1332 like monitors, speakers, and printers, among other output devices 1332 that require special adapters. The output adapters 1330 include, by way of illustration and not limitation, video and sound cards that provide a means of connection between the output device 1332 and the system bus 1308. It should be noted that other devices and/or systems of devices provide both input and output capabilities such as remote computer(s) 1338.
The computer 1302 can operate in a networked environment using logical connections to one or more remote computers, such as a remote computer 1324. The remote computer 1324 can be a personal computer, a server, a router, a network PC, a workstation, a microprocessor based appliance, a peer device, a smart phone, a tablet computer or other network node, and typically includes many of the elements associated with the computer 1302. For purposes of brevity, only a memory storage device 1326 is illustrated with remote computer 1324. Remote computer 1324 is logically connected to computer 1302 through a network 1322 and then connected via communication interface 1320. The network 1322 includes wired or wireless communication networks such as Local Area Networks (LANs) and Wide Area Networks (WANs), as well as cellular networks. LAN technologies include Fiber Distributed Data Interface (FDDI), copper Distributed Data Interface (CDDI), ethernet, token ring, and the like. WAN technologies include, but are not limited to, point-to-point links, circuit switching networks like Integrated Services Digital Networks (ISDN) and variations thereon, packet switching networks, and Digital Subscriber Lines (DSL).
The illustrated aspects of the disclosure may also be practiced in distributed computing environments where certain tasks are performed by remote processing devices that are linked through a communications network. In a distributed computing environment, program modules or stored information, instructions or the like may be located in both local and remote memory storage devices.
Further, it should be understood that the various components described herein may include circuitry that may include components and circuit elements of appropriate value in order to implement embodiments of the present disclosure. Further, it is understood that many different components may be implemented on one or more IC chips. For example, in one embodiment, a group of components may be implemented in a single IC chip. In other embodiments, one or more respective components are fabricated or implemented on separate IC chips.
In regard to the various functions performed by the above described components, architectures, circuits, processes, and the like, the terms (including a reference to a "means") used to describe such components are intended to correspond, unless otherwise indicated, to any component which performs the specified function of the described component (e.g., a functional equivalent), even though not structurally equivalent to the disclosed structure which performs the function in the herein illustrated exemplary aspects of the implementations. In this regard, it will also be recognized that the embodiments include a system as well as a computer-readable medium having computer-executable instructions for performing the acts and/or events of the various processes.
In addition, while a particular feature may have been disclosed with respect to only one of several implementations, such feature may be combined with one or more other features of the other implementations as may be desired and advantageous for any given or particular application. Furthermore, to the extent that the terms "includes," includes, "and variants thereof are used in either the detailed description or the claims, these terms are intended to be inclusive in a manner similar to the term" comprising.
As used in this application, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or". That is, unless specified otherwise, or clear from context, "X employs A or B" is intended to mean any of the naturally inclusive permutations. That is, if X employs A; b is used as X; or X employs A and B, then "X employs A or B" is satisfied under any of the foregoing circumstances. In addition, the articles "a" and "an" as used in this application and the appended claims should generally be construed to mean "one or more" unless specified otherwise or clear from context to be directed to a singular form.
Additional embodiments may be envisioned by one of ordinary skill in the art upon reading this disclosure. For example, in various embodiments, an erase operation may be initiated simultaneously for multiple ReRAM devices (e.g., 16, 32, etc.).
In other embodiments, combinations or sub-combinations of the above disclosed embodiments may be advantageously made. The block diagrams and flow charts of the architecture are grouped for ease of understanding. However, it should be understood that combinations of blocks, additions of new blocks, rearrangements of blocks, and the like are contemplated in alternative embodiments of the present disclosure.
It should also be understood that the examples and embodiments described herein are for illustrative purposes only and that various modifications or changes in light thereof will be suggested to persons skilled in the art and are to be included within the spirit and purview of this application and scope of the appended claims.
Claims (20)
1. A semiconductor device, comprising:
a first plurality of two-terminal memory devices, wherein each of the two-terminal memory devices is characterized by a programming voltage within a range of programming voltages, wherein the first plurality of two-terminal memory devices is associated with a first capacitance, and wherein the first plurality of two-terminal memory devices is selectively coupled in parallel between ground and a first common node;
a first capacitor coupled between ground and a second common node, wherein the first capacitor is characterized by a second capacitance;
a first voltage source configured to provide a first input voltage, wherein the first input voltage is lower than the programming voltage range;
a first operational amplifier comprising an inverting input, a non-inverting input, and an output, wherein the non-inverting input is coupled to the first voltage source, wherein the inverting input is coupled to a third common node, and wherein the output is coupled to a fourth common node;
a first resistive device coupled between the third common node and the fourth common node; and is
Wherein the first common node is coupled to the second common node and the third common node.
2. The apparatus of claim 1, wherein a capacitance value associated with a second capacitance of the first capacitor is greater than a capacitance value associated with a first capacitance of the first plurality of two-terminal memory devices.
3. The apparatus of claim 1, further comprising an inverter having an input and an output, wherein the input of the inverter is coupled to the fourth common node.
4. The apparatus of claim 1, further comprising at least one of:
a first switch disposed between the first common node and the third common node, wherein the first switch is configured to couple and decouple the first common node and the third common node; or alternatively
A first multiplexer to selectively couple and decouple respective first terminals of the first plurality of two-terminal memory devices to the first common node.
5. The apparatus of claim 1, wherein the first voltage source is further configured to provide a second input voltage to a non-inverting input, wherein the second input voltage is lower than the programming voltage range.
6. The device of claim 5, wherein a number of two-terminal memory devices of the first plurality of two-terminal memory devices is in a range of 20000 to 60000.
7. The device of claim 1, wherein a two-terminal memory device of the first plurality of two-terminal memory devices is selected from the group consisting of: a filamentous memory device; a non-volatile filamentary resistive switching device; a volatile wire resistive switching device; a non-volatile memory including a transistor, an optional capacitor, and a two-terminal resistive selector coupled to a gate of the transistor at a first selector terminal and to the optional capacitor at a second selector terminal; a magnetoresistive memory device; a phase change memory device; a carbon nanotube memory device; a conductive bridge memory device; silicon sub-oxide memory devices and metal oxide memory devices.
8. The apparatus of claim 1, further comprising:
a second plurality of two-terminal memory devices, wherein each two-terminal memory device of the second plurality of two-terminal memory devices is characterized by a second programming voltage within a second programming voltage range, wherein the second plurality of two-terminal memory devices is associated with a third capacitance, and wherein the second plurality of two-terminal memory devices is selectively coupled in parallel between ground and a fifth common node;
a second capacitor coupled between ground and a sixth common node;
a second voltage source configured to provide a second input voltage, wherein the second input voltage is smaller than the second programming voltage range;
a second operational amplifier comprising a second inverting input, a second non-inverting input, and a second output, wherein the second non-inverting input of the second operational amplifier is coupled to the second voltage source, wherein the second inverting input of the second operational amplifier is coupled to a seventh common node, and wherein the output of the second operational amplifier is coupled to an eighth common node;
a second resistive device coupled between the seventh common node and the eighth common node; and is
Wherein the fifth common node is coupled to the sixth common node and the seventh common node;
wherein the first plurality of two-terminal memory devices are disposed on a first portion of a semiconductor die;
wherein the second plurality of two-terminal memory devices are disposed on a second portion of the semiconductor die; and is
Wherein the first portion is not adjacent to the second portion.
9. The apparatus of claim 1, wherein the first operational amplifier is configured to oscillate at a first frequency in response to the first capacitance, the second capacitance, and the first resistance.
10. The apparatus of claim 9, further comprising a memory configured to store an indicator of the first frequency.
11. A method, comprising:
closing a first switch and coupling a first plurality of two-terminal memory devices to an inverting input of a first operational amplifier, wherein each two-terminal memory device of the first plurality of two-terminal memory devices is characterized by a programming voltage within a first programming voltage range, wherein a first capacitor is coupled between the inverting input of the first operational amplifier and ground, and wherein a first resistance device is coupled between the inverting input of the first operational amplifier and an output of the first operational amplifier;
providing a first input voltage to a non-inverting input of the first operational amplifier with a first voltage source, wherein the first input voltage is less than a minimum programming voltage in the first programming voltage range;
outputting a first signal with the first operational amplifier, wherein the first signal is characterized by a first oscillation frequency, wherein the first oscillation frequency is responsive to a first capacitance associated with the first plurality of two-terminal memory devices;
measuring a frequency value of the first oscillation frequency; and
an indicator associated with the first oscillation frequency measurement is stored in a memory.
12. The method of claim 11, wherein the first plurality of two-terminal memory devices, the first switch, the first operational amplifier, the first capacitor, the first resistance device, and the first voltage source are formed within a first die of a plurality of dies formed on a semiconductor wafer.
13. The method of claim 12, wherein the first and second light sources are selected from the group consisting of,
wherein a second die of the plurality of dies comprises a second plurality of two-terminal memory devices, a second switch, a second operational amplifier, a second capacitor, a second resistance device, and a second voltage source; and is
Wherein the method further comprises:
closing the second switch and coupling the second plurality of two-terminal memory devices to an inverting input of the second operational amplifier, wherein each two-terminal memory device of the second plurality of two-terminal memory devices is characterized by a second programming voltage within a second programming voltage range, wherein the second capacitor is coupled between the inverting input of the second operational amplifier and ground, and wherein the second resistance device is coupled between the inverting input of the second operational amplifier and an output of the second operational amplifier;
providing, with the second voltage source, a second input voltage to a non-inverting input of the second operational amplifier, wherein the second input voltage is less than a minimum programming voltage in the second range of programming voltages;
outputting a second signal with the second operational amplifier, wherein the second signal is characterized by a second oscillation frequency, wherein the second oscillation frequency is responsive to a second capacitance associated with the second plurality of two-terminal memory devices;
measuring a second frequency value of the second oscillation frequency; and
storing a second indicator associated with the second oscillation frequency in a second memory.
14. The method of claim 13, further comprising: determining a passing condition of the semiconductor wafer when a difference between a frequency value of the first oscillation frequency and a second frequency value of the second oscillation frequency is within a predetermined frequency range.
15. The method of claim 11, further comprising:
providing, with the first voltage source, a second input voltage to a non-inverting input of the first operational amplifier, wherein the second input voltage is less than a minimum programming voltage in the first programming voltage range; and
outputting a second signal with the first operational amplifier, wherein the second signal is characterized by a second oscillation frequency, wherein the second oscillation frequency is responsive to a first capacitance associated with the first plurality of two-terminal memory devices;
measuring a second frequency value of the second oscillation frequency; and
storing a second indicator associated with the second oscillation frequency in a memory.
16. The method of claim 15, further comprising: determining a pass condition of the first plurality of two-terminal memory devices when a difference between the first oscillation frequency and the second oscillation frequency is within a predetermined frequency range.
17. The method of claim 15, wherein a difference between the first input voltage and the second input voltage is less than 0.5 volts.
18. The method of claim 11, further comprising:
modifying a trim value in response to an indicator associated with the first oscillation frequency; and
storing the trim value in a memory;
wherein the trim value is associated with a parameter associated with the first plurality of two-terminal memory devices, wherein the parameter is selected from the group consisting of: read parameters, write parameters, and erase parameters.
19. The method of claim 11, wherein a number of two-terminal memory devices in the first plurality of two-terminal memory devices is in a range of 20,000 to 60,000.
20. The method of claim 11, wherein outputting the first signal with the first operational amplifier comprises:
outputting a second signal using the first operational amplifier, wherein the second signal is characterized by a second oscillation frequency; and
dividing the second oscillation frequency with a frequency divider to determine the first oscillation frequency.
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