CN115394781A

CN115394781A - Semiconductor memory device and method for manufacturing semiconductor memory device

Info

Publication number: CN115394781A
Application number: CN202210047812.6A
Authority: CN
Inventors: 裵炳郁
Original assignee: SK Hynix Inc
Current assignee: SK Hynix Inc
Priority date: 2021-05-06
Filing date: 2022-01-17
Publication date: 2022-11-25
Also published as: US20220359560A1; KR20220151473A

Abstract

The present application relates to a semiconductor memory device and a method of manufacturing the semiconductor memory device. A semiconductor memory device includes: a bit line; a common source pattern over the bit line; a channel layer contacting the common source pattern, the channel layer extending toward the bit line; and a filling insulation layer disposed between the bit line and the common source pattern, the filling insulation layer surrounding a first portion of the channel layer. The semiconductor memory device further includes a gate stack structure disposed between the bit line and the filling insulation layer, the gate stack structure surrounding a second portion of the channel layer. The semiconductor memory device further includes: a first etch stop pattern on a sidewall of the filling insulating layer; a second etch stop pattern between the first etch stop pattern and the filling insulating layer; and a memory pattern between the gate stack structure and the channel layer.

Description

Semiconductor memory device and method for manufacturing semiconductor memory device

Technical Field

The present disclosure relates generally to semiconductor memory devices and methods of manufacturing semiconductor memory devices, and more particularly, to three-dimensional semiconductor memory devices and methods of manufacturing three-dimensional semiconductor memory devices.

Background

A semiconductor memory device includes a plurality of memory cells capable of storing data. The three-dimensional semiconductor memory device may include a plurality of three-dimensionally arranged memory cells. Since the plurality of memory cells are three-dimensionally arranged, a substrate area occupied by the plurality of memory cells can be reduced, thereby improving the integration of the semiconductor memory device.

The operational reliability of the three-dimensional semiconductor memory device may be deteriorated due to various factors occurring in the process of manufacturing the three-dimensional semiconductor memory device.

Disclosure of Invention

According to an embodiment of the present disclosure, a semiconductor memory device includes: a bit line; a common source pattern over the bit line; a channel layer contacting the common source pattern, the channel layer extending toward the bit line; a filling insulation layer disposed between the bit line and the common source pattern, the filling insulation layer surrounding a first portion of the channel layer; a gate stack structure disposed between the bit line and the filling insulation layer, the gate stack structure surrounding a second portion of the channel layer; a first etch stop pattern on a sidewall of the filling insulating layer; a second etch stop pattern between the first etch stop pattern and the filling insulating layer; and a memory pattern between the gate stack structure and the channel layer.

According to an embodiment of the present disclosure, a method of manufacturing a semiconductor memory device includes: forming a groove in a substrate; sequentially laminating a first etching stop layer and a second etching stop layer along the surface of the groove; forming a filling insulating layer on the second etch stop layer such that a central region of the groove is filled with the filling insulating layer; forming a preliminary memory cell array including a gate stack structure on the filling insulating layer, a hole penetrating the gate stack structure and the filling insulating layer, a memory layer extending along a surface of the hole, and a channel layer on the memory layer; exposing the first etch stop layer by removing a portion of the substrate from a back surface of the substrate, the damaged back surface facing a direction opposite to a surface of the substrate facing the gate stack structure; selectively removing a portion of the first etch stop layer such that the second etch stop layer is exposed; selectively removing a portion of the second etch stop layer such that the memory layer is exposed; and selectively removing a portion of the memory layer such that the channel layer is exposed.

Drawings

Example embodiments will now be described more fully hereinafter with reference to the accompanying drawings; example embodiments may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

In the drawings, the size may be exaggerated for clarity. It will be understood that when an element is referred to as being "between" two elements, it can be the only element between the two elements, or additional intervening elements may also be present. Like reference numerals refer to like elements throughout the drawings.

Fig. 1 is a diagram schematically illustrating a memory cell array of a semiconductor memory device according to an embodiment of the present disclosure.

Fig. 2 is a circuit diagram illustrating the memory cell array shown in fig. 1.

Fig. 3A and 3B are cross-sectional views illustrating an embodiment of the memory cell array shown in fig. 1.

Fig. 4A and 4B are cross-sectional views illustrating a semiconductor memory device according to an embodiment of the present disclosure.

Fig. 5A to 5C are cross-sectional views illustrating a process of forming a protective pattern and a process of forming a preliminary memory cell array.

Fig. 6 is a cross-sectional view illustrating a process of forming a first interconnection and a first conductive bonding pattern.

Fig. 7 is a cross-sectional view illustrating a process of bonding a first conductive bond pad to a structure including a peripheral circuit structure, a second interconnect, and a second conductive bond pad.

Fig. 8A to 8D are cross-sectional views illustrating a process of exposing the channel layer.

Fig. 9 is a sectional view illustrating a process of forming a doped semiconductor layer.

Fig. 10 is a block diagram illustrating a configuration of a memory system according to an embodiment of the present disclosure.

Fig. 11 is a block diagram illustrating a configuration of a computing system according to an embodiment of the present disclosure.

Detailed Description

The specific structural and functional descriptions disclosed herein are merely illustrative for the purpose of describing embodiments according to the concepts of the present disclosure. Embodiments according to the disclosed concept may be embodied in various forms and they should not be construed as limited to the specific embodiments set forth herein.

In the following, the terms "first" and "second" are used to distinguish one component from another component and are not meant to imply a particular number or order of components. The terminology may be used to describe various components, but the components are not limited by the terminology.

Some embodiments relate to a semiconductor memory device having improved operational reliability and a method of manufacturing the semiconductor memory device.

Referring to fig. 1, the memory cell array MCA may include a plurality of bit lines BL, a common source pattern CSL, and a memory block 10.

The plurality of bit lines BL may be spaced apart from each other and extend parallel to each other. In an embodiment, the plurality of bit lines BL may be spaced apart from each other in the X-axis direction and extend in the Y-axis direction. However, the present disclosure is not limited thereto.

The common source pattern CSL may overlap a plurality of bit lines BL with the memory block 10 interposed therebetween. The common source pattern CSL may extend on the XY plane.

The memory blocks 10 may be disposed between the plurality of bit lines BL and the common source pattern CSL. Memory block 10 may include a plurality of memory cell strings. Each memory cell string may be connected not only to the corresponding bit line BL but also to the common source pattern CSL through the channel layer of the cell plug.

Fig. 2 is a circuit diagram illustrating the memory cell array MCA shown in fig. 1.

Referring to fig. 2, the memory cell array MCA may include a plurality of memory cell strings CS respectively connected to a plurality of bit lines BL. A plurality of memory cell strings CS may be connected in parallel to the common source pattern CSL.

Each memory cell string CS may include at least one drain select transistor DST, a plurality of memory cells MC, and at least one source select transistor SST.

The plurality of memory cells MC may be connected in series between the drain select transistor DST and the source select transistor SST. The plurality of memory cells MC may be connected to the common source pattern CSL via the source selection transistors SST. A plurality of memory cells MC may be correspondingly connected to bit lines via drain select transistors DST.

The plurality of memory cells MC may be respectively connected to a plurality of word lines WL. The operation of the plurality of memory cells MC may be controlled by gate signals applied to the plurality of word lines WL. The drain select transistor DST may be connected to a drain select line DSL. The operation of the drain select transistor DST may be controlled by a gate signal applied to the drain select line DSL. The source selection transistor SST may be connected to a source selection line SSL. The operation of the source select transistor SST may be controlled by a gate signal applied to a source select line SSL. The source select line SSL, the plurality of word lines WL, and the drain select line DSL may be implemented by conductive patterns stacked to be spaced apart from each other.

Fig. 3A and 3B are cross-sectional views illustrating an embodiment of the memory cell array MCA shown in fig. 1. Fig. 3A is a cross-sectional view of the memory cell array MCA taken in a direction crossing a plurality of bit lines BL, and fig. 3B is an enlarged cross-sectional view of the region a shown in fig. 3A.

Referring to fig. 3A and 3B, the memory cell array MCA may include bit lines BL, gate stacks GST, cell plugs CPL, a filling insulation layer 107, first etch stop patterns 103P, second etch stop patterns 105P, and a common source pattern CSL.

The common source pattern CSL and the bit line BL are conductive patterns for transmitting signals and may include various conductive materials. The common source pattern CSL may be disposed over the bit line BL. The common source pattern CSL and the bit line BL may be spaced apart from each other in the Z-axis direction. The common source pattern CSL may include a doped semiconductor layer 185. The doped semiconductor layer 185 may include at least one of an n-type impurity and a p-type impurity. In an embodiment, the doped semiconductor layer 185 may include n-type impurities.

The gate stack structure GST and the filling insulating layer 107 may be disposed between the bit line BL and the common source pattern CSL, and may be sequentially disposed in the Z-axis direction. In other words, the filling insulating layer 107 may be disposed between the bit line BL and the common source pattern CSL, and the gate stack structure GST may be disposed between the bit line BL and the filling insulating layer 107.

The gate stack structure GST may include a first interlayer insulating layer 111, and a plurality of conductive patterns 113 and a plurality of second interlayer insulating layers 115 between the first interlayer insulating layer 111 and the bit lines BL. The plurality of conductive patterns 113 and the plurality of second interlayer insulating layers 115 may be alternately disposed layer by layer in the Z-axis direction.

The first interlayer insulating layer 111 and each of the second interlayer insulating layers 115 may include the same insulating material. In an embodiment, the first and second

interlayer insulating layers

111 and 115 may include silicon oxide, for example, silicon dioxide SiO ₂ 。

The plurality of conductive patterns 113 may be insulated from each other by a plurality of second interlayer insulating layers 115. At least one conductive pattern adjacent to the common source pattern CSL among the plurality of conductive patterns 113 may serve as the source selection line SSL described with reference to fig. 2. At least one conductive pattern adjacent to the bit line BL among the plurality of conductive patterns 113 may serve as the drain select line DSL described with reference to fig. 2. A conductive pattern located between the source select line and the drain select line among the plurality of conductive patterns 113 may be used as the word line described with reference to fig. 2.

The first etch stop pattern 103P may be disposed on the sidewall SW1 of the filling insulation layer 107. The second etch stop pattern 105P may be disposed between the first etch stop pattern 103P and the filling insulation layer 107. The first etch stop pattern 103P and the second etch stop pattern 105P may be disposed at a height at which the filling insulation layer 107 is disposed.

The memory cell array MCA may further include a semiconductor pattern 101P on the sidewall SW2 of the first etch stop pattern 103P. The semiconductor pattern 101P may be disposed at a height at which the filling insulation layer 107 is disposed. The semiconductor pattern 101P may be configured as a semiconductor wafer.

According to the above-described embodiment of the present disclosure, the semiconductor pattern 101P having a relatively large volume compared to the filling insulating layer 107 and the filling insulating layer 107 made of a material different from the semiconductor pattern 101P may be spaced apart from each other by the first etch stop pattern 103P and the second etch stop pattern 105P as a pad type. The first etch stop pattern 103P may form an interface with the semiconductor pattern 101P, and the second etch stop pattern 105P may form an interface with the filling insulation layer 107. In the embodiment of the present disclosure, the first and second

etch stop patterns

103P and 105P serve as buffers, so that stress applied to the semiconductor pattern 101P and the filling insulation layer 107 may be reduced.

The gate stack structure GST and the common source pattern CSL may be formed to be wider than the filling insulating layer 107 as viewed from a plane intersecting the Z-axis direction. For example, the gate stack structure GST and the common source pattern CSL may extend to overlap the first etch stop pattern 103P, the second etch stop pattern 105P, and the semiconductor pattern 101P. The semiconductor pattern 101P may be insulated from the conductive pattern 113 by the first interlayer insulating layer 111.

The cell plug CPL may include a memory pattern 121P, a channel layer 123, a core insulation pattern 125P, and a capping pattern 127P.

The channel layer 123 may include a semiconductor layer such as silicon. The channel layer 123 may be in contact with the doped semiconductor layer 185 of the common source pattern CSL and extend toward the bit line BL. The channel layer 123 may include a first portion P1 surrounded by the filling insulation layer 107 and a second portion P2 surrounded by the gate stack structure GST. The stress applied to the channel layer 123 may be reduced by the first etch stop pattern 103P and the second etch stop pattern 105P serving as a buffer as described above.

The memory pattern 121P may be disposed between the second portion P2 of the channel layer 123 and the gate stack structure GST. The memory pattern 121P may extend between the first portion P1 of the channel layer 123 and the filling insulation layer 107. The memory pattern 121P may include a blocking insulating layer BI, a data storage layer DS, and a tunnel insulating layer TI. The barrier insulating layer BI may include a metal oxide layer, a silicon oxide layer, and the like. The data storage layer DS may be configured as a material layer capable of storing data changed using Fowler-Nordheim (Fowler-Nordheim) tunneling. The material layer may include a nitride layer in which charges may be trapped. However, embodiments of the present disclosure are not limited thereto, and the data storage layer DS may include nanodots or the like. The tunnel insulating layer TI may include an insulating material through which charges can tunnel. In an embodiment, the tunnel insulating layer TI may include a silicon oxide layer.

The core insulation pattern 125P and the cap pattern 127P may be disposed in a central region of the channel layer 123.

The core insulating pattern 125P may have a surface SU facing the doped semiconductor layer 185. The surface SU of the core insulating pattern 125P may be spaced apart from the doped semiconductor layer 185 by a first portion P1 of the channel layer 123 extending between the core insulating pattern 125P and the doped semiconductor layer 185. In other words, the doped semiconductor layer 185 may overlap the core insulating pattern 125P with the channel layer 123 interposed therebetween.

The capping pattern 127P may be disposed between the core insulating pattern 125P and the bit line BL. The capping pattern 127P may include a doped semiconductor layer. In an embodiment, the capping pattern 127P may include a doped silicon layer containing n-type impurities.

The cap pattern 127P and a conductive type impurity (e.g., an n-type impurity) of the impurity-doped semiconductor layer 185 may be diffused into the channel layer 123. Accordingly, both ends of the channel layer 123 adjacent to the cap pattern 127P and the doped semiconductor layer 185 may include conductive impurities.

The first etch stop pattern 103P, the second etch stop pattern 105P, and the filling insulation layer 107 may be designed in consideration of etch selectivity to reduce damage to the channel layer 123 in the process of manufacturing the semiconductor memory device. The first etch stop pattern 103P may include an insulating material having an etch selectivity with respect to a semiconductor wafer constituting the semiconductor pattern 101P. In an embodiment, the filling insulation layer 107 may include at least one of a nitride layer and an oxide layer, and the second etch stop pattern 105P may include a silicon layer. The second etch stop pattern 105P may be insulated from the conductive pattern 113 by the first interlayer insulating layer 111.

The channel layer 123 may include a third portion P3 protruding more toward the bit line BL than the gate stack structure GST from the second portion P2. The memory pattern 121P and the cap pattern 127P may extend along the third portion P3 toward the bit line BL.

The memory cell array MCA may include at least one insulating layer disposed between the gate stack structure GST and the bit line BL. In an embodiment, the memory cell array MCA may include a first insulating layer 131 between the gate stack structure GST and the bit line BL, a second insulating layer 135 between the first insulating layer 131 and the bit line BL, and a third insulating layer 139 between the second insulating layer 135 and the bit line BL. The first insulating layer 131 may cover an end of the cell plug CPL facing the bit line BL.

The bit line BL may penetrate the fourth insulating layer 143 overlapping the third insulating layer 139. The bit lines BL may be connected to the capping patterns 127P of the cell plugs CPL via bit line-channel connection structures BCC. The bit line-channel connection structure BCC may comprise conductive patterns having various structures. In an embodiment, the bit line-channel connection structure BCC may include a first conductive plug 133 extending from the capping pattern 127P to penetrate through the first insulating layer 131, a conductive pad 137 extending from the first conductive plug 133 to penetrate through the second insulating layer 135, and a second conductive plug 141 extending from the conductive pad 137 to penetrate through the third insulating layer 139.

Fig. 4A and 4B are cross-sectional views illustrating a semiconductor memory device according to an embodiment of the present disclosure. Fig. 4A is a sectional view illustrating an embodiment of a structure provided on the memory cell array MCA shown in fig. 3A, and fig. 4B is a sectional view illustrating an embodiment of a structure provided under the memory cell array MCA shown in fig. 3A.

Referring to fig. 4A, the common source pattern CSL of the semiconductor memory device may further include a metal blocking layer 191 and a metal layer 193 disposed on the doped semiconductor layer 185 of the memory cell array MCA described with reference to fig. 3A and 3B, in addition to the doped semiconductor layer 185. The resistance of the common source pattern CSL may be reduced by the metal layer 193.

Referring to fig. 4B, the semiconductor memory device may include a peripheral circuit structure 200, a first interconnection 153, a second interconnection 230, a first conductive bonding pad 155, and a second conductive bonding pad 231. The peripheral circuit structure 200, the first interconnect 153, the second interconnect 230, the first conductive bonding pad 155, and the second conductive bonding pad 231 may be disposed under the memory cell array MCA described with reference to fig. 3A and 3B.

The peripheral circuit structure 200 may include a semiconductor substrate 201 and a plurality of transistors TR. The semiconductor substrate 201 may include silicon, germanium, or the like. The semiconductor substrate 201 may include an active region divided by an isolation layer 203.

The plurality of transistors TR may constitute a peripheral circuit for controlling the operation of the memory cell array MCA. In an embodiment, the plurality of transistors TR may include a transistor of a page buffer circuit for controlling the bit line BL. Each transistor TR may include a gate insulating layer 205, a gate electrode 207, and a junction 201J. A gate insulating layer 205 and a gate electrode 207 may be stacked on the active region of the semiconductor substrate 201. The junction 201J may be provided as a source region and a drain region. The junction 201J may be provided by doping at least one of an n-type impurity and a p-type impurity into an active region exposed to both sides of the gate electrode 207.

The semiconductor substrate 201 and the plurality of transistors TR may be covered with a peripheral circuit side insulating structure 210.

The first interconnection 153 and the first conductive bonding pad 155 may be formed in the cell array side insulating structure 151 disposed between the peripheral circuit side insulating structure 210 and the memory cell array MCA described with reference to fig. 3A and 3B. The cell array side insulating structure 151 may include a single insulating layer or two or more insulating layers. The first interconnections 153 may include conductive patterns having various structures. The first conductive bond pad 155 may be connected to the bit line BL via a first interconnect 153.

The second interconnection 230 and the second conductive bonding pad 231 may be formed in the peripheral circuit side insulating structure 210. The peripheral circuit side insulating structure 210 may include two or more insulating layers. The second interconnection 230 may include a plurality of conductive patterns 211, 213, 215, 217, 219, 221, 223, and 225 connected to the transistor TR. The plurality of conductive patterns 211, 213, 215, 217, 219, 221, 223, and 225 may be formed in various structures. The second conductive bonding pad 231 may be connected to the transistor TR via the second interconnection 230.

The first and

second interconnections

153 and 230 may be connected to each other through an interconnection structure of the first and second

conductive bonding pads

155 and 231. In an embodiment, the first conductive bonding pad 155 and the second conductive bonding pad 231 may be coupled to each other through a bonding process.

According to the above structure, the bit line BL may be connected to the transistor TR via the first interconnect 153, the first conductive bonding pad 155, the second conductive bonding pad 231, and the second interconnect 230.

Hereinafter, a method of manufacturing a semiconductor memory device according to an embodiment of the present disclosure will be described.

Fig. 5A to 5C are sectional views illustrating a process of forming a protective pattern and a process of forming a preliminary memory cell array.

Referring to fig. 5A, the process of forming the protection pattern may include a process of forming a groove 101GV by etching the substrate 101 and a process of sequentially forming the first etch stop layer 103, the second etch stop layer 105, and the filling insulation layer 107 in the groove 101 GV.

The substrate 101 may be a semiconductor wafer. In an embodiment, the substrate 101 may include a silicon layer.

The first etch stop layer 103 and the second etch stop layer 105 may be sequentially stacked along the surface of the groove 101 GV. The first etch stop layer 103 and the second etch stop layer 105 may be conformally formed along the surface of the substrate 101 including the groove 101 GV. The first etch stop layer 103 may include an insulating material having an etch selectivity with respect to the substrate 101.

A filling insulating layer 107 may be formed on the second etch stop layer 105 to fill the central region of the groove 101 GV. The filling insulation layer 107 may include a material having an etch selectivity with respect to the second etch stop layer 105. In an embodiment, the second etch stop layer 105 may include a silicon layer, and the filling insulation layer 107 may include at least one of a nitride layer and an oxide layer.

Referring to fig. 5B, planarization may be performed on the filling insulating layer 107, the second etch stop layer 105, and the first etch stop layer 103 to expose the substrate 101. Accordingly, the protective pattern 110 filling the groove 101GV of the substrate 101 may be defined. The protective pattern 110 may include the filling insulation layer 107, the second etch stop layer 105, and the first etch stop layer 103 remaining in the groove 101 GV.

Referring to fig. 5C, after forming the protective pattern 110, a preliminary memory cell array PMCA may be formed on the substrate 101. The preliminary memory cell array PMCA may include a gate stack structure GST on the filling insulation layer 107, a hole 120 penetrating the gate stack structure GST and the filling insulation layer 107, and a cell plug CPL filling the hole 120. The cell plug CPL may include a memory layer 121 extending along a surface of the hole 120, a channel layer 123 on the memory layer 121, a core insulating pattern 125P filling a central region of the hole 120, and a cap pattern 127P, and the bit line BL is connected to the cap pattern 127P.

The gate stack structure GST may include a first interlayer insulating layer 111 on the filling insulating layer 107, and a plurality of conductive patterns 113 and a plurality of second interlayer insulating layers 115 alternately stacked on the first interlayer insulating layer 111.

In an embodiment, the process of forming the gate stack structure GST may include: a process of forming the first interlayer insulating layer 111; a process of sequentially laminating a plurality of sacrificial layers (not shown) and a plurality of second interlayer insulating layers 115 on the first interlayer insulating layer 111; a process of forming holes 120 penetrating the plurality of sacrificial layers (not shown), the plurality of second interlayer insulating layers 115, the first interlayer insulating layer 111, and the filling insulating layer 107 by an etching process using the mask pattern (not shown) as an etch stopper; a process of forming the cell plug CPL in the hole 120; and a process of replacing the plurality of sacrificial layers with the plurality of conductive patterns 113. The mask pattern may be removed after the cell plugs CPL are formed.

The first and second

interlayer insulating layers

111 and 115 may include an oxide layer, and the sacrificial layer may include a nitride layer having an etch selectivity with respect to the oxide layer. Since the filling insulating layer 107 includes at least one of an oxide layer and a nitride layer as the sacrificial layer, the first interlayer insulating layer 111, and the second interlayer insulating layer 115, the filling insulating layer 107 may be removed by an etching process for forming the hole 120. Since the second etch stop layer 105 includes a material having an etch selectivity with respect to the oxide layer, the nitride layer, and the filling insulation layer 107, the second etch stop layer 105 may be etch-resistant with respect to an etch process for forming the hole 120. Accordingly, the second etch stop layer 105 may serve as an etch stop layer during an etching process for forming the hole 120.

As shown in fig. 3B, the memory layer 121 of the cell plug CPL may include a blocking insulating layer BI, a data storage layer DS, and a tunnel insulating layer TI. The channel layer 123 may include a semiconductor layer. The core insulating pattern 125P may be formed to have a height lower than that of the channel layer 123. The capping pattern 127P may include a doped semiconductor layer as described with reference to fig. 3A and 3B, and overlap the core insulating pattern 125P. The conductive type impurities in the cap pattern 127P may be diffused into the channel layer 123 from the sidewall of the channel layer 123 contacting the cap pattern 127P.

Subsequently, the region from which the mask pattern is removed may be filled with the first insulating layer 131. The cell plug CPL may be covered by the first insulating layer 131.

The process of forming the bit lines BL connected to the cell plugs CPL may include a process of forming bit line-channel connection structures BCC connected to the capping patterns 127P of the cell plugs CPL and a process of forming the bit lines BL connected to the bit line-channel connection structures BCC. In an embodiment, the process of forming the bit line-channel connection structure BCC may include: a process of forming a first conductive plug 133 penetrating the first insulating layer 131; a process of forming a second insulating layer 135 covering the first conductive plug 133 and the first insulating layer 131; a process of forming a conductive pad 137 penetrating the second insulating layer 135; a process of forming a third insulating layer 139 covering the conductive pad 137 and the second insulating layer 135; and a process of forming a second conductive plug 141 penetrating the third insulating layer 139.

The process of forming the bit line BL may include a process of forming a fourth insulating layer 143 covering the second conductive plug 141 and the third insulating layer 139; a process of forming a trench penetrating the fourth insulating layer 143 and exposing the bit line-channel connection structure BCC; and a process of filling the trench with a conductive material.

Fig. 6 is a sectional view illustrating a process of forming a first interconnection and a first conductive bonding pattern.

Referring to fig. 6, a cell array-side insulating structure 151, a first interconnect 153 buried in the cell array-side insulating structure 151, and a first conductive bonding pad 155 may be formed on the initial memory cell array structure PMCA.

The cell array-side insulating structure 151 may include a single insulating layer or two or more insulating layers. The first interconnect 153 may be connected to the bit line BL. The structure of the first interconnections 153 is not limited to that shown in the drawings, and the first interconnections 153 may include conductive patterns having various structures. The first conductive bonding pad 155 may be connected to the first interconnection 153 and include a bonding surface that is not covered by the cell array side insulating structure 151.

Referring to fig. 7, a structure including the peripheral circuit structure 200, the second interconnections 230, and the second conductive bonding pads 231 described above with reference to fig. 4B may be provided through a separate manufacturing process distinguished from that of the initial memory cell array PMCA. Accordingly, a phenomenon in which the peripheral circuit structure 200 is deteriorated due to heat generated in a process of forming the preliminary memory cell array PMCA may be previously avoided.

The second interconnection 230 and the second conductive bonding pad 231 may be buried in the peripheral circuit side insulating structure 210 covering the peripheral circuit structure 200. The second conductive bonding pad 231 may be connected to the peripheral circuit structure 200 via the second interconnection 230, and include a bonding surface that is not covered by the peripheral circuit side insulating structure 210.

The first conductive bonding pad 155 may be bonded to the second conductive bonding pad 231. In addition, the peripheral circuit side insulating structure 210 may be bonded to the cell array side insulating structure 151.

Referring to fig. 8A, the first etch stop layer 103 may be exposed by removing a portion of the substrate 101 from the back surface 101BS of the substrate 101 illustrated in fig. 7. The back surface 101BS of the substrate 101 shown in fig. 7 may be defined as a surface of the substrate 101 facing a direction opposite to a surface facing the gate stack structure GST.

The process of removing a portion of the substrate 101 may include a planarization process such as Chemical Mechanical Polishing (CMP). The planarization end point may be detected using the first etch stop layer 103 having etch selectivity with respect to the substrate 101, and the planarization process may be stopped when the first etch stop layer 103 is exposed. Accordingly, the channel layer 123 is not exposed while a portion of the substrate 101 is removed. The channel layer 123 may be protected by a protection pattern 110 including the first etch stop layer 103.

Referring to fig. 8B, a portion of the first etch stop layer 103 may be selectively removed such that the second etch stop layer 105 is exposed. Accordingly, the channel layer 123 may be protected by the second etch stop layer 105 while selectively removing a portion of the first etch stop layer 103.

Referring to fig. 8C, a portion of the second etch stop layer 105 may be selectively removed such that the memory layer 121 is exposed. Accordingly, the channel layer 123 may be protected by the memory layer 121 while selectively removing a portion of the second etch stop layer 105.

Referring to fig. 8D, a portion of the memory layer 121 shown in fig. 8C may be selectively removed such that the channel layer 123 is exposed. Thus, the memory pattern 121P may be defined. The remaining portion of the substrate may be defined as a semiconductor pattern 101P, the remaining portion of the first etch stop layer may be defined as a first etch stop pattern 103P, and the remaining portion of the second etch stop layer may be defined as a second etch stop pattern 105P.

As described above, the channel layer 123 may be exposed through a plurality of selective etching processes including: a process of removing a portion of the substrate; a process of removing a portion of the first etch stop layer; a process of removing a portion of the second etch stop layer; and a process of removing a portion of the memory layer. According to this method, damage of the channel layer 123 may be reduced as compared to when the channel layer 123 is exposed by one etching process, and a state in which the core insulating pattern 125P is sealed by the end portion EG of the channel layer 123 may be stably maintained. Since the channel layer 123 is supported by the filling insulation layer 107, damage such as occurrence of cracks in the channel layer 123 due to an external force can be reduced.

Referring to fig. 9, a doped semiconductor layer 185 may be formed, the doped semiconductor layer 185 contacting the exposed end portion EG of the channel layer 123. The doped semiconductor layer 185 is a common source pattern as described with reference to fig. 3A and 3B, and may include conductive type impurities.

The doped semiconductor layer 185 may extend to overlap the filling insulating layer 107, the second etch stop pattern 105P, the first etch stop pattern 103P, and the semiconductor pattern 101P. The conductive type impurities of the impurity-doped semiconductor layer 185 may be diffused into the channel layer 123.

Although not shown in the drawings, a process of implanting conductive type impurities into the channel layer 123 may be performed before forming the doped semiconductor layer 185. The second etch stop pattern 105P including silicon and the semiconductor pattern 101P may be electrically connected to each other through the doped semiconductor layer 185.

According to the embodiment of the present disclosure, the contact between the core insulating pattern 125P and the doped semiconductor layer 185 may be blocked by the end EG of the channel layer 123. Accordingly, although a void or seam remains inside a portion of the core insulating pattern 125P adjacent to the end EG of the channel layer 123, a failure in which the doped semiconductor layer 185 penetrates into the void or seam may be delayed or avoided by the end EG of the channel layer 123. As a result, leakage current due to penetration of the doped semiconductor layer into the void or seam may be reduced, and thus operational reliability of the semiconductor memory device may be improved.

After the doped semiconductor layer 185 is formed, subsequent processes for the metal barrier layer 191 and the metal layer 193 shown in fig. 4A may be performed.

Referring to fig. 10, the memory system 1100 includes a memory device 1120 and a memory controller 1110.

Memory device 1120 may be a multi-chip package configured with multiple flash memory chips. The memory device 1120 may include a channel layer connected between the bit line and the common source pattern, a filling insulation layer surrounding a first portion of the channel layer, a gate stack structure surrounding a second portion of the channel layer between the bit line and the filling insulation layer, a first etch stop pattern on a sidewall of the filling insulation layer, a second etch stop pattern between the first etch stop pattern and the filling insulation layer, and a memory pattern between the gate stack structure and the channel layer.

The memory controller 1110 controls the memory device 1120, and may include a Static Random Access Memory (SRAM) 1111, a Central Processing Unit (CPU) 1112, a host interface 1113, an error correction block 1114, and a memory interface 1115. The SRAM 1111 serves as an operation memory for the CPU 1112, the CPU 1112 performs an overall control operation for data exchange of the memory controller 1110, and the host interface 1113 includes a data exchange protocol for a host connected to the memory system 1100. The error correction block 1114 detects errors contained in data read from the memory device 1120 and corrects the detected errors. The memory interface 1115 interfaces with the memory device 1120. The memory controller 1110 may further include a Read Only Memory (ROM) or the like for storing code data for interfacing with a host.

The memory system 1100 constructed as described above may be a memory card or a Solid State Disk (SSD) in which the memory device 1120 is combined with the memory controller 1110. For example, when the memory system 1100 is an SSD, the memory controller 1110 may communicate with the outside (e.g., host) through one of various interface protocols such as: a Universal Serial Bus (USB) protocol, a multi-media card (MMC) protocol, a Peripheral Component Interconnect (PCI) protocol, a PCI-express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a serial ATA (SATA) protocol, a parallel ATA (PATA) protocol, a Small Computer System Interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, and an Integrated Drive Electronics (IDE) protocol.

Referring to fig. 11, the computing system 1200 may include a CPU 1220, a Random Access Memory (RAM) 1230, a user interface 1240, a modem 1250, and a memory system 1210 electrically connected to a system bus 1260. When the computing system 1200 is a mobile device, a battery for providing an operating voltage to the computing system 1200 may be further included, and an application chipset, an image processor, a mobile DRAM, and the like may be further included.

The memory system 1210 may be configured with a memory device 1212 and a memory controller 1211.

The memory device 1212 may include a channel layer connected between the bit line and the common source pattern, a filler insulation layer surrounding a first portion of the channel layer, a gate stack structure surrounding a second portion of the channel layer between the bit line and the filler insulation layer, a first etch stop pattern on a sidewall of the filler insulation layer, a second etch stop pattern between the first etch stop pattern and the filler insulation layer, and a memory pattern between the gate stack structure and the channel layer.

The memory controller 1211 may have the same configuration as the memory controller 1110 described above with reference to fig. 10.

According to some embodiments of the present disclosure, using an etch selectivity between the first etch stop layer, the second etch stop layer, and the filling insulation layer disposed in the groove of the substrate makes it possible to reduce a phenomenon in which the channel layer is damaged in a process of exposing the channel layer. Accordingly, a leakage current caused by damage of the channel layer may be reduced, and thus, operational reliability of the semiconductor memory device may be improved.

Cross Reference to Related Applications

This application claims priority from korean patent application No.10-2021-0058760, filed on 6.5.2021, to the korean intellectual property office, the entire disclosure of which is incorporated herein by reference.

Claims

1. A semiconductor memory device, the semiconductor memory device comprising:

a bit line;

a common source pattern over the bit line;

a channel layer contacting the common source pattern, the channel layer extending toward the bit line;

a filling insulation layer disposed between the bit line and the common source pattern, the filling insulation layer surrounding a first portion of the channel layer;

a gate stack structure disposed between the bit line and the filling insulation layer, the gate stack structure surrounding a second portion of the channel layer;

a first etch stop pattern on sidewalls of the filling insulation layer;

a second etch stop pattern between the first etch stop pattern and the filling insulating layer; and

a memory pattern between the gate stack structure and the channel layer.

2. The semiconductor memory device according to claim 1, wherein the filling insulation layer comprises a material having an etch selectivity with respect to the second etch stop pattern.

3. The semiconductor memory device according to claim 2, wherein the filling insulation layer comprises at least one of a nitride layer and an oxide layer.

4. The semiconductor memory device according to claim 2, wherein the second etch stop pattern comprises a silicon layer.

5. The semiconductor memory device according to claim 1, wherein the first etch stop pattern comprises an insulating material having an etch selectivity with respect to a semiconductor wafer.

6. The semiconductor memory device according to claim 5, wherein the first etch stop pattern comprises an oxide layer.

7. The semiconductor memory device according to claim 1, wherein the first etching stop pattern and the second etching stop pattern are provided at a height at which the filling insulating layer is provided.

8. The semiconductor memory device according to claim 1, wherein the gate stack structure extends to overlap the first etch stop pattern and the second etch stop pattern.

9. The semiconductor memory device according to claim 1, further comprising a semiconductor pattern on a sidewall of the first etch stop pattern.

10. The semiconductor memory device according to claim 9, wherein the gate stack structure extends to overlap with the semiconductor pattern.

11. The semiconductor memory device according to claim 1, further comprising a core insulating pattern provided in a central region of the channel layer,

wherein the channel layer extends between the core insulation pattern and the common source pattern.

12. The semiconductor memory device according to claim 11,

the common source pattern includes a doped semiconductor layer in contact with the channel layer; and is

The doped semiconductor layer overlaps the core insulating pattern, and the channel layer is interposed between the doped semiconductor layer and the core insulating pattern.

13. A method of manufacturing a semiconductor memory device, the method comprising:

forming a groove in a substrate;

sequentially laminating a first etching stop layer and a second etching stop layer along the surface of the groove;

forming a filling insulating layer on the second etch stop layer such that a central region of the groove is filled with the filling insulating layer;

forming a preliminary memory cell array including a gate stack structure on the filling insulation layer, a hole penetrating the gate stack structure and the filling insulation layer, a memory layer extending along a surface of the hole, and a channel layer on the memory layer;

exposing the first etch stop layer by removing a portion of the substrate from a back surface of the substrate, the back surface facing an opposite direction from a surface of the substrate facing the gate stack structure;

selectively removing a portion of the first etch stop layer such that the second etch stop layer is exposed;

selectively removing a portion of the second etch stop layer such that the memory layer is exposed; and

selectively removing a portion of the memory layer such that the channel layer is exposed.

14. The method of claim 13, further comprising the steps of: forming a doped semiconductor layer in contact with the exposed portion of the channel layer.

15. The method of claim 14, wherein the doped semiconductor layer extends to overlap the fill insulating layer, the second etch stop layer, the first etch stop layer, and the substrate.

16. The method of claim 13, wherein the fill insulating layer comprises a material having an etch selectivity with respect to the second etch stop layer.

17. The method of claim 16, wherein the filler insulating layer comprises at least one of a nitride layer and an oxide layer.

18. The method of claim 16, wherein the second etch stop layer comprises a silicon layer.

19. The method of claim 13, wherein the first etch stop layer comprises an insulating material having an etch selectivity with respect to the substrate.

20. The method of claim 19, wherein the first etch stop layer comprises an oxide layer.