CN115394710A - Electronic electroplating chip of high-aspect-ratio through silicon via and preparation method - Google Patents
Electronic electroplating chip of high-aspect-ratio through silicon via and preparation method Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/0228—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76832—Multiple layers
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76876—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for deposition from the gas phase, e.g. CVD
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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Abstract
The invention relates to an electronic electroplating chip of a high-aspect-ratio through silicon via and a preparation method thereof, wherein the method comprises the following steps: s1, coating photoresist on the surface of a silicon substrate, and developing to expose hole sites after photoetching exposure; s2, covering a passivation layer on the exposed hole position part of the silicon substrate; s3, etching the bottom surface of the passivation layer and exposing the silicon substrate corresponding to the bottom surface of the hole site; s4, etching the silicon substrate corresponding to the bottom surface of the exposed hole site; s5, repeating the steps S2-S4 for multiple times to obtain the silicon through hole with the target depth, and cleaning and ashing the residual photoresist and passivation of the silicon through hole; and S6, depositing an insulating layer, a barrier layer and a seed layer on the inner wall of the silicon through hole by an ALD (atomic layer deposition) method to obtain the silicon through hole with the high aspect ratio. By adopting the three-pulse process, passivation, etching and etching are circularly carried out, the balance problem of etching and passivation during process modification is solved, and the stability of the process is ensured. Finally, ALD is selected to perform the sidewall deposition process to ensure that the sidewalls in the holes have sufficient coverage.
Description
Technical Field
The invention relates to the field of through silicon via preparation, in particular to an electronic electroplating chip of a high-aspect-ratio through silicon via and a preparation method thereof.
Background
The current advanced packaging technology mainly comprises six important technologies, namely flip chip packaging, wafer level chip size packaging, fan-out packaging, 3D wafer level chip size packaging, 2.5D middle level packaging and 3D IC integration. Different packaging modes are formed by combining different packaging processes such as salient points, re-wiring layers, chip-wafer/wafer-wafer, through silicon vias and stacking. Most of the packaging technologies are related to wafer level packaging, and advanced packaging is also developed towards system integration, high speed, high frequency, three-dimensional and ultra-fine interconnection pitch; among them, the 3D wafer level package attracts attention, and the three-dimensional package can greatly improve the integration level due to its optimal space utilization. For three-dimensional packaging, a plurality of chips are stacked in the vertical direction, so the interconnection mode among the chips is particularly important. The TSV interconnection technology is usually combined with the micro bump technology and the chip thinning technology, and the signal connection between the vertical chips is one of the core technologies of the 3 DIC.
In order to improve interconnection density while reducing chip occupation area, the importance of the TSV with high aspect ratio is increasingly appearing, and with further improvement of the aspect ratio, more challenges are provided for the TSV manufacturing process, and a plurality of technical indexes need to be considered: (1) the shape, size and aspect ratio of the TSV; (2) the shape of the etched side wall of the TSV and the size of etching damage; (3) The continuity and thickness of the deposition of the insulating layer, the barrier layer and the seed layer; (4) selection of plating solution capacity and plating current; and (5) electroplating equipment capacity.
The prior art has at least one or more of the following disadvantages:
1. the roughness of the side wall needs to be guaranteed for TSV etching, when the side wall is inevitably subjected to the Bosch etching, a scallop defect can occur, the defect has the most direct influence on the continuity of the side wall insulating layer, the barrier layer and the seed layer, and meanwhile, if the side wall is damaged in the etching process, extra leakage current can be introduced into the electrical performance test of the TSV.
2. Regarding the uniformity and continuity of the sidewall film deposition, if the uniformity is insufficient, the difference of the current density distribution will increase again during the electroplating process, so that the pinch-off phenomenon is more likely to occur; in sidewall continuity, if a film break or under-coverage occurs, the plating will preferentially deposit at the end of the film, thereby creating a void.
3. The electroplating liquid medicine of TSV mainly comprises an inhibitor, an accelerator and a leveling agent, and the electroplating liquid is required to have stronger capability of inhibiting orifice electroplating for electroplating TSV with a high aspect ratio. While selection of appropriate current parameters to provide an appropriate current density for the plating process can also prevent premature closing of the orifice to some extent. The electroplating solution in the TSV manufacturing process is also used as a high-end electronic chemical, and the market scale of the electroplating solution is not large compared with chemicals such as photoresist and CMP polishing solution. Electroplating additives, which are key materials in chip manufacturing, are basically monopolized by foreign companies, and the high technical difficulty and the relatively low market capacity thereof make most enterprises lose research interest. At present, the demand of electroplating solution for some domestic large-scale wafer factories is increasing year by year. The self-sufficiency of the basic plating solution (VMS) can be realized at present in China, and the VMS accounts for about 60 percent of the market share in China. However, the market share of domestic manufacturers in the field of additives required for high-end electroplating is almost zero, and most of the additives are in the stage of verification test, and continuous efforts are still needed.
Many factors need to be considered for a fab to develop a new production line of the TSV with high density and high aspect ratio, and the cost of the three-dimensional packaging process is greatly increased due to yield problems, so that the feasibility of the electroplating process needs to be simulated and verified urgently before mass production, and the demand for the TSV electroplating simulation chip is gradually increased, even the demand is not met.
The invention aims to design an electronic electroplating chip of a high-aspect-ratio through silicon via and a preparation method thereof aiming at the problems in the prior art.
Disclosure of Invention
In view of the problems in the prior art, the present invention provides an electronic plating chip of a high aspect ratio through silicon via and a method for manufacturing the same, which can effectively solve the problems in the prior art.
The technical scheme of the invention is as follows:
a method for preparing a through silicon via with a high aspect ratio comprises the following steps:
s1, coating photoresist on the surface of a silicon substrate, and developing to expose hole sites after photoetching exposure;
s2, covering a passivation layer on the exposed part of the silicon substrate;
s3, etching the bottom surface of the passivation layer, and exposing the silicon substrate corresponding to the bottom surface of the hole position;
s4, etching the silicon substrate corresponding to the bottom surface of the exposed hole site;
s5, repeating the steps S2-S4 for multiple times to obtain the silicon through hole with the target depth, and cleaning and ashing the residual photoresist and passivation substance of the silicon through hole;
and S6, depositing an insulating layer, a barrier layer and a seed layer on the inner wall of the silicon through hole by an ALD (atomic layer deposition) method to obtain the silicon through hole with the high aspect ratio.
Further, the coating of the photoresist on the surface of the silicon substrate includes: defining the depth of a through silicon via to be prepared as H and the thickness of the coated photoresist as D, then H: d = (48-52): 1, coating photoresist with the thickness of D on the surface of the silicon substrate.
Further, the partially covering passivation layer at the exposed hole site of the silicon substrate comprises:
and depositing a polymer on the inner surface of the part of the silicon substrate, which exposes the hole sites, by a plasma deposition process to form a passivation layer.
Further, the passivation layer is formed by depositing and polymerizing a process gas containing a fluorocarbon gas through a plasma deposition process.
Further, the depositing the insulating layer, the barrier layer and the seed layer on the inner wall of the through silicon via by the ALD deposition method includes:
s6.1, vacuumizing the silicon substrate, introducing an oxygen-containing reaction precursor, vacuumizing the silicon substrate when the surface of the through silicon via is adsorbed in a supersaturated state, introducing catalytic gas, and forming an oxide layer with the thickness of an atomic layer on the inner wall of the through silicon via;
s6.2, repeating the step S6.1 to enable the oxide layer to reach the target thickness, and finishing the deposition of the insulating layer on the inner wall of the through silicon via.
Further, the oxygen-containing reaction precursor is siloxane, the diameter of the through silicon via is defined as R, and the target thickness of the oxide layer is greater than 0.05R.
Further, the depositing the insulating layer, the barrier layer and the seed layer on the inner wall of the through silicon via by the ALD deposition method comprises:
s6.3, vacuumizing the silicon substrate, introducing a titanium-containing reaction precursor, vacuumizing the silicon substrate when the surface adsorption of the silicon through hole is in a supersaturated state, introducing a nitrogen-containing reaction precursor, and forming a titanium nitride layer with the thickness of an atomic layer on the inner wall of the silicon through hole;
s6.4, repeating the step S6.3 to enable the titanium nitride layer to reach the target thickness, and finishing the deposition of the barrier layer and the seed layer on the inner wall of the silicon through hole.
Further, the titanium-containing reaction precursor is titanium chloride, the nitrogen-containing reaction precursor is ammonia gas, and the target thickness of the titanium nitride layer is more than 40nm.
The electronic electroplating chip comprises a through silicon via, the through silicon via is prepared by the preparation method of the through silicon via with the high aspect ratio, and the aspect ratio of the through silicon via is 15:1 or more.
Further, the duty ratio of the through silicon via is 1:2 or more.
Accordingly, the present invention provides the following effects and/or advantages:
according to the method provided by the application, passivation, etching and etching are performed in a circulating manner through a three-pulse process, so that the balance problem of etching and passivation during process modification is solved, and the stability of the process is ensured. The silicon through hole with the high depth-to-width ratio can be stably prepared, the ALD is finally selected to carry out the side wall deposition process so as to ensure that the inner side wall of the hole has enough covering capability, the preparation of the silicon through hole with the high depth-to-width ratio is realized, and the prepared silicon through hole can reach the depth-to-width ratio of 15:1 or more, duty ratio is 1:2 or more.
The thickness of this application selection photoresist is H for the degree of depth of through-silicon via: the thickness of the photoresist 101 is (48-52): 1, when etching, the thickness of the photoresist is ensured not to be completely bombarded and fall off before etching is finished.
According to the method, the ALD deposition method is adopted to deposit the insulating layer, the barrier layer and the seed layer on the inner wall of the through silicon via, wherein the silicon substrate is used as a process base, silicon dioxide is used as the insulating layer to prevent TSV electric leakage and signal crosstalk between adjacent TSVs, tiN is used as the barrier layer 104 to prevent copper and silicon oxide from diffusing to influence the reliability of the device, and meanwhile, as the TiN is conductive, the sheet resistance of the TiN is low enough to serve as the seed layer of electronic plating when the thickness of the film reaches a certain degree. Therefore, the silicon through hole prepared by the method can realize the barrier layer and the seed layer at the same time only by titanium nitride with proper thickness.
The method is extremely easy to be applied to the mass preparation of TSV electronic electroplating simulation chips with high density and high depth-to-width ratio, and provides a material basis for the development of subsequent electroplating liquid.
The preparation problem of high-density high aspect ratio TSV electronic electroplating simulation chip is solved endeavouring to solve to this application to reduce the preparation that the cost realized electroplating simulation chip as far as possible, provide the chip basis for subsequent high-density high aspect ratio TSV electronic electroplating, in order to promote the development of TSV plating solution, provide the road for domestic electroplating additive development and development. The process has achieved an aspect ratio of 15;1 and 20: 1. duty ratio 1:1, the high-depth-to-width ratio high-density analog chip is prepared by only adopting a TiN direct electroplating process, has simplified process, lower cost and high fault tolerance, and is suitable for being used as a way for preparing TSV electronic electroplating analog chips.
It is to be understood that both the foregoing general description and the following detailed description of the present invention are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
Drawings
Fig. 1 is a schematic flow diagram of a method provided by the present invention.
Fig. 2 is a diagram illustrating the result obtained in step S1.
Fig. 3 is a diagram illustrating the result obtained in step S2.
Fig. 4 is a diagram illustrating the result obtained in step S3.
Fig. 5 is a diagram illustrating the result obtained in step S4.
Fig. 6 is a diagram illustrating the result obtained in step S5.
Fig. 7 is a diagram illustrating the result obtained in step S6.
Fig. 8-9 are pictorial views of through-silicon vias prepared by the methods provided herein.
Detailed Description
To facilitate understanding of those skilled in the art, the structure of the present invention will now be described in further detail by way of examples in conjunction with the accompanying drawings: it should be understood that, unless the order is specifically stated, the steps mentioned in the present embodiment can be performed in any order, or even simultaneously or partially simultaneously.
In the prior art, a bosch process is generally adopted for preparing the silicon through holes, namely, two steps of etching and passivating are circularly and alternately carried out, sulfur hexafluoride can be adopted for etching in the bosch process, the sulfur hexafluoride is used for providing F ions, and C and F are provided as 1 through tetracarbon octafluoride: 2 to form a passivation layer. And etching and passivating in a circulating way can be carried out layer by layer on the silicon substrate, deeper silicon through holes can be prepared downwards by etching-passivating each time, and the silicon substrate with the target depth can be obtained after multiple cycles. However, the number of cycles required is large, and it is difficult to achieve stability in the process of manufacturing high aspect ratio through silicon vias.
Referring to fig. 1, a method for manufacturing a through silicon via with a high aspect ratio includes the following steps:
s1, coating photoresist 101 on the surface of a silicon substrate 100, and developing to expose hole sites after photoetching exposure;
this step is a straightforward adoption of the prior art. The silicon substrate used in this embodiment is shown in fig. 2, and the basic pattern of the TSV array is defined thereon by using a photolithography method. By spin-coating the photoresist 101 on the silicon substrate 100, the photoresist is used as a mask for subsequent etching, and the thickness of the photoresist is determined by the final etching depth, and it is required to ensure that the verticality of the photoresist 101 is sufficient to avoid excessive deviation of the etching. At this time, the silicon substrate 100 exposing the hole sites to be etched is obtained.
S2, covering a passivation layer on the exposed part of the silicon substrate 100;
in S1, a silicon substrate 100 exposing a hole site where a through-silicon via needs to be etched is obtained. This step begins etching down at the hole sites. First, a passivation layer is covered on an exposed portion of the silicon substrate 100 through a passivation process. This step needs to be performed alternately with the subsequent steps, so that the exposed portion of the silicon substrate 100 is changed all the time, for example, the exposed portion of the silicon substrate 100 is the upper surface of the silicon substrate 100 at the beginning, and in the subsequent etching process, referring to fig. 3, a deeper and deeper through silicon via is formed downward on the silicon substrate 100, and the exposed portion of the substrate 100 is the inner wall of the through silicon via at this time.
S3, etching the bottom surface of the passivation layer 105, and exposing the silicon substrate 100 corresponding to the bottom surface of the hole position;
before the step is performed, the passivation layer 105 is as shown in fig. 3, and the passivation layer 105 covers the side wall and the bottom surface of the through-silicon via of the silicon substrate 100, where the passivation layer 105 may protect the exposed portion of the silicon substrate 100, and removing the passivation layer 105 may re-expose the portion of the silicon substrate 100 that needs to be etched, so as to etch the silicon substrate 100 again to reach a deeper depth.
In this step, only the bottom surface of the passivation layer 105 is etched, as shown in fig. 4, the passivation layer 105 located at the bottom only needs to be etched during etching, when the bottom surface 105 of the passivation layer formed in the step S2 is just etched away in the etching in this step, it is considered that the steps S2 and S3 reach a balanced state, at this time, the bottom of the through silicon via is exposed and is no longer protected by the passivation layer 105, and the passivation layer 105 remaining on the side wall of the through silicon via can protect the side wall from being affected by etching in the subsequent etching process.
S4, etching the silicon substrate 100 corresponding to the bottom surface of the exposed hole;
the step changes the existing passivation-etching circulating silicon through hole preparation method, adds the step S4, and can change the etching depth of the TSV only by changing the etching parameters of the step under the condition of ensuring the balance of the previous steps S2-S3 without influencing the etching/passivation balance.
By this step, when the former S2-S3 reach the ideal condition of equilibrium, the etching of S4 is the process of actually etching the silicon substrate 100. And through downward etching, the silicon through hole with deeper deep hole can be obtained.
S5, repeating the steps S2-S4 for multiple times to obtain the silicon through hole with the target depth, and cleaning and ashing the residual photoresist and passivation substance of the silicon through hole;
and performing periodic passivation, etching and etching by circulating the steps S2-S4, so that the TSV basic structure can be realized.
Finally, the photoresist 101 and the sidewall passivation layer 105 remaining by the cleaning and ashing processes remain after the etching is finished. S2-S5 circularly perform passivation, etching and etching through a three-pulse process, so that the balance problem of etching and passivation during process modification is solved, and the stability of the process is ensured. A high aspect ratio through-silicon via can be stably fabricated, resulting in the through-silicon via shown in fig. 6.
And S6, depositing an insulating layer 103, a barrier layer 104 and a seed layer 104 on the inner wall of the through silicon via by an ALD (atomic layer deposition) method to obtain the through silicon via with the high aspect ratio as shown in FIG. 7.
The through silicon via manufactured in step S5 is only a simple through hole, and an insulating layer, a barrier layer, and a seed layer are also required to be manufactured in the through silicon via, so that a through silicon via structure for signal connection between the vertical sides of the chip can be obtained.
The embodiment provides a preparation scheme of a TSV electroplating simulation chip with a high aspect ratio, but the conventional PVD and CVD deposition methods cannot be applied to a TSV electroplating simulation chip with an aspect ratio of 10: more than 1 TSV bottom deposits oxide or metal to cause the insulating layer, barrier layer, seed layer can not be covered in the hole uniformly, under the above conditions, this embodiment can select ALD to perform sidewall deposition process to ensure the sidewall in the hole has sufficient covering capability.
Further, the coating of the photoresist on the surface of the silicon substrate 100 includes: defining the depth of the silicon through hole to be prepared as H, and the thickness of the coating photoresist 101 as D, then H: d = (48-52): 1, coating photoresist 101 with the thickness of D on the surface of a silicon substrate.
In the above description, the photoresist 101 is used as a mask for subsequent etching, and the thickness thereof is determined by the final etching depth, and it is necessary to ensure that the verticality of the photoresist 101 is sufficient to avoid excessive deviation of the etching. During etching, the silicon substrate is mainly etched, but due to the action of part of physical bombardment, the photoresist can also be bombarded and fall off, so that the photoresist is not completely bombarded and fall off before etching is finished during etching.
In this embodiment, the depth of the through silicon via is H: the thickness D of the coating photoresist 101 was 50:1, the above effects can be surely achieved. In other embodiments, 48:1 or 52:1.
further, the partially covering passivation layer at the exposed hole site of the silicon substrate comprises:
and depositing a polymer on the inner surface of the part of the silicon substrate, which exposes the hole sites, by a plasma deposition process to form a passivation layer.
Further, the passivation layer is formed by depositing and polymerizing a process gas containing a fluorocarbon gas through a plasma deposition process.
In this embodiment, the passivation layer is directly covered on the exposed hole of the silicon substrate in the prior art. In the prior art, a plasma deposition process is generally adopted for passivation, and plasma chemical vapor deposition (plasma chemical vapor deposition) refers to a technique for activating a reaction gas by using plasma to promote a chemical reaction on a substrate surface or a near-surface space to generate a solid film.
A passivation layer may be formed on the exposed portions of the silicon substrate, the through-silicon via, by gas deposition with a fluorocarbon-containing gas. In this embodiment, the fluorocarbon-containing gas is C 4 F 8 Providing C and F are 1:2.
Further, the depositing the insulating layer, the barrier layer and the seed layer on the inner wall of the through silicon via by the ALD deposition method includes:
s6.1, vacuumizing the silicon substrate, introducing an oxygen-containing reaction precursor, wherein the oxygen-containing reaction precursor is siloxane, vacuumizing the silicon substrate when the surface of the silicon through hole is adsorbed in a supersaturated state, and introducing catalytic gas to form an oxide layer with the thickness of an atomic layer on the inner wall of the silicon through hole;
in this step, an ALD deposition method is used to form the insulating layer. The specific reaction process is as follows: the silicon substrate with the through silicon holes is placed in an ALD device, when the ALD device is in a vacuum state, a reaction precursor is introduced, the reaction precursor is an oxygen-containing reaction precursor, when the surface adsorption is in a supersaturated state, redundant gas is extracted to reach the vacuum state again, and then catalytic gas is introduced. At the moment, the surface reacts to generate silicon oxide with the thickness of one atomic layer; other reaction products were subsequently excluded.
S6.2, repeating the step S6.1, defining the diameter of the through silicon via as R, and defining the target thickness of the oxide layer as more than 0.05R, so that the oxide layer reaches the target thickness, and depositing the insulating layer on the inner wall of the through silicon via is completed.
In this step, the above process is repeated until the target thickness is reached. The thickness of the insulating layer 103 is selected according to the actual diameter R of the TSV, and generally needs to be greater than 0.05R to ensure that the TSV is not broken down to generate leakage current.
Further, the depositing the insulating layer, the barrier layer and the seed layer on the inner wall of the through silicon via by the ALD deposition method comprises:
s6.3, vacuumizing the silicon substrate, introducing a titanium-containing reaction precursor, vacuumizing the silicon substrate when the surface adsorption of the through silicon via is in a supersaturated state, introducing a nitrogen-containing reaction precursor, and forming a titanium nitride layer with the thickness of an atomic layer on the inner wall of the through silicon via;
in this step, the same as the step S6.1 except that the reaction precursor is different. In the step, in order to cover a titanium nitride layer in the through silicon via, the reaction precursor also needs to correspondingly contain titanium and nitrogen elements,
s6.4, repeating the step S6.3 to enable the titanium nitride layer to reach the target thickness, and finishing the deposition of the barrier layer and the seed layer on the inner wall of the silicon through hole.
Further, the titanium-containing reaction precursor is titanium chloride, the nitrogen-containing reaction precursor is ammonia gas, and the target thickness of the titanium nitride layer is more than 40nm.
The thickness of the barrier and seed layers 104 is selected to ensure that the sheet resistance is sufficient for successful copper plating, and is typically greater than 40nm.
In the step, through S6.1-S6.4, an insulating layer, a barrier layer and a seed layer can be deposited on the inner wall of the through silicon via by using an ALD deposition method. The silicon substrate 100 is used as a process foundation, the silicon dioxide is used as an insulating layer 103 to prevent TSV leakage and signal crosstalk between adjacent TSVs, the TiN is used as a barrier layer 104 to prevent copper and silicon oxide from diffusing to influence the reliability of the device, and meanwhile, the TiN has conductivity, so that the sheet resistance of the TiN is low enough to be used as a seed layer 104 for electronic plating when the thickness of a film reaches a certain degree. Therefore, the silicon through hole prepared by the method can realize the barrier layer and the seed layer at the same time only by titanium nitride with proper thickness.
Since the through-silicon via prepared by the embodiment has a high aspect ratio, the uniformity of the deposited film is difficult to ensure by a general PVD means in a sidewall deposition stage, and the uniformity of the film will seriously affect the electroplating effect, thereby affecting the effects of the insulating layer, the barrier layer and the seed layer. Therefore, the invention adopts the ALD deposition process, and simultaneously, because the traditional ALD process of the Cu seed layer is of a bubbling type and has lower deposition efficiency, tiN with higher deposition rate is adopted as the seed layer, thereby shortening the manufacturing process and saving the time and the cost
Further provides an electronic plating chip of the high aspect ratio through silicon via, the electronic plating chip comprises a through silicon via, the through silicon via is prepared by the preparation method of the high aspect ratio through silicon via, and the aspect ratio of the through silicon via is 15:1 or more.
Further, the duty ratio of the through silicon via is 1:2 or more.
Through the through silicon via preparation method provided by the embodiment, the through silicon via of the prepared electronic plating chip can reach the depth-to-width ratio of 15:1 or more. Meanwhile, according to the through silicon via preparation method provided by the embodiment, due to the adoption of the ALD deposition method, the reaction precursor or the catalytic gas can accurately, stably and uniformly reach the inside of the through silicon via, so that the depth-to-width ratio of the through silicon via prepared by the method can be higher, and the duty ratio can be higher. The technical effect can not be achieved by the prior art.
Experimental data
Referring to fig. 8-9, the through-silicon via prepared by the method provided by the present application has an aspect ratio of 15:1 or more. Wherein, the through-silicon via that figure 8 shows, the width is 5um, and the degree of depth is 100um, aspect ratio 20, duty cycle 1:2. the through-silicon via shown in fig. 9 has a width of 1.3um, a depth of 20um, an aspect ratio of 15.3, a duty ratio of 1:2.
the method provided by the application is feasible, and the depth-to-width ratio of the silicon through hole prepared by the application can reach 15: more than 1, the duty ratio of the through silicon via prepared by the method is 1:2 or more.
It should be noted that in the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The invention can be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means can be embodied by one and the same item of hardware. The usage of the words first, second and third, etcetera do not indicate any ordering. These words may be interpreted as names.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or may be connected through the use of two elements or the interaction of two elements. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above should not be understood to necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
Claims (10)
1. A method for preparing a silicon through hole with a high depth-to-width ratio is characterized by comprising the following steps: comprises the following steps:
s1, coating photoresist on the surface of a silicon substrate, and developing to expose hole sites after photoetching exposure;
s2, covering a passivation layer on the exposed hole position part of the silicon substrate;
s3, etching the bottom surface of the passivation layer and exposing the silicon substrate corresponding to the bottom surface of the hole site;
s4, etching the silicon substrate corresponding to the bottom surface of the exposed hole site;
s5, repeating the steps S2-S4 for multiple times to obtain the silicon through hole with the target depth, and cleaning and ashing the residual photoresist and passivation of the silicon through hole;
and S6, depositing an insulating layer, a barrier layer and a seed layer on the inner wall of the silicon through hole by an ALD (atomic layer deposition) method to obtain the silicon through hole with the high aspect ratio.
2. The method of claim 1, wherein the step of forming the through-silicon via has a high aspect ratio, comprises: the step of coating the photoresist on the surface of the silicon substrate comprises the following steps: defining the depth of a through silicon via to be prepared as H and the thickness of the coated photoresist as D, then H: d = (48-52): 1, coating photoresist with the thickness of D on the surface of the silicon substrate.
3. The method of claim 1, wherein the step of forming the through-silicon via has a high aspect ratio, comprises: the partial covering passivation layer at the exposed hole position of the silicon substrate comprises:
and depositing a polymer on the inner surface of the part of the silicon substrate, which exposes the hole sites, by a plasma deposition process to form a passivation layer.
4. The method of claim 3, wherein the step of forming the through-silicon via with high aspect ratio comprises: and depositing and polymerizing the process gas containing the carbon-fluorine gas by a plasma deposition process to form the passivation layer.
5. The method of claim 1, wherein the step of forming the through-silicon via has a high aspect ratio, comprises: the depositing of the insulating layer, the barrier layer and the seed layer on the inner wall of the through silicon via through the ALD method comprises the following steps:
s6.1, vacuumizing the silicon substrate, introducing an oxygen-containing reaction precursor, vacuumizing the silicon substrate when the surface of the silicon through hole is adsorbed in a supersaturated state, and introducing catalytic gas to form an oxide layer with the thickness of an atomic layer on the inner wall of the silicon through hole;
s6.2, repeating the step S6.1 to enable the oxide layer to reach the target thickness, and finishing the deposition of the insulating layer on the inner wall of the through silicon via.
6. The method of claim 5, wherein the step of forming the through-silicon via has a high aspect ratio, further comprises: the oxygen-containing reaction precursor is siloxane, the diameter of the through silicon via is defined as R, and the target thickness of the oxide layer is more than 0.05R.
7. The method of claim 1, wherein the step of forming the through-silicon via with high aspect ratio comprises: the depositing of the insulating layer, the barrier layer and the seed layer on the inner wall of the through silicon via through the ALD method comprises the following steps:
s6.3, vacuumizing the silicon substrate, introducing a titanium-containing reaction precursor, vacuumizing the silicon substrate when the surface adsorption of the through silicon via is in a supersaturated state, introducing a nitrogen-containing reaction precursor, and forming a titanium nitride layer with the thickness of an atomic layer on the inner wall of the through silicon via;
s6.4, repeating the step S6.3 to enable the titanium nitride layer to reach the target thickness, and finishing the deposition of the barrier layer and the seed layer on the inner wall of the silicon through hole.
8. The method of claim 7, wherein the step of forming the through-silicon via has a high aspect ratio, further comprises: the titanium-containing reaction precursor is titanium chloride, the nitrogen-containing reaction precursor is ammonia gas, and the target thickness of the titanium nitride layer is more than 40nm.
9. An electronic electroplating chip of a through silicon via with a high depth-to-width ratio is characterized in that: the electronic plating chip comprises a through silicon via, the through silicon via is prepared by the method for preparing the through silicon via with the high aspect ratio according to any one of claims 1 to 8, and the aspect ratio of the through silicon via is 15:1 or more.
10. The electronic plating chip of high aspect ratio through-silicon-via of claim 9, wherein: the duty ratio of the through silicon via is 1:2 or more.
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| PCT/CN2023/089762 WO2024066309A1 (en) | 2022-09-30 | 2023-04-21 | Preparation method for through-silicon via having high aspect ratio and electronic electroplating chip having same |
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| CN115394710A (en) * | 2022-09-30 | 2022-11-25 | 厦门大学 | Electronic electroplating chip of high-aspect-ratio through silicon via and preparation method |
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