CN115394239A - Display panel and display device - Google Patents

Abstract

The application discloses display panel and display device, this display panel includes a plurality of sub-pixels, many scanning lines and many data lines, through dispose at least a row of sub-pixel in pixel unit and include first sub-pixel, the second sub-pixel that distributes along the first direction in proper order in turn, then many scanning lines are used for driving odd row sub-pixel along the first direction in proper order earlier in a frame, again along the first direction drive even row sub-pixel in proper order, reduced display panel's power consumption.

Description

Display panel and display device

Technical Field

The application relates to the technical field of display, in particular to a display panel and a display device.

Background

The display panel is widely applied to mobile consumer electronics, and for the mobile consumer electronics, not only the corresponding display effect needs to be realized, but also the endurance time needs to be considered, and the power consumption is inversely proportional to the endurance time, so that the low power consumption is one of the targets that the display panel pursues.

Disclosure of Invention

The application provides a display panel and a display device to alleviate the technical problem that the power consumption is high due to frequent potential switching of data signals.

In a first aspect, the present application provides a display panel, which includes a plurality of sub-pixels, a plurality of scan lines, and a plurality of data lines, where the plurality of sub-pixels includes at least one pixel unit, each pixel unit includes N × 4 rows of sub-pixels, where N is a positive integer, and at least one column of sub-pixels in the pixel unit includes first sub-pixels and second sub-pixels alternately distributed in sequence along a first direction; the plurality of scanning lines are sequentially arranged along a first direction, each scanning line is connected with a corresponding row of sub-pixels in the pixel unit, and the plurality of scanning lines are used for sequentially driving odd-numbered rows of sub-pixels along the first direction and then sequentially driving even-numbered rows of sub-pixels along the first direction in one frame; the plurality of data lines are sequentially arranged along the second direction, each data line is connected with a column of sub-pixels corresponding to the pixel unit, and the plurality of data lines are used for outputting corresponding data signals according to the driving time sequence of the plurality of scanning lines.

In some embodiments, each pixel unit comprises a first row of sub-pixels, a second row of sub-pixels, a third row of sub-pixels and a fourth row of sub-pixels arranged in sequence along a first direction; the plurality of scanning lines comprise a first scanning line, a second scanning line, a third scanning line and a fourth scanning line which are sequentially arranged along a first direction, the first scanning line is connected with the first row of sub-pixels, the second scanning line is connected with the second row of sub-pixels, the third scanning line is connected with the third row of sub-pixels, and the fourth scanning line is connected with the fourth row of sub-pixels; in one frame, the first scanning line and the third scanning line sequentially drive the first row of sub-pixels and the third row of sub-pixels respectively, and the second scanning line and the fourth scanning line sequentially drive the second row of sub-pixels and the fourth row of sub-pixels respectively.

In some embodiments, each pixel unit further includes a fifth row of sub-pixels, a sixth row of sub-pixels, a seventh row of sub-pixels, and an eighth row of sub-pixels arranged in sequence along the first direction; the plurality of scanning lines further comprise a fifth scanning line, a sixth scanning line, a seventh scanning line and an eighth scanning line which are sequentially arranged along the first direction, the fifth scanning line is connected with the sub-pixels in the fifth row, the sixth scanning line is connected with the sub-pixels in the sixth row, the seventh scanning line is connected with the sub-pixels in the seventh row, and the eighth scanning line is connected with the sub-pixels in the eighth row; in one frame, a first scanning line, a third scanning line, a fifth scanning line and a seventh scanning line sequentially drive a first row of sub-pixels, a third row of sub-pixels, a fifth row of sub-pixels and a seventh row of sub-pixels respectively, and a second scanning line, a fourth scanning line, a sixth scanning line and an eighth scanning line sequentially drive a second row of sub-pixels, a fourth row of sub-pixels, a sixth row of sub-pixels and an eighth row of sub-pixels respectively.

In some embodiments, the pixel unit is configured with a first column of sub-pixels, a second column of sub-pixels and a third column of sub-pixels arranged in sequence along a second direction; the first column of sub-pixels comprise first sub-pixels and second sub-pixels which are sequentially and alternately distributed along a first direction, the second column of sub-pixels comprise a plurality of third sub-pixels which are distributed along the first direction, and the third column of sub-pixels comprise second sub-pixels and first sub-pixels which are sequentially and alternately distributed along the first direction.

In some embodiments, the first sub-pixel is one of a red sub-pixel, a green sub-pixel, or a blue sub-pixel, the second sub-pixel is another one of the red sub-pixel, the green sub-pixel, or the blue sub-pixel, and the third sub-pixel is another one of the red sub-pixel, the green sub-pixel, or the blue sub-pixel.

In some embodiments, in the pixel unit, a data line continuously charges at least two first sub-pixels and/or at least two second sub-pixels.

In some of these embodiments, each scan line transmits a scan signal; the driving time sequence of the plurality of scanning lines is the sequence of the pulses of the plurality of scanning signals appearing in one frame.

In some embodiments, the odd-row sub-pixels and the even-row sub-pixels are alternately distributed along the first direction.

In a second aspect, the present application provides a display device, which includes the display panel and the gate driving circuit in at least one of the above embodiments, wherein the gate driving circuit is connected to the plurality of scan lines respectively, and is configured to control a driving timing of the plurality of scan lines.

In some embodiments, the display device further includes a data driver connected to the plurality of data lines, respectively; each data line transmits a data signal; the data driver includes a data mapping module for modulating a voltage output timing of the data signal according to the driving timing.

According to the display panel and the display device, at least one column of sub-pixels are arranged in the pixel unit and comprise first sub-pixels and second sub-pixels which are sequentially and alternately distributed along the first direction, then the plurality of scanning lines are used for sequentially driving odd-row sub-pixels along the first direction and sequentially driving even-row sub-pixels along the first direction in one frame, so that data signals provided by the corresponding data lines can continuously provide the same charging voltage for at least two first sub-pixels or at least two second sub-pixels, the potential switching frequency of the data signals is reduced, and the power consumption of the display panel is further reduced.

Drawings

The technical solutions and other advantages of the present application will become apparent from the following detailed description of specific embodiments of the present application when taken in conjunction with the accompanying drawings.

Fig. 1 is a schematic structural diagram of a pixel circuit in the related art.

Fig. 2 is a timing diagram of the pixel circuit shown in fig. 1.

Fig. 3 is a diagram illustrating frame time allocation at different frequencies.

Fig. 4 is a schematic diagram of another structure of a pixel circuit in the related art.

FIG. 5 is a timing diagram of the pixel circuit shown in FIG. 4.

Fig. 6 is a schematic structural diagram of a display device according to an embodiment of the present disclosure.

Fig. 7 is a schematic structural diagram of a display device according to an embodiment of the present application.

FIG. 8 is a diagram illustrating a driving timing of the display device shown in FIG. 7 in the related art.

FIG. 9 is a diagram illustrating potential variations of the data signals in FIG. 8.

FIG. 10 is a timing diagram illustrating the driving of the display device shown in FIG. 7 according to the present application.

FIG. 11 is a diagram illustrating the potential variation of the data signal in FIG. 10.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

Fig. 1 is a schematic structural diagram of a pixel circuit in the related art, the pixel circuit includes a first initialization transistor T7, a second initialization transistor T4, a compensation transistor T3, a driving transistor T1, a writing transistor T2, a first light emission control transistor T5, a second light emission control transistor T6, a storage capacitor Cst, and a light emitting device LED, a positive power line is connected to one end of the storage capacitor Cst and one of the source/drain of the first light emission control transistor T5, the other of the source/drain of the first light emission control transistor T5 is connected to one of the source/drain of the writing transistor T2 and one of the source/drain of the driving transistor T1, a gate of the first light emission control transistor T5 is connected to a light emission control line, the other of the source/drain of the writing transistor T2 is connected to a data line, a gate of the writing transistor T2 is connected to a first control line, the other of the source/drain of the driving transistor T1 is connected to one of the source/drain of the compensating transistor T3 and one of the source/drain of the second light emission controlling transistor T6, the other of the source/drain of the second light emission controlling transistor T6 is connected to one of the anode of the light emitting device LED and the source/drain of the first initializing transistor T7, the cathode of the light emitting device LED is connected to the negative power line, the gate of the first initializing transistor T7 is connected to the second control line, the other of the source/drain of the first initializing transistor T7 is connected to one of the reference voltage line and the source/drain of the second initializing transistor T4, the gate of the second initializing transistor T4 is connected to the second control line, the other of the source/drain of the second initializing transistor T4 is connected to the other end of the storage capacitor Cst, the other of the source/drain of the compensation transistor T3 and the gate of the driving transistor T1 are connected, and the gate of the compensation transistor T3 is connected to a first control line.

Where point G is indicated as the gate of the drive transistor T1. The positive power line is used for transmitting a power positive signal ELVDD, the negative power line is used for transmitting a power negative signal ELVSS, the potential of the power positive signal ELVDD is generally positive voltage, and the potential of the power negative signal ELVSS is generally negative voltage. The emission control line is used to transmit an emission control signal EM. The DATA lines are used for transmitting DATA signals DATA. The reference voltage line is used for transmitting a reference voltage signal VREF. The first control line is used for transmitting a first control signal S2. The second control signal S1 is used to transmit the second control signal S1.

The light emitting device LED may be an organic light emitting diode, a micro light emitting diode, a mini light emitting diode, or a quantum dot light emitting diode.

The first initialization transistor T7, the second initialization transistor T4, the compensation transistor T3, the driving transistor T1, the writing transistor T2, the first light emitting control transistor T5, and the second light emitting control transistor T6 may all be P-channel thin film transistors, and may specifically be low temperature polysilicon thin film transistors.

Fig. 2 is a timing diagram of the pixel circuit shown in fig. 1, and the operation stage of the pixel circuit shown in fig. 1 in one frame includes the following stages:

reset phase P1: the second control signal S1 is at a low level, the first initialization transistor T7 and the second initialization transistor T4 are turned on, the emission control signal EM and the first control signal S2 are at a high level, and the other transistors are turned off. And pulling the potential of the point G and the anode of the light-emitting device LED to the potential of the reference voltage signal VREF, and resetting the anode of the light-emitting device LED and the grid electrode of the driving transistor T1, namely the point G.

And a charging compensation stage P2, wherein the first control signal S2 is at a low level, the second control signal S1 and the light-emitting control signal EM are at a high level, the compensation transistor T3 and the writing transistor T2 are turned on, and the driving transistor T1 is turned on to charge the point G because the potential of the point G in the reset stage P1 is the potential of the reference voltage signal VREF.

Light emission phase P3: the light emission control signal EM is at a low level, the first light emission control transistor T5, the second light emission control transistor T6, and the driving transistor T1 are turned on, and the other transistors are turned off, so that the light emitting device LED emits light.

The working frequency of the display product is not limited to 60hz, but may be 120hz, 90hz, and other frequency points, and in order to ensure the screen display effect and avoid the brightness difference caused by the switching of different frequencies, the data writing time T10 of different frequency points is the same, and the data writing time T10 is as shown in fig. 3. The data writing time T10 is the same for all frequencies in one frame (1 frame), and the rest of the time is filled in the blank time T11, and the blank time T11 is decreased as the frequency increases.

On the premise of the above driving scheme, the driving scheme for saving power consumption:

firstly, the method comprises the following steps: during the blank time T11, the voltage output of the DATA signal DATA is closed;

secondly, the method comprises the following steps: during the blank time T11, the first control signal S2 and/or the second control signal S1 associated with the data write time T10 are turned off.

The scheme mainly utilizes the fact that the corresponding signals and the corresponding voltages are turned off in the blank time T11, and the purpose of saving power consumption can be achieved. As can be seen from fig. 3, the blank time T11 has different time lengths at different frequencies, and the shorter the blank time T11 is at a higher frequency, the less power consumption can be relatively reduced, that is, the higher the frequency, the higher the power consumption. The scheme for saving power consumption is mainly realized by reducing the power consumption of each signal in the pixel circuit, and the reduced power consumption proportion is relatively small.

In order to save power consumption, a new LTPO (Low Temperature Polycrystalline Oxide) process is developed, that is, the compensation transistor T3, the first initialization transistor T7 and the second initialization transistor T4 in fig. 1 are replaced by metal Oxide thin film transistors, specifically indium gallium zinc Oxide thin film transistors, of which the channel types are as shown in fig. 4, so that the gate leakage current of the driving transistor T1 can be reduced, and Low-frequency driving is realized. Different frequencies are used according to the application scene displayed, for example, a 30Hz or 1Hz frequency can be used for a static image, and the aim of saving power consumption can be achieved as a whole.

Compared with the pixel circuit shown in fig. 1, in the pixel circuit shown in fig. 4, the compensation transistor T3, the first initialization transistor T7, and the second initialization transistor T4 are replaced by indium gallium zinc oxide thin film transistors, correspondingly, the gate of the first initialization transistor T7 is still connected to the second control signal S1, the connection signal of the gate of the second initialization transistor T4 is changed to the first control signal S2, the connection signal written into the gate of the transistor T2 is changed to the third control signal S3, and the connection signal of the gate of the compensation transistor T3 is changed to the fourth control signal S4.

The operation stages of the pixel circuit shown in fig. 4 in one frame are shown in fig. 5, and include the following stages:

the first stage is as follows: the first control signal S2 and the second control signal S1 are at a high level, and reset the gate potential of the driving transistor T1 and the anode potential of the light emitting device LED.

And a second stage: the third control signal S3 is at a low level, the fourth control signal S4 is at a high level, and the DATA signal DATA is written to the gate of the driving transistor T1.

And a third stage: the light emission control signal EM is at a low level, and the light emitting device LED emits light.

For the pixel circuits shown in fig. 4 and 5, there is still leakage current at the time of low frequency operation, resulting in flicker. To solve the flicker problem, the second control signal S1, the third control signal S3, and the DATA signal DATA still need to operate for a blank (Blanking) time, i.e., continuously consume power consumption. It can be seen that the solution for saving power consumption in the pixel circuits shown in fig. 1 to 3 cannot be applied to the pixel circuits shown in fig. 4 and 5.

In summary, the above schemes for reducing power consumption all have certain limitations. Therefore, it is necessary to provide a new driving scheme capable of reducing power consumption as a whole, so as to be suitable for various pixel circuits.

Fig. 6 is a schematic structural diagram of a display device according to an embodiment of the present application, where the display device includes a DATA driver 200 and a display panel 300, and the DATA driver 200 provides a control signal with power consumption and a DATA signal DATA for the display panel 300; the external driving power supplies provide the data driver 200 with the first power supply VDDIO, the second power supply AVDD, and the third power supply VCI, so as to ensure the normal operation of the data driver 200. Meanwhile, the light emitting power supplies the display panel 300 with a positive power supply signal ELVDD and a negative power supply signal ELVSS.

It is understood that reducing the power consumption of at least one of the first power supply VDDIO, the second power supply AVDD, the third power supply VCI, the control signal, the DATA signal DATA, the power positive signal ELVDD, and the power negative signal ELVSS may achieve the purpose of reducing the power consumption.

In view of the limitations of the above-mentioned technical means for reducing power consumption, it is therefore necessary to provide a technical means for reducing the switching frequency of the DATA signal DATA to reduce power consumption, and thus, the present embodiment provides a display panel 300, as shown in fig. 7, 10 and 11, and the display panel 300 includes a plurality of sub-pixels, a plurality of scan lines and a plurality of DATA lines, with reference to fig. 1 to 11.

The plurality of sub-pixels comprises at least one pixel unit, each pixel unit comprises N x 4 rows of sub-pixels, wherein N is a positive integer.

For example, when N is 1, one pixel unit may include 4 rows of sub-pixels as shown in fig. 7. It is understood that N may also be a positive integer of 2, 3, 4, 5.

At least one column of sub-pixels in the pixel unit includes first sub-pixels and second sub-pixels alternately distributed along the first direction DR 1.

It should be noted that, in different embodiments, the first sub-pixel may be one of a red sub-pixel, a green sub-pixel, or a blue sub-pixel; the second sub-pixel may be another one of the red sub-pixel, the green sub-pixel, or the blue sub-pixel.

The plurality of scanning lines are sequentially arranged along the first direction DR1, each scanning line is connected with a corresponding row of sub-pixels in the pixel unit, and the plurality of scanning lines are used for sequentially driving odd-numbered rows of sub-pixels along the first direction DR1 and then sequentially driving even-numbered rows of sub-pixels along the first direction DR1 in one frame.

It should be noted that, in this way, at least two first sub-pixels or at least two second sub-pixels in the same column of sub-pixels can be driven or turned on continuously, and it lays a foundation for the DATA signal DATA to provide the same charging voltage to at least two first sub-pixels or at least two second sub-pixels continuously.

The plurality of DATA lines are sequentially arranged along the second direction DR2, each DATA line is connected to a corresponding column of sub-pixels in the pixel unit, and the plurality of DATA lines are used for outputting corresponding DATA signals DATA according to the driving time sequence of the plurality of scanning lines.

It can be understood that, in the display panel 300 provided in this embodiment, at least one column of sub-pixels includes first sub-pixels and second sub-pixels alternately distributed in sequence along the first direction DR1, and then a plurality of scan lines are used to sequentially drive odd-row sub-pixels and then sequentially drive even-row sub-pixels along the first direction DR1 in one frame, so that the DATA signals DATA provided by the corresponding DATA lines can continuously provide the same charging voltage for at least two first sub-pixels or at least two second sub-pixels, thereby reducing the potential switching frequency of the DATA signals DATA and further reducing the power consumption of the display panel 300.

In one embodiment, as shown in fig. 7, each pixel unit includes a first row of sub-pixels, a second row of sub-pixels, a third row of sub-pixels, and a fourth row of sub-pixels arranged in sequence along the first direction DR 1; the plurality of scanning lines include a first scanning line GL1, a second scanning line GL2, a third scanning line GL3 and a fourth scanning line GL4 sequentially arranged along the first direction DR1, the first scanning line GL1 is connected to the first row of sub-pixels, the second scanning line GL2 is connected to the second row of sub-pixels, the third scanning line GL3 is connected to the third row of sub-pixels, and the fourth scanning line GL4 is connected to the fourth row of sub-pixels; in one frame, the first scanning line GL1 and the third scanning line GL3 sequentially drive the first row of sub-pixels and the third row of sub-pixels, respectively, and the second scanning line GL2 and the fourth scanning line GL4 sequentially drive the second row of sub-pixels and the fourth row of sub-pixels, respectively.

The first scanning line GL1, the second scanning line GL2, the third scanning line GL3, and the fourth scanning line GL4 are sequentially used for transmitting a first scanning signal G1, a second scanning signal G2, a third scanning signal G3, and a fourth scanning signal G4, respectively.

The first data line DL1 is connected to the first column of sub-pixels, the second data line DL2 is connected to the second column of sub-pixels, the third data line DL3 is connected to the third column of sub-pixels, and the fourth data line DL4 is connected to the fourth column of sub-pixels. The first data line DL1, the second data line DL2, the third data line DL3 and the fourth data line DL4 are sequentially used for transmitting a first data signal D1, a second data signal D2, a third data signal D3 and a fourth data signal D4, respectively.

It can be understood that, in this embodiment, when the first scanning line GL1 and the third scanning line GL3 sequentially drive the first row sub-pixel and the third row sub-pixel, respectively, the first DATA signal D1 can continuously charge the two first sub-pixels with the same color in the first column sub-pixel without switching the potential, so that the power consumption of the DATA signal DATA can be reduced. Similarly, when the second scanning line GL2 and the fourth scanning line GL4 sequentially drive the second row sub-pixel and the fourth row sub-pixel, respectively, the first DATA signal D1 can continuously charge the two second sub-pixels with the same color in the first column sub-pixel without switching the potential, so as to reduce the power consumption of the DATA signal DATA.

In one embodiment, each pixel unit further includes a fifth row of sub-pixels, a sixth row of sub-pixels, a seventh row of sub-pixels, and an eighth row of sub-pixels arranged in sequence along the first direction DR 1; the plurality of scanning lines further comprise a fifth scanning line, a sixth scanning line, a seventh scanning line and an eighth scanning line which are sequentially arranged along the first direction DR1, the fifth scanning line is connected with the sub-pixels in the fifth row, the sixth scanning line is connected with the sub-pixels in the sixth row, the seventh scanning line is connected with the sub-pixels in the seventh row, and the eighth scanning line is connected with the sub-pixels in the eighth row; in one frame, the first scanning line GL1, the third scanning line GL3, the fifth scanning line, and the seventh scanning line sequentially drive the first row of sub-pixels, the third row of sub-pixels, the fifth row of sub-pixels, and the seventh row of sub-pixels, respectively, and the second scanning line GL2, the fourth scanning line GL4, the sixth scanning line, and the eighth scanning line sequentially drive the second row of sub-pixels, the fourth row of sub-pixels, the sixth row of sub-pixels, and the eighth row of sub-pixels, respectively.

It should be noted that, the pixel unit in this embodiment includes eight rows of sub-pixels, and compared with four rows of sub-pixels, more power consumption can be saved, and so on, when the number of rows of sub-pixels included in the pixel unit is larger, more and more power consumption can be correspondingly saved.

It can be understood that, in this embodiment, when the first scanning line GL1, the third scanning line GL3, the fifth scanning line and the seventh scanning line sequentially drive the first row sub-pixel, the third row sub-pixel, the fifth row sub-pixel and the seventh row sub-pixel, respectively, the first DATA signal D1 can continuously charge the four first sub-pixels with the same color in the first column sub-pixel without switching the potentials, so that the power consumption of the DATA signal DATA can be further reduced. Similarly, when the second scanning line GL2, the fourth scanning line GL4, the sixth scanning line and the eighth scanning line sequentially drive the second row sub-pixel, the fourth row sub-pixel, the sixth row sub-pixel and the eighth row sub-pixel, respectively, the first DATA signal D1 can continuously charge the four second sub-pixels with the same color in the first column sub-pixel without switching the potential, so as to further reduce the power consumption of the DATA signal DATA.

In one embodiment, the pixel unit is configured with a first column of sub-pixels, a second column of sub-pixels and a third column of sub-pixels arranged in sequence along the second direction DR 2; the first column of sub-pixels includes first sub-pixels and second sub-pixels alternately distributed in sequence along the first direction DR1, the second column of sub-pixels includes a plurality of third sub-pixels distributed along the first direction DR1, and the third column of sub-pixels includes second sub-pixels and first sub-pixels alternately distributed in sequence along the first direction DR 1.

It should be noted that the second sub-pixels and the first sub-pixels in the third row of sub-pixels are also arranged in a manner that the power consumption of the third data signal D3 can be reduced, and further, the power consumption of the display panel 300 can be further reduced.

In one embodiment, the first sub-pixel is one of a red sub-pixel, a green sub-pixel, or a blue sub-pixel, the second sub-pixel is another one of the red sub-pixel, the green sub-pixel, or the blue sub-pixel, and the third sub-pixel is another one of the red sub-pixel, the green sub-pixel, or the blue sub-pixel.

It should be noted that, in some embodiments, the plurality of sub-pixels may further include a fourth sub-pixel, where if any two of the first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel are sequentially and alternately arranged in the same column, power consumption of the corresponding DATA signal DATA may be reduced.

In one embodiment, in the pixel unit, a data line continuously charges at least two first sub-pixels and/or at least two second sub-pixels.

It should be noted that, when the number of rows including the sub-pixels in the pixel unit is larger, the corresponding data lines may continuously charge more first sub-pixels and/or second sub-pixels without performing potential switching, which may save more power consumption.

In one embodiment, as shown in fig. 7 and 10, each scan line transmits a scan signal; the driving time sequence of the plurality of scanning lines is the sequence of the pulses of the plurality of scanning signals appearing in one frame.

For example, the driving timing of the plurality of scanning lines is to sequentially drive or open the first row of sub-pixels, the third row of sub-pixels, the second row of sub-pixels, and the fourth row of sub-pixels to allow the DATA signals DATA to be written into the corresponding sub-pixels.

In one embodiment, the odd-row sub-pixels and the even-row sub-pixels are alternately distributed along the first direction DR 1.

It should be noted that odd-row sub-pixels may be the first-row sub-pixels, the third-row sub-pixels, and so on, and even-row sub-pixels may be the second-row sub-pixels, the fourth-row sub-pixels, and so on.

In one embodiment, as shown in fig. 7, the present embodiment provides a display device, which includes the display panel 300 and the gate driving circuit 100 in at least one embodiment, wherein the gate driving circuit 100 is connected to a plurality of scan lines respectively, and is configured to control driving timings of the plurality of scan lines.

It can be understood that, in the display device provided in this embodiment, at least one column of sub-pixels includes first sub-pixels and second sub-pixels alternately distributed in sequence along the first direction DR1, and then a plurality of scan lines are used to sequentially drive odd-numbered rows of sub-pixels along the first direction DR1 and then sequentially drive even-numbered rows of sub-pixels along the first direction DR1 in one frame, so that the DATA signals DATA provided by the corresponding DATA lines can continuously provide the same charging voltage for at least two first sub-pixels or at least two second sub-pixels, thereby reducing the potential switching frequency of the DATA signals DATA and further reducing the power consumption of the display panel 300.

It should be noted that the gate driving circuit 100 may include a first gate driving unit GU1, a second gate driving unit GU2, a third gate driving unit GU3, and a fourth gate driving unit GU4, and the odd-even skip scan mode may be implemented by connecting the second gate driving unit GU2 to the third scanning line GL3 and connecting the third gate driving unit GU3 to the second scanning line GL2, or may be implemented by sequentially cascading the first gate driving unit GU1, the third gate driving unit GU, the second gate driving unit GU2, and the fourth gate driving unit GU 4.

In one embodiment, as shown in fig. 7, the display device further includes a data driver 200, the data driver 200 being connected to the plurality of data lines, respectively; each DATA line transmits a DATA signal DATA; the DATA driver 200 includes a DATA mapping module for modulating a voltage output timing of the DATA signal DATA according to the driving timing.

It should be noted that the modification of the scan timing also involves the adjustment of the charging sequence, and therefore, the adjustment of the charging sequence may be implemented by directly changing the format of the video DATA accessed from the outside according to the driving timing, or by adjusting the arrangement sequence of different voltages in the DATA signal DATA through the DATA mapping module configured in the present embodiment without changing the format of the video DATA.

Fig. 8 is a schematic diagram of a driving timing sequence of the display device shown in fig. 7 in the related art, in which a first scanning signal G1, a second scanning signal G2, a third scanning signal G3, and a fourth scanning signal G4 sequentially drive a first row of sub-pixels, a second row of sub-pixels, a third row of sub-pixels, and a fourth row of sub-pixels, respectively, and correspondingly, after a first data signal D1 and a third data signal D3 charge one sub-pixel each time, a potential switching is required, which requires a large power consumption; the second data signal D2 and the fourth data signal D4 can continuously charge one color sub-pixel, so that no potential switching is required, and no more power consumption for potential switching is required.

Where R may be used to represent a red sub-pixel, G may be used to represent a green sub-pixel, and B may be used to represent a blue sub-pixel.

Fig. 9 is a schematic diagram illustrating potential changes of the DATA signals DATA in fig. 8, when a red image is displayed, the first DATA signal D1 and the third DATA signal D3 both provide a low potential for the corresponding red sub-pixel and provide a high potential for the corresponding blue sub-pixel, but each time the charging object is replaced, the corresponding DATA signal DATA needs to be switched to a potential once, i.e., the high potential is switched to the low potential or the low potential is switched to the high potential, so that the first DATA signal D1 and the third DATA signal D3 need to consume large power consumption. The second data signal D2 and the fourth data signal D4 only need to provide constant potentials to the second column of sub-pixels and the fourth column of sub-pixels.

Similarly, when displaying a green image, the first DATA signal D1, the third DATA signal D3, the second DATA signal D2, and the fourth DATA signal D4 may provide a constant potential to the corresponding sub-pixel, so that the power consumption of the potential switching of the DATA signal DATA does not need to be considered, and the power consumption is the lowest.

Similarly, when displaying a blue image, the first DATA signal D1 and the third DATA signal D3 both provide a high potential for the corresponding red sub-pixel and provide a low potential for the blue sub-pixel, but each time the charging object is replaced, the corresponding DATA signal DATA needs to be switched to a potential once, i.e. the high potential is switched to the low potential or the low potential is switched to the high potential, so that the first DATA signal D1 and the third DATA signal D3 need to consume a large amount of power. The second data signal D2 and the fourth data signal D4 only need to provide constant potentials to the second column of sub-pixels and the fourth column of sub-pixels.

In view of this, fig. 10 sequentially and respectively drives the first row of sub-pixels, the third row of sub-pixels, the second row of sub-pixels, and the fourth row of sub-pixels by using the first scan signal G1, the third scan signal G3, the second scan signal G2, and the fourth scan signal G4, and correspondingly, after the first data signal D1 and the third data signal D3 charge two sub-pixels each time, the potential needs to be switched once, which can save 50% of power consumption compared with the driving timing shown in fig. 8; the second data signal D2 and the fourth data signal D4 can continuously charge one color sub-pixel, so that no potential switching is required, and no more power consumption for potential switching is required.

Fig. 11 is a schematic diagram illustrating the potential variation of the DATA signal DATA in fig. 10, when a red image is displayed, the first DATA signal D1 and the third DATA signal D3 both provide a low potential for the corresponding red sub-pixel and provide a high potential for the corresponding blue sub-pixel. After at least two same-color sub-pixels are continuously charged, the voltage level needs to be switched once, i.e., the voltage level is switched from the high voltage level to the low voltage level or from the low voltage level to the high voltage level, so that the switching frequency of the first data signal D1 and the third data signal D3 is reduced by at least half compared with the switching frequency shown in fig. 8, and correspondingly, the power consumption required for voltage level switching is also reduced by half. The second data signal D2 and the fourth data signal D4 only need to provide constant potentials to the second column of sub-pixels and the fourth column of sub-pixels.

Similarly, when displaying a green image, the first DATA signal D1, the third DATA signal D3, the second DATA signal D2, and the fourth DATA signal D4 all provide a constant potential to the corresponding sub-pixel, so that the power consumption of the potential switching of the DATA signal DATA does not need to be considered, and the power consumption is the lowest.

Similarly, when displaying a blue image, the first data signal D1 and the third data signal D3 both provide a high voltage level for the corresponding red sub-pixel and provide a low voltage level for the blue sub-pixel. After at least two same-color sub-pixels are continuously charged, the voltage level needs to be switched once, i.e., the voltage level is switched from the high voltage level to the low voltage level or from the low voltage level to the high voltage level, so that the switching frequency of the first data signal D1 and the third data signal D3 is reduced by at least half compared with the switching frequency shown in fig. 8, and correspondingly, the power consumption required for voltage level switching is also reduced by half. The second data signal D2 and the fourth data signal D4 only need to provide constant potentials to the second column of sub-pixels and the fourth column of sub-pixels.

In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to the related descriptions of other embodiments.

The display panel 300 and the display device provided in the embodiments of the present application are described in detail above, and specific examples are applied herein to explain the principles and embodiments of the present application, and the description of the embodiments is only used to help understand the technical solutions and the core ideas of the present application; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure as defined by the appended claims.

Claims (10)

1. A display panel, comprising:

the pixel comprises a plurality of sub-pixels, wherein the plurality of sub-pixels comprise at least one pixel unit, each pixel unit comprises N x 4 rows of sub-pixels, N is a positive integer, and at least one column of sub-pixels in the pixel unit comprises a first sub-pixel and a second sub-pixel which are sequentially and alternately distributed along a first direction;

the plurality of scanning lines are sequentially arranged along the first direction, each scanning line is connected with a corresponding row of sub-pixels in the pixel unit, and the plurality of scanning lines are used for sequentially driving odd-numbered rows of sub-pixels along the first direction and then sequentially driving even-numbered rows of sub-pixels along the first direction in one frame; and

the data lines are sequentially arranged along a second direction, each data line is connected with a corresponding column of sub-pixels in the pixel unit, and the data lines are used for outputting corresponding data signals according to the driving time sequence of the scanning lines.

2. The display panel according to claim 1, wherein each of the pixel units comprises a first row of sub-pixels, a second row of sub-pixels, a third row of sub-pixels and a fourth row of sub-pixels arranged in sequence along the first direction;

the plurality of scanning lines comprise a first scanning line, a second scanning line, a third scanning line and a fourth scanning line which are sequentially arranged along the first direction, the first scanning line is connected with the first row of sub-pixels, the second scanning line is connected with the second row of sub-pixels, the third scanning line is connected with the third row of sub-pixels, and the fourth scanning line is connected with the fourth row of sub-pixels;

in one frame, the first scanning line and the third scanning line sequentially drive the first row of sub-pixels and the third row of sub-pixels, respectively, and the second scanning line and the fourth scanning line sequentially drive the second row of sub-pixels and the fourth row of sub-pixels, respectively.

3. The display panel according to claim 2, wherein each of the pixel units further comprises a fifth row of sub-pixels, a sixth row of sub-pixels, a seventh row of sub-pixels and an eighth row of sub-pixels arranged in sequence along the first direction;

the plurality of scanning lines further comprise a fifth scanning line, a sixth scanning line, a seventh scanning line and an eighth scanning line which are sequentially arranged along the first direction, the fifth scanning line is connected with the sub-pixels in the fifth row, the sixth scanning line is connected with the sub-pixels in the sixth row, the seventh scanning line is connected with the sub-pixels in the seventh row, and the eighth scanning line is connected with the sub-pixels in the eighth row;

in a frame, the first scanning line, the third scanning line, the fifth scanning line, and the seventh scanning line sequentially drive the first row of sub-pixels, the third row of sub-pixels, the fifth row of sub-pixels, and the seventh row of sub-pixels, respectively, and the second scanning line, the fourth scanning line, the sixth scanning line, and the eighth scanning line sequentially drive the second row of sub-pixels, the fourth row of sub-pixels, the sixth row of sub-pixels, and the eighth row of sub-pixels, respectively.

4. The display panel according to claim 1, wherein the pixel unit is configured with a first column of sub-pixels, a second column of sub-pixels, and a third column of sub-pixels arranged in sequence along the second direction;

the first column of sub-pixels comprises the first sub-pixels and the second sub-pixels which are sequentially and alternately distributed along the first direction, the second column of sub-pixels comprises a plurality of third sub-pixels which are distributed along the first direction, and the third column of sub-pixels comprises the second sub-pixels and the first sub-pixels which are sequentially and alternately distributed along the first direction.

5. The display panel according to claim 4, wherein the first sub-pixel is one of a red sub-pixel, a green sub-pixel, or a blue sub-pixel, the second sub-pixel is another one of the red sub-pixel, the green sub-pixel, or the blue sub-pixel, and the third sub-pixel is still another one of the red sub-pixel, the green sub-pixel, or the blue sub-pixel.

6. The display panel according to claim 1, wherein in the pixel unit, one of the data lines charges at least two of the first sub-pixels and/or at least two of the second sub-pixels continuously.

7. The display panel according to claim 1, wherein each of the scan lines transmits a scan signal; the driving time sequence of the scanning lines is the sequence of the pulses of the scanning signals appearing in one frame.

8. The display panel according to claim 1, wherein the odd row sub-pixels and the even row sub-pixels are alternately distributed along the first direction.

9. A display device, comprising:

the display panel according to any one of claims 1 to 8; and

and the grid driving circuit is respectively connected with the plurality of scanning lines and is used for controlling the driving time sequence of the plurality of scanning lines.

10. The display device according to claim 9, further comprising a data driver connected to the plurality of data lines, respectively;

wherein, each data line transmits a data signal; the data driver includes a data mapping module for modulating a voltage output timing of the data signal according to the driving timing.

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