CN115394235A

CN115394235A - Shift register, display panel and display device

Info

Publication number: CN115394235A
Application number: CN202211255675.1A
Authority: CN
Inventors: 张蒙蒙
Original assignee: Wuhan Tianma Microelectronics Co Ltd
Current assignee: Wuhan Tianma Microelectronics Co Ltd
Priority date: 2022-10-13
Filing date: 2022-10-13
Publication date: 2022-11-25

Abstract

The invention discloses a shift register, a display panel and a display device, comprising a plurality of shift register units which are arranged in a cascade manner; the shift register unit comprises a signal input end, a first clock end, a second clock end and a signal output end; each stage of shift register unit is used for controlling the scanning signal output by the signal output end according to the first clock signal, the second clock signal and the input signal of the signal input end; the effective levels of the scanning signals output by the shift register units at all levels are shifted in sequence, and the shift quantity of the effective levels of the scanning signals output by the shift register units at all levels is smaller than the width of the effective levels; in the same shift register unit, the effective pulse of the first clock signal and the effective pulse of the second clock signal are not overlapped; the time of the effective level of the input signal received by the signal input end is overlapped with the time of at least one effective pulse of the first clock signal and is overlapped with the time of one effective pulse of the second clock signal, so that the display effect can be effectively improved.

Description

Shift register, display panel and display device

Technical Field

The invention relates to the technical field of display, in particular to a shift register, a display panel and a display device.

Background

At present, with the development of display technology, display panels have penetrated various aspects of people's daily life. The display panel can display in different application scenes by adopting different image refresh rates, for example, a driving (also called high-frequency driving) mode with a higher image refresh rate is adopted to drive and display a dynamic picture so as to ensure the fluency of the picture; and a driving method (also referred to as low-frequency driving) with a low image refresh rate is used to drive a still picture to reduce power consumption.

In order to implement the image refresh function, each pixel circuit of the display panel is usually scanned with a scan period matching the image refresh frequency, and at this time, a shift register circuit is usually disposed in the display panel, and the shift register circuit sequentially provides an enable level of a scan signal for each row of pixel circuits, so that the display unit driven by each row of pixel circuits can perform display. However, the conventional shift register circuit structure causes glitches in the output scan signal, for example, a momentary output of an disable level occurs during the period of outputting the enable level of the scan signal, so that display stripes appear on the display screen, thereby affecting the display effect.

Disclosure of Invention

The invention provides a shift register, a display panel and a display device, which are used for improving the stability of scanning signals output by the shift register and improving the display effect.

According to an aspect of the present invention, there is provided a shift register including: a plurality of shift register units arranged in cascade;

the shift register unit comprises a signal input end, a first clock end, a second clock end and a signal output end; the first clock end is used for receiving a first clock signal, and the second clock end is used for receiving a second clock signal;

a signal input end of the shift register unit of the first stage receives a starting signal; in the adjacent two stages of shift register units, the signal input end of the next shift register unit is electrically connected with the signal output end of the previous shift register unit; each shift register unit is used for controlling the scanning signal output by the signal output end according to the first clock signal, the second clock signal and the input signal of the signal input end;

the effective levels of the scanning signals output by the shift register units at each stage are sequentially shifted, and the shift quantity of the effective levels of the scanning signals output by the shift register units at each stage is smaller than the width of the effective levels;

in the same shift register unit, the effective pulse of the first clock signal and the effective pulse of the second clock signal are not overlapped; the time of an active level of an input signal received by the signal input terminal overlaps with the time of at least one active pulse of the first clock signal and with the time of one active pulse of the second clock signal.

According to another aspect of the present invention, there is provided a display panel including: the shift register

According to another aspect of the present invention, there is provided a display device including: the display panel is provided.

According to the shift register provided by the invention, the plurality of cascaded shift register units are arranged, and each shift register unit respectively receives the first clock signal, the second clock signal and the signal input by the signal input end of the shift register unit, so that the effective levels of the scanning signals output by each shift register unit are sequentially shifted, and the shift quantity of the effective levels of the scanning signals output by each shift register unit is smaller than the width of the effective levels, so that the line-by-line scanning of the display panel can be realized when the pixel circuit in the display panel is driven, and the complete display of a frame of picture can be realized; in addition, the time of the effective level of the input signal received by the signal input end in the shift register unit is overlapped with the time of at least one effective pulse of the first clock signal, and is overlapped with the time of one effective pulse of the second clock signal, so that the situation that the effective pulse of the scanning signal cannot be continuously kept at the effective level and a transient ineffective level, namely, the effective pulse of the scanning signal generates burrs, is avoided when the second clock signal jumps during the period that the scanning signal output by the shift register unit is the effective pulse, and the shift register unit can stably output the effective pulse of the scanning signal on the premise that the shift register unit can accurately output the scanning signal by controlling the second clock signal to only comprise one effective pulse during the period that the input signal received by the signal input end is the effective level.

It should be understood that the statements in this section are not intended to identify key or critical features of the embodiments of the present invention, nor are they intended to limit the scope of the invention. Other features of the present invention will become apparent from the following description.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a timing diagram of driving a shift register in the prior art;

fig. 2 is a schematic structural diagram of a shift register according to an embodiment of the present invention;

FIG. 3 is a timing diagram of a shift register according to an embodiment of the present invention;

FIG. 4 is a diagram illustrating a shift register unit according to an embodiment of the present invention;

FIG. 5 is a diagram illustrating another shift register unit according to an embodiment of the present invention;

FIG. 6 is a diagram illustrating a structure of another shift register unit according to an embodiment of the present invention;

FIG. 7 is a diagram illustrating a shift register unit according to another embodiment of the present invention;

FIG. 8 is a timing diagram illustrating driving operations of another shift register according to an embodiment of the present invention;

FIG. 9 is a diagram illustrating an alternative shift register according to an embodiment of the present invention;

FIG. 10 is a diagram illustrating a structure of another shift register according to an embodiment of the present invention;

FIG. 11 is a diagram illustrating a structure of another shift register according to an embodiment of the present invention;

fig. 12 is a schematic structural diagram of a display device according to an embodiment of the present invention.

Detailed Description

In order to make those skilled in the art better understand the technical solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

Fig. 1 is a timing diagram of driving a shift register according to the prior art, as shown in fig. 1, a first clock signal ck ' and a second clock signal xck ', which are pulse signals having enable levels that do not overlap with each other, at time t1', an input signal stv ' transitions to an active level (e.g., a high level), the first clock signal ck ' transitions to an active level (e.g., a low level), the second clock signal xck ' transitions to an inactive level (e.g., a high level), and a scan signal sn ' output by the shift register remains unchanged and remains as a first level signal (a low level signal); at time t2', the first clock signal ck' is at an invalid level, the second clock signal xck 'jumps to an active level, and the scanning signal sn' output by the shift register jumps to a second level signal (high level signal); at the time t3', when the second clock signal xck ' jumps to an invalid level, the scanning signal sn ' output by the shift register still maintains the second level signal; at time t4', the second clock signal xck ' transitions to the active level again, that is, while the scan signal sn ' is at the active level, the second clock signal xck ' transitions to the active level for the second time at time t4', at which time the scan signal sn ' output by the shift register changes to the first level signal and rapidly returns to the second level signal after the instantaneous change, so that the scan signal sn ' has an instantaneous inactive level, that is, the active pulse of the scan signal sn ' has glitch, as shown by the dashed box a '. Therefore, when the scanning signal sn' is adopted to drive the pixel circuit of the display area in the display panel, the light emission of the pixel circuit is unstable, and the display horizontal stripes can be seriously generated to influence the display effect.

Based on the above technical problem, an embodiment of the present invention provides a shift register, including: a plurality of shift register units which are arranged in a cascade manner; the shift register unit comprises a signal input end, a first clock end, a second clock end and a signal output end; the first clock end is used for receiving a first clock signal, and the second clock end is used for receiving a second clock signal; the signal input end of the first-stage shift register unit receives a starting signal; in the adjacent two stages of shift registering units, the signal input end of the next stage of shift registering unit is electrically connected with the signal output end of the previous stage of shift registering unit; each stage of shift register unit is used for controlling the scanning signal output by the signal output end according to the first clock signal, the second clock signal and the input signal of the signal input end; the effective levels of the scanning signals output by the shift register units at all levels are shifted in sequence, and the shift quantity of the effective levels of the scanning signals output by the shift register units at all levels is smaller than the width of the effective levels; in the same shift register unit, the effective pulse of the first clock signal and the effective pulse of the second clock signal are not overlapped; the signal input receives an input signal having an active level whose time overlaps with the time of at least one active pulse of the first clock signal and with the time of one active pulse of the second clock signal.

By adopting the technical scheme, the cascade-connected shift register units are arranged, and each shift register unit respectively receives the first clock signal, the second clock signal and the signal input by the signal input end of the shift register unit, so that the effective level of the scanning signal output by each shift register unit can be sequentially shifted, and the shift quantity of the effective level of the scanning signal output by each shift register unit is smaller than the width of the effective level, so that when a pixel circuit in a display panel is driven, the line-by-line scanning of the display panel can be realized, and the complete display of a frame of picture can be realized; in addition, the time of the effective level of the input signal received by the signal input end in the shift register unit is overlapped with the time of at least one effective pulse of the first clock signal, and is overlapped with the time of one effective pulse of the second clock signal, so that the situation that the effective pulse of the scanning signal cannot be continuously kept at the effective level and a transient ineffective level, namely, the effective pulse of the scanning signal generates burrs, is avoided when the second clock signal jumps during the period that the scanning signal output by the shift register unit is the effective pulse, and the shift register unit can stably output the effective pulse of the scanning signal on the premise that the shift register unit can accurately output the scanning signal by controlling the second clock signal to only comprise one effective pulse during the period that the input signal received by the signal input end is the effective level.

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, which are the core ideas of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art based on the embodiments of the present invention without any creative work, belong to the protection scope of the present invention.

Fig. 2 is a schematic structural diagram of a shift register according to an embodiment of the present invention, and fig. 3 is a timing diagram of driving the shift register according to the embodiment of the present invention, with reference to fig. 2 and fig. 3, the shift register includes a plurality of shift register units 10 arranged in cascade; the shift register unit 10 includes a signal input terminal IN, a first clock terminal CK, a second clock terminal XCK, and a signal output terminal OUT; the first clock terminal CK is used for receiving a first clock signal CK, and the second clock terminal XCK is used for receiving a second clock signal XCK; a signal input end IN of the first stage shift register unit 10 receives a start signal stv; IN the adjacent two stages of shift register units 10, the signal input end IN of the next shift register unit 10 is electrically connected with the signal output end OUT of the previous shift register unit 10; each shift register unit 10 is configured to control a scan signal output by a signal output end OUT according to a first clock signal ck, a second clock signal xck, and an input signal of a signal input end IN; the effective levels of the scanning signals output by the shift register units 10 at all levels are sequentially shifted, and the shift quantity of the effective levels of the scanning signals output by the shift register units 10 at all levels is smaller than the width of the effective levels; in the same shift register unit 10, the effective pulse of the first clock signal ck and the effective pulse of the second clock signal xck are not overlapped with each other; the time of the active level of the input signal received by the signal input IN overlaps with the time of at least one active pulse of the first clock signal ck and with the time of one active pulse of the second clock signal xck.

Illustratively, as shown in fig. 2, four shift register units are cascaded in sequence in a shift register, that is, the shift register includes a first-stage shift register unit 11, a second-stage shift register unit 12, a third-stage shift register unit 13, and a fourth-stage shift register unit 14, which are cascaded in sequence. A first clock end CK of the first stage shift register unit 11 is electrically connected to a first clock signal line CK1, and is configured to receive a first clock signal CK1 transmitted by the first clock signal line CK1, and a second clock end XCK of the first stage shift register unit 11 is electrically connected to a second clock signal line XCK1, and is configured to receive a second clock signal XCK1 transmitted by the second clock signal line XCK1; a first clock terminal CK of the second stage shift register unit 12 is electrically connected to the first clock signal line CK2, and is configured to receive the first clock signal CK2 transmitted by the first clock signal line CK2, and a second clock terminal XCK of the second stage shift register unit 12 is electrically connected to the second clock signal line XCK2, and is configured to receive the second clock signal XCK2 transmitted by the second clock signal line XCK2; a first clock terminal CK of the third stage shift register unit 13 is electrically connected to the first clock signal line CK3, and is configured to receive the first clock signal CK3 transmitted by the first clock signal line CK3, and a second clock terminal XCK of the third stage shift register unit 13 is electrically connected to the second clock signal line XCK3, and is configured to receive the second clock signal XCK3 transmitted by the second clock signal line XCK3; a first clock terminal CK of the fourth stage shift register unit 14 is electrically connected to the first clock signal line CK4 for receiving the first clock signal CK4 transmitted by the first clock signal line CK4, and a second clock terminal XCK of the fourth stage shift register unit 14 is electrically connected to the second clock signal line XCK4 for receiving the second clock signal XCK4 transmitted by the second clock signal line XCK4. A signal input end IN of the first stage shift register unit 11 receives a start signal stv; a signal input end IN of the second-stage shift register unit 12 is electrically connected with a signal output end OUT of the first-stage shift register unit 11, and receives a scanning signal sn1 output by the first-stage shift register unit 11; the signal input terminal IN of the third shift register unit 13 is electrically connected to the signal output terminal OUT of the second shift register unit 12 for receiving the scan signal sn2 output by the second shift register unit 12, and the signal input terminal IN of the fourth shift register unit 14 is electrically connected to the signal output terminal OUT of the third shift register unit 13 for receiving the scan signal sn3 output by the third shift register unit 13.

The first clock signal ck may be a pulse signal in which a high-level signal (e.g., vgh) and a low-level signal (e.g., vgl) are alternately performed, and similarly, the second clock signal xck may also be a pulse signal in which a high-level signal vgh and a low-level signal vgl are alternately performed, where generally one high-level signal vgh and one low-level signal vgl continuous to the high-level signal vgh form one pulse period, and a pulse period of the first clock signal may be the same as or different from a pulse period of the second clock signal, which is not particularly limited in the embodiment of the present invention. Illustratively, the low-level signal vgl may be an active level of the first clock signal ck and the second clock signal xck, and the high-level signal vgh is an inactive level of the first clock signal ck and the second clock signal xck; alternatively, the high level signal vgh may be an active level of the first clock signal ck and the second clock signal xck, and the low level signal vgl may be an inactive level of the first clock signal ck and the second clock signal xck. It is to be understood that the active levels and the inactive levels of the first clock signal ck and the second clock signal xck may be set according to needs, which is not specifically limited in the embodiments of the present invention, and in the following embodiments, without specific description, the low level signal vgl is the active level of the first clock signal ck and the second clock signal xck, and the high level signal vgh is the inactive level of the first clock signal ck and the second clock signal xck.

The operation of each shift register unit 10 is similar, and shifts sequentially only in time sequence, so for convenience of description, only the operation of one shift register unit 10 is exemplarily described herein.

Taking the working process of the first stage shift register unit 11 as an example, at time t1, the start signal stv jumps from a first level signal (preferably, a low level signal, and also preferably, an invalid level signal of the scan signal sn) to a second level signal (preferably, a high level signal, and also preferably, an valid level signal of the scan signal sn), and at this time, the scan signal sn1 output by the first stage shift register unit 11 is kept as the first level signal; at the time t3, the second electrical clock signal xck1 jumps from high level to low level, the first clock signal ck1 is high level, and at the moment, the scanning signal sn1 jumps from the first level signal to the second level signal; when the first clock signal ck1 jumps from high level to low level at the time t5 and the time t8, the scanning signal sn1 is kept as the second level signal and is not changed; the second clock signal xck1 remains at a high level at a stage t4 to t10 without generating a transition, and changes from the high level to a low level at a time t10, at which time the start signal stv is a first level signal, and at this time the scan signal sn1 output by the first stage shift register unit 11 transitions to the first level signal. That is, at the stage t3 to t10 when the scan signal sn1 is kept at the second level signal, the second clock signal xck1 does not make a transition, so that the period in which the scan signal sn1 is a pulse overlaps with only one active pulse (low level at the stage t3 to t 4) of the second clock signal xck1, and the period in which the scan signal output by the shift register unit 11 is an active pulse does not have an instantaneous inactive level due to the transition of the second clock signal, that is, the active pulse of the scan signal cannot be kept at the active level continuously, and thus a glitch occurs.

It should be understood that the statements in this section do not necessarily identify key or critical features of the embodiments of the present invention, nor do they necessarily limit the scope of the invention. Other features of the present invention will become apparent from the following description.

It should be noted that the structure of each shift register unit in the shift register provided in the embodiment of the present invention may be set according to actual needs, which is not specifically limited in the embodiment of the present invention, and a typical structure of the shift register unit is exemplarily described below.

Optionally, fig. 4 is a schematic structural diagram of a shift register unit according to an embodiment of the present invention, and as shown in fig. 4, the shift register unit further includes a first control module 10a, a charge pump module 10b, a second control module 10c, and an output module 10d; in the same shift register unit 10: the first control module 10a is electrically connected to the signal input terminal IN, the first clock terminal CK and the output module 10d, respectively, and the first control module 10a and the output module 10d are electrically connected to the first node N1; the first control module 10a is configured to control a transmission path through which an input signal at the signal input terminal IN is transmitted to the first node N1 according to the first clock signal ck; the charge pump module 10b is electrically connected to the second clock terminal XCK and the first node N1, respectively; the charge pump module 10b is configured to control a coupling amount of the second clock signal xck to the first node N1 when the second clock signal xck jumps; the second control module 10c is electrically connected to the first clock terminal CK, the second clock terminal XCK, the first node N1, the first level terminal VGL, and the output module 14, respectively, and the second control module 10c and the output module 10d are electrically connected to the second node N2; the second control module 10c is configured to control the potential of the second node N2 according to the potential of the first node N1, the first clock signal ck, the second clock signal xck, and the first level signal VGL of the first level end VGL; the output module 10d is further electrically connected to the first level terminal VGL, the second level terminal VGH, and the signal output terminal OUT, respectively; the output module 10d is configured to control a transmission path of the first level signal Vgl to the signal output end OUT according to the potential of the first node N1, and control a transmission path of the second level signal VGH of the second level end VGH to the second node N2 according to the potential of the second node N2.

The first level signal VGL of the first level end VGL and the second level signal VGH of the second level end VGH may be two fixed signals with opposite polarities, for example, when the first level signal VGL of the first level end VGL is a low level signal (e.g., VGL), the second level signal VGH of the second level end VGH may be a high level signal (e.g., VGH); on the contrary, when the first level signal VGL of the first level terminal VGL is the high level signal VGH, the second level signal VGH of the second level terminal VGH may be the low level signal VGL. It can be understood that the first level signal VGL of the first level terminal VGL and the second level signal VGH of the second level terminal VGH may be set according to needs, and this is not particularly limited in the embodiment of the present invention. Without specific description, the following embodiments exemplarily describe that the first level signal Vgl is a low level signal Vgl, and the second level signal Vgh can be a high level signal Vgh. The first level signal vgl is preferably an inactive level of the scan signal sn, and the second level signal vgh is preferably an active level of the scan signal sn.

Specifically, taking the working process of the first stage shift register unit 11 as an example, referring to fig. 2 and fig. 3, at a stage t1 to t2, the start signal stv received by the signal input terminal IN of the first stage shift register unit 11 is a second level signal, the second clock signal XCK1 received by the second clock terminal XCK is an invalid level, the first clock signal CK1 received by the first clock terminal CK is an valid level, so that the first control module 10a is turned on under the control of the first clock signal CK1, the invalid level of the start signal stv is transmitted to the first node N1, and the potential of the first node N1 is an invalid level. Since the second clock signal xck is kept at the inactive level of the previous stage during the period from t1 to t2, the charge amount of the charge pump module 10b coupled to the first node N1 is kept unchanged. The second control module 10c enables the first level signal VGL at the first level end VGL not to be transmitted to the second node N2 under the control of the first clock signal ck1, the second clock signal xck1 and the inactive level signal of the first node N1, so that the potential of the second node N2 is maintained at the inactive level of the previous stage. Since the potentials of the first node N1 and the second node N2 are both at an invalid level, the scan signal sn1 output by the output module 10d of the first stage shift register unit 11 is consistent with the previous stage and is the first level signal Vgl.

At the stage t3 to t4, the first clock signal CK1 received by the first clock terminal CK of the first stage shift register unit 11 is at an invalid level, the second clock signal XCK1 received by the second clock terminal XCK jumps to an valid level, the first control module 10a is turned off under the control of the first clock signal CK1, and the first node N1 is kept at the invalid level of the previous stage. The second control module 10c transmits the first level signal VGL of the first level end VGL to the second node N2 under the control of the first clock signal ck1, the second clock signal xck1 and the inactive level signal of the first node N1, and the potential of the second node N2 changes from the high level to the active level, so that the output module 10d transmits the second level signal VGH of the second level end VGH to the signal output end OUT according to the active level signal of the second node N2, that is, the first-stage scan signal sn1 output by the first-stage shift register unit 11 is at the active level at this time.

At the stage t11 to t12, the first clock signal CK1 received by the first clock terminal CK of the first stage shift register unit 11 is at an inactive level, the start signal st received by the signal input terminal IN is at a low level, and the second clock signal XCK1 received by the second clock terminal XCK jumps to an active level, so that the charge pump module 10b couples the potential of the first node N1 to a low level, and the output module 10d transmits the first level signal VGL at the first level terminal VGL to the signal output terminal OUT according to the active level signal at the first node N1, that is, the first stage shift register unit 10 outputs the scan signal sn1 at an inactive level. That is, the first stage scan signal sn1 output by the first stage shift register unit 11 is at the active level in the stage from t3 to t 11.

As shown in fig. 1, in the period t1' to t5' when the scan signal output by the shift register unit 10 is at the high level, when the second clock signal xck ' jumps to the low level for the second time at t3' to t4', the potential of the first node N1 is pulled low, so that the output module 10d transmits the first level signal VGL of the first level terminal VGL to the signal output terminal OUT under the control of the first node N1, and since the output module 10d continues to transmit the second level signal VGH of the second level terminal VGH to the signal output terminal OUT under the control of the second node N2 at this time, the first level signal VGL is embodied as a glitch signal with short time and small amplitude. When the scanning signal is used to drive the pixel circuit in the display panel, the picture displayed by the display panel is unstable, and the display effect is affected.

With continuing reference to fig. 2, fig. 3 and fig. 4, by overlapping the time of the active level of the input signal received at the signal input terminal IN of each shift register unit 10 with the time of only one active pulse of the second clock signal xck, for example, during the period t1 to t9 when the start signal stv received by the first-stage shift register unit 11 is active (high), the second clock signal xck1 received by the first-stage shift register unit 11 is inactive during the period t3 to t4, and during the period t3 to t11 when the first-stage scan signal sn1 received by the second-stage shift register unit 12 is active, the second clock signal xck2 received by the second-stage shift register unit 12 is inactive during the period t5 to t 6. Alternatively, the time of the active level of the scan signal sn output from the signal output terminal OUT of each shift register cell 10 may overlap only with the time of one active pulse of the second clock signal xck, and in the t3 to t11 stages where the first-stage scan signal sn1 is active, only the second clock signal xck1 in the t3 to t4 stages is inactive, and in the t5 to t13 stages where the second-stage scan signal sn2 is active, only the second clock signal xck2 in the t5 to t6 stages is inactive. Therefore, compared with the situation that the time of the effective level of the input signal and the time of the two effective pulses of the second clock signal xck are overlapped in the prior art, or the situation that the time of the effective level of the output scanning signal sn and the time of the two effective pulses of the second clock signal xck are overlapped, the situation that the electric potential of the first node N1 changes to the effective level transiently when the second clock signal xck jumps to the effective level can be effectively avoided, so that burrs are generated during the effective pulse period of the scanning signal output by the shift register unit can be avoided, the effective pulse of the scanning signal is stable, and thus, when the scanning signal is adopted to drive a pixel circuit in a display panel, the picture displayed by the display panel can be stable, and the display effect can be effectively improved.

IN an alternative embodiment, fig. 5 is a schematic structural diagram of another shift register unit according to an embodiment of the present invention, as shown IN fig. 5, IN the same shift register unit 10, the first control module 10a may include a first transistor T1, wherein a gate of the first transistor T1 is electrically connected to the first clock terminal CK, a first pole of the first transistor T1 is electrically connected to the signal input terminal IN, and a second pole of the first transistor T1 is electrically connected to the first node N1. When the first clock signal CK of the first clock terminal CK is at an active level capable of controlling the first transistor T1 to be turned on, the signal received by the signal input terminal IN can be transmitted to the first node N1 through the first transistor T1, and when the first clock signal CK of the first clock terminal CK is at an inactive level capable of controlling the first transistor T1 to be turned off, the signal received by the signal input terminal IN can not be transmitted to the first node N1 through the first transistor T1.

Optionally, with reference to fig. 5, the charge pump module 10b includes a first capacitor C1, the first capacitor C1 is electrically connected between the second clock signal terminal XCK and the first node N1, and when the second clock signal XCK of the second clock signal terminal XCK transitions to an inactive level (for example, a high level vgh), the potential of the first node N1 is made to be the same as the inactive level of the second clock signal XCK through the coupling effect of the first capacitor C1. Similarly, when the second clock signal XCK of the second clock signal terminal XCK transitions to an active level (e.g., a low level vgl), the potential of the first node N1 is made to be the same as the active level of the second clock signal XCK by the coupling effect of the first capacitor C1. Since the second clock signal xck makes one transition from the inactive level to the active level only when the scan signal sn output from the shift register unit 10 changes from the inactive level to the active level, and makes one transition from the active level to the inactive level only when the scan signal sn is kept at the active level, the first capacitor C1 does not couple the active level of the second clock signal xck to the first node N1 during the period when the scan signal sn is kept at the active level, and thus it is possible to ensure that the potential of the first node N1 can be kept at the inactive level during the period when the scan signal sn is kept at the active level, so that the scan signal sn output from the register unit 10 is kept stable.

Optionally, with continued reference to fig. 5, the second control module 10C includes a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a second capacitor C2. Wherein. A gate of the second transistor T2 is electrically connected to the first node N1, a first electrode of the second transistor T2 is electrically connected to the first clock terminal CK, a second electrode of the second transistor T2 is electrically connected to a second electrode of the third transistor T3, a gate of the fourth transistor T4, and a first end of the second capacitor C2 is electrically connected to the third node N3, a gate of the third transistor T3 is electrically connected to the first clock terminal CK, a first electrode of the third transistor T3 is electrically connected to the first level terminal VGL, a second end of the second capacitor C2 is electrically connected to a second electrode of the fourth transistor and a first electrode of the fifth transistor T5 is electrically connected to the fourth node N4, a first electrode of the fourth transistor T4 and a gate of the fifth transistor T5 are electrically connected to the second clock terminal XCK, and a second electrode of the fifth transistor T5 is electrically connected to the second node. Thus, the second transistor T2 may be turned on or off under the control of the potential of the first node N1, and transmit the first clock signal CK of the first clock terminal CK to the third node N3 when turned on; the third transistor T3 may be turned on or off under the control of the first clock signal ck, and transmit the first level signal VGL of the first level terminal VGL to the third node N3 when turned on; the fourth transistor T4 may be turned on or off under the control of the potential of the third node N3, and transmit the second clock signal XCK of the second clock terminal XCK to the fourth node N4 when turned on; the fifth transistor T5 may be turned on or off under the control of the second clock signal xck, and transmit the potential of the fourth node N4 to the second node N2 when turned on, so that the potential of the second node N2 is at an enable level; due to the second capacitor C2, the potential of the second node N2 can be more stably maintained at the active level.

Optionally, with continued reference to fig. 5, the output module includes a sixth transistor T6, a seventh transistor T7, and a third capacitor C3. A gate of the sixth transistor T6 and a first end of the third capacitor C3 are electrically connected to the second node N2. The second terminal of the third capacitor C3 and the first pole of the sixth transistor T6 are electrically connected to the second level terminal VGH, the second pole of the sixth transistor T6 and the second pole of the seventh transistor T7 are electrically connected to the signal output terminal OUT, the first pole of the seventh transistor T7 is electrically connected to the first level terminal VGL, and the gate of the first transistor T1 is electrically connected to the first node N1. When the potential of the first node N1 is at an effective level capable of controlling the seventh transistor T7 to be turned on, the first level signal VGL of the first level terminal VGL is transmitted to the signal output terminal OUT through the seventh transistor T7; when the potential of the first node N1 is at an inactive level for controlling the seventh transistor T7 to be turned off, the first level signal VGL of the first level terminal VGL cannot be transmitted to the signal output terminal OUT through the seventh transistor T7. When the potential of the second node N2 is at an effective level capable of controlling the sixth transistor T6 to be turned on, the second level signal VGH of the second level terminal VGH is transmitted to the signal output terminal OUT through the sixth transistor T6; when the potential of the second node N2 is at an inactive level for controlling the sixth transistor T6 to be turned off, the second level signal VGH of the second level terminal VGH cannot be transmitted to the signal output terminal OUT through the sixth transistor T6.

Optionally, fig. 6 is a schematic structural diagram of another shift register unit according to an embodiment of the present invention, and as shown in fig. 6, the shift register unit 10 further includes an interlock module 10e; in the same shift register unit 10, the interlock module 10e is electrically connected to the second level terminal VGH, the first node N1, and the second node N2, respectively; the interlock module 10e is configured to control a transmission path through which the second level signal Vgh is transmitted to the second node N2 according to the potential of the first node N1, and control a transmission path through which the second level signal Vgh is transmitted to the first node N1 according to the potential of the second node N2.

Specifically, when the signal output end OUT needs to output the first level signal Vgl, the potential of the first node N1 should be an enable level capable of controlling the output module 10d to transmit the first level signal Vgl to the signal output end OUT, and at this time, in order to ensure the accuracy of the first level signal Vgl output by the signal output end OUT, the potential of the second node N2 should be a non-enable level incapable of controlling the output module 10d to transmit the second level signal Vgh to the signal output end OUT; when the signal output terminal OUT needs to output the second level signal Vgh, the potential of the second node N2 should be an enable level capable of controlling the output module 10d to transmit the second level signal Vgh to the signal output terminal OUT, and at this time, in order to ensure the accuracy of the second level signal Vgh output by the signal output terminal OUT, the potential of the first node N1 should be a non-enable level incapable of controlling the output module 10d to transmit the first level signal Vgl to the signal output terminal OUT.

Thus, when the signal output end OUT needs to output the first level signal Vgl, the interlock module 10e transmits the second level signal Vgh to the second node N2 under the control of the potential of the first node N1, so that the potential of the second node N2 is kept at the disable level; and when the signal output end OUT needs to output the second level signal Vgh, the interlock module 10e transmits the second level signal Vgh to the first node N1 under the potential control of the second node N2, so that the potential of the first node N1 is kept at the non-enable level, and thus the potential of the first node N1 and the potential of the second node N2 are clamped with each other, the shift register circuit is ensured to work orderly, and the accuracy and stability of the output signal of the shift register circuit are improved.

Optionally, with continued reference to fig. 6, the interlock module 10e may include an eighth transistor T8 and a ninth transistor T9, a gate of the eighth transistor T8 is electrically connected to the first node N1, a first pole of the eighth transistor T8 is electrically connected to the second level terminal VGH, and a second pole of the eighth transistor T8 is electrically connected to the second node N2; a gate of the ninth transistor T9 is electrically connected to the second node N2, a first pole of the ninth transistor T9 is electrically connected to the second level terminal VGH, and a second pole of the ninth transistor T9 is electrically connected to the first node N1 through the charge pump module 10 b. The eighth transistor T8 may be turned on or off under the control of the potential of the first node N1, and transmit the second level signal Vgh to the second node N2 when it is turned on; the ninth transistor T9 can be turned on or off under the control of the potential of the second node N2, and transmits the second level signal Vgh to the first node N1 through the charge pump module 10b when it is turned on, so as to clamp the second node N2 and the first node N1 to each other.

Optionally, fig. 7 is a schematic structural diagram of another shift register unit according to an embodiment of the present invention, and as shown in fig. 7, the shift register unit 10 further includes an interlock module 10e; in the same shift register unit 10, the interlock module 10e is electrically connected to the second clock terminal XCK, the second level terminal VGH, the second control module 10c, the first node N1, and the second node N2, respectively; the interlock module 10e is configured to control a transmission path through which the second level signal Vgh is transmitted to the second node N2 according to the potential of the first node N1, and to control a transmission path through which the second level signal Vgh is transmitted to the first node N1 under the control of the second clock signal Vgh and the second control module 10 c.

Specifically, when the signal output end OUT needs to output the first level signal Vgl, the interlock module 500 transmits the second level signal Vgh to the second node N2 under the control of the potential of the first node N1, so that the potential of the second node N2 is kept at an invalid level; and when the signal output end OUT needs to output the second level signal Vgh, the interlock module 500 transmits the second level signal Vgh to the first node N1 under the control of the second clock signal xck and the second control module 10c, so that the potential of the first node N1 is kept at the non-enabled level, and thus the potential of the first node N1 and the potential of the second node N2 are clamped with each other, the shift register circuit is guaranteed to work orderly, and the accuracy and the stability of the output signal of the shift register circuit are improved.

Optionally, with continued reference to fig. 7, the interlock module 10e may include an eighth transistor T8, a ninth transistor T9, and a tenth transistor T10; a gate of the eighth transistor T8 is electrically connected to the first node N1, a first pole of the eighth transistor T8 is electrically connected to the second level terminal VGH, and a second pole of the eighth transistor T8 is electrically connected to the second node N2; a gate of the ninth transistor T9 is electrically connected to the third node N3, a first pole of the ninth transistor T9 is electrically connected to the second level terminal VGH, and a second pole of the ninth transistor T9 is electrically connected to the first pole of the tenth transistor T10; a gate of the tenth transistor T10 is electrically connected to the second clock terminal XCK, and a second pole of the tenth transistor T10 is electrically connected to the first node N1.

Specifically, the eighth transistor T8 may be turned on or off under the control of the potential of the first node N1, and transmit the second level signal Vgh to the second node N2 when it is turned on; the ninth transistor T9 may be turned on or off under the control of the potential of the third node N3, the tenth transistor T10 may be turned on or off under the control of the second clock signal xck, and when both the ninth transistor T9 and the tenth transistor T10 are turned on, the second level signal Vgh may be transmitted to the first node N1, so as to implement mutual clamping of the second node N2 and the first node N1, so that when the output module 10d includes the sixth transistor T6 and the seventh transistor T7, the seventh transistor T7 controlled by the potential of the first node N1 and the sixth transistor T6 controlled by the second node N2 may not be turned on at the same time, so that a path may not be formed between the second level terminal Vgh and the first level terminal VGL, and the second level terminal Vgh and the first level terminal VGL may be prevented from being short-circuited, thereby being capable of preventing flicker of the display panel when displaying light. The eighth transistor T8, the ninth transistor T9, and the tenth transistor T10 may be N-channel transistors or P-channel transistors, and may be designed as needed, which is not specifically limited in the embodiment of the present invention.

Optionally, the shift register unit 10 may further include a voltage stabilizing module 10f, the voltage stabilizing module 10f is electrically connected to the first level terminal VGL, the first node N1, the first control module 10a, and the interlock module 10e, and the voltage stabilizing module 10f is configured to stabilize the potential of the first node N1.

Specifically, the voltage stabilizing module 10f may include an eleventh transistor T11, a gate of the eleventh transistor T11 is electrically connected to the first level terminal VGL, a first pole of the eleventh transistor T11 is electrically connected to the first node N1, a second pole of the eleventh transistor T11 is electrically connected to the second pole of the first transistor T1 and the second pole of the tenth transistor T10, and the eleventh transistor T11 is preferably a P-type transistor, where the first level signal VGL controls the eleventh transistor T11 to be in a conducting state, and a voltage drop of the eleventh transistor T11 may cause that the potential of the first node N1 is not too low, so as to affect the operation of the shift register circuit. In addition, due to the existence of the threshold voltage of the eleventh transistor T11, when the difference between the first level signal Vgl and the potential of the first pole of the eleventh transistor T11 or the difference between the first level signal Vgl and the potential of the second pole of the eleventh transistor T11 is smaller than the threshold voltage of the eleventh transistor T11, the eleventh transistor T11 is in the on state, and when this condition is not satisfied, the eleventh transistor T11 is in the off state, and at this time, the eleventh transistor T11 can protect the device electrically connected to the other node when the potential of the node connected to one of the first pole and the second pole is abnormal.

It is understood that each transistor in the shift register unit 10 may be an N-type transistor or a P-type transistor, when each transistor is an N-type transistor, the active level for controlling the transistor to be turned on is a high level, and when each transistor is a P-type transistor, the active level for controlling the transistor to be turned on is a low level, and the type of the transistor may be set according to the requirement, which is not specifically limited in the embodiment of the present invention.

Optionally, referring to fig. 2 and fig. 3 in combination, in a clock cycle, in two adjacent shift register units 10, a first clock signal CK at the first clock terminal CK of each shift register unit 10 is sequentially shifted, and a second clock signal XCK at the second clock terminal XCK of each shift register unit 10 is sequentially shifted. That is, the first clock signal ck1 received by the first stage shift register unit 11 and the first clock signal ck2 received by the second stage shift register unit 12 can be shifted in sequence, the first clock signal ck2 received by the second stage shift register unit 12 and the first clock signal ck3 received by the third stage shift register unit and 13 can be shifted in sequence, and the first clock signal ck3 received by the third stage shift register unit and 13 and the first clock signal ck4 received by the fourth stage shift register unit and 14 can be shifted in sequence. Similarly, the second clock signal xck1 received by the first stage shift register unit 11 and the second clock signal xck2 received by the second stage shift register unit 12 shift sequentially, the second clock signal xck2 received by the second stage shift register unit 12 and the second clock signal xck3 received by the third stage shift register unit 13 shift sequentially, and the second clock signal xck3 received by the third stage shift register unit 13 and the second clock signal xck4 received by the fourth stage shift register unit 14 shift sequentially. In this way, the shift register units 10 of two adjacent stages are electrically connected to different clock signal lines, so that each clock signal line can electrically connect fewer shift register units, the load on each clock signal line is reduced, and the accuracy of the scanning signal output by each shift register unit can be ensured.

In another alternative embodiment, referring to fig. 2 and fig. 3 in combination, before the scan signal sn1 output by the first stage shift register unit 11 jumps to the active level at time t3, the first clock signal ck1 is at the active level at the t 1-t 2 stages, and at the t 3-t 11 stages where the scan signal sn1 remains at the active level, the first clock signal ck1 is at the active level at the t 5-t 6 stages and at t 9-t 10 stages, and after the scan signal sn1 jumps from the active level to the inactive level at time t11, the first clock signal ck1 is at the active level at the t 13-t 14 stages, so that the first clock signal ck1 jumps twice within the time of the active level of the scan signal sn1. Accordingly, the shift amount of the effective level of the scan signal sn3 output by the third stage shift register unit 13 compared with the effective level of the scan signal sn1 output by the first stage shift register unit 11 is one clock cycle of the first clock signal ck, so that the first clock signal ck1 and the first clock signal ck3 have the same transition condition before the scan signal sn3 output by the third stage shift register unit 13 transitions to the effective level at time t7, and therefore, the shift register units 10 of adjacent odd stages can share the same clock signal line. Based on the same principle, the transition timings of the first clock signal ck2 of the scan signal sn2 outputting the effective pulses in the second stage shift register units 12 and the first clock signal ck4 of the fourth stage shift register units 14 are the same, and the effective pulses overlap, that is, the shift register units 10 of adjacent even-numbered stages may share the same clock signal line. Therefore, the arrangement of clock signal lines can be reduced and the circuit structure can be simplified on the basis of ensuring that each shift register unit 10 outputs scanning signals normally.

For example, the above embodiments have been described by taking the example that the periods of the first clock signal ck and the second clock signal xck are different, and in other embodiments of the present invention, the periods of the first clock signal ck and the second clock signal xck may also be the same.

Optionally, fig. 8 is a driving timing diagram of another shift register according to an embodiment of the invention, as shown in fig. 8, in one clock cycle, in the same shift register unit 10, an effective pulse of the first clock signal CK at the first clock terminal CK and an effective pulse of the second clock signal XCK at the second clock terminal XCK are sequentially shifted. Namely, the first clock signal ck1 and the second clock signal xck1 received by the first-stage shift register unit 11 shift in sequence, the first clock signal ck2 and the second clock signal xck2 received by the second-stage shift register unit 12 shift in sequence, the first clock signal ck3 and the second clock signal xck3 received by the third-stage shift register unit 13 shift in sequence, and the first clock signal ck4 and the second clock signal xck4 received by the fourth-stage shift register unit 14 shift in sequence, so that the first clock signal ck and the second clock signal xck shifted in sequence can be output in pairs, a driving chip for outputting clock signals only calculates the output time of the first clock signal ck and the second clock signal xck, the logic calculation amount of the driving chip is reduced, and the driving performance of the IC can be ensured.

Optionally, fig. 9 is a schematic structural diagram of another shift register according to an embodiment of the present invention, as shown in fig. 9, in two adjacent shift register units 10, a second clock signal XCK of a second clock terminal XCK of a previous shift register unit 10 is multiplexed into a first clock signal CK of a first clock terminal CK of a next shift register unit 10.

Specifically, referring to fig. 8 and fig. 9 in combination, taking the first stage shift register unit 11 and the second stage shift register unit 12 as an example, when the second clock signal xck1 received by the first stage shift register unit 11 jumps to the active level at time t3, the scan signal sn1 output by the first stage shift register unit jumps to the active level, that is, the second clock signal xck1 jumps together with the scan signal sn1 at time t 3. When the second clock signal xck2 received by the second stage shift register unit 12 jumps to the active level at time t5, the scan signal sn2 output by the second stage shift register unit transitions to the active level, that is, the second clock signal xck2 and the scan signal sn2 transition together at time t 5. Because the scanning signals sn1 and sn2 output by the first-stage shift register unit 11 and the second-stage shift register unit 12 need to be shifted in sequence, the second clock signal xck1 and the second clock signal xck2 also need to be shifted in sequence, and because the first clock signal ck and the second clock signal xck of the same shift register unit 10 also shift in sequence, the second clock signal xck1 and the second clock signal xck2 shift in sequence, so that the second clock signal xck1 received by the first-stage shift register unit 11 and the first clock signal ck received by the second-stage shift register unit 12 have the same transition process, and therefore, the second clock signal xck1 received by the first-stage shift register unit 11 can be multiplexed into the first clock signal ck received by the second-stage shift register unit 12. Based on the same principle, the scan signals sn output from the first stage shift register unit 11, the second stage shift register unit 12, the third stage shift register unit 13, and the fourth stage shift register unit 14 need to be sequentially shifted, so the second clock signals xck received by the shift register units 10 that are sequentially cascaded also need to be sequentially shifted. Since the first clock signal CK and the second clock signal XCK of the same shift register unit 10 are also shifted in sequence, when it is ensured that the second clock signal XCK received by each shift register unit 10 cascaded in sequence is shifted in sequence, in the adjacent two shift register units 10, the second clock signal XCK received by the previous shift register unit 10 and the first clock signal CK received by the next shift register unit 10 have the same transition process, so that the second clock signal XCK of the second clock terminal XCK of the previous shift register unit 10 can be multiplexed into the first clock signal CK of the first clock terminal CK of the next shift register unit 10, and thus, on the basis of ensuring that each shift register unit 10 can accurately output scanning signals, the setting of clock signal lines is reduced, and the circuit structure can be simplified.

Optionally, fig. 10 is a schematic structural diagram of another shift register provided in an embodiment of the present invention, and as shown in fig. 10, a plurality of shift registering unit sets 100 of the shift register 10; each shift register unit group 100 comprises at least four shift register units 10 which are sequentially cascaded; in the same shift register unit group 100, the effective level of the first clock signal CK at the first clock terminal CK of each shift register unit 10 is sequentially shifted, and the effective level of the second clock signal XCK at the second clock terminal XCK of each shift register unit 10 is sequentially shifted.

Specifically, each shift register unit group 100 includes an even number of shift register units 10, and at least four shift register units 10 cascaded in sequence, where a first clock signal ck received by each shift register unit 10 cascaded in sequence is shifted in sequence, and a second clock signal xck received by each shift register unit 10 cascaded in sequence is shifted in sequence, so that the effective levels of the scan signals output by each shift register unit group 100 form a scan cycle. The first clock signal ck and the second clock signal xck of each shift register unit group 100 may be the same or different, and may be set according to design requirements.

Illustratively, taking two shift register unit sets 100 in the shift register and each shift register unit set 100 includes four shift register units 10 as an example, referring to fig. 10, taking the shift register unit set 100 including a first-stage shift register unit 11, a second-stage shift register unit 12, a third-stage shift register unit 13 and a fourth-stage shift register unit 14 as an example, first, based on the above-mentioned embodiment, a first clock signal ck and a second clock signal xck located in the same shift register unit 10 are sequentially shifted, and on the basis of fig. 8, when the second clock signal xck1 received by the first-stage shift register unit 11 jumps to an active level at time t3, a scan signal sn1 output by the first-stage shift register unit jumps to an active level at time t5, when the second clock signal xck2 received by the second-stage shift register unit 12 jumps to an active level at time t5, a scan signal sn2 output by the first-stage shift register unit is an active level, when the second clock signal xck2 received by the third-stage shift register unit 13 jumps to an active level at time t7, a scan signal sn2 output by the third-stage shift register unit 13, and a scan signal xck4, namely, the scan signal xck2 is an active level at time t4, and the scan signal xck is an active level. Therefore, by sequentially shifting the effective levels of the second clock signals xck received by the shift register units 10 that are sequentially cascaded, the effective levels of the scan signals sn output by the shift register units 10 that are sequentially cascaded can be sequentially shifted. Therefore, by sequentially shifting the effective level of the first clock signal CK at the first clock terminal CK of each shift register unit 10 and sequentially shifting the effective level of the second clock signal XCK at the second clock terminal XCK of each shift register unit 10 in the same shift register unit group 100, it is ensured that the scanning signals output by the sequentially cascaded shift register units 10 in the same shift register unit group 100 are sequentially shifted.

It is understood that when each shift register unit group 100 includes more than four shift register units 10, for example, when each shift register unit group 100 includes six shift register units 10, a corresponding clock signal line may be additionally provided for the shift register units 10 of the last two stages. Or, the first clock signal of the fifth stage shift register unit may multiplex the first clock signal ck1 of the first stage shift register unit, and the second clock signal of the fifth stage shift register unit may multiplex the second clock signal xck1 of the first stage shift register unit; the first clock signal of the sixth stage shift register unit may multiplex the first clock signal ck2 of the second stage shift register unit, and the second clock signal of the sixth stage shift register unit may multiplex the second clock signal xck2 of the second stage shift register unit. Thus, the arrangement of the signal lines can be reduced, and the circuit structure can be simplified.

Alternatively, referring to fig. 10, the shift register further includes a plurality of clock signal lines (a plurality of first clock signal lines Ck1, ck2, ck3, ck4, and a plurality of second clock signal lines xCk1, xCk2, xCk3, xCk4 shown in fig. 3); in the same shift register unit group 100, the first clock terminal CK of each shift register unit 10 is electrically connected to different clock signal lines, and the second clock terminal XCK of each shift register unit 10 is electrically connected to different clock signal lines.

Specifically, for the same shift registering unit group 100, a first clock signal line for transmitting a first clock signal ck corresponding to each shift registering unit 10 one to one, and a second clock signal line for transmitting a second clock signal xck corresponding to each shift registering unit 10 one to one may be provided, so that the effective levels of the first clock signals ck of the shift registering units 10 sequentially arranged in cascade are sequentially shifted, and the effective levels of the second clock signals xck of the shift registering units 10 sequentially arranged in cascade are sequentially shifted, thereby ensuring the same shift registering unit group 100.

Optionally, with continued reference to fig. 10, the shift register unit set 100 includes a first shift register unit 111; in the shift register unit group 100, the start time of the effective level of the scan signal output by the signal output end OUT of the first shift register unit 111 is before the start time of the effective level of the scan signal output by the signal output end OUT of the other shift register units 10; the effective levels of the scanning signals output by the signal output ends of the first shift register units 111 of each shift register unit group 100 do not overlap; in each shift register unit 10, the first clock terminal CK of each shift register unit 10 with the same arrangement number is electrically connected to the same clock signal line, and the second clock terminal XCK of each shift register unit 10 with the same arrangement number is electrically connected to the same clock signal line.

Specifically, referring to fig. 8 and 10, the first clock signals ck1, ck2, and ck4 received by the sequentially cascaded shift registers 11 are sequentially shifted, and if the fifth-stage shift register unit includes a cascaded fifth-stage shift register unit, that is, the signal input end IN of the fifth-stage shift register unit is electrically connected to the signal output end OUT of the fourth-stage shift register unit, the clock signal received by the first clock end of the fifth-stage shift register unit is the same as the first clock signal ck1 received by the first-stage shift register unit, that is, the first clock signal ck received by every four sequentially cascaded shift register units is a cycle, so that each shift register unit group 100 can share the first clock signal ck and the second clock signal xck, that is, the first shift register unit 111 IN each shift register unit group 100 shares the first clock signal ck1 and the second clock signal xck1, and the second shift register unit 12 IN each shift register unit group 100 shares the first clock signal ck2 and the second clock signal xck2, and so on. Therefore, the arrangement of clock signal lines can be greatly reduced, and the circuit structure is favorably simplified. On this basis, by setting the same shift register unit group 100, the start time of the effective level of the scanning signal output by the signal output end OUT of the first shift register unit 111 is before the start time of the effective level of the scanning signal output by the signal output end OUT of the other shift register units 10, and the effective levels of the scanning signals output by the signal output ends of the first shift register units 111 of the shift register unit groups 100 do not overlap with each other, the effective levels of the scanning signals output by the shift register unit groups 100 can be sequentially shifted, so that when the pixel circuits in the display panel are driven, the progressive scanning of the display panel can be realized, and the complete display of one frame of picture can be realized.

Optionally, fig. 11 is a schematic structural diagram of another shift register according to an embodiment of the present invention, and as shown in fig. 11, in each shift register unit 10 of the same shift register unit group 100, the second clock signal XCK of the second clock terminal XCK of the previous shift register unit 10 is multiplexed into the first clock signal CK of the first clock terminal CK of the next shift register unit 10.

Specifically, in the same shift register unit group 100, since the effective level of the second clock signal XCK of the second clock terminal XCK of the previous shift register unit 10 overlaps with the effective level of the first clock signal CK of the first clock terminal CK of the next shift register unit 10 in the two adjacent cascaded shift units 10, the second clock signal XCK of the second clock terminal XCK of the previous shift register unit 10 can be multiplexed into the first clock signal CK of the first clock terminal CK of the next shift register unit 10 in the two adjacent cascaded shift units 10 located in the same shift register unit group 100, on the basis of which the first clock terminals CK of the shift register units 10 with the same arrangement number are electrically connected to the same clock signal line, and the second clock terminals XCK of the shift register units 10 with the same arrangement number are electrically connected to the same clock signal line in each shift register unit group 100, which can further reduce the arrangement of clock signal lines and simplify the circuit structure.

Based on the same inventive concept, embodiments of the present invention further provide a display panel, where the display panel includes the shift register provided in any embodiment of the present invention, and therefore the display panel provided in the embodiments of the present invention includes technical features of the shift register provided in any embodiment of the present invention, and can achieve beneficial effects of the shift register provided in any embodiment of the present invention, and the same points can be referred to the above description of the shift register provided in the embodiments of the present invention, and are not repeated herein.

Based on the same inventive concept, embodiments of the present invention further provide a display device, where the display device includes the display panel provided in the embodiments of the present invention, so that the display device provided in the embodiments of the present invention includes technical features of the display panel provided in the embodiments of the present invention, and beneficial effects of the display panel provided in the embodiments of the present invention can be achieved. The display panel may be an organic light emitting display panel or a micro light emitting diode display panel.

Fig. 12 is a schematic structural diagram of a display device according to an embodiment of the present invention, and the display device 00 may be any electronic product with a display function, including but not limited to the following categories: the mobile terminal comprises a television, a notebook computer, a desktop display, a tablet computer, a digital camera, a mobile phone, an intelligent bracelet, intelligent glasses, a vehicle-mounted display, medical equipment, industrial control equipment, a touch interaction terminal and the like.

It should be understood that various forms of the flows shown above may be used, with steps reordered, added, or deleted. For example, the steps described in the present invention may be executed in parallel, sequentially, or in different orders, and are not limited herein as long as the desired results of the technical solution of the present invention can be achieved.

The above-described embodiments should not be construed as limiting the scope of the invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions may be made in accordance with design requirements and other factors. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A shift register, comprising: a plurality of shift register units which are arranged in a cascade manner;

a signal input end of the shift register unit of the first stage receives a starting signal; in the adjacent two stages of shift register units, the signal input end of the next shift register unit is electrically connected with the signal output end of the previous shift register unit; each stage of the shift register unit is used for controlling the scanning signal output by the signal output end according to the first clock signal, the second clock signal and the input signal of the signal input end;

2. The shift register of claim 1, wherein the shift register unit further comprises a first control module, a charge pump module, a second control module, and an output module;

in the same shift register unit:

the first control module is electrically connected with the signal input end, the first clock end and the output module respectively, and the first control module and the output module are electrically connected with a first node; the first control module is used for controlling a transmission path for transmitting an input signal of the signal input end to the first node according to the first clock signal;

the charge pump module is electrically connected with the second clock end and the first node respectively; the charge pump module is used for controlling the coupling quantity coupled to the first node when the second clock signal jumps;

the second control module is electrically connected with the first clock end, the second clock end, the first node, the first level end and the output module respectively, and the second control module is electrically connected with the output module at a second node; the second control module is used for controlling the electric potential of the second node according to the electric potential of the first node, the first clock signal, the second clock signal and the first level signal of the first level end;

the output module is also electrically connected with the first level end, the second level end and the signal output end respectively; the output module is used for controlling a transmission path for transmitting the first level signal to the signal output end according to the potential of the first node, and controlling a transmission path for transmitting the second level signal of the second level end to the second node according to the potential of the second node.

3. The shift register of claim 2, wherein the shift register unit further comprises an interlock module;

in the same shift register unit, the interlock module is electrically connected to the second level terminal, the first node and the second node, respectively; the interlock module is configured to control a transmission path through which the second level signal is transmitted to the second node according to the potential of the first node, and control a transmission path through which the second level signal is transmitted to the first node according to the potential of the second node.

4. The shift register of claim 2, wherein the shift register unit further comprises an interlock module;

in the same shift register unit, the interlock module is electrically connected to the second clock terminal, the second level terminal, the second control module, the first node, and the second node, respectively; the interlock module is used for controlling a transmission path for transmitting the second level signal to the second node according to the potential of the first node, and controlling the transmission path for transmitting the second level signal to the first node under the control of the second clock signal and the second control module.

5. The shift register of claim 1, wherein in two adjacent stages of the shift register units in one clock cycle, a first clock signal at the first clock terminal of each shift register unit is sequentially shifted, and a second clock signal at the second clock terminal of each shift register unit is sequentially shifted.

6. The shift register of claim 5, wherein in a same shift register unit, a valid pulse of the first clock signal at the first clock terminal is sequentially shifted from a valid pulse of the second clock signal at the second clock terminal in one clock cycle.

7. The shift register of claim 6, wherein in two adjacent stages of the shift register units, a second clock signal at the second clock terminal of a preceding stage of the shift register units is multiplexed into a first clock signal at the first clock terminal of a succeeding stage of the shift register units.

8. The shift register according to claim 6, comprising: a plurality of shift register unit groups; each shift register unit group comprises at least four shift register units which are sequentially cascaded;

in the same shift register unit group, the effective levels of the first clock signals at the first clock end of each shift register unit are sequentially shifted, and the effective levels of the second clock signals at the second clock end of each shift register unit are sequentially shifted.

9. The shift register of claim 8, further comprising: a plurality of clock signal lines;

in the same shift register unit group, the first clock end of each shift register unit is electrically connected to different clock signal lines, and the second clock end of each shift register unit is electrically connected to different clock signal lines.

10. The shift register of claim 9, wherein the shift registering unit group includes a first shift registering unit; in the same shift register unit group, the start time of the effective level of the scanning signal output by the signal output end of the first shift register unit is before the start time of the effective level of the scanning signal output by the signal output end of the other shift register units;

the effective levels of the scanning signals output by the signal output ends of the first shift register units of each shift register unit group are not overlapped;

in each shift register unit, the first clock end of each shift register unit with the same arrangement serial number is electrically connected with the same clock signal line, and the second clock end of each shift register unit with the same arrangement serial number is electrically connected with the same clock signal line.

11. The shift register of claim 8, wherein in each of the shift register units in the same shift register unit group, the second clock signal at the second clock terminal of the shift register unit in the previous stage is multiplexed into the first clock signal at the first clock terminal of the shift register unit in the subsequent stage.

12. A display panel, comprising: a shift register as claimed in any one of claims 1 to 11.

13. A display device, comprising: the display panel of claim 12.