CN115391258B - Interface management circuit, method, apparatus, device, storage medium, and program product - Google Patents

Interface management circuit, method, apparatus, device, storage medium, and program product Download PDF

Info

Publication number
CN115391258B
CN115391258B CN202210978374.5A CN202210978374A CN115391258B CN 115391258 B CN115391258 B CN 115391258B CN 202210978374 A CN202210978374 A CN 202210978374A CN 115391258 B CN115391258 B CN 115391258B
Authority
CN
China
Prior art keywords
resistor
power supply
interface
capacitor
charging
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202210978374.5A
Other languages
Chinese (zh)
Other versions
CN115391258A (en
Inventor
黄坤
邱辉辉
林嵘
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yunma Intelligent Hainan Technology Co ltd
Original Assignee
Yunma Intelligent Hainan Technology Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yunma Intelligent Hainan Technology Co ltd filed Critical Yunma Intelligent Hainan Technology Co ltd
Priority to CN202210978374.5A priority Critical patent/CN115391258B/en
Publication of CN115391258A publication Critical patent/CN115391258A/en
Application granted granted Critical
Publication of CN115391258B publication Critical patent/CN115391258B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/00032—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries characterised by data exchange
    • H02J7/00034—Charger exchanging data with an electronic device, i.e. telephone, whose internal battery is under charge
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/0029—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries with safety or protection devices or circuits
    • H02J7/0036—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries with safety or protection devices or circuits using connection detecting circuits
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/0042—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries characterised by the mechanical construction
    • H02J7/0045—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries characterised by the mechanical construction concerning the insertion or the connection of the batteries
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/0047—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries with monitoring or indicating devices or circuits
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0042—Universal serial bus [USB]
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J2207/00—Indexing scheme relating to details of circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J2207/20—Charging or discharging characterised by the power electronics converter
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J2207/00—Indexing scheme relating to details of circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J2207/30—Charge provided using DC bus or data bus of a computer

Abstract

The embodiment of the disclosure discloses an interface management circuit, a method, an apparatus, a device, a storage medium and a program product, wherein the interface management circuit comprises: the micro control unit MCU, the first DC-DC power supply conversion circuit, the second DC-DC power supply conversion circuit, the first interface power supply isolation control circuit, the second interface power supply isolation control circuit, the third interface power supply isolation control circuit, the charging circuit, the battery, the USB interface and the base interface. The technical scheme is simple to realize and convenient to operate, and can meet different requirements of different users on interface use.

Description

Interface management circuit, method, apparatus, device, storage medium, and program product
Technical Field
The embodiment of the disclosure relates to the technical field of communication, in particular to an interface management circuit, a method, a device, equipment, a storage medium and a program product.
Background
With the development of communication technology and the wide use of POS devices, users have increasingly demanded to use POS devices, for example, to charge a base of a POS device or to charge a USB, it is desirable that a POS device can be used as a charging device, and it is desirable that a POS device can use a USB uplink/downlink communication function while charging. However, in the prior art, the USB interface and the base interface belong to the same power network, so that the USB interface cannot synchronously realize the USB uplink communication function when the USB interface and the base interface are simultaneously connected to a power supply; in addition, when the base interface is used for charging, the USB interface cannot synchronously realize the functions of downlink power supply and communication. Accordingly, there is a need for an interface management scheme that can meet the above-mentioned various needs of users.
Disclosure of Invention
Embodiments of the present disclosure provide an interface management circuit, method, apparatus, device, storage medium, and program product.
In a first aspect, an interface management circuit is provided in an embodiment of the present disclosure.
Specifically, the interface management circuit includes: the micro control unit MCU, first DC-DC power supply conversion circuit, second DC-DC power supply conversion circuit, first interface power supply isolation control circuit, second interface power supply isolation control circuit, third interface power supply isolation control circuit, charging circuit, battery, USB interface and base interface, wherein:
the first DC-DC power supply conversion circuit is connected with the micro control unit MCU, the battery and the second interface power supply isolation control circuit and is used for realizing the conversion from the battery voltage to the preset voltage under the control of the micro control unit MCU;
the second DC-DC power supply conversion circuit is connected with the micro control unit MCU and the battery and is used for converting the battery voltage into the power supply voltage of the micro control unit MCU so as to supply power for the power supply of the micro control unit MCU;
the first interface power isolation control circuit is connected with the micro control unit MCU, the charging circuit and the USB interface and is used for realizing the switching-on and switching-off of a passage between a USB interface power supply VUSB and a charging power supply VCHG under the control of the micro control unit MCU;
The second interface power isolation control circuit is connected with the micro control unit MCU, the first DC-DC power conversion circuit and the USB interface and is used for realizing the disconnection of a passage between the USB interface power VUSB and a preset voltage power under the control of the micro control unit MCU;
the third interface power isolation control circuit is connected with the micro control unit MCU, the charging circuit and the base interface and is used for realizing the disconnection of a passage between the base interface power supply and the charging power supply VCHG under the control of the micro control unit MCU;
the charging circuit is connected with the micro control unit MCU, the battery, the first interface power supply isolation control circuit and the third interface power supply isolation control circuit and is used for realizing charging management of the charging power supply VCHG for the battery power supply Vbat under the control of the micro control unit MCU;
the USB interface is connected with the micro control unit MCU, the first interface power supply isolation control circuit and the second interface power supply isolation control circuit and is used for realizing the charge management of the charging power supply VCHG for the battery power supply Vbat under the control of the micro control unit MCU;
the base interface is connected with the third interface power isolation control circuit and is used for providing input power.
In an embodiment of the present disclosure, the first DC-DC power conversion circuit includes: DC-DC chip U1, inductance L1, electric capacity C2, electric capacity C3, electric capacity C4, electric capacity C5, electric capacity C6, resistance R1, resistance R2, resistance R3 and resistance R4, wherein:
the capacitor C1, the capacitor C2 and the capacitor C3 are connected in parallel to form a parallel capacitor group;
the switch control SW pin of the DC-DC chip U1 is connected with one end of the inductor L1 and one end of the capacitor C4;
the other end of the inductor L1 is connected with one end of the parallel capacitor group, one end of the resistor R1 and a preset voltage power supply end, wherein the preset voltage power supply end is also connected with the second interface power supply isolation control circuit;
the other end of the capacitor C4 is connected with a boosting VBST pin of the DC-DC chip U1;
the other end of the resistor R1 is connected with a voltage feedback VFB pin of the DC-DC chip U1 and one end of the resistor R2;
the other end of the resistor R2 is grounded;
the power input VIN pin of the DC-DC chip U1 is connected with the battery power supply Vbat and one end of the capacitor C6;
the other end of the capacitor C6 is grounded;
an enable EN pin of the DC-DC chip U1 is connected with one end of a resistor R3, one end of a capacitor C5 and one end of a resistor R4;
The other end of the resistor R3 and the other end of the capacitor C5 are grounded;
the other end of the resistor R4 is connected with the MCU.
In an embodiment of the present disclosure, the second DC-DC power conversion circuit includes: DC-DC chip U2, inductance L2, electric capacity C7, electric capacity C8, electric capacity C9, electric capacity C10, electric capacity C11, resistance R5, resistance R6, resistance R7, wherein:
the capacitor C7, the capacitor C8 and the capacitor C9 are connected in parallel to form a parallel capacitor group;
the switch control SW pin of the DC-DC chip U2 is connected with one end of the inductor L2 and one end of the capacitor C10;
the other end of the inductor L2 is connected with one end of the parallel capacitor group, one end of the resistor R5 and the MCU;
the other end of the capacitor C10 is connected with a boosting VBST pin of the DC-DC chip U2;
the other end of the resistor R5 is connected with the voltage feedback VFB pin of the DC-DC chip U2 and one end of the resistor R6;
the other end of the resistor R6 is grounded;
the power input VIN pin of the DC-DC chip U2 is connected with the battery power supply Vbat, one end of a resistor R7 and one end of a capacitor C11;
the other end of the resistor R7 is connected with an enable EN pin of the DC-DC chip U2;
the grounding GND pin of the DC-DC chip U2 is grounded.
In one embodiment of the disclosure, the first interface power isolation control circuit includes: the power supply path composed of a PMOS tube Q1 and a diode D1 is a PMOS switch control circuit composed of an NPN triode Q2, an NPN triode Q3, a capacitor C12, a resistor R8, a resistor R9, a resistor R10 and a resistor R11, wherein:
the drain electrode of the PMOS tube Q1 is connected with a charging power supply VCHG through a diode D1, the source electrode of the PMOS tube Q1 is connected with one end of a capacitor C12 and a USB interface power supply VUSB, and the grid electrode of the PMOS tube Q1 is connected with the other end of the capacitor C12 and one end of a resistor R8;
the other end of the resistor R8 is connected with one end of the resistor R9 and the collector of the NPN triode Q2;
the other end of the resistor R9 is connected with one end of a resistor R10 and a USB interface power supply VUSB;
the emitter of the NPN triode Q2 is grounded, and the base electrode of the NPN triode Q2 is connected with the other end of the resistor R10 and the collector electrode of the NPN triode Q3;
the emitter of the NPN triode Q3 is grounded, and the base electrode of the NPN triode Q3 is connected with the MCU through a resistor R11.
In an embodiment of the disclosure, the second interface power isolation control circuit includes: the power supply path composed of a PMOS tube Q4 and a diode D2 comprises a PMOS switch control circuit composed of an NPN triode Q5, an NPN triode Q6, a capacitor C13, a resistor R12, a resistor R13, a resistor R14 and a resistor R15, wherein:
The drain electrode of the PMOS tube Q4 is connected with a USB interface power supply VUSB through a diode D2, the source electrode of the PMOS tube Q4 is connected with one end of a capacitor C13 and a preset voltage power supply, and the grid electrode of the PMOS tube Q4 is connected with the other end of the capacitor C13 and one end of a resistor R12;
the other end of the resistor R12 is connected with one end of the resistor R13 and the collector of the NPN triode Q5;
the other end of the resistor R13 is connected with one end of the resistor R14 and a preset voltage power supply;
the emitter of the NPN triode Q5 is grounded, and the base electrode of the NPN triode Q5 is connected with the other end of the resistor R14 and the collector electrode of the NPN triode Q6;
the emitter of the NPN triode Q6 is grounded, and the base electrode of the NPN triode Q6 is connected with the MCU through a resistor R15.
In an embodiment of the disclosure, the third interface power isolation control circuit includes: the power supply path composed of a PMOS tube Q7 and a diode D3 comprises a PMOS switch control circuit composed of an NPN triode Q8, an NPN triode Q9, a capacitor C14, a resistor R16, a resistor R17, a resistor R18 and a resistor R19, wherein:
the drain electrode of the PMOS tube Q7 is connected with a charging power supply VCHG through a diode D3, the source electrode of the PMOS tube Q7 is connected with one end of a capacitor C14 and a base interface power supply, and the grid electrode of the PMOS tube Q7 is connected with the other end of the capacitor C14 and one end of a resistor R16;
The other end of the resistor R16 is connected with one end of the resistor R17 and the collector of the NPN triode Q8;
the other end of the resistor R17 is connected with one end of the resistor R18 and the base interface power supply;
the emitter of the NPN triode Q8 is grounded, and the base electrode of the NPN triode Q8 is connected with the other end of the resistor R18 and the collector electrode of the NPN triode Q9;
the emitter of the NPN triode Q9 is grounded, and the base electrode of the NPN triode Q9 is connected with the MCU through a resistor R19.
In one embodiment of the present disclosure, the charging circuit includes: charging chip U3, inductance L3, diode D4, electric capacity C15, electric capacity C16, electric capacity C17, electric capacity C18, electric capacity C19, electric capacity C20, electric capacity C21, electric capacity C22, resistance R20, resistance R21, resistance R23 and NPN triode Q10, wherein:
the capacitor C15, the capacitor C16 and the capacitor C17 are connected in parallel to form a first parallel capacitor group, wherein one end of the first parallel capacitor group is grounded;
the capacitor C18 and the capacitor C19 are connected in parallel to form a second parallel capacitor group, wherein one end of the second parallel capacitor group is grounded;
the capacitor C20, the capacitor C21 and the capacitor C22 are connected in parallel to form a third parallel capacitor group, wherein one end of the third parallel capacitor group is grounded;
The power supply input VIN pin of the charging chip U3 is connected with the other end of the first parallel capacitor group and one end of the inductor L3;
the other end of the inductor L3 is connected with an external power supply VBS pin of the charging chip U3 through a diode D4, and is connected with the other end of the second parallel capacitor group and an inductance connection LX pin of the charging chip U3;
the power supply STAT pin of the charging chip U3 is connected with the micro control unit MCU;
the ground AGND pin of the charging chip U3 is grounded;
the battery BAT pin of the charging chip U3 is connected with the other end of the third parallel capacitor group and the battery power supply Vbat;
an enable EN pin of the charging chip U3 is connected with one end of a resistor R21 and a collector electrode of an NPN triode Q10, wherein the resistor R21 is a thermistor, and the other end of the resistor R21 is grounded;
the base electrode of the NPN triode Q10 is connected with one end of a resistor R22 and one end of a resistor R23, the emitter electrode of the NPN triode Q10 is grounded, the other end of the resistor R22 is grounded, and the other end of the resistor R23 is connected with the MCU;
the charging ICHG pin of the charging chip U3 is connected with one end of a resistor R20, and the other end of the resistor R20 is grounded.
In an embodiment of the disclosure, the interface management circuit further includes a battery state monitoring module, where the battery state monitoring module is connected with the MCU and the battery, and is configured to monitor a power supply state of the MCU.
In one embodiment of the present disclosure, the battery state monitoring module includes a resistor R24 and a resistor R25, wherein:
one end of the resistor R24 and one end of the resistor R25 are connected with the MCU;
the other end of the resistor R24 is connected with a battery power supply Vbat, and the other end of the resistor R25 is grounded.
In an embodiment of the disclosure, the interface management circuit further includes a base power supply access state monitoring module vin_adc, where the base power supply access state monitoring module vin_adc is connected to the MCU and the base interface power supply, and is configured to monitor a power supply state of the base interface power supply.
In an embodiment of the disclosure, the base power access status monitoring module vin_adc includes a resistor R26 and a resistor R27, where:
one end of the resistor R26 and one end of the resistor R27 are connected with the MCU;
the other end of the resistor R26 is connected with a base interface power supply, and the other end of the resistor R27 is grounded.
In a second aspect, an embodiment of the present disclosure provides an interface management method.
Specifically, the interface management method includes:
judging whether the USB interface is in a connection state or not in a starting-up state;
when judging that the USB interface is in a connection state, judging whether the connection equipment is downlink communication OTG equipment or not;
when the base interface is judged to be connected with the power VIN, the micro control unit MCU controls the third interface power isolation control circuit to be conducted to realize the charging function of the base interface and the downlink communication function of the USB interface;
when the base interface is judged not to be connected with the downlink communication OTG equipment, judging whether the base interface is connected with the power supply VIN or not, when the base interface is judged to be connected with the power supply VIN, the micro-control unit MCU controls the first interface power supply isolation control circuit and the second interface power supply isolation control circuit to be in a closed state so as to realize a charging function of the base interface and an uplink communication function of the USB interface, and when the base interface is judged not to be connected with the power supply VIN, the micro-control unit MCU controls the first interface power supply isolation control circuit to be in a conducting and opening state, and the second interface power supply isolation control circuit and the third interface power supply isolation control circuit to be in a closed state so as to realize a charging function and an uplink communication function of the USB interface;
When the USB interface is judged not to be in a connection state, judging whether the base interface is connected with the power supply VIN, when the base interface is judged to be connected with the power supply VIN, the micro control unit MCU controls the first interface power supply isolation control circuit and the second interface power supply isolation control circuit to be closed, controls the third interface power supply isolation control circuit to be opened and connected, only realizes the charging function of the base interface, when the base interface is judged not to be connected with the power supply VIN, judges whether the USB interface is connected with the power supply VUSB, when the USB interface is judged to be connected with the power supply VUSB, the micro control unit MCU controls the first interface power supply isolation control circuit to be in a connection and on state, the second interface power supply isolation control circuit and the third interface power supply isolation control circuit are in an off state, only realizes the charging function of the USB interface, and when the USB interface is judged not to be connected with the power supply VUSB, the process is ended.
In a third aspect, an embodiment of the present disclosure provides an interface management apparatus.
Specifically, the interface management device includes:
the first judging module is configured to judge whether the USB interface is in a connection state or not in a starting-up state;
the second judging module is configured to judge whether the connecting equipment is downlink communication OTG equipment or not when judging that the USB interface is in a connecting state;
The third judging module is configured to judge whether the base interface is connected with the power supply VIN or not when the connecting equipment is judged to be downlink communication OTG equipment, and when the base interface is judged to be connected with the power supply VIN, the micro control unit MCU controls the first interface power supply isolation control circuit to be closed, the third interface power supply isolation control circuit to be conducted, the charging function of the base interface and the downlink communication function of the USB interface are realized, and when the base interface is judged not to be connected with the power supply VIN, the micro control unit MCU controls the first interface power supply isolation control circuit to be closed, the first DC-DC power supply conversion circuit to start to work, and the second interface power supply isolation control circuit to be conducted only realizes the downlink power supply and the downlink communication function of the USB interface;
the fourth judging module is configured to judge whether the base interface is connected with the power supply VIN or not when the connecting equipment is judged not to be the downlink communication OTG equipment, and when the base interface is judged to be connected with the power supply VIN, the micro control unit MCU controls the first interface power supply isolation control circuit and the second interface power supply isolation control circuit to be in a closed state so as to realize the charging function of the base interface and the uplink communication function of the USB interface, and when the base interface is judged not to be connected with the power supply VIN, the micro control unit MCU controls the first interface power supply isolation control circuit to be in a conducting and opening state, and the second interface power supply isolation control circuit and the third interface power supply isolation control circuit to be in a closing state so as to realize the charging and uplink communication functions of the USB interface;
And a fifth judging module configured to judge whether the base interface is connected to the power supply VIN when the USB interface is judged not to be in a connected state, and to cause the micro control unit MCU to control the first interface power supply isolation control circuit and the second interface power supply isolation control circuit to be turned off when the base interface is judged to be connected to the power supply VIN, and to turn on the third interface power supply isolation control circuit to realize only the base interface charging function, and to judge whether the USB interface is connected to the power supply VUSB when the base interface is judged not to be connected to the power supply VIN, and to cause the micro control unit MCU to control the first interface power supply isolation control circuit to be in a turned-on state when the USB interface is judged to be connected to the power supply VUSB, and to cause the second interface power supply isolation control circuit and the third interface power supply isolation control circuit to be in a turned-off state to realize only the USB interface charging function, and to finish when the USB interface is judged not to be connected to the power supply VUSB.
In a fourth aspect, an embodiment of the present disclosure provides an electronic device, including a memory for storing one or more computer instructions supporting an interface management apparatus to perform the above-described interface management method, and a processor configured to execute the computer instructions stored in the memory. The interface management means may further comprise a communication interface for the interface management means to communicate with other devices or a communication network.
In a fifth aspect, embodiments of the present disclosure provide a computer readable storage medium storing computer instructions for use by an interface management device, including computer instructions for performing the above-described interface management method for an interface management device.
In a sixth aspect, embodiments of the present disclosure provide a computer program product comprising computer programs/instructions which, when executed by a processor, implement the steps of the interface management method described above.
The technical scheme provided by the embodiment of the disclosure can comprise the following beneficial effects:
according to the technical scheme, the working states of the interfaces are controlled by arranging the plurality of interface power isolation control circuits, so that the charging functions of the USB interface and the base interface and the charging and data transmission functions of the USB interface can be flexibly switched. The technical scheme is simple to realize and convenient to operate, and can meet different requirements of different users on interface use.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of embodiments of the disclosure.
Drawings
Other features, objects and advantages of the embodiments of the present disclosure will become more apparent from the following detailed description of non-limiting embodiments, taken in conjunction with the accompanying drawings. In the drawings:
FIG. 1 shows a circuit block diagram of an interface management circuit according to an embodiment of the present disclosure;
fig. 2 shows a circuit configuration diagram of a first DC-DC power conversion circuit according to an embodiment of the present disclosure;
fig. 3 shows a circuit configuration diagram of a second DC-DC power conversion circuit according to an embodiment of the present disclosure;
FIG. 4 shows a circuit block diagram of a first interface power isolation control circuit according to an embodiment of the present disclosure;
FIG. 5 illustrates a circuit block diagram of a second interface power isolation control circuit according to an embodiment of the present disclosure;
FIG. 6 shows a circuit block diagram of a third interface power isolation control circuit according to an embodiment of the present disclosure;
fig. 7 shows a circuit configuration diagram of a charging circuit according to an embodiment of the present disclosure;
FIG. 8 illustrates a circuit block diagram of a battery condition monitoring module according to an embodiment of the present disclosure;
FIG. 9 shows a circuit block diagram of a base power access status monitoring module according to an embodiment of the present disclosure;
FIG. 10 illustrates a flow chart of an interface management method according to an embodiment of the present disclosure;
FIG. 11 shows a system block diagram of an interface management device according to an embodiment of the present disclosure;
FIG. 12 shows a block diagram of an electronic device according to an embodiment of the present disclosure;
Fig. 13 is a schematic diagram of a computer system suitable for use in implementing an interface management method according to an embodiment of the present disclosure.
Detailed Description
Hereinafter, exemplary implementations of the embodiments of the present disclosure will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement them. In addition, for the sake of clarity, portions irrelevant to description of the exemplary embodiments are omitted in the drawings.
In the presently disclosed embodiments, it is to be understood that the terms such as "comprises" or "comprising" and the like are intended to indicate the presence of features, numbers, steps, acts, components, portions, or combinations thereof disclosed in the present specification, and are not intended to exclude the possibility of one or more other features, numbers, steps, acts, components, portions, or combinations thereof being present or added.
In addition, it should be noted that, without conflict, the embodiments of the present disclosure and features of the embodiments may be combined with each other. Embodiments of the present disclosure will be described in detail below with reference to the attached drawings in conjunction with the embodiments.
According to the technical scheme provided by the embodiment of the disclosure, the working states of the interfaces are controlled by arranging the plurality of interface power isolation control circuits, so that the charging functions of the USB interfaces and the base interfaces and the charging and data transmission functions of the USB interfaces can be flexibly switched. The technical scheme is simple to realize and convenient to operate, and can meet different requirements of different users on interface use.
Fig. 1 shows a circuit configuration diagram of an interface management circuit according to an embodiment of the present disclosure, wherein the interface management circuit is installed in a POS machine, and as shown in fig. 1, the interface management circuit includes a micro control unit MCU, a first DC-DC power conversion circuit, a second DC-DC power conversion circuit, a first interface power isolation control circuit, a second interface power isolation control circuit, a third interface power isolation control circuit, a charging circuit, a battery, a USB interface, and a base interface, wherein:
the first DC-DC power supply conversion circuit is connected with the micro control unit MCU, the battery and the second interface power supply isolation control circuit and is used for realizing the conversion from the battery voltage to the preset voltage under the control of the micro control unit MCU;
the second DC-DC power supply conversion circuit is connected with the micro control unit MCU and the battery and is used for converting the battery voltage into the power supply voltage of the micro control unit MCU so as to supply power for the power supply of the micro control unit MCU;
the first interface power isolation control circuit is connected with the micro control unit MCU, the charging circuit and the USB interface and is used for realizing the switching-on and switching-off of a passage between a USB interface power supply VUSB and a charging power supply VCHG under the control of the micro control unit MCU;
The second interface power isolation control circuit is connected with the micro control unit MCU, the first DC-DC power conversion circuit and the USB interface and is used for realizing the disconnection of a passage between the USB interface power VUSB and a preset voltage power under the control of the micro control unit MCU;
the third interface power isolation control circuit is connected with the micro control unit MCU, the charging circuit and the base interface and is used for realizing the disconnection of a passage between the base interface power supply and the charging power supply VCHG under the control of the micro control unit MCU;
the charging circuit is connected with the micro control unit MCU, the battery, the first interface power supply isolation control circuit and the third interface power supply isolation control circuit and is used for realizing charging management of the charging power supply VCHG for the battery power supply Vbat under the control of the micro control unit MCU;
the USB interface is connected with the micro control unit MCU, the first interface power supply isolation control circuit and the second interface power supply isolation control circuit and is used for realizing the charge management of the charging power supply VCHG for the battery power supply Vbat under the control of the micro control unit MCU;
the base interface is connected with the third interface power isolation control circuit and is used for providing input power.
In one embodiment of the present disclosure, as shown in fig. 2, the first DC-DC power conversion circuit includes: DC-DC chip U1, inductance L1, electric capacity C2, electric capacity C3, electric capacity C4, electric capacity C5, electric capacity C6, resistance R1, resistance R2, resistance R3 and resistance R4, wherein:
the capacitor C1, the capacitor C2 and the capacitor C3 are connected in parallel to form a parallel capacitor group;
the switch control SW pin of the DC-DC chip U1, namely pin 2, is connected with one end of the inductor L1 and one end of the capacitor C4;
the other end of the inductor L1 is connected with one end of the parallel capacitor group, one end of the resistor R1 and a preset voltage power supply end, wherein the preset voltage power supply end is also connected with the second interface power supply isolation control circuit;
the other end of the capacitor C4 is connected with a boosting VBST pin, namely a pin 6, of the DC-DC chip U1;
the other end of the resistor R1 is connected with a voltage feedback VFB pin, namely pin 4, of the DC-DC chip U1 and one end of the resistor R2;
the other end of the resistor R2 is grounded;
the power input VIN pin of the DC-DC chip U1, namely pin 3, is connected with the battery power supply Vbat and one end of the capacitor C6;
the other end of the capacitor C6 is grounded;
the enable EN pin of the DC-DC chip U1, namely pin 5, is connected with one end of a resistor R3, one end of a capacitor C5 and one end of a resistor R4;
The other end of the resistor R3 and the other end of the capacitor C5 are grounded;
the other end of the resistor R4 is connected with the MCU.
In this embodiment, when the control signal of the MCU outputs a high level, the enable EN pin of the DC-DC chip U1 of the first DC-DC power conversion circuit detects the high level, and the first DC-DC power conversion circuit starts to operate and provides a preset voltage output at the preset voltage power supply terminal; when the control signal of the micro control unit MCU outputs a low level, the enable EN pin of the DC-DC chip U1 of the first DC-DC power conversion circuit detects the low level, the first DC-DC power conversion circuit stops working, and the preset voltage output of the preset voltage power supply terminal is turned off, where the preset voltage may be set according to the actual application requirement, for example, may be set to 5V.
In one embodiment of the present disclosure, as shown in fig. 3, the second DC-DC power conversion circuit includes: DC-DC chip U2, inductance L2, electric capacity C7, electric capacity C8, electric capacity C9, electric capacity C10, electric capacity C11, resistance R5, resistance R6, resistance R7, wherein:
the capacitor C7, the capacitor C8 and the capacitor C9 are connected in parallel to form a parallel capacitor group;
The switch control SW pin of the DC-DC chip U2, namely pin 2, is connected with one end of the inductor L2 and one end of the capacitor C10;
the other end of the inductor L2 is connected with one end of the parallel capacitor group, one end of the resistor R5 and the MCU;
the other end of the capacitor C10 is connected with a boosting VBST pin, namely a pin 6, of the DC-DC chip U2;
the other end of the resistor R5 is connected with a voltage feedback VFB pin, namely pin 4, of the DC-DC chip U2 and one end of the resistor R6;
the other end of the resistor R6 is grounded;
the power input VIN pin of the DC-DC chip U2, i.e. pin 3, is connected to the battery power Vbat, one end of the resistor R7, and one end of the capacitor C11;
the other end of the resistor R7 is connected with an enable EN pin, namely a pin 5, of the DC-DC chip U2;
the ground GND pin of the DC-DC chip U2, i.e., pin 1, is grounded.
In this embodiment, the enable EN pin of the DC-DC chip U2, i.e. pin 5, is connected to the battery power source Vbat through a resistor R7, and therefore, the DC-DC chip U2 is in a continuous operation state, and continuously supplies power to the power source VCC of the micro control unit MCU.
In one embodiment of the present disclosure, as shown in fig. 4, the first interface power isolation control circuit includes: the power supply path composed of a PMOS tube Q1 and a diode D1 is a PMOS switch control circuit composed of an NPN triode Q2, an NPN triode Q3, a capacitor C12, a resistor R8, a resistor R9, a resistor R10 and a resistor R11, wherein:
The drain electrode of the PMOS tube Q1 is connected with a charging power supply VCHG through a diode D1, the source electrode of the PMOS tube Q1 is connected with one end of a capacitor C12 and a USB interface power supply VUSB, and the grid electrode of the PMOS tube Q1 is connected with the other end of the capacitor C12 and one end of a resistor R8;
the other end of the resistor R8 is connected with one end of the resistor R9 and the collector of the NPN triode Q2;
the other end of the resistor R9 is connected with one end of a resistor R10 and a USB interface power supply VUSB;
the emitter of the NPN triode Q2 is grounded, and the base electrode of the NPN triode Q2 is connected with the other end of the resistor R10 and the collector electrode of the NPN triode Q3;
the emitter of the NPN triode Q3 is grounded, and the base electrode of the NPN triode Q3 is connected with the MCU through a resistor R11.
In this embodiment, when the output signal of the MCU is at a high level, the NPN triode Q3 is turned on, and the NPN triode Q2 is turned off, so as to control the PMOS tube Q1 to be turned off, and at this time, the USB interface power supply VUSB cannot be connected to the charging power supply VCHG through the PMOS tube Q1 and the diode D1; when the output signal of the micro control unit MCU is at a low level, the NPN triode Q3 is turned off, and the NPN triode Q2 is turned on, so as to control the PMOS tube Q1 to be turned on, and at this time, the USB interface power supply VUSB may be connected to the charging power supply VCHG through the PMOS tube Q1 and the diode D1.
In one embodiment of the present disclosure, as shown in fig. 5, the second interface power isolation control circuit includes: the power supply path composed of a PMOS tube Q4 and a diode D2 comprises a PMOS switch control circuit composed of an NPN triode Q5, an NPN triode Q6, a capacitor C13, a resistor R12, a resistor R13, a resistor R14 and a resistor R15, wherein:
the drain electrode of the PMOS tube Q4 is connected with a USB interface power supply VUSB through a diode D2, the source electrode of the PMOS tube Q4 is connected with one end of a capacitor C13 and a preset voltage power supply, and the grid electrode of the PMOS tube Q4 is connected with the other end of the capacitor C13 and one end of a resistor R12;
the other end of the resistor R12 is connected with one end of the resistor R13 and the collector of the NPN triode Q5;
the other end of the resistor R13 is connected with one end of the resistor R14 and a preset voltage power supply;
the emitter of the NPN triode Q5 is grounded, and the base electrode of the NPN triode Q5 is connected with the other end of the resistor R14 and the collector electrode of the NPN triode Q6;
the emitter of the NPN triode Q6 is grounded, and the base electrode of the NPN triode Q6 is connected with the MCU through a resistor R15.
In this embodiment, when the output signal of the MCU is at a high level, the NPN triode Q6 is turned on, and the NPN triode Q5 is turned off, so as to control the PMOS tube Q4 to be turned off, and at this time, the preset voltage power supply cannot be connected to the USB interface power supply VUSB through the PMOS tube Q4 and the diode D2; when the output signal of the micro control unit MCU is at a low level, the NPN triode Q6 is turned off, and the NPN triode Q5 is turned on, so as to control the PMOS tube Q4 to be turned on, and at this time, the preset voltage power supply may be connected to the USB interface power supply VUSB through the PMOS tube Q4 and the diode D2.
In one embodiment of the present disclosure, as shown in fig. 6, the third interface power isolation control circuit includes: the power supply path composed of a PMOS tube Q7 and a diode D3 comprises a PMOS switch control circuit composed of an NPN triode Q8, an NPN triode Q9, a capacitor C14, a resistor R16, a resistor R17, a resistor R18 and a resistor R19, wherein:
the drain electrode of the PMOS tube Q7 is connected with a charging power supply VCHG through a diode D3, the source electrode of the PMOS tube Q7 is connected with one end of a capacitor C14 and a base interface power supply, and the grid electrode of the PMOS tube Q7 is connected with the other end of the capacitor C14 and one end of a resistor R16;
the other end of the resistor R16 is connected with one end of the resistor R17 and the collector of the NPN triode Q8;
the other end of the resistor R17 is connected with one end of the resistor R18 and the base interface power supply;
the emitter of the NPN triode Q8 is grounded, and the base electrode of the NPN triode Q8 is connected with the other end of the resistor R18 and the collector electrode of the NPN triode Q9;
the emitter of the NPN triode Q9 is grounded, and the base electrode of the NPN triode Q9 is connected with the MCU through a resistor R19.
In this embodiment, when the output signal of the MCU is at a high level, the NPN triode Q9 is turned on, and the NPN triode Q8 is turned off, so as to control the PMOS tube Q7 to be turned off, and at this time, the base interface power supply cannot be connected to the charging power supply VCHG through the PMOS tube Q7 and the diode D3; when the output signal of the micro control unit MCU is at a low level, the NPN triode Q9 is closed, the NPN triode Q8 is conducted, so that the PMOS tube Q7 is controlled to be conducted, and at the moment, a base interface power supply can be communicated to the charging power supply VCHG through the PMOS tube Q7 and the diode D3.
In one embodiment of the present disclosure, as shown in fig. 7, the charging circuit includes: charging chip U3, inductance L3, diode D4, electric capacity C15, electric capacity C16, electric capacity C17, electric capacity C18, electric capacity C19, electric capacity C20, electric capacity C21, electric capacity C22, resistance R20, resistance R21, resistance R23 and NPN triode Q10, wherein:
the capacitor C15, the capacitor C16 and the capacitor C17 are connected in parallel to form a first parallel capacitor group, wherein one end of the first parallel capacitor group is grounded;
the capacitor C18 and the capacitor C19 are connected in parallel to form a second parallel capacitor group, wherein one end of the second parallel capacitor group is grounded;
the capacitor C20, the capacitor C21 and the capacitor C22 are connected in parallel to form a third parallel capacitor group, wherein one end of the third parallel capacitor group is grounded;
the power input VIN pin of the charging chip U3, namely pin 1, is connected with the other end of the first parallel capacitor group and one end of the inductor L3;
the other end of the inductor L3 is connected with an external power supply VBS pin, namely a pin 4, of the charging chip U3 through a diode D4, and is connected with the other end of the second parallel capacitor group and an inductor connection LX pin, namely a pin 3, of the charging chip U3;
The power supply STAT pin, namely pin 8, of the charging chip U3 is connected with the micro control unit MCU;
the ground AGND pin of the charging chip U3, namely pin 2, is grounded;
the battery BAT pin of the charging chip U3, namely pin 5, is connected with the other end of the third parallel capacitor group and the battery power supply Vbat;
an enable EN pin, namely a pin 7, of the charging chip U3 is connected with one end of a resistor R21 and a collector electrode of an NPN triode Q10, wherein the resistor R21 is a thermistor, and the other end of the resistor R21 is grounded;
the base electrode of the NPN triode Q10 is connected with one end of a resistor R22 and one end of a resistor R23, the emitter electrode of the NPN triode Q10 is grounded, the other end of the resistor R22 is grounded, and the other end of the resistor R23 is connected with the MCU;
the charging ICHG pin of the charging chip U3, i.e. pin 6, is connected to one end of the resistor R20, and the other end of the resistor R20 is grounded.
In this embodiment, when the control signal of the micro control unit MCU outputs a high level, the NPN triode Q10 is turned on, the charging enable of the charging chip U3 is pulled down, and the charging function of the charging circuit is turned off; when the control signal of the micro control unit MCU outputs a low level, the NPN triode Q10 is turned off, the charging enable of the charging chip U3 is pulled high, the charging function of the charging circuit is turned on, and at the same time, the micro control unit MCU can also monitor the charging state of the charging chip U3, specifically: when the charging function of the charging chip U3 is opened and in a charging state, a pin 8 of the charging chip U3 outputs a low level, the micro control unit MCU monitors the low level, and at the moment, the micro control unit MCU determines that the charging chip U3 is in the charging state; when the charging function of the charging chip is closed or charging is completed and charging is stopped, the pin 8 of the charging chip U3 outputs an OD state, and the micro control unit MCU monitors a high level through the pull-up resistor inside the micro control unit MCU, and at the moment, the micro control unit MCU determines that the charging chip U3 is in a charging stop state.
In an embodiment of the disclosure, the interface management circuit may further include a battery state monitoring module bat_adc, where the battery state monitoring module is connected to the MCU and the battery, and is configured to monitor a power supply state of the MCU.
In one embodiment of the present disclosure, as shown in fig. 8, the battery state monitoring module includes a resistor R24 and a resistor R25, wherein: one end of the resistor R24 and one end of the resistor R25 are connected with the MCU, the other end of the resistor R24 is connected with the battery power supply Vbat, and the other end of the resistor R25 is grounded.
In an embodiment of the disclosure, the interface management circuit may further include a base power access state monitoring module vin_adc, where the base power access state monitoring module vin_adc is connected to the MCU and the base interface power supply, and is configured to monitor a power supply state of the base interface power supply.
In an embodiment of the present disclosure, as shown in fig. 9, the base power access status monitoring module vin_adc includes a resistor R26 and a resistor R27, where: one end of the resistor R26 and one end of the resistor R27 are connected with the MCU, the other end of the resistor R26 is connected with a base interface power supply, and the other end of the resistor R27 is grounded.
Based on the interface management circuit, the control of the working states of the interfaces can be realized by means of the control of the power isolation control circuits of the interfaces, so that the charging functions of the USB interface and the base interface and the charging and data transmission functions of the USB interface can be flexibly switched. Specifically:
1. when the POS machine is in a starting-up state, the POS machine can be divided into the following cases:
(1) When the external power supply VIN is connected to the base interface, the base power supply connection state monitoring module VIN_ADC monitors the base interface power supply connection, the micro control unit MCU controls the first interface power supply isolation control circuit and the second interface power supply isolation control circuit to be closed, controls the third interface power supply isolation control circuit to be opened and conducted, the charging power supply VCHG obtains the voltage conducted by the base interface power supply, the micro control unit MCU outputs a low-level control signal, the charging function of the charging chip U3 in the charging circuit is opened, and the charging function of the base interface is realized. At this time, since the first interface power supply isolation control circuit and the second interface power supply isolation control circuit are in the off state, the USB interface power supply VUSB has no voltage generation.
(2) When the charging function of the base interface is realized according to the step (1), if the base interface is connected to the uplink communication device (such as a computer PC) through the USB interface, the first interface power isolation control circuit and the second interface power isolation control circuit are still in the off state, and the USB interface does not provide charging current, but the uplink communication device can identify the USB port of the MCU to realize the uplink communication function, that is, the charging function of the base interface and the uplink communication function of the USB interface are realized at the moment.
(3) When the charging of the base interface and the uplink communication function of the USB interface are realized according to the steps (1) and (2), the external power supply VIN accessed by the base interface is removed, at the moment, the base power supply access state monitoring module VIN_ADC monitors the change of the power supply access voltage of the base interface, and then the micro control unit MCU also monitors the removal of the external power supply VIN of the base, but because the USB interface is accessed with the uplink communication equipment, the voltage exists in the USB interface power supply VUSB, at the moment, the micro control unit MCU is conducted by controlling the first interface power supply isolation control circuit and controls the third interface power supply isolation control circuit to be closed, so that the function of continuing to charge through the USB interface is realized, namely, the charging and the uplink communication function of the USB interface are realized at the moment.
(4) When the base interface charging function is realized according to the step (1), if the USB interface is connected to OTG (universal serial bus downlink) equipment at the moment, the micro control unit MCU detects that an ID pin signal of the USB interface is at a low level, which indicates that the USB interface is connected to OTG equipment at the moment, the micro control unit MCU controls the first DC-DC power supply switching circuit to start working and controls the second interface power supply isolation control circuit to be conducted, and the USB interface power supply VUSB generates voltage from preset voltage at the moment. Because the first interface power isolation control circuit is still in a closed state at this time, the USB interface power VUSB only provides power for the OTG equipment, so that the functions of charging the base interface, supplying power to the OTG equipment by the USB interface and communicating downstream of the USB interface can be simultaneously realized at this time;
(5) When the USB interface is connected to an external power supply, the micro control unit MCU detects that the USB interface is connected to the external power supply through the USB interface power supply VUSB, controls the first interface power supply isolation control circuit to be in a conducting and on state, and controls the second interface power supply isolation control circuit and the third interface power supply isolation control circuit to be in an off state, so that the USB interface charging function can be realized;
(6) When the USB interface is connected to the uplink communication equipment, the MCU controls the first interface power supply isolation control circuit to be in a conducting and opening state, and controls the second interface power supply isolation control circuit and the third interface power supply isolation control circuit to be in a closing state, so that the USB interface charging and the USB interface uplink communication functions can be realized at the same time;
(7) When the USB interface charging and USB interface uplink communication function is realized according to (5) or (6), if the external power VIN is accessed through the base interface, the third interface power isolation control circuit is in a closed state at the moment, so that the USB interface charging and/or USB interface uplink communication function is still realized. Of course, at this time, the micro control unit MCU can control the connection and disconnection relationship between the first interface power isolation control circuit and the third interface power isolation control circuit according to the actual application requirement, and the charging of the base interface or the charging of the USB interface can be selected.
(8) When the OTG equipment is accessed only through the USB interface, the MCU monitors the low level of the ID signal in the USB interface, and then monitors that the USB interface is accessed to the OTG equipment, at the moment, the MCU controls the first interface power isolation control circuit to be closed, controls the first DC-DC power conversion circuit to start working, and controls the second interface power isolation control circuit to be conducted, so that the power supply to the OTG equipment through the USB interface and the downlink communication function of the USB interface are realized;
(9) When the USB interface is used for supplying power to the OTG equipment and realizing the downlink communication function of the USB interface according to the step (8), if the external power source VIN is accessed through the base interface, the MCU controls the third interface power isolation control circuit to be conducted after monitoring the access of the external power source VIN, and the downlink communication of the USB interface and the charging function of the base interface can be realized at the same time.
2. When the POS machine is in a shutdown state, the POS machine can be divided into the following cases:
(1) When the external power supply VIN is accessed only through the base interface, the pin connected with the third interface power supply isolation control circuit is defaulted to be low level under the shutdown state of the MCU, and the pin connected with the charging circuit is defaulted to be low level, so that the third interface power supply isolation control circuit is conducted, the charging circuit can work normally, and the charging function of the base interface can be realized at the moment;
(2) When the uplink communication equipment or the external power supply is connected only through the USB interface, the pin connected with the first interface power supply isolation control circuit is defaulted to be low level under the shutdown state of the MCU, and the pin connected with the charging circuit is defaulted to be low level, so that the first interface power supply isolation control circuit is conducted, the charging circuit can work normally, and the USB interface charging function can be realized at the moment;
(3) When the base interface and the USB interface are simultaneously connected with an external power supply, the charging function of the base interface or the USB interface can be realized according to the voltage of the connected power supply, namely, the charging current is provided by the power supply with relatively higher voltage.
Fig. 10 shows a flowchart of an interface management method according to an embodiment of the present disclosure, which is applicable to the interface management circuit, as shown in fig. 10, and includes the steps of:
judging whether the USB interface is in a connection state or not in a starting-up state;
when judging that the USB interface is in a connection state, judging whether the connection equipment is downlink communication OTG equipment or not;
when the base interface is judged to be connected with the power VIN, the micro control unit MCU controls the first interface power isolation control circuit to be closed, the third interface power isolation control circuit to be conducted, the charging function of the base interface is realized, and the downlink communication function of the USB interface is realized;
When the base interface is judged not to be connected with the power supply VIN, the micro control unit MCU controls the first interface power supply isolation control circuit and the second interface power supply isolation control circuit to be in a closed state to realize a base interface charging function and a USB interface uplink communication function;
when the USB interface is judged not to be in a connection state, judging whether the base interface is connected with the power supply VIN, when the base interface is judged to be connected with the power supply VIN, enabling the micro control unit MCU to control the first interface power supply isolation control circuit and the second interface power supply isolation control circuit to be closed, enabling the third interface power supply isolation control circuit to be opened and conducting, only realizing a base interface charging function, when the base interface is judged not to be connected with the power supply VIN, judging whether the USB interface is connected with the power supply VUSB, when the USB interface is judged to be connected with the power supply VUSB, enabling the micro control unit MCU to control the first interface power supply isolation control circuit to be in a conducting and on state, enabling the second interface power supply isolation control circuit and the third interface power supply isolation control circuit to be in an off state, only realizing a USB interface charging function, and when the USB interface is judged not to be connected with the power supply VUSB, ending the process.
As mentioned above, with the development of communication technology and the wide use of POS devices, users have increasingly demanded to use POS devices, for example, to charge a base of a POS device or to charge a USB, it is desirable that a POS device can be used as a charging device, and it is desirable that a POS device can use a USB uplink/downlink communication function while charging. However, in the prior art, the USB interface and the base interface belong to the same power network, so that the USB interface cannot synchronously realize the USB uplink communication function when the USB interface and the base interface are simultaneously connected to a power supply; in addition, when the base interface is used for charging, the USB interface cannot synchronously realize the functions of downlink power supply and communication. Accordingly, there is a need for an interface management scheme that can meet the above-mentioned various needs of users.
In view of the above, in this embodiment, an interface management method is proposed that enables control of the operation states of the interfaces by controlling the power isolation control circuits for the plurality of interfaces, so that the charging functions of the USB interface and the cradle interface and the charging and data transmission functions of the USB interface can be flexibly switched. The technical scheme is simple to realize and convenient to operate, and can meet different requirements of different users on interface use.
In the above embodiment, by monitoring the connection state of the USB interface and the access state of the base interface power supply VIN, the MCU circuit controls the working states of the first DC-DC power conversion circuit by means of turning on and off the first interface power supply isolation control circuit, the second interface power supply isolation control circuit, and the third interface power supply isolation control circuit, so as to achieve the working states required by the USB interface and the base interface.
The following are device embodiments of the present disclosure that may be used to perform method embodiments of the present disclosure.
Fig. 11 shows a block diagram of an interface management apparatus according to an embodiment of the present disclosure, which may be implemented as part or all of an electronic device by software, hardware, or a combination of both. As shown in fig. 11, the interface management apparatus includes:
a first judging module 1101 configured to judge whether the USB interface is in a connected state in a power-on state;
a second judging module 1102, configured to judge whether the connection device is a downlink communication OTG device when judging that the USB interface is in a connection state;
the third judging module 1103 is configured to, when the connecting device is judged to be a downlink communication OTG device, judge whether the base interface is connected to the power VIN, and when the base interface is judged to be connected to the power VIN, make the micro control unit MCU control the first interface power isolation control circuit to be turned off, the third interface power isolation control circuit to be turned on, so as to realize the base interface charging function and the USB interface downlink communication function, and when the base interface is judged not to be connected to the power VIN, make the micro control unit MCU control the first interface power isolation control circuit to be turned off, the first DC-DC power conversion circuit to start working, and the second interface power isolation control circuit to be turned on, so as to only realize the USB interface downlink power supply and downlink communication function;
A fourth judging module 1104, configured to, when it is judged that the connection device is not a downlink communication OTG device, judge whether the base interface is connected to the power VIN, and when it is judged that the base interface is connected to the power VIN, make the micro control unit MCU control the first interface power isolation control circuit and the second interface power isolation control circuit to be in a closed state, so as to implement a base interface charging function and a USB interface uplink communication function, and when it is judged that the base interface is not connected to the power VIN, make the micro control unit MCU control the first interface power isolation control circuit to be in a conductive and on state, and make the second interface power isolation control circuit and the third interface power isolation control circuit be in a closed state, so as to implement a USB interface charging and uplink communication function;
and a fifth judging module 1105 configured to judge whether the base interface is connected to the power VIN when the USB interface is judged not to be in the connected state, and to cause the micro control unit MCU to control the first interface power isolation control circuit and the second interface power isolation control circuit to be turned off when the base interface is judged to be connected to the power VIN, and to turn on the third interface power isolation control circuit to realize only the base interface charging function, and to judge whether the USB interface is connected to the power VUSB when the base interface is judged not to be connected to the power VIN, and to cause the micro control unit MCU to control the first interface power isolation control circuit to be in the on-state when the USB interface is judged to be connected to the power VUSB, and to cause the second interface power isolation control circuit and the third interface power isolation control circuit to be in the off-state to realize only the USB interface charging function, and to end when the USB interface is judged not to be connected to the power VUSB.
As mentioned above, with the development of communication technology and the wide use of POS devices, users have increasingly demanded to use POS devices, for example, to charge a base of a POS device or to charge a USB, it is desirable that a POS device can be used as a charging device, and it is desirable that a POS device can use a USB uplink/downlink communication function while charging. However, in the prior art, the USB interface and the base interface belong to the same power network, so that the USB interface cannot synchronously realize the USB uplink communication function when the USB interface and the base interface are simultaneously connected to a power supply; in addition, when the base interface is used for charging, the USB interface cannot synchronously realize the functions of downlink power supply and communication. Accordingly, there is a need for an interface management scheme that can meet the above-mentioned various needs of users.
In view of the above, in this embodiment, an interface management apparatus is proposed that realizes control of the operation state of an interface by control of a plurality of interface power isolation control circuits, so that the charging functions of a USB interface and a cradle interface and the charging and data transfer functions of the USB interface can be flexibly switched. The technical scheme is simple to realize and convenient to operate, and can meet different requirements of different users on interface use.
The present disclosure also discloses an electronic device, fig. 12 shows a block diagram of the electronic device according to an embodiment of the present disclosure, and as shown in fig. 12, the electronic device 1200 includes a memory 1201 and a processor 1202; wherein, the liquid crystal display device comprises a liquid crystal display device,
the memory 1201 is configured to store one or more computer instructions that are executed by the processor 1202 to perform the method steps described above.
Fig. 13 is a schematic diagram of a computer system suitable for use in implementing an interface management method according to an embodiment of the present disclosure.
As shown in fig. 13, the computer system 1300 includes a processing unit 1301 that can execute various processes in the above-described embodiments according to a program stored in a Read Only Memory (ROM) 1302 or a program loaded from a storage portion 1308 into a Random Access Memory (RAM) 1303. In the RAM1303, various programs and data necessary for the operation of the computer system 1300 are also stored. The processing unit 1301, the ROM1302, and the RAM1303 are connected to each other through a bus 1304. An input/output (I/O) interface 1305 is also connected to bus 1304.
The following components are connected to the I/O interface 1305: an input section 1306 including a keyboard, a mouse, and the like; an output portion 1307 including a Cathode Ray Tube (CRT), a Liquid Crystal Display (LCD), and the like, and a speaker, and the like; a storage portion 1308 including a hard disk or the like; and a communication section 1309 including a network interface card such as a LAN card, a modem, or the like. The communication section 1309 performs a communication process via a network such as the internet. The drive 1310 is also connected to the I/O interface 1305 as needed. Removable media 1311, such as magnetic disks, optical disks, magneto-optical disks, semiconductor memory, and the like, is installed as needed on drive 1310 so that a computer program read therefrom is installed as needed into storage portion 1308. The processing unit 1301 may be implemented as a processing unit such as CPU, GPU, TPU, FPGA, NPU.
In particular, according to embodiments of the present disclosure, the methods described above may be implemented as computer software programs. For example, embodiments of the present disclosure include a computer program product comprising a computer program tangibly embodied on a medium readable thereby, the computer program comprising program code for performing the method. In such an embodiment, the computer program can be downloaded and installed from a network via the communication portion 1309 and/or installed from the removable medium 1311.
The disclosed embodiments also disclose a computer program product comprising a computer program/instructions which, when executed by a processor, implement any of the method steps described above.
The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
The units or modules described in the embodiments of the present disclosure may be implemented by software, or may be implemented by hardware. The units or modules described may also be provided in a processor, the names of which in some cases do not constitute a limitation of the unit or module itself.
As another aspect, the embodiments of the present disclosure also provide a computer-readable storage medium, which may be a computer-readable storage medium included in the apparatus described in the above-described embodiment; or may be a computer-readable storage medium, alone, that is not assembled into a device. The computer-readable storage medium stores one or more programs for use by one or more processors in performing the methods described in the embodiments of the present disclosure.
The foregoing description is only of the preferred embodiments of the present disclosure and description of the principles of the technology being employed. It will be appreciated by those skilled in the art that the scope of the invention in the embodiments of the present disclosure is not limited to the specific combination of the above technical features, but encompasses other technical features formed by any combination of the above technical features or their equivalents without departing from the inventive concept. Such as the technical solution formed by mutually replacing the above-mentioned features and the technical features with similar functions (but not limited to) disclosed in the embodiments of the present disclosure.

Claims (10)

1. An interface management circuit, comprising: the micro control unit MCU, first DC-DC power supply conversion circuit, second DC-DC power supply conversion circuit, first interface power supply isolation control circuit, second interface power supply isolation control circuit, third interface power supply isolation control circuit, charging circuit, battery, USB interface and base interface, wherein:
the first DC-DC power supply conversion circuit is connected with the micro control unit MCU, the battery and the second interface power supply isolation control circuit and is used for realizing the conversion from the battery voltage to the preset voltage under the control of the micro control unit MCU;
the second DC-DC power supply conversion circuit is connected with the micro control unit MCU and the battery and is used for converting the battery voltage into the power supply voltage of the micro control unit MCU so as to supply power for the power supply of the micro control unit MCU;
the first interface power isolation control circuit is connected with the micro control unit MCU, the charging circuit and the USB interface and is used for realizing the switching-on and switching-off of a passage between a USB interface power supply VUSB and a charging power supply VCHG under the control of the micro control unit MCU;
the second interface power isolation control circuit is connected with the micro control unit MCU, the first DC-DC power conversion circuit and the USB interface and is used for realizing the disconnection of a passage between the USB interface power VUSB and a preset voltage power under the control of the micro control unit MCU;
The third interface power isolation control circuit is connected with the micro control unit MCU, the charging circuit and the base interface and is used for realizing the disconnection of a passage between the base interface power supply and the charging power supply VCHG under the control of the micro control unit MCU;
the charging circuit is connected with the micro control unit MCU, the battery, the first interface power supply isolation control circuit and the third interface power supply isolation control circuit and is used for realizing charging management of the charging power supply VCHG for the battery power supply Vbat under the control of the micro control unit MCU;
the USB interface is connected with the micro control unit MCU, the first interface power supply isolation control circuit and the second interface power supply isolation control circuit and is used for realizing the charge management of the charging power supply VCHG for the battery power supply Vbat under the control of the micro control unit MCU;
the base interface is connected with the third interface power isolation control circuit and is used for providing input power.
2. The circuit of claim 1, the first DC-DC power conversion circuit comprising: DC-DC chip U1, inductance L1, electric capacity C2, electric capacity C3, electric capacity C4, electric capacity C5, electric capacity C6, resistance R1, resistance R2, resistance R3 and resistance R4, wherein:
The capacitor C1, the capacitor C2 and the capacitor C3 are connected in parallel to form a parallel capacitor group;
the switch control SW pin of the DC-DC chip U1 is connected with one end of the inductor L1 and one end of the capacitor C4;
the other end of the inductor L1 is connected with one end of the parallel capacitor group, one end of the resistor R1 and a preset voltage power supply end, wherein the preset voltage power supply end is also connected with the second interface power supply isolation control circuit;
the other end of the capacitor C4 is connected with a boosting VBST pin of the DC-DC chip U1;
the other end of the resistor R1 is connected with a voltage feedback VFB pin of the DC-DC chip U1 and one end of the resistor R2;
the other end of the resistor R2 is grounded;
the power input VIN pin of the DC-DC chip U1 is connected with the battery power supply Vbat and one end of the capacitor C6;
the other end of the capacitor C6 is grounded;
an enable EN pin of the DC-DC chip U1 is connected with one end of a resistor R3, one end of a capacitor C5 and one end of a resistor R4;
the other end of the resistor R3 and the other end of the capacitor C5 are grounded;
the other end of the resistor R4 is connected with the MCU.
3. The circuit of claim 1, the second DC-DC power conversion circuit comprising: DC-DC chip U2, inductance L2, electric capacity C7, electric capacity C8, electric capacity C9, electric capacity C10, electric capacity C11, resistance R5, resistance R6, resistance R7, wherein:
The capacitor C7, the capacitor C8 and the capacitor C9 are connected in parallel to form a parallel capacitor group;
the switch control SW pin of the DC-DC chip U2 is connected with one end of the inductor L2 and one end of the capacitor C10;
the other end of the inductor L2 is connected with one end of the parallel capacitor group, one end of the resistor R5 and the MCU;
the other end of the capacitor C10 is connected with a boosting VBST pin of the DC-DC chip U2;
the other end of the resistor R5 is connected with the voltage feedback VFB pin of the DC-DC chip U2 and one end of the resistor R6;
the other end of the resistor R6 is grounded;
the power input VIN pin of the DC-DC chip U2 is connected with the battery power supply Vbat, one end of a resistor R7 and one end of a capacitor C11;
the other end of the resistor R7 is connected with an enable EN pin of the DC-DC chip U2;
the grounding GND pin of the DC-DC chip U2 is grounded.
4. The circuit of claim 1, the first interface power isolation control circuit comprising: the power supply path composed of a PMOS tube Q1 and a diode D1 is a PMOS switch control circuit composed of an NPN triode Q2, an NPN triode Q3, a capacitor C12, a resistor R8, a resistor R9, a resistor R10 and a resistor R11, wherein:
the drain electrode of the PMOS tube Q1 is connected with a charging power supply VCHG through a diode D1, the source electrode of the PMOS tube Q1 is connected with one end of a capacitor C12 and a USB interface power supply VUSB, and the grid electrode of the PMOS tube Q1 is connected with the other end of the capacitor C12 and one end of a resistor R8;
The other end of the resistor R8 is connected with one end of the resistor R9 and the collector of the NPN triode Q2;
the other end of the resistor R9 is connected with one end of a resistor R10 and a USB interface power supply VUSB;
the emitter of the NPN triode Q2 is grounded, and the base electrode of the NPN triode Q2 is connected with the other end of the resistor R10 and the collector electrode of the NPN triode Q3;
the emitter of the NPN triode Q3 is grounded, and the base electrode of the NPN triode Q3 is connected with the MCU through a resistor R11.
5. The circuit of claim 1, the second interface power isolation control circuit comprising: the power supply path composed of a PMOS tube Q4 and a diode D2 comprises a PMOS switch control circuit composed of an NPN triode Q5, an NPN triode Q6, a capacitor C13, a resistor R12, a resistor R13, a resistor R14 and a resistor R15, wherein:
the drain electrode of the PMOS tube Q4 is connected with a USB interface power supply VUSB through a diode D2, the source electrode of the PMOS tube Q4 is connected with one end of a capacitor C13 and a preset voltage power supply, and the grid electrode of the PMOS tube Q4 is connected with the other end of the capacitor C13 and one end of a resistor R12;
the other end of the resistor R12 is connected with one end of the resistor R13 and the collector of the NPN triode Q5;
the other end of the resistor R13 is connected with one end of the resistor R14 and a preset voltage power supply;
The emitter of the NPN triode Q5 is grounded, and the base electrode of the NPN triode Q5 is connected with the other end of the resistor R14 and the collector electrode of the NPN triode Q6;
the emitter of the NPN triode Q6 is grounded, and the base electrode of the NPN triode Q6 is connected with the MCU through a resistor R15.
6. The circuit of claim 1, the third interface power isolation control circuit comprising: the power supply path composed of a PMOS tube Q7 and a diode D3 comprises a PMOS switch control circuit composed of an NPN triode Q8, an NPN triode Q9, a capacitor C14, a resistor R16, a resistor R17, a resistor R18 and a resistor R19, wherein:
the drain electrode of the PMOS tube Q7 is connected with a charging power supply VCHG through a diode D3, the source electrode of the PMOS tube Q7 is connected with one end of a capacitor C14 and a base interface power supply, and the grid electrode of the PMOS tube Q7 is connected with the other end of the capacitor C14 and one end of a resistor R16;
the other end of the resistor R16 is connected with one end of the resistor R17 and the collector of the NPN triode Q8;
the other end of the resistor R17 is connected with one end of the resistor R18 and the base interface power supply;
the emitter of the NPN triode Q8 is grounded, and the base electrode of the NPN triode Q8 is connected with the other end of the resistor R18 and the collector electrode of the NPN triode Q9;
The emitter of the NPN triode Q9 is grounded, and the base electrode of the NPN triode Q9 is connected with the MCU through a resistor R19.
7. The circuit of claim 1, the charging circuit comprising: charging chip U3, inductance L3, diode D4, electric capacity C15, electric capacity C16, electric capacity C17, electric capacity C18, electric capacity C19, electric capacity C20, electric capacity C21, electric capacity C22, resistance R20, resistance R21, resistance R23 and NPN triode Q10, wherein:
the capacitor C15, the capacitor C16 and the capacitor C17 are connected in parallel to form a first parallel capacitor group, wherein one end of the first parallel capacitor group is grounded;
the capacitor C18 and the capacitor C19 are connected in parallel to form a second parallel capacitor group, wherein one end of the second parallel capacitor group is grounded;
the capacitor C20, the capacitor C21 and the capacitor C22 are connected in parallel to form a third parallel capacitor group, wherein one end of the third parallel capacitor group is grounded;
the power supply input VIN pin of the charging chip U3 is connected with the other end of the first parallel capacitor group and one end of the inductor L3;
the other end of the inductor L3 is connected with an external power supply VBS pin of the charging chip U3 through a diode D4, and is connected with the other end of the second parallel capacitor group and an inductance connection LX pin of the charging chip U3;
The power supply STAT pin of the charging chip U3 is connected with the micro control unit MCU;
the ground AGND pin of the charging chip U3 is grounded;
the battery BAT pin of the charging chip U3 is connected with the other end of the third parallel capacitor group and the battery power supply Vbat;
an enable EN pin of the charging chip U3 is connected with one end of a resistor R21 and a collector electrode of an NPN triode Q10, wherein the resistor R21 is a thermistor, and the other end of the resistor R21 is grounded;
the base electrode of the NPN triode Q10 is connected with one end of a resistor R22 and one end of a resistor R23, the emitter electrode of the NPN triode Q10 is grounded, the other end of the resistor R22 is grounded, and the other end of the resistor R23 is connected with the MCU;
the charging ICHG pin of the charging chip U3 is connected with one end of a resistor R20, and the other end of the resistor R20 is grounded.
8. The circuit of claim 1, the interface management circuit further comprising a battery status monitoring module, wherein the battery status monitoring module is coupled to the micro control unit MCU and a battery for monitoring a power status of the micro control unit MCU.
9. The circuit of claim 8, the battery condition monitoring module comprising a resistor R24 and a resistor R25, wherein:
One end of the resistor R24 and one end of the resistor R25 are connected with the MCU;
the other end of the resistor R24 is connected with a battery power supply Vbat, and the other end of the resistor R25 is grounded.
10. The circuit of claim 1, the interface management circuit further comprising a base power on status monitoring module vin_adc, wherein the base power on status monitoring module vin_adc is connected to the micro control unit MCU and a base interface power supply for monitoring a power status of the base interface power supply.
CN202210978374.5A 2022-08-16 2022-08-16 Interface management circuit, method, apparatus, device, storage medium, and program product Active CN115391258B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202210978374.5A CN115391258B (en) 2022-08-16 2022-08-16 Interface management circuit, method, apparatus, device, storage medium, and program product

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210978374.5A CN115391258B (en) 2022-08-16 2022-08-16 Interface management circuit, method, apparatus, device, storage medium, and program product

Publications (2)

Publication Number Publication Date
CN115391258A CN115391258A (en) 2022-11-25
CN115391258B true CN115391258B (en) 2023-05-02

Family

ID=84120250

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202210978374.5A Active CN115391258B (en) 2022-08-16 2022-08-16 Interface management circuit, method, apparatus, device, storage medium, and program product

Country Status (1)

Country Link
CN (1) CN115391258B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116054334B (en) * 2023-01-31 2023-12-08 云码智能(海南)科技有限公司 Power supply control circuit, method, electronic device, storage medium, and program product

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013196179A (en) * 2012-03-16 2013-09-30 Ricoh Co Ltd Charge control device and electronic apparatus
CN107632949A (en) * 2017-09-30 2018-01-26 广东欧珀移动通信有限公司 Data wire identification circuit, method and terminal
CN107643998A (en) * 2017-09-07 2018-01-30 上海移远通信技术股份有限公司 OTG and the difunctional system that charges are realized based on intelligent object
CN107658920A (en) * 2017-09-07 2018-02-02 上海移远通信技术股份有限公司 OTG and the difunctional system that charges are realized based on external charging
CN208571664U (en) * 2018-07-27 2019-03-01 漳州市利利普电子科技有限公司 A kind of charge control system of built-in terminal
CN213185551U (en) * 2020-08-17 2021-05-11 北京微智天工物联网技术有限公司 OTG and isolation circuit and mobile terminal charge

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107302251A (en) * 2017-08-11 2017-10-27 天津瑞发科半导体技术有限公司 A kind of intelligent movable power supplies and the method that usb data communication is carried out with it
TWI713280B (en) * 2020-05-20 2020-12-11 奇源科技有限公司 Charging power supply circuit for portable electronic device and portable electronic device

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013196179A (en) * 2012-03-16 2013-09-30 Ricoh Co Ltd Charge control device and electronic apparatus
CN107643998A (en) * 2017-09-07 2018-01-30 上海移远通信技术股份有限公司 OTG and the difunctional system that charges are realized based on intelligent object
CN107658920A (en) * 2017-09-07 2018-02-02 上海移远通信技术股份有限公司 OTG and the difunctional system that charges are realized based on external charging
CN107632949A (en) * 2017-09-30 2018-01-26 广东欧珀移动通信有限公司 Data wire identification circuit, method and terminal
CN208571664U (en) * 2018-07-27 2019-03-01 漳州市利利普电子科技有限公司 A kind of charge control system of built-in terminal
CN213185551U (en) * 2020-08-17 2021-05-11 北京微智天工物联网技术有限公司 OTG and isolation circuit and mobile terminal charge

Also Published As

Publication number Publication date
CN115391258A (en) 2022-11-25

Similar Documents

Publication Publication Date Title
CN106787055B (en) A kind of charging circuit, system, method and terminal
CN112202222B (en) Charger, charging control method and device
CN107465227B (en) Electronic equipment and control method thereof
CN104467109B (en) Method for supplying power to electronic equipment and electronic equipment
CN115391258B (en) Interface management circuit, method, apparatus, device, storage medium, and program product
CN105932733B (en) OTG power supply and its method of supplying power to, OTG equipment and mobile communication equipment
CN105576753A (en) Information processing method and electronic equipment
CN114513035B (en) Battery pack address allocation system, method and computer readable storage medium
CN101403943A (en) Intelligent computer power supply integration system
CN105468083A (en) Power supply interface
CN108181978B (en) Power control method and device for electronic equipment
CN102768570A (en) Electronic equipment
CN111030247A (en) Switching circuit for switching host mode and device mode of type C
CN101626201B (en) Switch power supply circuit
CN211790827U (en) Power supply circuit and power supply device
US9831698B2 (en) Mobile power supply terminal and power supply method thereof
CN201298200Y (en) Power supply integrated system of intelligent computer
CN101403941A (en) Intelligent computer uninterruptable power supply method
CN112803525A (en) Electronic device and charging control method thereof
CN103095929B (en) Method and system capable of preventing terminal from restarting repeatedly and mobile terminal using the same
CN213182728U (en) Uninterrupted power interface circuit
CN217821586U (en) USB switching circuit and USB switching device
CN114069768B (en) Charging circuit, charging control method and device and electronic equipment
CN219204146U (en) Dual-battery management circuit and electronic equipment
CN215987295U (en) Interface expansion device and interface expansion equipment

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant