CN115378887B

CN115378887B - TT service switching device of time-triggered Ethernet switch

Info

Publication number: CN115378887B
Application number: CN202210783860.1A
Authority: CN
Inventors: 潘伟涛; 高璐; 邱智亮; 黄进建
Original assignee: Xidian University
Current assignee: Xidian University
Priority date: 2022-07-05
Filing date: 2022-07-05
Publication date: 2024-01-23
Anticipated expiration: 2042-07-05
Also published as: CN115378887A

Abstract

The invention relates to a TT service switching device of a time triggered Ethernet switch, which comprises the steps of preemptively receiving TT frames supporting high priority, preemptively receiving TT frames supporting low priority, designing a virtual multicast port to convert multicast problems into unicast problems, designing a scheduler for completing TT frame scheduling according to a scheduling table by adopting a registration and table look-up mode, enabling addition or deletion of a certain service stream not to influence other service streams, optimizing and designing a single-frame storage TT plane for buffer areas of an input side and an output side, providing differentiated services for TT streams with different time delay requirements, designating that the sending delay of the TT streams not influence other TT streams, thereby reducing the constraint conditions required to be additionally added during scheduling planning, reducing the forwarding relevance of scheduling planning and switching hardware, supporting multiple TT service forwarding behaviors and guaranteeing the reliable transmission of the TT service.

Description

TT service switching device of time-triggered Ethernet switch

Technical Field

The invention belongs to the technical field of communication, and relates to a TT service switching device of a time-triggered Ethernet switch.

Background

With the development of information technology, electronic devices and systems in the fields of industry, aviation, etc. place more importance on the real-time performance, safety and certainty of tasks, and conventional ethernet cannot meet the requirements, so time triggered ethernet (Time Triggered Eth-internet, TTE) has been developed. By planning TT service in advance, equipment in the network is guaranteed to provide deterministic guarantee for TT service, and collision between TT service and other services is avoided.

In the existing TTE switch, the forwarding of TT frames mainly comprises the following modes:

the first is a cut-through forwarding scheme. In 2006, a TTE Switch proposed by a Time-Triggered Ethernet (TTE) Switch adopts a through forwarding mode, ET service adopts a store forwarding mode, and when ET service collides with TT service, the ET service is preempted by the TT service and then is continuously retransmitted. However, this forwarding method needs to avoid collision of TT services by using a communication protocol, and since TT services are not buffered, when two or more TT frames arrive at the same time, the low-priority TT frames are discarded.

The second is a store-and-forward scheme. In 2020, dual-Plane Switch Architecture for Time-Triggered Ethernet proposes a biplane switching architecture for handling ET traffic and TT traffic separately. The output port of the TT service transmits TT frames according to a transmission schedule, and the buffer memory of the output side is increased. However, the technical scheme has the following defects:

(1) Since TT frames are not cached at the input side, the input side TT collision dependency schedule is avoided;

(2) The buffer area at the output side can only finish single-frame buffer, and has insufficient flexibility for complex scheduling;

(3) The TT receiving window only allows receiving a single TT frame, and for TT service needing slicing, the TT receiving window depends on scheduling coordination of a terminal system;

(4) When a multicast frame needs to be sent, the prior art scheme needs to wait for all destination output ports of the multicast frame to be idle for scheduling, which may cause the multicast frame to miss a sending time point;

(5) Additional constraints need to be added to avoid collisions when scheduling a plan, including but not limited to: (1) the condition that a plurality of input ports receive signals to be sent to the same output port at the same moment is avoided; (2) and when the output port is transmitting the TT frame, the input port receives a new TT frame which needs to be transmitted to the output port. (3) The sending sequence of TT frames of the output ports is not inconsistent with the sequence of TT frames entering the TT plane. When the service planning in the network is complex and the traffic is large, the additional constraint condition may cause the generation of the scheduling table to fail.

(6) The scheduling planning flexibility is poor, when a TT service is wanted to be added in the network, a time period that the equipment on the path is idle needs to be found, and if the time period is not found, all the services need to be planned again.

In the feasibility scheme of the TTE switch, the TT service reliability and deterministic transmission problem are especially important. In the above 2 schemes, the practical requirements of the TTE switch cannot be well met in the aspects of independence, practical feasibility and cost overhead of the system.

Disclosure of Invention

In order to solve the problems in the prior art, the invention provides a TT service switching device of a time-triggered Ethernet switch. The technical problems to be solved by the invention are realized by the following technical scheme:

the embodiment of the invention provides a TT service switching device of a time-triggered Ethernet switch, which comprises the following components:

the overall control module is used for initializing after detecting that the TT service switching plane of the time-triggered Ethernet switch is electrified, and controlling other modules to enter a working state after waiting for clock synchronization;

the receiving schedule module is used for sending the receiving schedule to the input control module according to the system time according to the receiving schedule;

the transmission schedule module is used for transmitting the transmission schedule to the output control module according to the system time according to the transmission schedule;

the input control module is used for receiving legal TT frames according to the receiving schedule sent by the receiving schedule module and storing the legal TT frames into an input buffer area, wherein the input control module corresponds to the ports one by one;

the full interconnection exchange control module is used for completing the connection between the input control module and the output control module and sending the TT frames cached in the input cache area to the corresponding output control module;

The output control module is used for selecting a TT frame to be received from the data channels of each input control module, calculating the maximum frame length which can be received according to the size of an output buffer area, storing the received TT frame into the output buffer area, storing the position of the TT frame in the output buffer area, acquiring transmission information from the transmission schedule table stored in the transmission schedule information FIFO when the local direct approach transmission time exists, and carrying out transmission schedule searching in the output buffer area; the output buffer area adopts SRAM to realize the slicing buffer area, and the buffer area is indexed by the buffer descriptor; wherein, the output control module includes: a unicast output control module and a multicast output control module;

and the unicast and multicast output control module is used for accessing the TT buffer area according to the transmission schedule transmitted by the transmission schedule module, and selecting and outputting the output data of the unicast and multicast output control module, or transmitting the TT frame at a specified transmission time point.

In one embodiment of the present invention,

the receiving schedule module is further used for performing a table reading operation when the receiving schedule information FIFO is detected to be not full;

The receiving schedule module is further configured to sequentially read each entry in the receiving schedule primary table, wherein the receiving schedule primary table is read from an entry with a starting address of 0, and sequentially access each receiving schedule primary table according to a linked list next-hop address in each entry;

the receiving schedule module is further configured to calculate a hash value for a key value of a first TT ID in each entry in the receiving schedule primary table, and access each entry in the receiving schedule secondary table respectively with the hash value;

the receiving schedule module is further configured to check whether a second TT ID in an entry accessed by the receiving schedule secondary table is consistent with the first TT ID in an entry of the receiving schedule primary table;

if the second TT ID is consistent with the first TT ID and the admission port and the sending port are effective, the inquiry is correct, and the receiving schedule module is further used for splicing the table entry in the receiving schedule secondary table corresponding to the second TT ID and the table entry in the receiving schedule primary table corresponding to the first TT ID to obtain a spliced table;

if the second TT ID is consistent with the first TT ID and the access port and the sending port are invalid, searching fails;

If the second TT ID is inconsistent with the first TT ID and the linked list effective field in the receiving schedule primary table is effective, the receiving schedule module is further used for continuing indexing by taking the next hop as an address;

if the second TT ID is inconsistent with the first TT ID and the linked list valid field in the receiving scheduling primary table is invalid, searching fails;

the receiving schedule module is further configured to send the splicing table to the input control module.

In one embodiment of the present invention,

the sending schedule module is further used for performing a table reading operation when the sending schedule information FIFO is detected to be not full;

the transmission schedule module is further configured to read the transmission schedule from a table entry with a starting address of 0, and sequentially access the table entries of the transmission schedule according to a next-hop address corresponding to each table entry in the transmission schedule;

and the transmission schedule module is further used for transmitting the transmission schedule to each output control module after the search is completed.

In one embodiment of the present invention,

the input control module is further used for detecting whether a port corresponding to the input control module is one of entry admission ports of the receiving schedule;

If yes, the input control module is further configured to receive an entry of the receiving schedule table, and store the entry in a receiving schedule information FIFO;

the input control module is further configured to read the receiving schedule information from the receiving schedule information FIFO according to the system time, and generate a receiving window according to a receiving time point and a receiving window length; wherein, each time the receive window counter is reset, a receive statistics pulse is generated, the receive statistics pulse indicates that a new TT frame can be received again, and each time a TT frame is received, a pulse is consumed;

the input control module is further used for determining whether to receive the TT frame according to whether the receiving window is opened or not when the TT frame arrives;

if the TT frame falls in the receiving window, the input control module is further used for caching the TT frame;

the input control module is also used for detecting whether the TT frame receives errors or not;

if the error is received, the input control module is further configured to return the write address of the input buffer to the initial position of the error frame; if the receiving is correct, writing the receiving scheduling information corresponding to the TT frame into the receiving scheduling information FIFO;

the input control module is further configured to take out scheduling information of a next frame from the received scheduling information FIFO, send the TT frame and the scheduling information of the next frame to a data bus, and monitor whether a feedback signal exists in a target output control module on a control channel;

And if the feedback signal is received, the input control module is further used for continuously moving the next TT frame.

In one embodiment of the present invention,

the output control module is further used for determining TT frames to be transmitted from TT frames with TT frame lengths meeting preset frame lengths by using a priority encoder when TT frames which are not being transmitted are not available;

the output control module is further configured to, if there are TT frames being transmitted and there are a plurality of input channels corresponding to the input control modules for transmission, obtain, from each application transmission time, a target input channel corresponding to a target input control module that is less than the transmission time of the TT frame being transmitted, suspend reception of the current TT frame, and receive a new TT frame meeting the requirements;

the output control module is further configured to suspend receiving the current TT frame if a new TT frame satisfies a transmission condition and a transmission time is closer to the current time than a transmission time of the current TT frame in a process of receiving the TT frame, suspend a receiving state of the current TT frame, complete suspension of the receiving state by adopting a structure of a last-in-first-out, and start receiving more urgent TT frames;

and the output control module is further used for firstly checking whether the TT frame is suspended after one TT frame is transmitted, and if so, preferentially transmitting the suspended TT frame.

In one embodiment of the present invention,

the output control module is further configured to use a receiving time point of the TT frame and a splice value of the TT ID as an identifier, obtain hash values by using two different hash functions, and index a first registry and a second registry with the two hash values respectively to obtain a first table entry and a second table entry;

the output control module is further configured to write the registration information into the first table entry if the first table entry and the second table entry are both empty;

the output control module is further configured to check whether an entry corresponding to the hash value is locked if the first entry or the second entry has the current registration value;

the output control module is further configured to, if not locked, write original information in the entry into a registration failure FIFO, and write the current registration value into the entry;

the output control module is further configured to, if locked, write the current registration value into an unlock waiting FIFO by the registry control module;

the output control module is further configured to write the registration value into a registration failure FIFO if the output control module is locked and the waiting unlock FIFO is full;

The output control module is further configured to, if only one of the first entry and the second entry is empty and the empty entry and the current registration information do not match, write the current registration value into the empty entry by the registry control module;

and the output control module is further configured to, if the first table entry and the second table entry are both non-empty and occupied by other registration information, determine that the registration fails, and write the registration value into a registration failure FIFO.

In one embodiment of the present invention,

and the output control module is further configured to feed back a failure in searching if the first entry and the second entry have no current registration value.

The output control module is further configured to determine whether logout is required according to whether the current output ports are all the output ports if the first entry or the second entry has the current registration value;

The output control module is further used for writing an invalid table entry into the searched table entry by the registry control module if the registry control module needs to be logged off, and feeding back a searching result;

and the output control module is also used for updating the output port of the table entry to be the remaining ports to be transmitted if the log-out is not needed, locking the table entry once and feeding back the search result.

In one embodiment of the present invention,

the output control module is further configured to store the buffer descriptor in an idle slice FIFO in an initial state;

the output control module is further configured to obtain the buffer descriptor from the idle fragment FIFO when there is a TT frame to be stored;

and the output control module is further used for rewriting the buffer descriptor into the idle fragment FIFO if the registration fails, the TT frame is sent successfully or buffer release is needed.

In one embodiment of the present invention,

the unicast and multicast output control module is further configured to obtain a buffer descriptor corresponding to the output TT frame from the TT frame transmission FIFO;

the unicast and multicast output control module is further configured to extract the output TT frame from the tile buffer area, and send the output TT frame at a specified sending time point;

And the unicast and multicast output control module is further configured to release the slicing buffer area of the output TT frame for drinking after the transmission is completed, or unlock the entry corresponding to the output TT frame in the registry once.

Compared with the prior art, the invention has the beneficial effects that:

the invention designs preemptive receiving TT frames supporting high priority and preempting TT frames with low priority in the TT service switching device of the time-triggered Ethernet switch, designs a virtual multicast port to convert multicast problems into unicast problems, designs a scheduler for completing TT frame scheduling according to a scheduling table by adopting a registration and table look-up mode, ensures that the addition or deletion of one service stream does not affect other service streams, optimally designs an input side buffer memory area and an output side buffer memory area to improve a single frame storage TT plane, provides differentiated services for TT streams with different time delay requirements, and specifies that the transmission delay of the TT stream does not affect other TT streams, thereby reducing the constraint conditions required to be additionally added during scheduling planning, reducing the forwarding relevance of scheduling planning and switching hardware, supporting the forwarding behavior of various TT services and guaranteeing the reliable transmission of the TT service.

Other aspects and features of the present invention will become apparent from the following detailed description, which refers to the accompanying drawings. It is to be understood that the drawings are designed solely for purposes of illustration and not as a definition of the limits of the invention, for which reference should be made to the appended claims. It should be further understood that the drawings are not necessarily drawn to scale and that, unless otherwise indicated, they are merely intended to conceptually illustrate the structures and procedures described herein.

Drawings

Fig. 1 is a schematic structural diagram of a TT service switching device of a time triggered ethernet switch according to an embodiment of the present invention;

fig. 2 is a schematic structural diagram of a receiving schedule module according to an embodiment of the present invention;

fig. 3 is a schematic structural diagram of a transmission schedule module according to an embodiment of the present invention;

fig. 4 is a schematic structural diagram of an input control module according to an embodiment of the present invention;

fig. 5 is a waveform diagram of a receiving table entry module according to an embodiment of the present invention;

fig. 6 is a waveform diagram of a receiving table entry module according to an embodiment of the present invention;

FIG. 7 is a waveform diagram of a read table entry module according to an embodiment of the present invention;

fig. 8 is a waveform diagram of a received information control module according to an embodiment of the present invention;

fig. 9 is a waveform diagram of a receiving window controlled by a receiving information control module according to an embodiment of the present invention;

fig. 10 is a waveform diagram of a frame reception control module according to an embodiment of the present invention;

fig. 11 is a waveform diagram of a receiving and scheduling control module according to an embodiment of the present invention;

fig. 12 is a schematic structural diagram of an output control module according to an embodiment of the present invention;

FIG. 13 is a waveform diagram of a receiving arbitration control module according to an embodiment of the present invention;

Fig. 14 is a schematic diagram of a special-shaped CIOQ two-stage switching structure according to an embodiment of the present invention;

fig. 15 is a waveform diagram of a forwarding and receiving control module according to an embodiment of the present invention;

FIG. 16 is a waveform diagram of a registry control module registration provided by an embodiment of the present invention;

FIG. 17 is a waveform diagram of a registry control module sending a scheduling lookup provided by an embodiment of the present invention;

fig. 18 is a flowchart of a time triggered ethernet switch TT service switching method according to an embodiment of the present invention;

fig. 19 is a waveform diagram of a transmission scheduling module according to an embodiment of the present invention;

fig. 20 is a flowchart of a time triggered ethernet switch TT service switching method according to an embodiment of the present invention;

FIG. 21 is a waveform diagram of a buffer release module according to an embodiment of the present invention;

FIG. 22 is a waveform diagram of an idle burst FIFO according to an embodiment of the present invention;

fig. 23 is a waveform diagram of a transmission control module according to an embodiment of the present invention;

fig. 24 is a waveform diagram of preemptive transmission of a 1-port receiving and scheduling control module according to an embodiment of the present invention;

fig. 25 is a waveform diagram of a 2-port receiving and scheduling control module being preempted according to an embodiment of the present invention;

FIG. 26 is a waveform diagram of a receiving arbitration control module according to an embodiment of the present invention when preemption occurs;

Fig. 27 is a waveform diagram of a forwarding and receiving control module according to an embodiment of the present invention when preemption occurs;

fig. 28 is a workflow of a TT service switching device of a time triggered ethernet switch according to an embodiment of the present invention;

fig. 29 is a schematic diagram of forwarding behavior of a TT frame supportable by a TT service switching device of a time triggered ethernet switch according to an embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to specific examples, but embodiments of the present invention are not limited thereto.

The TT service switching device of the time-triggered Ethernet switch is realized through a programmable logic chip FPGA.

Referring to fig. 1, fig. 1 is a schematic structural diagram of a TT service switching device of a time triggered ethernet switch according to an embodiment of the present invention. The invention provides a TT service switching device of a time-triggered Ethernet switch, which comprises:

the general control module 1 is used for initializing after detecting that the time triggers the TT service switching plane of the Ethernet switch to be electrified, and controlling other modules to enter a working state after waiting for clock synchronization;

specifically, the overall control module is used for controlling the working flow of the TT service plane, initializing the system after powering on, and entering the working state after waiting for clock synchronization. If the system is out of step or the system is reset, the reset operation is performed.

The receiving schedule module 2 is used for sending the receiving schedule to the input control module according to the system time according to the receiving schedule;

in one implementation, the receive schedule module is further configured to perform a read operation when the receive schedule information FIFO is detected to be not full;

the receiving schedule module is further used for sequentially reading all the table items in the receiving schedule primary table, wherein the receiving schedule primary table is read from the table item with the initial address of 0, and each receiving schedule primary table is sequentially accessed according to the next-hop address of the linked list in each table item; the primary schedule format may be as shown in table 1:

table 1 schedule primary table format

Reception time	Transmission time	TT ID	Linked list next hop
				64bit	64bit	16bit	16bit

Fig. 2 is a schematic structural diagram of a receiving schedule module according to an embodiment of the present invention, where in an embodiment, a receiving schedule primary table may be accessed by a reading primary table module in fig. 2, and an initial address is 0, and accesses are sequentially performed according to a linked list next hop address.

The receiving schedule module is further used for calculating a hash value for a key value of a first TT ID in each table item in the receiving schedule primary table, and accessing each table item in the receiving schedule secondary table respectively by the hash value;

In one embodiment, the hash value may be calculated by the read secondary table module in fig. 2 with the first TT ID as a key value, and the receive schedule secondary table may be accessed with the hash value, where the receive schedule secondary table format may be as shown in table 2:

table 2 receiving schedule two-level table

TT ID

Admission port

Transmitting port

Receiving window length

Limiting frame length

Linked list efficiency

Next hop

16bit

32bit

16bit

11bit

1bit

12bit

The receiving schedule module is further used for checking whether the second TT ID in the table entry accessed by the receiving schedule secondary table is consistent with the first TT ID in the table entry of the receiving schedule primary table;

if the second TT ID is consistent with the first TT ID, and the admission port and the sending port are effective, the inquiry is correct, and the receiving schedule module is also used for splicing the table entry in the receiving schedule secondary table corresponding to the second TT ID and the table entry in the receiving schedule primary table corresponding to the first TT ID to obtain a spliced table;

if the second TT ID is consistent with the first TT ID and the access port and the sending port are invalid, the searching fails;

if the second TT ID is inconsistent with the first TT ID and the linked list effective field in the receiving scheduling primary table is effective, the receiving scheduling table module is also used for continuing indexing by taking the next hop as an address;

In one embodiment, it may be checked by the transmit table entry module in FIG. 2 whether the second TTID is consistent with the first TTID. If the access port and the sending port are consistent, the access port and the sending port are effective, the query is correct, and the table items are spliced; if the access port is consistent with the sending port, and the access port and the sending port are invalid, the searching fails; if the two addresses are inconsistent, and the effective fields of the linked list are effective, continuing to index by taking the next hop as the address; if the search is inconsistent and the linked list valid field is invalid, the search fails.

The receiving schedule module is also used for sending the splicing table to the input control module;

in one embodiment, the splice table may be sent to the input control module by the send table entry module in FIG. 2.

In one implementation, if the receive schedule is in a single level table format, a two level table may be generated by:

(1) establishing a conflict-free set and a conflict-free set: traversing a single-stage receiving schedule, calculating a hash value of the TTID, and if the hash value does not exist in the conflict-free set, placing the table item in the conflict-free set; otherwise, the entry is placed in the conflict set.

(2) Traversing the single-stage receiving schedule again, placing the single-stage receiving schedule at the corresponding address according to the traversing sequence in the first-stage schedule, continuously increasing the next hop of the linked list, and jumping back to the starting address for the last table item.

(3) For the secondary table, if the table item is in a conflict-free set, placing the hash value of the TTID at a corresponding position of the secondary table; otherwise, the entry is skipped temporarily. All entries of the collision-free set have been written to the secondary table at this point.

(4) Traversing the secondary table, obtaining unfilled addresses of all the secondary tables, and recording in sequence.

(5) Traversing the single-stage receiving schedule again, for the list item with the conflict set, acquiring an address from the unfilled address of the secondary list, filling the secondary list content of the list item at the address, and setting the linked list as invalid. Calculating the hash value of the TTID to access the secondary table, and if the next hop is invalid, modifying the hash value into the recorded secondary table address; otherwise, continuing indexing with the next jump until invalid, and modifying the second-level table address into the second-level table address of the current record again.

A transmission schedule module 6, configured to transmit the transmission schedule to the output control module according to the system time according to the transmission schedule; wherein, the transmission schedule is a single-stage table lookup, and the transmission schedule format is shown in table 3:

table 3 transmit schedule format

Transmission time

Reception time

TT ID

Transmitting port

Transmission window length

Multicast indication

Next hop

64bit

16bit

32bit

14bit

1bit

16bit

Specific:

the sending schedule module is also used for reading a table when detecting that the sending schedule information FIFO is not full;

Fig. 3 is a schematic structural diagram of a transmission schedule module according to an embodiment of the present invention, and in an embodiment, a table reading operation may be performed by using the table reading module shown in fig. 3.

The sending schedule module is further used for reading the sending schedule from the table item with the initial address of 0, and sequentially accessing the table items of each sending schedule according to the next hop address corresponding to each table item in the sending schedule;

and the sending schedule module is also used for sending the sending schedule to each output control module after the searching is completed.

Specifically, the reception schedule may be distributed to each output control module through the transmission entry module shown in fig. 3.

The input control module 3 is used for receiving legal TT frames according to the receiving schedule sent by the receiving schedule module and storing the legal TT frames in the input buffer area, wherein the input control module corresponds to the ports one by one;

specifically, the input control modules are in one-to-one correspondence with the ports, and the legal TT frames are received according to the receiving schedule sent by the receiving schedule module and stored in the input buffer area. And forwarding the TT frame to a corresponding output buffer area according to the state of the output control module of the target output port.

Because the receiving schedule is distributed to the input control module in a broadcasting mode, the input control module is also used for detecting whether the port corresponding to the input control module is one of entry admission ports of the receiving schedule;

Specifically, fig. 4 is a schematic structural diagram of an input control module according to an embodiment of the present invention, where whether a corresponding port is received may be determined by a receiving table entry module in fig. 4 according to whether the corresponding port is one of the receiving schedule table entry access ports, and fig. 5 and fig. 6 are waveform diagrams of the receiving table entry module according to an embodiment of the present invention.

If yes, the input control module is also used for receiving the table items of the receiving schedule table and storing the table items into a receiving schedule information FIFO; the schedule information FIFO is shown in table 4:

table 4 receive scheduling information FIFO

Limiting frame length	Forwarding port	Receiving window length	TT ID	Transmission time	Reception time
						11	32	16	16	64	64

The input control module is also used for reading the receiving scheduling information from the receiving scheduling list information FIFO according to the system time and generating a receiving window according to the receiving time point and the receiving window length; wherein, each time the receiving window counter is reset, a receiving statistical pulse is generated, the receiving statistical pulse indicates that a new TT frame can be received again, and each time the TT frame is received, a pulse is consumed;

specifically, the receiving schedule information can be read from the receiving schedule information FIFO by the reading table entry module in fig. 4 according to the system time, and the receiving information control module generates a receiving window according to the receiving time point and the receiving window length. In order to avoid that a plurality of receiving windows are adhered due to the fact that the receiving windows receive the same TTID frame reset, a receiving statistics pulse needs to be generated each time a receiving window counter is reset, wherein, FIG. 7 is a waveform diagram of a reading table entry module provided by an embodiment of the present invention, FIG. 8 is a waveform diagram of a receiving information control module provided by an embodiment of the present invention starting to work, and FIG. 9 is a waveform diagram of a receiving information control module provided by an embodiment of the present invention controlling the receiving windows.

The input control module is also used for determining whether to receive the TT frame according to whether the receiving window is opened or not when the TT frame arrives;

if the TT frame falls in the receiving window, the TT frame is input into the control module and is also used for caching the TT frame;

if the error is received, the input control module is also used for returning the write address of the input buffer area to the initial position of the error frame; if the receiving is correct, writing the receiving scheduling information corresponding to the TT frame into a receiving scheduling information FIFO;

specifically, when the TT frame arrives, the frame receiving control module in fig. 4 may determine whether to receive the TT frame according to whether the receiving window is opened. If the TT frame falls in the receiving window, caching the data, extracting data information and checking; if the check is wrong, the receiving window is closed in the receiving process, and the TT frames exceeding the quantity required by the dispatching or the receiving buffer area overflows, the receiving error is judged. If the error is received, the frame receiving control module returns the writing address of the input buffer area to the initial position of the error frame; if the reception is correct, the receiving schedule information such as the TT frame length is written into the receiving schedule FIFO, and fig. 10 is a waveform diagram of the frame receiving control module provided in the embodiment of the invention, where the receiving schedule FIFO is shown in table 5:

TABLE 5 receive schedule FIFO

Limiting frame length	Forwarding port	TT ID	Transmission time	Reception time
					11	32	16	64	64

The input control module is also used for taking out the scheduling information of the next frame from the receiving scheduling information FIFO, sending the scheduling information of the TT frame and the next frame to the data bus, and monitoring whether the target output control module on the control channel has a feedback signal or not;

if the feedback signal is received, the control module is input and is further used for continuously moving the next TT frame.

Specifically, the receiving schedule control module in fig. 4 may take the schedule information of the next frame from the receiving schedule FIFO, send the TT frame and the schedule information to the data bus, and monitor whether the target output control module on the control channel has a feedback signal. If a feedback signal is received, the next TT frame is continuously moved, where fig. 11 is a waveform diagram of a receiving and scheduling control module provided in an embodiment of the present invention.

Further, as shown in fig. 4, the input control modules are in one-to-one correspondence with the ports, and receive legal TT frames according to the receiving schedule sent by the receiving schedule module and store the legal TT frames in the input buffer. And forwarding the TT frame to a corresponding output buffer area according to the state of the output control module of the target output port. The receiving list item module acquires a receiving schedule list, restores the receiving schedule list and stores the receiving schedule list into a receiving schedule information FIFO; the reading table entry module finishes reading the receiving scheduling information FIFO according to the system time; the receiving information control module controls the opening and closing of a receiving window and generates a receiving statistical pulse to indicate the number of TT frames which can be received by the receiving window; the frame receiving control module stores TT frames into an input buffer area, generates TT frame descriptors, stores the TT frame descriptors into a receiving scheduling FIFO, and completes bit width conversion, receiving verification and error verification of the TT frames; the receiving scheduling control module acquires the TT frame descriptor from the receiving scheduling FIFO, acquires the TT frame from the input buffer and sends the TT frame to the output control module of the target output port.

The full interconnection exchange control module 4 is used for completing connection between the input control module and the output control module and sending TT frames cached in the input cache area to the corresponding output control module;

and the full interconnection exchange control module is used for completing the connection between the input control module and the output control module and controlling the data and information interaction between the input control module and the output control module through the data channel and the control channel.

The output control module 5 is configured to select a TT frame to be received from the data channels of each input control module, calculate a maximum frame length that can be received according to the size of the output buffer, store the received TT frame in the output buffer, store the position of the TT frame in the output buffer, obtain transmission information from the transmission schedule stored in the transmission schedule information FIFO when the local is directly adjacent to the transmission time, and perform transmission schedule search in the output buffer; the output buffer area adopts SRAM to realize the slicing buffer area, and the buffer area is indexed by the buffer descriptor; wherein, the output control module includes: a unicast output control module and a multicast output control module; the unicast output control modules are in one-to-one correspondence with the ports.

Specifically, fig. 12 is a schematic structural diagram of an output control module according to an embodiment of the present invention, where TT frames are sent to an output control module of a corresponding port through a full-interconnection switching module, a receiving arbitration control module in the output control module selects one TT frame to be received this time from data channels of each input control module, and calculates a maximum frame length that can be received according to a size of an output buffer zone, where fig. 13 is a waveform diagram of the receiving arbitration control module according to an embodiment of the present invention.

The store-and-forward device in the present disclosure adopts a heterogeneous CIOQ two-stage switching structure as shown in fig. 14, which is based on the Crossbar structure of CIOQ, and adds a virtual multicast port. Multicast frames are sent to the virtual multicast ports, which are forwarded to all ports.

Further, the output control module is further configured to determine, when there is no TT frame being transmitted, a TT frame to be transmitted from TT frames whose TT frame length satisfies a preset frame length using a priority encoder;

specifically, if there is no TT frame being transmitted, the receiving arbitration control module in fig. 12 does not require the transmission time, and only requires the TT frame length. However, there may be a plurality of TT frames meeting the requirements, and the forwarding and receiving control module determines the TT frames to be transmitted using a priority encoder, where fig. 15 is a waveform diagram of the forwarding and receiving control module according to an embodiment of the present invention.

The output control module is also used for suspending the receiving of the current frame and receiving a new frame meeting the requirements if the TT frame being transmitted exists and a plurality of input channel applications corresponding to the input control modules are transmitted, and acquiring a target input channel corresponding to a target input control module which is smaller than the transmitting time of the TT frame being transmitted currently from the transmitting time of each application;

specifically, if there are a TT frame being transmitted and there are multiple input channels for transmission, the receiving arbitration module in fig. 12 may compare the time of the application transmission in parallel, and find the time less than the time of the transmission of the current transmission frame.

The output control module is also used for suspending the receiving of the current TT frame when a new TT frame meets the transmission condition and the transmission time is closer to the current time than the transmission time of the current TT frame in the receiving process of the TT frame, suspending the receiving state of the current TT frame, completing the suspension of the receiving state by adopting a structure of last-in first-out, and starting to receive more urgent TT frames;

and the output control module is also used for firstly checking whether a suspended TT frame exists after one TT frame finishes transmission, and if so, preferentially transmitting the suspended TT frame.

Specifically, in the receiving process, a new TT frame meets the sending condition and is more urgent than the current TT frame, the forwarding and receiving control module in fig. 12 suspends the receiving of the current TT frame, suspends the receiving state of the current frame, and adopts a last-in-first-out (LIFO) structure to complete the suspension of the receiving state, so as to start receiving more urgent frames. When one TT frame finishes transmitting, the forwarding and receiving control module firstly checks whether the TT frame is suspended, and if so, the TT frame is preferentially transmitted.

Further, as shown in fig. 12, after the TT frame is cached in the output buffer, the registry control module performs a "registration" operation, records the position of the TT frame in the buffer, and is used for indexing the TT frame during transmission scheduling, where fig. 16 is a waveform diagram of registration of the registry control module provided by the embodiment of the present invention, and fig. 17 is a waveform diagram of transmission scheduling lookup of the registry control module provided by the embodiment of the present invention, specifically:

the output control module is further used for using a receiving time point of the TT frame and a splicing value of the TT ID as identifiers, using two different hash functions to obtain hash values, and respectively indexing a first registry and a second registry by using the two hash values to obtain a first table item and a second table item; wherein the registry is shown in Table 6:

Table 6 registry (231X 512)

Reception time	TT ID	Transmitting port	Frame length	Fragment ID
					64	16	32	11	108

And the output control module is also used for writing the registration information into the first table item if the first table item and the second table item are empty.

The output control module is further used for checking whether the table item corresponding to the hash value is locked or not if the first table item or the second table item has the registered value; the output control module is also used for writing original information in the table entry into the registration failure FIFO and writing the registration value into the table entry if the registration failure FIFO is not locked;

the output control module is also used for writing the registration value into the waiting unlocking FIFO if the lock is locked;

the output control module is also used for writing the registration value into the registration failure FIFO if the register value is locked and the waiting unlocking FIFO is full;

the output control module is further used for writing the registration value into the empty table entry if only one of the first table entry and the second table entry is empty and the non-empty table entry is not in accordance with the registration information;

and the output control module is also used for judging registration failure by the registry control module if the first table item and the second table item are both non-empty and occupied by other registration information, and writing the registration value into the registration failure FIFO.

In particular, with reference to fig. 12 and 18,

(1) The registry control module uses a receiving time point of the TT frame and a splicing value of the TT ID as identification, obtains hash values by using two different hash functions, and respectively indexes a registry A and a registry B by using the two hash values to obtain itemA and itemB.

(2) If both the itemA and the itemB are empty, the registry control module writes the registration information into the itemA.

(3) If the item mA or item B has the registered value, checking whether the table item is locked:

(1) if not locked, the registry control module writes the original information in the table entry into the registration failure FIFO, and writes the current registration value into the table entry.

(2) If locked, indicating that the old TT frame is scheduled but not yet transmitted, the registry control module writes the current registration value into the waiting unlock FIFO.

(3) If the lock is already locked and the waiting unlock FIFO is full, the registry control module writes the current registration value into the registration failure FIFO.

(4) If only one item of the item mA and the item B is empty and the non-empty entry is not consistent with the registration information, the registration table control module writes the registration value into the empty entry.

(5) If both the itemA and the itemB are not empty and occupied by other registration information, the registry control module judges that the registration fails, and writes the registration value into a registration failure FIFO.

Further, as shown in fig. 12, when the local is directly close to the transmission time, the transmission scheduling module in the output control module acquires the transmission information from the transmission scheduling information FIFO and performs transmission scheduling search, and fig. 19 is a waveform diagram of the transmission scheduling module provided by the embodiment of the present invention.

Specifically, the output control module is further configured to use a receiving time point of the TT frame and a splice value of the TT ID as an identifier, obtain hash values by using two different hash functions, and index the first registry and the second registry with the two hash values respectively to obtain a first table entry and a second table entry;

and the output control module is also used for feeding back failure in searching if the first table item and the second table item have no current registration value.

The output control module is further configured to determine whether to cancel according to whether the current output ports are all the output ports if the first table entry or the second table entry has the current registration value;

the output control module is also used for writing the invalid table entry in the searched table entry if the registration control module needs to cancel, and feeding back the search result;

Specifically, referring to fig. 12 and 20:

the registry control module uses a receiving time point of the TT frame and a splicing value of the TT ID as identification, obtains hash values by using two different hash functions, and respectively indexes a registry A and a registry B by using the two hash values to obtain itemA and itemB.

(2) If neither the itemA nor the itemB has the registration value, the feedback search fails.

(3) If the item mA or item B has the registration value, judging whether to cancel according to whether the output ports at this time are all the output ports:

(3) if the log-out is needed, the registry control module writes the invalid table entry in the searched table entry and feeds back the search result.

(4) If the log-off is not needed, updating the rest of the sending ports, locking the table entry once, and feeding back the search result.

(4) A search failure does not mean a scheduling failure, and it may be decided whether to initiate a search again according to the transmission window.

Furthermore, the output buffer area adopts SRAM to realize the slicing buffer area, and the buffer area is indexed by the buffer descriptor.

Specifically, the output control module is further configured to store the buffer descriptor in the idle slice FIFO in an initial state;

the output control module is also used for acquiring a buffer descriptor from the idle fragment FIFO when TT frames need to be stored;

And the output control module is also used for rewriting the buffer descriptor into the idle fragment FIFO if the registration fails, the TT frame is sent successfully or buffer release is needed.

The buffer descriptor may be rewritten into the free burst FIFO by the buffer release module in fig. 12, fig. 21 is a waveform diagram of the buffer release module provided by the embodiment of the present invention, and fig. 22 is a waveform diagram of the free burst FIFO provided by the embodiment of the present invention.

Specifically, as shown in fig. 12, the output control modules are divided into a unicast output control module and a multicast output control module, where the unicast output control modules are in one-to-one correspondence with the ports. And caching the TT frames in an output buffer area, accessing the TT buffer area according to a transmission schedule transmitted by a transmission schedule module, and transmitting the TT frames. The receiving control module arbitrates the forwarding request in the TT frame and gives the request meeting the requirements to the forwarding and receiving control module; the forwarding and receiving control module selects a received TT frame from the requests meeting the requirements by adopting a priority encoder, if a new application sent by the receiving arbitration control module is received in the receiving process of the TT frame, the TT frame is suspended, the new TT frame is received, and the suspended TT frame is preferentially sent after the TT frame is received; the registry control module completes the read-write operation related to the registry, fairly polls related FIFO, and completes the registration application or sends the scheduling search application; the receiving table entry module receives the sending scheduling table and writes the sending scheduling table into the sending scheduling information FIFO; the sending scheduling module finishes reading the sending scheduling information FIFO according to the system time, generates a sending window, initiates a sending scheduling list table searching request to the registry control module, and waits for a table searching result; the buffer release module writes the buffer descriptors needing to be released into the idle fragment FIFO; the transmission control module obtains the TT frame descriptor from the TT frame transmission FIFO, and moves the TT frame from the corresponding fragment buffer, and sends the TT frame, and after the movement is completed, the buffer or the registry entry is released, and fig. 23 is a waveform diagram of the transmission control module provided in the embodiment of the present invention.

And the unicast and multicast output control module 6 is used for accessing the TT buffer area according to the transmission schedule sent by the transmission schedule module, selecting and outputting the output data of the unicast and multicast output control module, or sending the TT frame at a specified transmission time point.

Specifically, the unicast output control module 6 further includes a transmission control module, where the above steps may be performed by the transmission control module, that is, the transmission control module is configured to access the TT buffer area according to the transmission schedule sent by the transmission schedule module, and select to output the unicast output control module, or, send the output data of the multicast output control module at a specified transmission time point to the TT frame.

The unicast/multicast output control modules are in one-to-one correspondence with the ports, and output data of the unicast/multicast output control modules are selected to be output. Outputting a virtual multicast port TT frame when detecting that the port is one of destination ports of the virtual multicast port TT frame; otherwise, outputting TT frame of the port output control module.

Specifically, the transmission control module is further configured to obtain a buffer descriptor corresponding to the output TT frame from the TT frame transmission FIFO;

the sending control module is also used for extracting and outputting TT frames from the slicing buffer area and sending the TT frames at a specified sending time point;

And the transmission control module is also used for releasing the fragment buffer area corresponding to the output TT frame after the transmission is completed, or unlocking the table entry corresponding to the output TT frame in the registry once.

The invention aims to provide a time triggered Ethernet TT service switching device aiming at the defects of the prior art, wherein a preemptive receiving TT frame supporting high priority is designed to preempt TT frames supporting low priority, FIG. 24 is a waveform chart of preemptive transmission of a 1-port receiving scheduling control module provided by the embodiment of the invention, FIG. 25 is a waveform chart of preempted 2-port receiving scheduling control module provided by the embodiment of the invention, FIG. 26 is a waveform chart of preemptive receiving arbitration control module provided by the embodiment of the invention, FIG. 27 is a waveform chart of when preemptive receiving control module provided by the embodiment of the invention occurs, a virtual multicast port is designed to convert multicast problems into unicast problems, a scheduler for completing TT frame scheduling according to a schedule is designed by adopting a registration and table-lookup mode, so that the addition or deletion of a certain service flow does not affect other service flows, the improvement of a single-frame storage TT plane is optimally designed, differentiated services are provided for different flows, the sending delay of a designated TT flow does not affect other TT flows, thus the delay condition is required to be added when scheduling is reduced, the TT is required to be additionally scheduled, the forwarding performance is required to be reduced, and the forwarding performance is associated with the TT is planned to be supported by a plurality of hardware.

The method comprises the steps of designing preemptive receiving TT frames supporting high priority to preempt TT frames supporting low priority, designing a virtual multicast port to convert multicast problems into unicast problems, designing a scheduler for completing TT frame scheduling according to a scheduling table in a registration and table look-up mode, enabling addition or deletion of one service flow not to affect other service flows, optimizing and designing buffer areas of an input side and an output side to improve a single frame storage type TT plane, providing differentiated services for TT flows with different time delay requirements, enabling transmission deferral of a designated TT flow not to affect other TT flows, accordingly reducing constraint conditions required to be additionally added during scheduling planning, reducing relativity between scheduling planning and switching hardware forwarding, supporting forwarding behaviors of multiple TT services, and guaranteeing reliable transmission of TT services.

Fig. 28 is a workflow of a TT service switching device of a time triggered ethernet switch according to an embodiment of the present invention, as shown in fig. 28:

1. and initializing after the system is powered on, and entering a working state after waiting for clock synchronization.

The system is powered on to initialize, asynchronous reset and synchronous release are completed, and other modules are controlled to execute initialization operation; and waiting for the clock to be synchronized and then entering into a working state. If the system is out of step or the system is reset, the reset operation is performed.

2. And respectively distributing the receiving schedule and the sending schedule to each input control module and each output control module according to the system time.

Further, the step 2 includes the steps of:

(1) Receiving a schedule dispatch flow:

(1) the receiving schedule is divided into two levels of table lookup, and when the receiving schedule information FIFO is not full, the table reading operation is carried out.

(2) And accessing the primary table, wherein the initial address is 0, and the primary table is accessed sequentially according to the next hop address of the linked list.

(3) And calculating a hash value by taking the TTID as a key value, and accessing the secondary table by using the hash value.

(4) It is checked whether the TTID is consistent with the primary table. If TTID is consistent and the admission port and the sending port are valid, the query is correct, and the table items are spliced; if TT ID is consistent and the admission port and the sending port are invalid, searching fails; if TTID is inconsistent and the linked list effective field is effective, continuing indexing by taking the next hop as an address; if TTID is inconsistent and the linked list valid field is invalid, the search fails.

(5) After the successful search and the information splicing, the receiving schedule is distributed to each input control module.

(2) The sending schedule dispatch flow:

(1) the transmission schedule is divided into a single-stage table lookup, and when the transmission schedule information FIFO is not full, a table reading operation is performed.

(2) The initial address is 0, and the access is sequentially carried out according to the next hop address of the linked list.

(3) After the search is completed, the transmission schedule is distributed to each output control module.

(3) If the receive schedule is in a single level table format, a two level table may be generated.

Step 2 proposes a two-stage searching method for receiving schedule, because TT frames of the same TT ID may be received for multiple times in different time periods in the matrix period, the receiving and transmitting ports, receiving windows and frame length information of the TT frames are the same, and the two-stage searching method can avoid repeated information access and reduce resource consumption.

3. The input control module acquires a receiving schedule, receives TT frames according to the receiving schedule, and stores the TT frames in a receiving buffer area. And forwarding the received data to a corresponding output control module according to the sequence of the received data.

Further, the step 3 includes the steps of:

(1) In step 2, the receiving schedule is distributed to the input control module in a broadcast manner, so that it is necessary to determine whether to receive the entry according to whether the corresponding port is one of the entry admission ports of the receiving schedule. If so, the received scheduling information is stored in a received scheduling information FIFO.

(2) And reading the receiving scheduling information from the receiving scheduling information FIFO according to the system time, and generating a receiving window according to the receiving time point and the receiving window length. In order to avoid that the receiving window is stuck due to the fact that the receiving window is reset by receiving the same TTID frame, a receiving statistics pulse needs to be generated each time the receiving window counter is reset to indicate that a new TT frame can be received again, and each time the TT frame is received, a pulse needs to be consumed.

(3) When the TT frame arrives, whether to receive the TT frame is determined according to whether the receiving window is opened or not. If the TT frame falls in the receiving window, caching the data, extracting data information and checking; if the check is wrong, the receiving window is closed in the receiving process, and the TT frames exceeding the quantity required by the dispatching or the receiving buffer area overflows, the receiving error is judged.

(4) If the error is received, the write address of the input buffer area is returned to the initial position of the error frame; if the receiving is correct, the receiving scheduling information such as TT frame length is written into the receiving scheduling FIFO.

(5) And taking out the scheduling information of the next frame from the receiving scheduling FIFO, sending the TT frame and the scheduling information to a data bus, and monitoring whether a target output control module on a control channel has a feedback signal or not. If the feedback signal is received, the next TT frame is continuously moved.

Step 3 provides a TT frame input buffer method, which ensures that TT services which are required to be sent to the same output port are not lost when a plurality of input ports receive the TT frames at the same moment.

And 4. The TT frames are sent to the output control modules of the corresponding ports through the full-interconnection exchange modules, the output control modules select one TT frame to be received from the data channels of each input control module, and the maximum frame length which can be received is calculated according to the size of the output buffer area. The store-and-forward device adopts a special CIOQ two-stage switching structure, and is based on a CIOQ Crossbar structure, and a virtual multicast port is added. Multicast frames are sent to the virtual multicast ports, which are forwarded to all ports.

Further, the step 4 includes the steps of:

(1) If no TT frame is being transmitted, the transmission time is not required, and only the TT frame length is required. But this may be satisfactory with multiple TT frames, the TT frames to be transmitted being determined using a priority encoder.

(2) If there are TT frames being transmitted and a plurality of input channels for transmission, the time of the transmission application is compared in parallel, and the transmission time smaller than the current transmission time of the frames is found.

(3) In the receiving process, if a new TT frame meets the sending condition and is more urgent than the current TT frame, the receiving of the current TT frame is suspended, the receiving state of the current frame is suspended, the suspending of the receiving state is completed by adopting a structure of Last In First Out (LIFO), and the more urgent frame is started to be received.

(4) When one TT frame finishes transmitting, firstly checking whether the TT frame is suspended, if so, preferentially transmitting the TT frame.

And step 4, adopting a special CIOQ two-stage switching structure, avoiding the mixed scheduling of unicast and multicast, providing a preemptive receiving mode, guaranteeing the internal forwarding of TT frames with urgent sending time and reducing the complexity of a scheduling algorithm.

And 5. After the TT frames are cached in the output buffer area, registering, recording the positions of the TT frames in the buffer area, and using the TT frames for indexing the TT frames during dispatching.

Further, the step 5 includes the steps of:

(1) And using the receiving time point of the TT frame and the splicing value of the TT ID as identifiers, using two different hash functions to obtain hash values, and respectively indexing a registry A and a registry B by using the two hash values to obtain itemA and itemB.

(2) If both the itemA and the itemB are empty, the registration information is written into the itemA.

(1) if not, writing original information in the table entry into the registration failure FIFO, and writing the registration value into the table entry.

(2) If locked, indicating that the old TT frame is scheduled but the transmission is not completed, writing the registration value into the waiting unlock FIFO.

(3) If the lock is already locked and the waiting unlock FIFO is full, the registration value is written into the registration failure FIFO.

(4) If only one item of the item mA and the item B is empty and the empty entry is not in accordance with the registration information, writing the registration value into the empty entry.

(5) If both the itemA and the itemB are not empty and occupied by other registration information, judging that the registration fails, and writing the registration value into a registration failure FIFO.

6. And when the local is directly close to the transmission time, acquiring the transmission information from the transmission scheduling information FIFO, and carrying out transmission scheduling searching.

Further, the step 6 includes the steps of:

(1) if the log-out is needed, writing the table entry in the searched table entry to be invalid, and feeding back the search result.

(2) If the log-off is not needed, updating the rest of the sending ports, locking the table entry once, and feeding back the search result.

And 5, 6, providing a scheduler for registration and table lookup index, improving scheduling flexibility, and adding and deleting a certain data flow table entry does not affect other data flows.

7. The output buffer area adopts SRAM to realize the slicing buffer area, and the buffer area is indexed by the buffer descriptor.

Further, the step 7 includes the steps of:

(1) In the initial state, the buffer descriptor is stored in the free slice FIFO.

(2) When TT frames need to be stored, a buffer descriptor is obtained from the idle fragment FIFO.

(3) Registration failure, successful TT frame sending, need of buffer release, and re-write the buffer descriptor into the idle fragment FIFO.

And 7, managing output side buffering by adopting a buffering and slicing mode, so that the buffering utilization rate is improved, and a plurality of TT frames can be buffered.

8. And accessing the TT buffer according to a transmission schedule transmitted by the transmission schedule module, selecting output data of the output unicast/multicast output control module, and transmitting the TT frame at a specified transmission time point.

Further, the step 8 includes the steps of:

(1) The transmit control module obtains the buffer descriptor from the TT frame transmit FIFO.

(2) And extracting the TT frames from the slicing buffer area, and sending out the TT frames at a specified sending time point.

(3) After the transmission is completed, the buffer area is released, or the corresponding table entry in the registry is unlocked once.

Fig. 29 is a schematic diagram of forwarding behavior of a TT frame supportable by a TT service switching device of a time triggered ethernet switch according to an embodiment of the present invention, where, as shown in fig. 10, a TT plane of a single frame buffer may complete forwarding of TT services in a sequence without overlapping, but a buffer area to be sent needs to be overlapped in sequence to support multi-frame buffer. The reverse order is the reverse order of the different TTID frames. Input collision means that TT frames sent to the same output port exist in different input ports at the same time. The mutual forwarding means that TT frames input by different input ports at the same time are forwarded to different ports. The output collision means that TT frames input by the same input port in sequence need to be sent to different output ports at the same time. Simultaneous multicast means that multicast TT frames need to be sent to all output ports at the same time. Time-sharing multicast means that multicast TT frames need to be sent to all output ports at different times.

The TT service exchange plane of the time triggered Ethernet switch supports TT frames with high priority to preempt TT frames with low priority, designs a virtual multicast port to convert multicast problems into unicast problems, adopts a registration and table look-up mode to design a scheduler for completing TT frame scheduling according to a schedule, improves a single frame storage type TT plane, and optimally designs input side and output side buffer areas.

Compared with the prior art, the method has the following technical effects:

(1) The input side buffer memory is added, and TT services which are required to be sent to the same output port are received by a plurality of input ports at the same moment, so that frames cannot be lost;

(2) And the output side buffer memory is managed in a buffer memory slicing mode, so that the buffer memory utilization rate is improved, a plurality of TT frames can be buffered, and when the TT frames are transmitted by the output port, the TT frames which are received by the input port and are required to be transmitted to the output port are not discarded.

(3) And a preemptive internal forwarding mechanism is adopted to preferentially receive TT frames with more urgent transmission time, so that the TT frames can arrive at a transmission buffer in real time to be correctly scheduled.

(4) The design realizes a heterogeneous CIOQ switching structure, adds virtual multicast output ports, converts the multicast problem into a unicast problem, and solves the problem that the multicast frame needs to wait for all the output ports to be idle to schedule, so that the transmission time point can be missed.

(5) The TT frames with the same TT ID are supported to be received, and the TT frames with the specified number are received by a 'sticky' receiving window.

(6) Output scheduling is carried out by adopting a registration and table lookup method, scheduling flexibility is improved, scheduling planning and switching hardware forwarding design are decoupled, and the probability of failure in generating a complex network topology scheduling table is reduced.

(7) The receiving schedule and the sending schedule adopt a linked list design, the dynamic schedule configuration is supported, and the addition and deletion of a certain data flow table entry does not affect other data flows.

(8) The transmission order of the TT frames depends only on the transmission schedule, and the TT frames may be held for an arbitrary time. Differentiated services are provided for TT flows with different time delay requirements, and the sending delay of the appointed TT flow does not affect other TT flows.

In the description of the present invention, the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present invention, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.

In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic point described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristic data points described may be combined in any suitable manner in any one or more embodiments or examples. Further, one skilled in the art can engage and combine the different embodiments or examples described in this specification.

The foregoing is a further detailed description of the invention in connection with the preferred embodiments, and it is not intended that the invention be limited to the specific embodiments described. It will be apparent to those skilled in the art that several simple deductions or substitutions may be made without departing from the spirit of the invention, and these should be considered to be within the scope of the invention.

Claims

1. A time triggered ethernet switch TT service switching apparatus, the apparatus comprising:

The unicast and multicast output control module is used for accessing the TT buffer area according to the transmission schedule transmitted by the transmission schedule module, and selecting and outputting the output data of the unicast and multicast output control module, or transmitting the TT frame at a specified transmission time point;

the receiving schedule module is further used for sending the splicing table to the input control module;

the sending schedule module is further used for reading the sending schedule from the table item with the initial address of 0, and sequentially accessing the table items of each sending schedule according to the next-hop address corresponding to each table item in the sending schedule;

The sending schedule module is further used for sending the sending schedule to each output control module after the searching is completed;

2. The time triggered ethernet switch TT service switching apparatus of claim 1, wherein,

3. The time triggered ethernet switch TT service switching apparatus of claim 1, wherein,

4. The time triggered ethernet switch TT service switching apparatus of claim 1, wherein,

5. The time triggered ethernet switch TT service switching apparatus of claim 1, wherein,

the output control module is further configured to feedback a failure in searching if the first entry and the second entry have no current registration value;

6. The time triggered ethernet switch TT service switching apparatus of claim 1, wherein,

7. The time triggered Ethernet switch TT service switching apparatus of claim 4,