CN115378887A

CN115378887A - TT (transfer terminal) service switching device of time-triggered Ethernet switch

Info

Publication number: CN115378887A
Application number: CN202210783860.1A
Authority: CN
Inventors: 潘伟涛; 高璐; 邱智亮; 黄进建
Original assignee: Xidian University
Current assignee: Xidian University
Priority date: 2022-07-05
Filing date: 2022-07-05
Publication date: 2022-11-22
Anticipated expiration: 2042-07-05
Also published as: CN115378887B

Abstract

The invention relates to a TT service switching device of a time-triggered Ethernet switch, which is characterized in that a TT frame supporting high priority is preemptively received by designing a preemptive receiving manner to preempt a TT frame of low priority, a virtual multicast port is designed to convert a multicast problem into a unicast problem, a scheduler which completes TT frame scheduling according to a scheduling table is designed by adopting a registration and table look-up manner, so that the addition or deletion of a certain service flow does not influence other service flows, an input side cache region and an output side cache region are optimally designed to improve a single frame storage type TT plane, different services are provided for TT flows with different delay requirements, the transmission delay of the appointed TT flow does not influence other TT flows, the additional added constraint condition during scheduling planning is reduced, the forwarding relevance of scheduling planning and switching hardware is reduced, multiple TT service forwarding behaviors are supported, and the reliable transmission of TT services is guaranteed.

Description

TT (transfer terminal) service switching device of time-triggered Ethernet switch

Technical Field

The invention belongs to the technical field of communication, and relates to a TT (transfer terminal) service switching device of a time-triggered Ethernet switch.

Background

With the development of information technology, electronic devices and systems in the fields of industry, aviation and the like pay more and more attention to the real-Time performance, safety and certainty of tasks, and the traditional ethernet cannot meet the requirement, so that Time Triggered Ethernet (TTE) is produced. By planning TT services in advance, devices in the network are guaranteed to provide deterministic guarantee for the TT services, and conflict between the TT services and other services is avoided.

In the existing TTE switch, there are several ways to forward the TT frame:

the first is a cut-through forwarding scheme. In 2006, a Time-Triggered Ethernet (TTE) Switch proposed by document a Time-Triggered Ethernet (TTE) Switch adopts a pass-through forwarding mode, ET services adopt a store-and-forward mode, and when ET services conflict with TT services, ET services are preempted by TT services and then continue to be retransmitted. However, the forwarding method needs to avoid the conflict of TT services through the communication protocol, and because TT services are not buffered, when two or more TT frames arrive at the same time, TT frames with low priority can be discarded.

The second is a store-and-forward approach. In 2020, the document Dual-Plane Switch Architecture for Time-Triggered Ethernet proposes a Dual-Plane switching Architecture, in which ET traffic and TT traffic are processed separately. Wherein, the output port of TT service transmits TT frame according to the transmission schedule and adds buffer memory on the output side. However, the technical scheme has the following defects:

(1) Because TT frames are not buffered on the input side, the input side TT conflicts and depends on the schedule to avoid;

(2) The buffer area at the output side can only complete single-frame buffer, and the flexibility of complex scheduling is not enough;

(3) The designed TT receiving window only allows a single TT frame to be received, and depends on scheduling cooperation of an end system for TT services needing fragmentation;

(4) When a multicast frame needs to be sent, the existing technical scheme needs to wait for all destination output ports of the multicast frame to be idle for scheduling, which may cause the multicast frame to miss a sending time point;

(5) Additional constraints need to be added to avoid conflicts when scheduling the planning, including but not limited to: (1) the condition that a plurality of input ports receive signals to be sent to the same output port at the same time is ensured not to occur; (2) ensuring that the input port receives a new TT frame which needs to be sent to the output port when the output port is sending the TT frame does not occur. (3) Ensuring that no inconsistency of the output port TT frame transmission sequence with the TT frame entering TT plane occurs. When the service planning in the network is complex and the traffic is large, the additional constraint condition may cause the generation of the scheduling table to fail.

(6) Scheduling planning flexibility is poor, when a TT service is added to the network, a time period in which all devices on the path are idle needs to be found, and if the TT service cannot be found, all services need to be re-planned.

In the feasible scheme of the known TTE switch, it is very important to solve the problems of TT service reliability and deterministic transmission. In the above 2 schemes, the practical requirements of the TTE switch cannot be well met in terms of system independence, practical feasibility and cost overhead.

Disclosure of Invention

In order to solve the above problems in the prior art, the present invention provides a time triggered ethernet switch TT service switching apparatus. The technical problem to be solved by the invention is realized by the following technical scheme:

the embodiment of the invention provides a TT service switching device of a time-triggered Ethernet switch, which comprises:

the total control module is used for initializing after detecting that the time-triggered Ethernet switch TT service switching plane is electrified, and controlling other modules to enter a working state after waiting for clock synchronization;

the receiving scheduling table module is used for sending the receiving scheduling table to the input control module according to the receiving scheduling table and the system time;

the transmission scheduling table module is used for transmitting the transmission scheduling table to the output control module according to the transmission scheduling table and the system time;

the input control module is used for receiving a legal TT frame according to the receiving scheduling table sent by the receiving scheduling table module and storing the legal TT frame in an input cache region, wherein the input control module corresponds to the ports one to one;

the full-interconnection switching control module is used for completing the connection of the input control module and the output control module and sending the TT frame cached in the input cache region to the corresponding output control module;

the output control module is used for selecting a TT frame which is received from the data channels of the input control modules, calculating the length of the maximum frame which can be received according to the size of an output buffer area, storing the received TT frame into the output buffer area, storing the position of the TT frame in the output buffer area, acquiring transmission information from the transmission scheduling table stored in the transmission scheduling information FIFO when the local time is directly close to the transmission time, and performing transmission scheduling search in the output buffer area; the output cache region adopts an SRAM to realize a partitioned cache region, and the cache region is indexed by a cache descriptor; wherein, output control module includes: a unicast output control module and a multicast output control module;

and the single multicast output control module is used for accessing the TT buffer area according to the sending schedule table sent by the sending schedule table module, selectively outputting the single multicast output control module, or sending the output data of the multicast output control module to the TT frame at the specified sending time point.

In one embodiment of the present invention, the substrate is,

the receiving scheduling module is also used for reading the table when detecting that the FIFO of the receiving scheduling information is not full;

the receiving scheduling table module is further configured to read each entry in the receiving scheduling primary table in sequence, where the receiving scheduling primary table is read from an entry whose starting address is 0, and each receiving scheduling primary table is sequentially accessed according to a linked list next-hop address in each entry;

the receiving scheduling table module is further configured to calculate a hash value for a key value of a first TT ID in each entry in the receiving and scheduling primary table, and access each entry in the receiving and scheduling secondary table by using the hash value respectively;

the receiving scheduling table module is further configured to check whether a second TT ID in an entry accessed in the receiving scheduling secondary table is consistent with the first TT ID in an entry of the receiving scheduling primary table;

if the second TT ID is consistent with the first TT ID and an access port and a sending port are effective, the query is correct, and the receiving scheduling table module is also used for splicing the table items in the receiving scheduling secondary table corresponding to the second TT ID and the table items in the receiving scheduling primary table corresponding to the first TT ID to obtain a spliced table;

if the second TT ID is consistent with the first TT ID and the access port and the sending port are invalid, the search is failed;

if the second TT ID is inconsistent with the first TT ID and the effective field of the chain table in the receiving and dispatching primary table is effective, the receiving dispatching table module is also used for continuing indexing by taking the next hop as an address;

if the second TT ID is inconsistent with the first TT ID and the valid field of the chain table in the receiving and dispatching primary table is invalid, the searching is failed;

the receiving scheduling table module is also used for sending the splicing table to the input control module.

In one embodiment of the present invention, the,

the sending scheduling module is also used for reading the table when the FIFO of the sending scheduling information is detected to be not full;

the sending scheduling table module is also used for reading the sending scheduling table from the table entry with the starting address of 0 and sequentially accessing the table entries of the sending scheduling table according to the next hop address corresponding to each table entry in the sending scheduling table;

and the transmission scheduling table module is also used for transmitting the transmission scheduling table to each output control module after the searching is finished.

In one embodiment of the present invention, the substrate is,

the input control module is further configured to detect whether a port corresponding to the input control module is one of entry admission ports of the receiving scheduling table;

if yes, the input control module is also used for receiving the table entry of the receiving scheduling table and storing the table entry into the receiving scheduling information FIFO;

the input control module is also used for reading receiving scheduling information from the receiving scheduling information FIFO according to the system time and generating a receiving window according to the receiving time point and the receiving window length; wherein each time the receive window counter is reset, a receive statistic pulse is generated, said receive statistic pulse indicates that a new TT frame can be received again, and each time a pulse is consumed to receive a TT frame;

the input control module is also used for determining whether to receive the TT frame according to whether the receiving window is opened or not when the TT frame arrives;

if the TT frame falls into the receiving window, the input control module is also used for caching the TT frame;

the input control module is further configured to detect whether the TT frame is received with errors;

if receiving an error, the input control module is also used for returning the write address of the input cache area to the initial position of the error frame; if the reception is correct, writing the reception scheduling information corresponding to the TT frame into the reception scheduling information FIFO;

the input control module is also used for taking out the scheduling information of the next frame from the received scheduling information FIFO, sending the TT frame and the scheduling information of the next frame to a data bus, and monitoring whether a target output control module on a control channel has a feedback signal;

and if the feedback signal is received, the input control module is also used for continuously moving the next TT frame.

In one embodiment of the present invention, the substrate is,

the output control module is also used for determining a TT frame to be transmitted from the TT frames with the frame length meeting the preset frame length by using the priority encoder when the TT frame is not transmitted;

the output control module is also used for obtaining a target input channel corresponding to a target input control module which is less than the sending time of the TT frame currently being transmitted from each sending application time if the TT frame currently being transmitted exists and a plurality of input channels corresponding to the input control module apply for sending, pausing the receiving of the current TT frame and receiving a new TT frame meeting the requirements;

the output control module is further configured to, when a new TT frame meets a transmission condition and the transmission time is closer to the current time than the transmission time of the current TT frame in the process of receiving the TT frame, suspend reception of the current TT frame, suspend the reception state of the current TT frame, complete suspension of the reception state by adopting a last-in first-out structure, and start receiving a more urgent TT frame;

the output control module is further configured to, after one TT frame is completely transmitted, first check whether there is a suspended TT frame, and if there is a suspended TT frame, preferentially transmit the suspended TT frame.

In one embodiment of the present invention, the substrate is,

the output control module is further configured to use the receiving time point of the TT frame and the spliced value of the TT ID as identifiers, use two different hash functions to obtain hash values, and use the two hash values to index the first registry and the second registry respectively, so as to obtain a first entry and a second entry;

the output control module is further configured to, if the first entry and the second entry are both empty, write the current registration information into the first entry by the registry control module;

the output control module is further configured to check whether the entry corresponding to the hash value is locked if the first entry or the second entry has the current registration value;

the output control module is also used for writing the original information in the table entry into the registration failure FIFO and writing the current registration value into the table entry if the table entry is not locked;

the output control module is also used for writing the current registration value into an FIFO waiting for unlocking by the registry control module if the current registration value is locked;

the output control module is also used for writing the current registration value into a registration failure FIFO if the current registration value is locked and the waiting unlocking FIFO is full;

the output control module is further configured to, if only one of the first table entry and the second table entry is empty and an empty table entry does not match the current registration information, write the current registration value into the empty table entry by the registry control module;

and the output control module is further configured to, if the first entry and the second entry are both non-empty and occupied by other registration information, determine that registration fails and write the current registration value into a registration failure FIFO.

In one embodiment of the present invention, the,

the output control module is further configured to, if neither the first table entry nor the second table entry has the current registration value, fail the feedback lookup.

The output control module is further configured to, if the first entry or the second entry has a current registration value, determine whether to cancel the output port according to whether the current output port is all output ports;

the output control module is also used for writing the invalid table entry in the searched table entry and feeding back the search result if the log-off is required;

and the output control module is also used for updating the output port of the list item to be the residual port to be sent if the log-off is not needed, locking the list item once, and feeding back a search result.

In one embodiment of the present invention, the,

the output control module is further configured to store the cache descriptor in an idle fragmentation FIFO in an initial state;

the output control module is also used for acquiring the buffer descriptor from the idle fragment FIFO when TT frames need to be stored;

the output control module is further configured to rewrite the buffer descriptor into the free fragment FIFO if registration fails, the TT frame is successfully transmitted, or buffer release is required.

In one embodiment of the present invention, the substrate is,

the single multicast output control module is also used for acquiring a cache descriptor corresponding to the output TT frame from the TT frame transmission FIFO;

the single multicast output control module is further configured to extract the output TT frame from the fragmentation buffer and send out the output TT frame at a specified sending time point;

the single multicast output control module is further configured to release the fragment cache area of the output TT frame for drinking after the transmission is completed, or unlock the entry corresponding to the output TT frame in the registry once.

Compared with the prior art, the invention has the beneficial effects that:

a preemptive receiving and low-priority TT frame supporting TT frames with high priority is designed in the TT service switching device of the time-triggered Ethernet switch, a virtual multicast port is designed to convert a multicast problem into a unicast problem, a scheduler which completes TT frame scheduling according to a scheduling table is designed in a registration and table look-up mode, so that the addition or deletion of one service flow does not affect other service flows, a single-frame storage type TT plane is improved by optimally designing buffer areas at an input side and an output side, different services are provided for TT flows with different delay requirements, the transmission delay of the specified TT flow does not affect other TT flows, the constraint condition which needs to be additionally added in scheduling planning is reduced, the forwarding relevance of scheduling planning and switching hardware is reduced, multiple TT service forwarding behaviors are supported, and the reliable transmission of TT services is guaranteed.

Other aspects and features of the present invention will become apparent from the following detailed description, which proceeds with reference to the accompanying drawings. It is to be understood, however, that the drawings are designed solely for purposes of illustration and not as a definition of the limits of the invention, for which reference should be made to the appended claims. It should be further understood that the drawings are not necessarily drawn to scale and that, unless otherwise indicated, they are merely intended to conceptually illustrate the structures and procedures described herein.

Drawings

Fig. 1 is a schematic structural diagram of a TT service switching apparatus of a time-triggered ethernet switch according to an embodiment of the present invention;

fig. 2 is a schematic structural diagram of a receiving scheduling table module according to an embodiment of the present invention;

fig. 3 is a schematic structural diagram of a transmission scheduling table module according to an embodiment of the present invention;

fig. 4 is a schematic structural diagram of an input control module according to an embodiment of the present invention;

fig. 5 is a waveform diagram of a table entry receiving module according to an embodiment of the present invention;

fig. 6 is a waveform diagram of a table entry receiving module according to an embodiment of the present invention;

fig. 7 is a waveform diagram of a read table entry module according to an embodiment of the present invention;

fig. 8 is a waveform diagram illustrating the start of the received information control module according to an embodiment of the present invention;

fig. 9 is a waveform diagram of a control module for controlling a receiving window according to an embodiment of the present invention;

fig. 10 is a waveform diagram of a frame reception control module according to an embodiment of the present invention;

fig. 11 is a waveform diagram of a receiving scheduling control module according to an embodiment of the present invention;

fig. 12 is a schematic structural diagram of an output control module according to an embodiment of the present invention;

FIG. 13 is a waveform diagram of a receive arbitration control module according to an embodiment of the present invention;

fig. 14 is a schematic diagram of a heterotype CIOQ two-stage switching structure according to an embodiment of the present invention;

fig. 15 is a waveform diagram of a forwarding and receiving control module according to an embodiment of the present invention;

FIG. 16 is a waveform diagram illustrating registry control module registration according to an embodiment of the present invention;

fig. 17 is a waveform diagram of a schedule lookup sent by a registry control module according to an embodiment of the present invention;

fig. 18 is a flowchart of a method for switching TT traffic of a time-triggered ethernet switch according to an embodiment of the present invention;

fig. 19 is a waveform diagram of a transmission scheduling module according to an embodiment of the present invention;

fig. 20 is a flowchart of a method for time-triggered ethernet switch TT service switching according to an embodiment of the present invention;

fig. 21 is a waveform diagram of a buffer release module according to an embodiment of the present invention;

FIG. 22 is a waveform diagram of an idle slice FIFO according to an embodiment of the present invention;

fig. 23 is a waveform diagram of a transmission control module according to an embodiment of the present invention;

fig. 24 is a waveform diagram illustrating a 1-port receiving scheduling control module preempting transmission according to an embodiment of the present invention;

fig. 25 is a waveform diagram illustrating a preempted 2-port receiving scheduling control module according to an embodiment of the present invention;

fig. 26 is a waveform diagram illustrating a receiving arbitration control module during preemption according to an embodiment of the present invention;

fig. 27 is a waveform diagram of a forwarding and receiving control module during preemption according to an embodiment of the present invention;

fig. 28 is a workflow of a time-triggered ethernet switch TT service switching apparatus according to an embodiment of the present invention;

fig. 29 is a schematic diagram of forwarding behaviors of TT frames supportable by the TT service switching apparatus of the time-triggered ethernet switch according to the embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.

The TT service switching device of the time-triggered Ethernet switch is realized by a programmable logic chip FPGA.

Referring to fig. 1, fig. 1 is a schematic structural diagram of a TT service switching apparatus of a time-triggered ethernet switch according to an embodiment of the present invention. The invention provides a TT business switching device of a time-triggered Ethernet switch, which comprises:

the overall control module 1 is used for initializing after detecting that a TT service switching plane of the Ethernet switch is electrified and controlling other modules to enter a working state after waiting for clock synchronization;

specifically, the overall control module is used for controlling the working process of the TT business plane, initializing the system after power-on, and entering a working state after clock synchronization. And if the system is out of step or the system is reset, resetting operation is carried out.

The receiving scheduling table module 2 is used for sending the receiving scheduling table to the input control module according to the receiving scheduling table and the system time;

in an implementation manner, the receiving scheduling table module is further configured to perform a table reading operation when detecting that the receiving scheduling information FIFO is not full;

the receiving scheduling table module is also used for sequentially reading each table item in the receiving scheduling primary table, wherein the receiving scheduling primary table is read from the table item with the starting address of 0, and the receiving scheduling primary table is sequentially accessed according to the next jump address of the linked list in each table item; the scheduling primary table format may be as shown in table 1:

table 1 scheduling primary table format

Receiving time	Time of transmission	TT ID	Linked list next hop
				64bit	64bit	16bit	16bit

Fig. 2 is a schematic structural diagram of a receiving scheduling table module according to an embodiment of the present invention, and in an embodiment, a receiving scheduling primary table may be accessed through the primary table reading module in fig. 2, where an initial address is 0, and the receiving scheduling primary table is accessed sequentially according to a next hop address of a linked list.

The receiving scheduling table module is also used for calculating a hash value by taking the first TT ID in each table item in the receiving scheduling primary table as a key value, and respectively accessing each table item in the receiving scheduling secondary table by using the hash value;

in one embodiment, a hash value may be calculated by the read secondary table module in fig. 2 with the first TT ID as a key value, and the receiving scheduling secondary table is accessed with the hash value, wherein the format of the receiving scheduling secondary table may be as shown in table 2:

table 2 receive schedule secondary table format

TT ID

Admission port

Transmission port

Length of receiving window

Limiting frame length

Linked list validation

Next hop

16bit

32bit

16bit

11bit

1bit

12bit

The receiving scheduling table module is also used for checking whether a second TT ID in the table entry accessed by the receiving scheduling secondary table is consistent with a first TT ID in the table entry of the receiving scheduling primary table;

if the second TT ID is consistent with the first TT ID and the access port and the sending port are effective, the query is correct, the scheduling table module is received, and the table entry in the receiving and scheduling secondary table corresponding to the second TT ID and the table entry in the receiving and scheduling primary table corresponding to the first TT ID are spliced to obtain a spliced table;

if the second TT ID is not consistent with the first TT ID and the effective field of the linked list in the primary receiving and dispatching table is effective, the receiving dispatching table module is also used for continuing to index by taking the next hop as an address;

in one embodiment, it may be checked by the send table entry module of FIG. 2 whether the second TT ID is consistent with the first TT ID. If the table entries are consistent with each other, and the access port and the sending port are effective, the query is correct, and the table entries are spliced; if the two are consistent and the access port and the sending port are invalid, the search fails; if the two are not consistent, and the valid field of the linked list is valid, continuing to index by taking the next hop as an address; if the fields are not consistent and the valid fields of the linked list are invalid, the search fails.

The receiving scheduling table module is also used for sending the splicing table to the input control module;

in one embodiment, the splice table may be sent to the input control module by the send table entry module of FIG. 2.

In one implementation, if the receiving schedule is in a single-level table format, the two-level table may be generated as follows:

(1) establishing a conflict-free set and a conflict set: traversing the single-level receiving scheduling table, calculating the hash value of TT ID, and if the hash value does not exist in the conflict-free set, putting the table entry in the conflict-free set; otherwise, the table entry is placed in the conflict set.

(2) And traversing the single-level receiving scheduling table again, placing the single-level receiving scheduling table at the corresponding address according to the traversing sequence in the first-level table, continuously increasing the next hop of the linked list, and jumping back to the initial address for the last table entry.

(3) For the secondary table, if the table item is in the conflict-free set, the table item is placed in the corresponding position of the secondary table according to the hash value of the TT ID; otherwise, the list item is temporarily skipped. At this point all the entries of the conflict-free set have been written into the secondary table.

(4) And traversing the secondary table, acquiring all unfilled addresses of the secondary table, and recording in sequence.

(5) Traversing the single-level receiving scheduling table again, acquiring an address from the unfilled address of the second-level table for the table entry with the conflict set, filling the content of the second-level table of the table entry at the address, and setting the linked list as invalid. Calculating a hash value of the TT ID to access the secondary table, and if the next hop is invalid, modifying the address of the secondary table recorded at this time; otherwise, continuing the index by the next jump until the index is invalid, and modifying the secondary table address recorded at this time again.

A transmission schedule table module 6 for transmitting the transmission schedule table to the output control module according to the system time based on the transmission schedule table; wherein, the sending scheduling table is a single-level table look-up, and the format of the sending scheduling table is shown in table 3:

table 3 transmission schedule table format

Time of transmission

Time of reception

TT ID

Transmitting port

Length of sending window

Multicast indication

Next hop

64bit

16bit

32bit

14bit

1bit

16bit

Specifically, the method comprises the following steps:

fig. 3 is a schematic structural diagram of a sending schedule module according to an embodiment of the present invention, and in an embodiment, a table reading operation may be performed by the table reading module shown in fig. 3.

The sending scheduling table module is also used for reading the sending scheduling table from the table entry with the starting address of 0 and sequentially accessing the table entries of the sending scheduling tables according to the next hop address corresponding to each table entry in the sending scheduling table;

Specifically, the receiving schedule may be dispatched to each output control module by the sending table entry module shown in fig. 3.

The input control module 3 is used for receiving the legal TT frame according to the receiving scheduling table sent by the receiving scheduling table module and storing the legal TT frame in an input cache region, wherein the input control module corresponds to the ports one by one;

specifically, the input control module corresponds to the ports one by one, and legal TT frames are received and stored in the input buffer area according to the receiving schedule table sent by the receiving schedule table module. And forwarding the TT frame to a corresponding output buffer area according to the output control module state of the target output port.

The receiving dispatch table is distributed to the input control module in a broadcasting mode, so that the input control module is also used for detecting whether a port corresponding to the input control module is one of entry admittance ports of the receiving dispatch table;

specifically, fig. 4 is a schematic structural diagram of an input control module according to an embodiment of the present invention, and the table entry receiving module in fig. 4 may determine whether to receive the table entry according to whether the corresponding port is one of the entry ports of the receiving schedule table entry, and fig. 5 and fig. 6 are waveform diagrams of the table entry receiving module according to the embodiment of the present invention.

If yes, inputting the table entry into a control module, receiving the table entry of the scheduling table and storing the table entry into the receiving scheduling information FIFO; the scheduling information FIFO is shown in table 4:

TABLE 4 receive scheduling information FIFO

Limiting frame length	Forwarding port	Length of receiving window	TT ID	Time of transmission	Receiving time
							11	32	16	16	64	64

The input control module is also used for reading the receiving scheduling information from the receiving scheduling information FIFO according to the system time and generating a receiving window according to the receiving time point and the receiving window length; wherein, each time the receiving window counter is reset, a receiving statistic pulse is generated, the receiving statistic pulse indicates that a new TT frame can be received again, and each time the TT frame is received, a pulse is consumed;

specifically, the table entry reading module in fig. 4 may read the receiving schedule information from the receiving schedule information FIFO according to the system time, and the receiving information control module may generate a receiving window according to the receiving time point and the receiving window length. In order to avoid multiple receive window conglutinations occurring when the receive window receives the same TT ID frame reset, a receive statistical pulse needs to be generated each time the receive window counter is reset, where fig. 7 is a waveform diagram of the read table entry module provided in the embodiment of the present invention, fig. 8 is a waveform diagram of the start of operation of the receive information control module provided in the embodiment of the present invention, and fig. 9 is a waveform diagram of the control of the receive window by the receive information control module provided in the embodiment of the present invention.

if the TT frame is in the receiving window, inputting the TT frame into a control module and caching the TT frame;

the input control module is also used for detecting whether the TT frame is received wrongly;

if receiving error, the input control module is also used for returning the write address of the input cache area to the initial position of the error frame; if the reception is correct, writing the reception scheduling information corresponding to the TT frame into a reception scheduling information FIFO;

specifically, when the TT frame arrives, the frame reception control module in fig. 4 may determine whether to receive the TT frame according to whether the receiving window is opened. If the TT frame is in the receiving window, caching the data, extracting data information and checking; and if the errors are checked, a receiving window is closed in the receiving process, TT frames exceeding the scheduling requirement are received or a receiving buffer area overflows, judging that the receiving is in errors. If receiving error, the frame receiving control module returns the write address of the input buffer area to the initial position of the error frame; if the reception is correct, the reception scheduling information such as the TT frame length is written into the reception scheduling FIFO, fig. 10 is a waveform diagram of the frame reception control module provided in the embodiment of the present invention, and the reception scheduling FIFO is shown in table 5:

TABLE 5 receive Schedule FIFO

Limiting frame length	Forwarding port	TT ID	Time of transmission	Receiving time
						11	32	16	64	64

The input control module is also used for taking out the scheduling information of the next frame from the received scheduling information FIFO, sending the scheduling information of the TT frame and the next frame to a data bus and monitoring whether a feedback signal exists in a target output control module on the control channel;

and if the feedback signal is received, inputting the feedback signal into the control module, and further moving the next TT frame continuously.

Specifically, the receiving scheduling control module in fig. 4 may take out the scheduling information of the next frame from the receiving scheduling FIFO, send the TT frame and the scheduling information to the data bus, and monitor whether the target output control module on the control channel has a feedback signal. If a feedback signal is received, the next TT frame is moved, where fig. 11 is a waveform diagram of the receiving scheduling control module according to the embodiment of the present invention.

Further, as shown in fig. 4, the input control module corresponds to the ports one to one, and stores the received valid TT frame in the input buffer according to the receiving schedule sent by the receiving schedule module. And forwarding the TT frame to a corresponding output buffer area according to the output control module state of the target output port. The receiving table item module obtains a receiving schedule table, restores the receiving schedule table and stores the restored receiving schedule table into receiving schedule information FIFO; the table item reading module finishes reading the received scheduling information FIFO according to the system time; the receiving information control module controls the opening and closing of the receiving window and generates a receiving statistical pulse to indicate the number of TT frames which can be received by the receiving window; the frame receiving control module stores the TT frame into an input buffer area, generates a TT frame descriptor and stores the TT frame descriptor into a receiving scheduling FIFO, and completes bit width conversion, receiving verification and error verification of the TT frame; and the receiving scheduling control module acquires the TT frame descriptor from the receiving scheduling FIFO and acquires the TT frame from the input buffer and sends the TT frame to the output control module of a target output port.

The full-interconnection switching control module 4 is used for completing the connection of the input control module and the output control module and sending the TT frame cached in the input cache region to the corresponding output control module;

the full-interconnection exchange control module completes the connection of the input control module and the output control module, and controls the data and information interaction of the input control module and the output control module through the data channel and the control channel.

The output control module 5 is used for selecting a TT frame which is received from the data channels of each input control module, calculating the length of the maximum frame which can be received according to the size of the output buffer area, storing the received TT frame into the output buffer area, storing the position of the TT frame in the output buffer area, acquiring the transmission information from the transmission scheduling table stored in the transmission scheduling information FIFO when the local time is directly close to the transmission time, and carrying out transmission scheduling search in the output buffer area; the output cache region adopts an SRAM to realize a partitioned cache region, and the cache region is indexed by a cache descriptor; wherein, output control module includes: a unicast output control module and a multicast output control module; the unicast output control modules correspond to the ports one by one.

Specifically, fig. 12 is a schematic structural diagram of an output control module according to an embodiment of the present invention, where a TT frame is sent to an output control module of a corresponding port through a fully interconnected switch module, and a receiving arbitration control module in the output control module selects a TT frame that is received at this time from data channels of each input control module, and calculates a maximum frame length that can be received according to a size of an output buffer area, where fig. 13 is a waveform diagram of the receiving arbitration control module according to the embodiment of the present invention.

The store-and-forward device in the present disclosure uses a heterogeneous CIOQ two-stage switching structure as shown in fig. 14, which is based on a Crossbar structure of CIOQ, and adds a virtual multicast port. The multicast frame is sent to the virtual multicast port and forwarded by the virtual multicast port to all ports.

Further, the output control module is also used for determining a TT frame to be transmitted from the TT frames with the frame length meeting the preset frame length by using the priority encoder when the TT frame which is being transmitted does not exist;

specifically, if there is no TT frame being transmitted, the receiving arbitration control module in fig. 12 does not require the transmission time, but only requires the length of the TT frame. However, there may be multiple TT frames that are satisfactory, and the forwarding and receiving control module determines the TT frame to be transmitted by using the priority encoder, where fig. 15 is a waveform diagram of the forwarding and receiving control module provided in the embodiment of the present invention.

The output control module is also used for obtaining a target input channel corresponding to the target input control module which is less than the sending time of the TT frame currently being transmitted from each sending application time if the TT frame currently being transmitted exists and a plurality of input channels corresponding to the input control module apply for sending, pausing the receiving of the current frame and receiving a new frame meeting the requirements;

specifically, if there is a TT frame being transmitted and there are multiple input channels applying for transmission, the receiving arbitration module in fig. 12 may compare the time of applying for transmission in parallel to find the transmission time less than the current frame being transmitted.

The output control module is also used for pausing the reception of the current TT frame if a new TT frame meets the transmission condition and the transmission time is closer to the current time than the transmission time of the current TT frame in the process of receiving the TT frame, suspending the receiving state of the current TT frame, finishing the suspension of the receiving state by adopting a last-in first-out structure and starting to receive the more urgent TT frame;

and the output control module is also used for firstly checking whether a suspended TT frame exists after one TT frame is sent, and if so, preferentially sending the suspended TT frame.

Specifically, in the receiving process, a new TT frame meets the sending condition and is more urgent than the current TT frame, the forwarding and receiving control module in fig. 12 suspends the receiving of the current TT frame, suspends the receiving state of the current frame, completes the suspension of the receiving state by adopting a Last In First Out (LIFO) structure, and starts to receive the more urgent frame. When a TT frame is sent, the forwarding and receiving control module firstly checks whether the suspended TT frame exists or not, and if yes, the TT frame is sent preferentially.

Further, as shown in fig. 12, after the TT frame is buffered in the output buffer, the registry control module performs a "registration" operation to record a position of the TT frame in the buffer for use in sending an index of the TT frame during scheduling, where fig. 16 is a waveform diagram of registration of the registry control module according to the embodiment of the present invention, and fig. 17 is a waveform diagram of sending, scheduling, and searching by the registry control module according to the embodiment of the present invention, specifically:

the output control module is also used for acquiring a hash value by using two different hash functions and using the receiving time point of the TT frame and the splicing value of the TT ID as an identifier, and respectively indexing the first registry and the second registry by using the two hash values to acquire a first table item and a second table item; wherein, the registry is shown in table 6:

table 6 registry (231 x 512)

Receiving time	TT ID	Transmitting port	Frame length	Fragment ID
					64	16	32	11	108

And the output control module is also used for writing the current registration information into the first table entry if the first table entry and the second table entry are both empty.

The output control module is also used for checking whether the table entry corresponding to the hash value is locked if the first table entry or the second table entry has the current registration value; the output control module is also used for writing the original information in the table entry into the registration failure FIFO and writing the current registration value into the table entry if the table entry is not locked;

the output control module is also used for writing the current registration value into the FIFO waiting for unlocking by the registry control module if the current registration value is locked;

the output control module is also used for writing the current registration value into the registration failure FIFO if the locking is carried out and the waiting unlocking FIFO is full;

the output control module is also used for writing the registration value of this time into the empty table entry if only one of the first table entry and the second table entry is empty and the non-empty table entry is not accordant with the registration information of this time;

and the output control module is also used for judging that the registration fails and writing the current registration value into the registration failure FIFO if the first table item and the second table item are both non-empty and occupied by other registration information.

In particular, with reference to figures 12 and 18,

(1) The registry control module uses the receiving time point of the TT frame and the splicing value of the TT ID as identification, uses two different hash functions to obtain hash values, and uses the two hash values to respectively index the registry A and the registry B to obtain itemA and itemB.

(2) And if iteMA and iteMB are empty, the registry control module writes the registration information into iteMA.

(3) If iteMA or itemB has the current registration value, checking whether the table entry is locked:

(1) if not locked, the control module of the registry writes the original information in the table entry into the registration failure FIFO and writes the current registration value into the table entry.

(2) If the current registered value is locked, the old TT frame is scheduled but is not sent completely, and the registry control module writes the current registered value into the waiting unlocking FIFO.

(3) If the locking is already carried out and the unlocking FIFO is full, the registry control module writes the current registration value into the registration failure FIFO.

(4) If only one of iteMA and itemB is empty and the non-empty table entry is not in accordance with the current registration information, the registry control module writes the current registration value into the empty table entry.

(5) If iteMA and iteMB are both not empty and occupied by other registration information, the registry control module judges that the registration fails, and writes the current registration value into a registration failure FIFO.

Further, as shown in fig. 12, when the local area directly approaches the transmission time, the transmission scheduling module in the output control module acquires the transmission information from the transmission scheduling information FIFO to perform transmission scheduling search, and fig. 19 is a waveform diagram of the transmission scheduling module according to the embodiment of the present invention.

Specifically, the output control module is further configured to use the receiving time point of the TT frame and the splicing value of the TT ID as identifiers, use two different hash functions to obtain hash values, and use the two hash values to index the first registry and the second registry respectively, so as to obtain a first entry and a second entry;

and the output control module is also used for feeding back and searching failure if the first table entry and the second table entry do not have the current registration value.

The output control module is also used for judging whether to need logout according to whether the current output port is all the output ports or not if the first table entry or the second table entry has the current registration value;

and the output control module is also used for updating the output port of the list item to be the residual port to be sent if the log-off is not needed, locking the list item once and feeding back the search result.

Specifically, with reference to fig. 12 and 20:

the registry control module uses the receiving time point of the TT frame and the splicing value of the TT ID as identification, uses two different hash functions to obtain hash values, and uses the two hash values to respectively index the registry A and the registry B to obtain itemA and itemB.

(2) And if both iteMA and iteMB have no registration value, the feedback search fails.

(3) If iteMA or itemB has the current registration value, whether logout is needed is judged according to whether the current output port is all the output ports:

(3) if the user needs to log off, the registry control module writes the invalid entry in the searched entry and feeds back the search result.

(4) If not, updating the rest sending ports, locking the list item once, and feeding back the search result.

(4) A lookup failure does not mean a scheduling failure and it can be decided whether to initiate the lookup again according to the transmission window.

Furthermore, the output cache region adopts an SRAM to realize a partitioned cache region, and the cache region is indexed by the cache descriptor.

Specifically, the output control module is further configured to store the buffer descriptor in the free fragment FIFO in an initial state;

the output control module is also used for acquiring a buffer descriptor from the free fragment FIFO when the TT frame needs to be stored;

and the output control module is also used for rewriting the buffer descriptor into the free fragment FIFO if the registration fails, the TT frame is successfully sent or the buffer release is needed.

The buffer descriptor may be rewritten into the free slice FIFO by the buffer release module in fig. 12, fig. 21 is a waveform diagram of the buffer release module according to the embodiment of the present invention, and fig. 22 is a waveform diagram of the free slice FIFO according to the embodiment of the present invention.

Specifically, as shown in fig. 12, the output control module is divided into a unicast output control module and a multicast output control module, and the unicast output control module corresponds to the port one to one. And caching the TT frame in an output buffer area, accessing the TT buffer area according to a transmission schedule table transmitted by the transmission schedule table module, and transmitting the TT frame. The receiving control module arbitrates the internal forwarding request of the TT frame, and sends the request meeting the requirement to the forwarding receiving control module; the forwarding and receiving control module adopts a priority encoder to select a received TT frame from the requests meeting the requirements, if a new application sent by the receiving arbitration control module is received in the process of receiving the TT frame, the TT frame is suspended, a new TT frame is received, and after the reception of the TT frame is finished, the suspended TT frame is preferentially sent; the registry control module completes read-write operation related to the registry, fairly polls related FIFO, and completes registration application or sends scheduling search application; the receiving table item module receives the sending scheduling table and writes sending scheduling information FIFO; the sending scheduling module finishes reading the sending scheduling information FIFO according to the system time, generates a sending window, initiates a sending scheduling table look-up request to the registry control module, and waits for a table look-up result; the cache release module writes a cache descriptor to be released into the free fragment FIFO; the transmission control module acquires a TT frame descriptor from the TT frame transmission FIFO, moves the TT frame from the corresponding fragment buffer area, and transmits the TT frame, and releases the buffer or unlocks the registry entry after the movement is completed, fig. 23 is a waveform diagram of the transmission control module provided by the embodiment of the present invention.

And the single multicast output control module 6 is used for accessing the TT buffer area according to the transmission schedule table transmitted by the transmission schedule table module, selecting and outputting the single broadcast output control module or the output data of the multicast output control module, and transmitting the TT frame at the specified transmission time point.

Specifically, the single-multicast output control module 6 further includes a transmission control module, and the above steps can be completed by the transmission control module, that is, the transmission control module is configured to access the TT buffer according to the transmission schedule sent by the transmission schedule module, and select to output the unicast output control module, or output data of the multicast output control module, and send the TT frame at the specified transmission time point.

The single multicast output control module corresponds to the ports one by one and selects to output the output data of the unicast/multicast output control module. When detecting that the port is one of the destination ports of the virtual multicast port TT frame, outputting the virtual multicast port TT frame; otherwise, outputting the TT frame of the port output control module.

Specifically, the transmission control module is further configured to obtain a buffer descriptor corresponding to the output TT frame from the TT frame transmission FIFO;

the transmission control module is also used for extracting the TT frame from the fragment cache region and transmitting the TT frame at a specified transmission time point;

and the transmission control module is also used for releasing the fragment cache region corresponding to the output TT frame or unlocking the table entry corresponding to the output TT frame in the registry once after the transmission is finished.

The invention aims to provide a time-triggered Ethernet TT service switching device aiming at the defects of the prior art, wherein preemptive receiving is designed to support TT frames with high priority to preempt TT frames with low priority, FIG. 24 is a waveform diagram of preemptive transmission of a 1-port receiving scheduling control module provided by the embodiment of the invention, FIG. 25 is a waveform diagram of preempted 2-port receiving scheduling control module provided by the embodiment of the invention, FIG. 26 is a waveform diagram of preemptive receiving arbitration control module provided by the embodiment of the invention, FIG. 27 is a waveform diagram of preemptive transmission of a forwarding receiving control module provided by the embodiment of the invention, a virtual multicast port is designed to convert a multicast problem into a unicast problem, a scheduler which completes TT frame scheduling according to the increase or deletion of a certain service flow is designed in a registration and table look-up mode, so that the addition or deletion of the certain service flow does not influence other service flows, an improved single-frame TT plane of an input side and output side buffer area is optimally designed, differentiated services are provided for TT flows with different delay requirements, the transmission delay does not influence other scheduling schedules, thereby reducing additional constraint conditions required to be added when scheduling, reducing the switching conditions and switching transmission reliability of the TT and ensuring the transmission of the multiple services.

The method comprises the steps of designing preemptive receiving to support TT frames with high priority to preempt TT frames with low priority, designing a virtual multicast port to convert a multicast problem into a unicast problem, designing a scheduler to complete TT frame scheduling according to a scheduling table in a registration and table look-up mode, enabling the addition or deletion of a certain service flow not to affect other service flows, optimally designing an input side cache region and an output side cache region to improve a single-frame storage type TT plane, providing differentiated services for TT flows with different delay requirements, designating the transmission delay of the TT flow not to affect other TT flows, reducing constraint conditions needing to be additionally added during scheduling planning, reducing the forwarding relevance of scheduling planning and switching hardware, supporting multiple TT service forwarding behaviors, and guaranteeing reliable transmission of TT services.

Fig. 28 is a workflow of a time-triggered ethernet switch TT service switching apparatus according to an embodiment of the present invention, as shown in fig. 28:

1. the system is initialized after being electrified, and enters a working state after the clock synchronization.

The system is electrified for initialization, asynchronous reset synchronous release is completed, and other modules are controlled to execute initialization operation; and entering a working state after the clock is synchronized. And if the system is out of step or the system is reset, resetting operation is carried out.

2. And respectively dispatching the receiving scheduling table and the sending scheduling table to each input control module and each output control module according to the system time.

Further, the step 2 comprises the following steps:

(1) Receiving a dispatch table dispatching flow:

(1) the receiving scheduling table is divided into two stages of table lookup, and when the receiving scheduling information FIFO is not full, the table reading operation is carried out.

(2) And accessing the primary table, wherein the initial address is 0, and sequentially accessing according to the next jump address of the linked list.

(3) And calculating a hash value by taking the TT ID as a key value, and accessing the secondary table by using the hash value.

(4) It is checked whether the TT ID is consistent with the primary table. If the TT IDs are consistent and the access port and the sending port are effective, the inquiry is correct, and the table entries are spliced; if the TT IDs are consistent and the access port and the sending port are invalid, the search is failed; if the TT IDs are inconsistent and the valid field of the linked list is valid, continuing to index by taking the next hop as an address; if the TT IDs are inconsistent and the valid field of the linked list is invalid, the search fails.

(5) And after the information is searched successfully and spliced, dispatching the receiving scheduling table to each input control module.

(2) Sending schedule dispatching flow:

(1) the sending scheduling table is divided into a single-stage table look-up table, and when the FIFO of the sending scheduling information is not full, the table reading operation is carried out.

(2) The initial address is 0, and the access is performed in sequence according to the next hop address of the linked list.

(3) And after the searching is finished, dispatching the sending scheduling table to each output control module.

(3) If the receiving scheduling table is in a single-level table format, a two-level table can be generated.

Step 2 provides a method for searching a receiving schedule table in two stages, because TT frames of the same TT ID can be received for many times in different time in a matrix period, the information of a receiving and sending port, a receiving window and a frame length of the TT frame is the same, and the two stages of table lookup can avoid the access of repeated information and reduce the resource consumption.

3. And the input control module acquires the receiving scheduling table, receives the TT frame according to the receiving scheduling table and stores the TT frame in a receiving buffer area. And forwarding to the corresponding output control module according to the received data sequence.

Further, the step 3 comprises the following steps:

(1) In step 2, the receiving schedule is distributed to the input control module in a broadcast manner, so that whether the entry is received or not needs to be judged according to whether the corresponding port is one of the entry admission ports of the receiving schedule. If receiving, storing into receiving scheduling information FIFO.

(2) According to the system time, the receiving schedule information is read from the receiving schedule information FIFO, and a receiving window is generated according to the receiving time point and the receiving window length. In order to avoid multiple receive window blocking caused by receiving the same TT ID frame reset, each time the receive window counter is reset, a receive statistic pulse is generated to indicate that a new TT frame can be received again, and each time a TT frame is received, a pulse is consumed.

(3) When the TT frame arrives, whether the TT frame is received or not is determined according to whether the receiving window is opened or not. If the TT frame is in the receiving window, caching the data, extracting data information and checking; and if the errors are checked, a receiving window is closed in the receiving process, TT frames exceeding the scheduling requirement are received or a receiving buffer area overflows, judging that the receiving is in errors.

(4) If receiving an error, returning the write address of the input cache area to the initial position of the error frame; if the reception is correct, the reception scheduling information such as the TT frame length is written into the reception scheduling FIFO.

(5) And taking out the scheduling information of the next frame from the receiving scheduling FIFO, sending the TT frame and the scheduling information to a data bus, and monitoring whether a target output control module on the control channel has a feedback signal. If the feedback signal is received, the next TT frame is moved continuously.

Step 3 provides a method for TT frame input buffer, which ensures that a plurality of input ports receive TT services which need to be sent to the same output port at the same time and can not lose frames.

And 4. The TT frame is sent to an output control module of a corresponding port through the full interconnection switching module, the output control module selects one TT frame which is received from the data channels of all the input control modules, and the maximum frame length which can be received is calculated according to the size of the output buffer area. The store-and-forward device adopts a heterotype CIOQ two-stage switching structure, which is based on a Crossbar structure of CIOQ and is added with a virtual multicast port. The multicast frame is sent to the virtual multicast port and forwarded by the virtual multicast port to all ports.

Further, the step 4 comprises the following steps:

(1) If there is no TT frame being transmitted, the sending time is not required, and only the length of the TT frame is required. But this may require multiple TT frames, with the priority encoder determining the TT frames to transmit.

(2) If there is TT frame being transmitted and there are multiple input channels applying for sending, then the time of applying for sending is compared in parallel, and the sending time less than the current frame being transmitted is found.

(3) When a new TT frame meets the sending condition and is more urgent than the current TT frame in the receiving process, the receiving of the current TT frame is suspended, the receiving state of the current frame is suspended, the suspension of the receiving state is completed by adopting a last-in-first-out (LIFO) structure, and the more urgent frame is received.

(4) When a TT frame is finished transmitting, whether there is a suspended TT frame is checked firstly, if there is a TT frame, the TT frame is transmitted preferentially.

And 4, a special CIOQ two-stage switching structure is adopted, the mixed scheduling of unicast and multicast is avoided, a preemptive receiving mode is provided, the internal forwarding of TT frames with urgent sending time is guaranteed, and the complexity of a scheduling algorithm is reduced.

And 5, after the TT frame is cached in the output buffer area, performing 'registration' operation, and recording the position of the TT frame in the buffer area for sending the index of the TT frame during scheduling.

Further, the step 5 comprises the following steps:

(1) And using the receiving time point of the TT frame and the splicing value of the TT ID as an identifier, using two different hash functions to obtain hash values, and using the two hash values to respectively index the registry A and the registry B to obtain iteMA and iteMB.

(2) And if the iteMA and the iteMB are both empty, writing the registration information into the iteMA.

(3) If iteMA or iteMB has the current registration value, checking whether the list item is locked:

(1) if not locked, the original information in the table entry is written into the registration failure FIFO, and the current registration value is written into the table entry.

(2) If the current registered value is locked, the current registered value is written into the waiting unlocking FIFO, which indicates that the old TT frame is scheduled but has not finished transmitting.

(3) If the locking is already carried out and the unlocking FIFO is full, the current registration value is written into the registration failure FIFO.

(4) If only one of iteMA and itemB is empty and the empty table entry does not accord with the current registration information, the current registration value is written into the empty table entry.

(5) And if the iteMA and iteMB are both not empty and occupied by other registration information, judging that the registration fails, and writing the current registration value into a registration failure FIFO.

6. And when the local is directly close to the sending time, the sending information is obtained from the sending scheduling information FIFO, and the sending scheduling search is carried out.

Further, the step 6 comprises the following steps:

(1) And using the receiving time point of the TT frame and the splicing value of the TT ID as identification, using two different hash functions to obtain hash values, and using the two hash values to respectively index the registry A and the registry B to obtain iteMA and itemB.

(2) And if neither iteMA nor iteMB has the registration value, the feedback search fails.

(1) and if the user needs to log off, writing an invalid table entry into the searched table entry, and feeding back a search result.

(2) If not, updating the rest sending ports, locking the list item once, and feeding back the search result.

(4) A lookup failure does not mean a scheduling failure and it can be decided whether to initiate lookup again according to the transmission window.

And 5, steps 6 provide a scheduler for registering and table look-up indexing, so that the scheduling flexibility is improved, and the addition and deletion of a certain data flow table entry cannot influence other data flows.

7. The output cache region adopts SRAM to realize the partitioned cache region, and indexes the cache region through the cache descriptor.

Further, the step 7 includes the steps of:

(1) In the initial state, the buffer descriptors are stored in the free fragmentation FIFO.

(2) When TT frames need to be stored, obtaining the buffer descriptor from the free slice FIFO.

(3) And (4) failing to register, successfully sending the TT frame and needing buffer release, and rewriting the buffer descriptor into the free fragment FIFO.

And step 7, the output side cache is managed by adopting a cache fragmentation mode, so that the cache utilization rate is improved, and a plurality of TT frames can be cached.

8. And accessing the TT buffer area according to the sending schedule table sent by the sending schedule table module, selecting and outputting the output data of the unicast/multicast output control module, and sending the TT frame at the specified sending time point.

Further, the step 8 includes the steps of:

(1) The transmission control module acquires the buffer descriptor from the TT frame transmission FIFO.

(2) And extracting the TT frame from the fragment buffer area, and sending out the TT frame at a specified sending time point.

(3) And after the transmission is finished, releasing the cache region or unlocking the corresponding table entry in the registry once.

Fig. 29 is a schematic diagram of a forwarding behavior of a TT frame that can be supported by the TT service switching apparatus of the time-triggered ethernet switch according to the embodiment of the present invention, and as shown in fig. 10, a TT plane of a single-frame buffer can complete sequential TT service forwarding without overlapping, but a transmission buffer area needs to support multi-frame buffering when sequential TT services are overlapped. The reverse order is the reverse order of the different TT ID frames. Input collision means that TT frames sent to the same output port exist in different input ports at the same time. The mutual forwarding means that TT frames input by different input ports at the same time are forwarded to different ports. The output conflict means that TT frames input successively by the same input port need to be sent to different output ports at the same time. Simultaneous multicast means that multicast TT frames need to be sent to all output ports at the same time. Time-shared multicast means that multicast TT frames need to be sent to all output ports at different times.

The TT service switching plane of the time-triggered Ethernet switch provided by the invention supports TT frames with high priority to preempt TT frames with low priority, designs a virtual multicast port to convert multicast problems into unicast problems, designs a scheduler for completing TT frame scheduling according to the scheduling table in a registration and table look-up mode, improves a single-frame storage type TT plane, and optimally designs buffer areas at an input side and an output side.

Compared with the prior art, the method has the following technical effects:

(1) An input side cache is added, and a plurality of input ports receive TT services needing to be sent to the same output port at the same time without losing frames;

(2) The output side cache is managed by adopting a cache fragmentation mode, the cache utilization rate is improved, a plurality of TT frames can be cached, and when the output port is sending the TT frames, new TT frames which are received by the input port and need to be sent to the output port cannot be discarded.

(3) And a preemptive internal forwarding mechanism is adopted, the TT frame with more urgent sending time is received preferentially, and the TT frame can reach the sending buffer in time and be scheduled correctly.

(4) The design realizes an opposite sex CIOQ switching structure, increases virtual multicast output ports, converts the multicast problem into the unicast problem, and solves the problem that the multicast frame can not miss the sending time point because the scheduling can be carried out only by waiting for all the output ports to be idle.

(5) And the receiving of TT frames with the same TT ID is supported, and the 'sticky' receiving window is allowed to receive the specified number of TT frames.

(6) The output scheduling is carried out by adopting a method of registration and table lookup, the scheduling flexibility is improved, the scheduling planning and the switching hardware forwarding design are decoupled, and the probability of the failure of generating the complex network topology scheduling table is reduced.

(7) The receiving scheduling table and the sending scheduling table are designed by adopting a linked list, the configuration of the dynamic scheduling table is supported, and the addition and deletion of a certain data flow table entry cannot influence other data flows.

(8) The transmission order of the TT frames depends only on the transmission schedule, and the TT frames can stay for any time. The method provides differentiated service for TT flows with different delay requirements, and transmission delay of the TT flow is not influenced by other TT flows.

In the description of the present invention, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.

In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic data point described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples described in this specification can be combined and combined by those skilled in the art.

The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.

Claims

1. A time-triggered ethernet switch, TT, traffic switching apparatus, the apparatus comprising:

the all-interconnection switching control module is used for completing the connection between the input control module and the output control module and sending the TT frame cached in the input cache region to the corresponding output control module;

2. The time-triggered Ethernet switch TT traffic switching apparatus of claim 1,

the receiving scheduling module is also used for reading the table when the receiving scheduling information FIFO is detected to be not full;

the receiving scheduling table module is further configured to read each table entry in the receiving scheduling primary table in sequence, where the receiving scheduling primary table is read from a table entry with a start address of 0, and each receiving scheduling primary table is sequentially accessed according to a next hop address of a linked list in each table entry;

the receiving and dispatching table module is further configured to calculate a hash value for a key value of a first TT ID in each entry in the receiving and dispatching primary table, and access each entry in the receiving and dispatching secondary table with the hash value respectively;

the receiving scheduling table module is further used for checking whether a second TT ID in an item accessed in the receiving scheduling secondary table is consistent with the first TT ID in the item of the receiving scheduling primary table;

if the second TT ID is not consistent with the first TT ID and the valid field of the linked list in the receiving and dispatching primary table is invalid, the searching is failed;

3. The time-triggered Ethernet switch TT traffic switching apparatus of claim 1,

4. The time-triggered Ethernet switch (TT) traffic switching apparatus of claim 1,

5. The time-triggered Ethernet switch TT traffic switching apparatus of claim 1,

the output control module is also used for pausing the receiving of the current TT frame if a new TT frame meets the sending condition and the sending time is closer to the current time than the sending time of the current TT frame in the process of receiving the TT frame, suspending the receiving state of the current TT frame, finishing the suspension of the receiving state by adopting a last-in first-out structure and starting to receive the more urgent TT frame;

the output control module is further configured to, after the TT frame is completely transmitted, first check whether there is a suspended TT frame, and if there is a suspended TT frame, preferentially transmit the suspended TT frame.

6. The time-triggered Ethernet switch (TT) traffic switching apparatus of claim 1,

the output control module is further configured to use the receiving time point of the TT frame and the spliced value of the TT ID as identifiers, use two different hash functions to obtain hash values, and use the two hash values to respectively index the first registry and the second registry to obtain a first entry and a second entry;

7. The time-triggered Ethernet switch TT traffic switching apparatus of claim 1,

the output control module is also used for writing the invalid table entry in the searched table entry and feeding back the search result if the log-out is required;

8. The time-triggered Ethernet switch TT traffic switching apparatus of claim 1,

9. The time-triggered Ethernet switch TT traffic switching apparatus of claim 1,

the single multicast output control module is further configured to release the partitioned cache area of the output TT frame for drinking after the transmission is completed, or unlock the entry corresponding to the output TT frame in the registry once.