CN115378566B - Time offset correction method, FPGA and communication receiving equipment - Google Patents
Time offset correction method, FPGA and communication receiving equipment Download PDFInfo
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- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
- H04L7/002—Arrangements for synchronising receiver with transmitter correction of synchronization errors correction by interpolation
- H04L7/0029—Arrangements for synchronising receiver with transmitter correction of synchronization errors correction by interpolation interpolation of received data signal
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
- H04L7/0033—Correction by delay
- H04L7/0037—Delay of clock signal
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
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Abstract
The invention relates to the technical field of communication, and provides a time offset correction method, an FPGA (field programmable gate array) and communication receiving equipment, wherein the FPGA is electrically connected with a signal conversion device and comprises a correction module, an adjustment module and an estimation module; the correction module sequentially receives M signal segments in the digital signal to be processed, which is sent by the signal conversion device, wherein M is a natural number greater than 1; performing time deviation correction on the ith signal segment to obtain the ith first signal segment, wherein i is a natural number which is more than 0 and less than M + 1; then the adjustment module adjusts the ith first signal segment to obtain an ith second signal segment; and finally, the estimation module carries out time deviation estimation on the ith second signal segment to obtain an (i + 1) th time deviation parameter, and the (i + 1) th time deviation parameter is used for carrying out time deviation correction on the (i + 1) th signal segment by the correction module. The signal output by the correction module is adjusted by the adjustment module, so that the error is reduced, and the calculation accuracy is improved.
Description
Technical Field
The invention relates to the technical field of communication, in particular to a time offset correction method, an FPGA and communication receiving equipment.
Background
In a communication receiving system, in the process of sampling an analog signal, the deviation of the sampling clock frequency can cause the digital signal to generate time deviation, thereby influencing the demodulation of the signal. In the process of correcting the time deviation by the traditional FPGA feedback loop, the calculation is inaccurate due to errors.
Disclosure of Invention
In view of the above, the present invention provides a time offset correction method, an FPGA and a communication receiving device.
In order to achieve the purpose, the technical scheme adopted by the invention is as follows:
in a first aspect, the present invention provides a time offset correction method, which is applied to an FPGA, wherein the FPGA is electrically connected to a signal conversion device, the FPGA includes a correction module, an adjustment module, and an estimation module, and the method includes:
the correction module sequentially receives M signal segments in the digital signal to be processed sent by the signal conversion device, wherein M is a natural number greater than 1;
the correction module performs time offset correction on the ith signal segment to obtain the ith first signal segment, wherein i is a natural number which is more than 0 and less than M + 1;
the adjusting module adjusts the ith first signal segment to obtain an ith second signal segment;
the estimation module carries out time deviation estimation on the ith second signal segment to obtain an (i + 1) th time deviation parameter; and the (i + 1) th time deviation parameter is used for the correction module to carry out time deviation correction on the (i + 1) th signal segment.
In an alternative embodiment, the ith signal segment includes a plurality of signal data therein;
the step of correcting the time deviation of the ith signal segment by the correction module to obtain the ith first signal segment comprises the following steps:
the correction module acquires an ith time deviation parameter;
the correction module performs interpolation processing on all signal data in the ith signal segment based on the ith time deviation parameter and a first preset algorithm to obtain each interpolation point;
and the correction module performs resampling processing on the ith signal segment based on each interpolation point to obtain the ith first signal segment.
In an optional implementation manner, the step of performing, by the estimation module, time offset estimation on the ith second signal segment to obtain an i +1 th time offset parameter includes:
the estimation module estimates the time deviation of the ith second signal segment based on a second preset algorithm to obtain an (i + 1) th initial deviation parameter;
and the estimation module carries out smoothing processing on the (i + 1) th initial deviation parameter to obtain the (i + 1) th time deviation parameter.
In an alternative embodiment, the ith first signal segment comprises a plurality of signal data;
the adjusting module adjusts the ith first signal segment to obtain an ith second signal segment, and the adjusting module comprises:
the adjusting module obtains an adjusting parameter based on the time delay parameter and a preset data rate;
the time delay parameter represents the time length of processing a signal segment by the FPGA; the preset data rate represents the number of signal data received by the correction module in a preset unit time; the adjustment parameter represents the number of signal data to be adjusted;
and the adjusting module adjusts the ith first signal segment based on the adjusting parameter to obtain the ith second signal segment.
In an optional implementation manner, the step of obtaining, by the adjusting module, an adjustment parameter based on the delay parameter and the preset data rate includes:
the adjusting module acquires a preset clock frequency, a preset delay parameter and the preset data rate;
wherein the preset clock frequency represents the reciprocal of a preset clock period; the preset delay parameter represents a multiple of a preset clock period used by the FPGA for processing a signal segment;
the adjusting module calculates based on the preset clock frequency, the preset delay parameter and the preset data rate according to a preset formula to obtain the adjusting parameter;
the preset formula is as follows:
t=k/clk；
n=floor(t*R)；
wherein k represents a preset delay parameter; clk represents a preset clock frequency; t represents a delay parameter; r represents a preset data rate; n represents an adjustment parameter; floor denotes taking the integer downwards.
In an optional implementation manner, the adjusting module adjusts the ith first signal segment based on the adjustment parameter to obtain the ith second signal segment, including:
and the adjusting module sets the first n signal data in the ith first signal segment to zero to obtain the ith second signal segment, wherein n is equal to the adjusting parameter.
In a second aspect, the present invention provides an FPGA, the FPGA being electrically connected to a signal conversion device, the FPGA comprising a correction module, an adjustment module and an estimation module;
the correction module is used for sequentially receiving M signal segments in the digital signal to be processed sent by the signal conversion device, wherein M is a natural number greater than 1; carrying out time deviation correction on the ith signal segment to obtain the ith first signal segment, wherein i is a natural number which is more than 0 and less than M + 1;
the adjusting module is used for adjusting the ith first signal segment to obtain an ith second signal segment;
the estimation module is used for carrying out time deviation estimation on the ith second signal segment to obtain an (i + 1) th time deviation parameter; and the (i + 1) th time deviation parameter is used for the correction module to carry out time deviation correction on the (i + 1) th signal segment.
In an alternative embodiment, the ith signal segment includes a plurality of signal data therein; the correction module is specifically configured to:
acquiring an ith time deviation parameter;
performing interpolation processing on all signal data in the ith signal segment based on the ith time deviation parameter and a first preset algorithm to obtain each interpolation point;
and resampling the ith signal segment based on each interpolation point to obtain the ith first signal segment.
In an alternative embodiment, the estimation module is specifically configured to:
estimating the time deviation of the ith second signal segment based on a second preset algorithm to obtain an (i + 1) th initial deviation parameter;
and performing smoothing processing on the (i + 1) th initial deviation parameter to obtain the (i + 1) th time deviation parameter.
In a third aspect, the present invention provides a communication receiving apparatus comprising signal conversion means and an FPGA according to any one of the preceding embodiments.
According to the time deviation correction method, the FPGA and the communication receiving equipment, the FPGA is electrically connected with the signal conversion device and comprises a correction module, an adjustment module and an estimation module; the correction module sequentially receives M signal segments in the digital signal to be processed, which is sent by the signal conversion device, wherein M is a natural number greater than 1; performing time deviation correction on the ith signal segment to obtain the ith first signal segment, wherein i is a natural number which is more than 0 and less than M + 1; then the adjustment module adjusts the ith first signal segment to obtain an ith second signal segment; and finally, the estimation module carries out time deviation estimation on the ith second signal segment to obtain an (i + 1) th time deviation parameter, and the (i + 1) th time deviation parameter is used for carrying out time deviation correction on the (i + 1) th signal segment by the correction module. The signal output by the correction module is adjusted by the adjusting module, so that the estimation module carries out time deviation estimation based on the adjusted signal, thereby reducing errors and improving the accuracy of calculation.
In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
FIG. 1 shows a schematic diagram of a prior art FPGA feedback loop architecture;
FIG. 2 illustrates an exemplary diagram of a prior art time offset correction method;
FIG. 3 is a schematic diagram illustrating an FPGA feedback loop structure provided by an embodiment of the present invention;
FIG. 4 is a flow chart illustrating a method for time offset correction according to an embodiment of the present invention;
FIG. 5 is a second flowchart of the time offset calibration method according to the embodiment of the present invention;
FIG. 6 is a third schematic flow chart of a time offset correction method according to an embodiment of the present invention;
FIG. 7 is a fourth flowchart illustrating a time offset calibration method according to an embodiment of the present invention;
FIG. 8 is a diagram illustrating an example of a time offset correction method provided by an embodiment of the present invention;
fig. 9 is a block diagram of a communication receiving device according to an embodiment of the present invention.
Icon: 100-a communication receiving device; 110-signal conversion means; 120-FPGA.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present invention without making any creative effort, shall fall within the protection scope of the present invention.
It is noted that relational terms such as "first" and "second," and the like, may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising a … …" does not exclude the presence of another identical element in a process, method, article, or apparatus that comprises the element.
In a communication receiving system, in the process of sampling an analog signal, a deviation of a sampling clock frequency can cause a time deviation of a digital signal, and the signal recovery based on the digital signal can cause signal distortion, thereby affecting the demodulation effect of the signal. Currently, the FPGA feedback loop structure shown in fig. 1 is generally used to correct the time offset. The inventor finds that, as the FPGA needs a certain time to process data, that is, there is a time delay, an error is generated, and the calculation is inaccurate, which will be described in detail with reference to fig. 1.
As shown in fig. 1, the fpga includes a module 1 and a module 2, and a plurality of data blocks are sequentially input to the module 1, and each data block includes a plurality of data. Module 1 according to ith parameter output from module 2, for ith input data block
Processing and outputting the ith data block
(ii) a Module 2 outputs the ith data block according to module 1
Calculating the (i + 1) th parameter
And transmits to the module 1 to enable the module 1 to work according to the (i + 1) th parameter
For the (i + 1) th input data block
And (6) processing. That is, the module 2 calculates the parameters of the data block acting on the next input module 1 according to the data block currently output by the module 1, thereby realizing feedback.
Since the module 2 is based on data blocks
Calculating parameters
A certain time is required, which may occur when the module 1 receives the parameters
Time, data block
Has passed through module 1, and therefore the data block output by module 1
Presence is not based on parameters
And (4) calculating the obtained data.
For ease of understanding, reference will now be made to FIG. 2. For example, the module 1 is based on parameters
For input data block
Processing and outputting the data block
And transmitted to module 2, and then module 1 starts to process the incoming data block
Carrying out treatment; however, in this case, the module 2 does not calculate the parameters
So that the module 1 remains dependent on the parameters
For data block
Carrying out treatment; when module 1 processes to the data block
When the a-th data in (1), the module 2 calculates the parameters
And transmitted to the module 1, and then the module 1 is based on the parameters
For data block
Processing the rest data to input data block
. Due to the data block
Wherein the partial data is composed of parameters
Calculated, and therefore result in a block based data
Calculated parameters
There are errors that accumulate multiple times in the feedback structure, resulting in inaccurate calculations.
Further, an embodiment of the present invention provides a time offset correction method, which is applied to the FPGA feedback loop structure shown in fig. 3. Fig. 3 is a schematic diagram of a feedback loop structure of an FPGA according to an embodiment of the present invention, where the FPGA includes a correction module, an adjustment module, and an estimation module. Compared with the existing FPGA feedback loop structure, the structure provided by the embodiment of the present invention adds an adjustment module between the correction module (which may be regarded as module 1) and the estimation module (which may be regarded as module 2), and the adjustment module is used for adjusting an error generated in the time offset correction process, so as to reduce the influence caused by the time delay.
The following describes a time offset correction method provided by an embodiment of the present invention with an FPGA feedback loop structure shown in fig. 3. Referring to fig. 4, fig. 4 is a flowchart illustrating a time offset calibration method according to an embodiment of the invention.
Step S202, a correction module receives M signal segments in the digital signal to be processed sent by a signal conversion device in sequence, wherein M is a natural number greater than 1;
in this embodiment, the FPGA is electrically connected to a signal conversion device, and the signal conversion device converts the received analog signal into a digital signal, i.e., a to-be-processed digital signal, and transmits the to-be-processed digital signal to the FPGA. The digital signal to be processed comprises a plurality of signal segments, namely M signal segments. And a correction module in the FPGA receives each signal segment in the digital signal to be processed in sequence.
Step S204, a correction module performs time deviation correction on the ith signal segment to obtain the ith first signal segment, wherein i is a natural number which is more than 0 and less than M + 1;
in this embodiment, the correction module performs time offset correction on each received signal segment to obtain a first signal segment corresponding to each signal segment.
As shown in FIG. 3, the calibration module receives a plurality of signal segments in sequence, e.g., in the form of a plurality of chips
(ii) a When the correction module receives the ith signal segment
For the ith signal segment
Correcting time deviation to obtain the ith signal segment
The corresponding first signal segment, i.e. the ith first signal segment
And dividing the ith first signal segment
And transmitting the data to an adjusting module.
It can be understood that each signal segment received by the correction module can be regarded as input data of the FPGA, and each first signal segment output by the correction module can be regarded as output data of the FPGA, that is, the correction module can transmit the first signal segment to the adjustment module and also can transmit the first signal segment to other devices connected to the FPGA, so that the other devices process according to the first signal segment.
Step S206, the adjustment module adjusts the ith first signal segment to obtain an ith second signal segment;
in this embodiment, the adjusting module adjusts each received first signal segment to obtain a second signal segment corresponding to each first signal segment.
As shown in FIG. 3, when the adjusting module receives the ith first signal segment
For the ith first signal segment
Adjusting to obtain the ith first signal
Corresponding second, i.e. ith, second signal segment
And segmenting the ith second signal
And transmitting to an estimation module.
Step S208, the estimation module carries out time deviation estimation on the ith second signal segment to obtain an (i + 1) th time deviation parameter; the (i + 1) th time deviation parameter is used for correcting the time deviation of the (i + 1) th signal segment by the correction module;
in this embodiment, the estimation module performs time offset estimation on each received second signal segment to obtain a time offset parameter corresponding to each second signal segment.
As shown in FIG. 3, when the estimation module receives the ith second signal segment
For the ith second signal segment
Estimating the time deviation to obtain the ith second signal segment
Corresponding time deviation parameter i +1 th time deviation parameter
And the (i + 1) th time deviation parameter
Transmitting to the correction module to base the correction module on the (i + 1) th time deviation parameter
For the (i + 1) th signal segment
Time offset correction is performed.
Based on the steps, the correction module sequentially receives M signal segments in the digital signal to be processed, which is sent by the signal conversion device, wherein M is a natural number greater than 1; performing time deviation correction on the ith signal segment to obtain the ith first signal segment, wherein i is a natural number which is more than 0 and less than M + 1; then an adjusting module adjusts the ith first signal segment to obtain an ith second signal segment; and finally, the estimation module carries out time deviation estimation on the ith second signal segment to obtain an (i + 1) th time deviation parameter, and the (i + 1) th time deviation parameter is used for carrying out time deviation correction on the (i + 1) th signal segment by the correction module. The signal output by the correction module is adjusted by the adjusting module, so that the estimation module carries out time deviation estimation based on the adjusted signal, thereby reducing errors and improving the accuracy of calculation.
Optionally, regarding step S204, a possible implementation manner is provided in the embodiment of the present invention, please refer to fig. 5, where step S204 may include the following steps:
step S204-1, a correction module acquires an ith time deviation parameter;
in this embodiment, when i is 1, the calibration module obtains a1 st time deviation parameter, where the 1 st time deviation parameter is a preset value, i.e. a preset value. And when the i is a natural number which is larger than 1 and smaller than M +1, the correction module acquires an ith time deviation parameter, wherein the ith time deviation parameter is a time deviation parameter obtained based on the (i-1) th signal segment.
S204-3, the correction module performs interpolation processing on all signal data in the ith signal segment based on the ith time deviation parameter and a first preset algorithm to obtain each interpolation point;
in the present embodiment, each signal segment includes a plurality of signal data; the first preset algorithm may be a lagrangian interpolation algorithm; the correction module may be an interpolator. The correction module may be based on the ith time offset parameter
And Lagrange interpolation algorithm for the ith signal segment
And performing interpolation processing on all the signal data to obtain each interpolation point.
Step S204-5, the correction module performs resampling processing on the ith signal segment based on each interpolation point to obtain the ith first signal segment;
in this embodiment, the correction module is based on the ith signal segment
Determines the optimal sampling time, and determines the ith signal segment based on the optimal sampling time
Resampling to obtain the ith first signal segment
。
It will be appreciated that a sampling clock frequency deviation, i.e. a sampling instant is not accurate, which may result in distortion of the signal recovered from the sampled digital signal. The correction module obtains interpolation points through carrying out interpolation processing on the signal segments, determines that the best sampling moment carries out resampling on the signal segments, compensates sampling clock frequency deviation, corrects time deviation, can avoid signal distortion through resampling, and therefore improves the demodulation effect of signals.
Optionally, for the step S208, the embodiment of the present invention provides a possible implementation manner. Referring to fig. 6, step S208 may include the following steps:
s208-1, the estimation module estimates the time deviation of the ith second signal segment based on a second preset algorithm to obtain an (i + 1) th initial deviation parameter;
in this embodiment, the second preset algorithm may be O&M algorithm, which is a timing error detection algorithm based on non-data assistance. The estimation module may be based on O&M algorithm for ith second signal segment
The time deviation is estimated to obtain the (i + 1) th initial deviation parameter.
And step S208-3, the estimation module carries out smoothing processing on the (i + 1) th initial deviation parameter to obtain an (i + 1) th time deviation parameter.
In this embodiment, the estimation module may include a smoothing filter, and the (i + 1) th initial offset parameter is smoothed by the smoothing filter to obtain the (i + 1) th time offset parameter
. The estimation module is used for calculating the (i + 1) th time deviation parameter
Transmitting to the correction module to make the correction module based on the (i + 1) th time deviation parameter
For the i +1 th signal segment
Time offset correction is performed.
As can be seen, the estimation module estimates the time deviation of the ith second signal segment based on a second preset algorithm to obtain an (i + 1) th initial deviation parameter, and performs smoothing processing on the (i + 1) th initial deviation parameter to obtain an (i + 1) th time deviation parameter. Namely, the estimation module carries out time deviation estimation based on the second signal segment adjusted by the adjustment module, thereby reducing errors and improving the accuracy of time deviation estimation.
Optionally, for the step S206, the embodiment of the present invention provides a possible implementation manner. Referring to fig. 7, step S206 may include the following steps:
step S206-1, the adjusting module obtains an adjusting parameter based on the time delay parameter and the preset data rate;
the time delay parameter represents the time length of processing a signal segment by the FPGA; the preset data rate represents the number of signal data received by the correction module in a preset unit time; the adjustment parameter indicates the number of signal data to be adjusted.
And S206-3, adjusting the ith first signal segment by the adjusting module based on the adjusting parameter to obtain the ith second signal segment.
It will be appreciated that in an ideal feedback loop, the correction module processes the received signal segments in real time based on the corresponding time offset parameter, i.e. all signal data in the ith signal segment is processed by the ith time offset parameter. However, as described in fig. 1, a delay occurs when data is actually processed by the FPGA, and the delay is a time duration, i.e., a delay parameter, used by the FPGA to process one signal segment.
In this embodiment, the time duration for processing a signal segment by the FPGA is preset, i.e., the delay parameter is preset. The preset data rate may be given by the means for transmitting signals to the FPGA. For example, the signal conversion device transmits the digital signal to be processed to the FPGA, and the preset data rate may be understood as the number of signal data input to the correction module by the signal conversion device in a preset unit time, such as b signal data per second.
The adjusting module calculates adjusting parameters based on the time delay parameters and the preset data rate. If the adjusting module multiplies the time delay parameter by the preset data rate, the adjusting parameter is obtained. The adjustment parameter may be understood as the number of signal data affected by the time delay in one signal segment, that is, the number of signal data to be adjusted. As shown in fig. 1, one data block is regarded as one signal segment, and a signal segment has a signal data affected by the time delay.
The adjusting module adjusts the ith first signal segment based on the adjusting parameter to obtain the ith second signal segment. It can be understood that, the adjusting module transmits the adjusted second signal segment to the estimating module, which can ensure the accuracy of the time deviation parameter calculated by the estimating module.
Optionally, for the step S206-1, the embodiment of the present invention provides a possible implementation manner, and the step S206-1 may further include the following steps:
step S206-1-1, the adjusting module obtains a preset clock frequency, a preset delay parameter and a preset data rate;
wherein the preset clock frequency represents the reciprocal of the preset clock period; the preset delay parameter represents a multiple of a preset clock period used by the FPGA to process one signal segment.
The preset clock period can be understood as the minimum time unit set in the communication system where the FPGA is located. For example, the minimum time unit is 1ms, i.e. the predetermined clock period is 1ms, and the predetermined clock frequency is the reciprocal of the predetermined clock period, i.e. 1000Hz.
The preset delay parameter can be understood as the number of cycles used by the FPGA to process one signal segment, i.e. how many preset clock cycles are required to process one signal segment. The magnitude of the pre-set delay parameter is related to the logic circuit implementing the correction module and the estimation module.
Step S206-1-3, calculating by the adjusting module according to a preset formula based on a preset clock frequency, a preset delay parameter and a preset data rate to obtain an adjusting parameter;
wherein, the preset formula is as follows: t = k/clk; n = floor (t × R); k represents a preset delay parameter; clk represents a preset clock frequency; t represents a delay parameter; r represents a preset data rate; n represents an adjustment parameter; floor denotes the downward integer.
In this embodiment, the adjusting module obtains a preset clock frequency, a preset delay parameter and a preset data rate, and calculates according to a preset formula to obtain an adjusting parameter. If the adjusting module calculates the quotient of the preset delay parameter and the preset clock frequency, a time delay parameter is obtained; and calculating the product of the time delay parameter and the preset data rate to obtain an adjustment parameter.
For example, the preset clock frequency clk =160MHz, the preset delay parameter k =10, and the preset data rate R =80MHz. The adjusting module calculates according to a preset formula to obtain an adjusting parameter n of 5, that is, 5 signal data affected by time delay in one signal segment, and 5 signal data to be adjusted.
Optionally, as for the step S206-3, the embodiment of the present invention provides a possible implementation manner, that is, the adjusting module sets zero to the first n signal data in the ith first signal segment to obtain the ith second signal segment, where n is equal to the adjusting parameter.
In this embodiment, the adjusting module may include a counter and a data selector, and the counter counts the number of the signal data received in the ith first signal segment to obtain a statistical value, and transmits the statistical value to the data selector. And the data selector sets the first n signal data in the ith first signal segment to 0 according to the received statistical value, and the residual signal data are unchanged to obtain the ith second signal segment.
For example, the ith first signal segment
Including N signal data such as
The adjusting module is used for dividing the ith first signal segment
The first n signal data in the sequence are set to zero to obtain the ith second signal segment
Is composed of
。
The adjusting module is used for dividing the first signal segment into a plurality of signal segments
Is to be understood as the first n signal segments are zeroed out
Is not determined by a time offset parameter
Setting all the obtained signal data to be 0; the remaining N-N signal data are kept unchanged, which is understood to mean that the first signal segment is formed
Middle time deviation parameter
All the signal data obtained by processing are kept unchanged to obtain a second signal segment
. The adjusting module is used for dividing the second signal segment into two signal segments
The transmission to the estimation module, which is not affected by the time delay, can be based on the parameter of the total time deviation
Treating the obtained secondSignal segment
And the estimation is carried out, so that the error generated by time delay is reduced, and the calculation accuracy is ensured.
In order to facilitate better understanding of the present invention, the embodiment of the present invention compares an effect of implementing time offset correction by using an existing FPGA feedback loop structure with an effect of implementing time offset correction by using an FPGA feedback loop structure provided by the present invention. For example, assume that the sampling clock frequency, i.e., the preset clock frequency, is 160mhz, the clock frequency deviation caused by adc sampling is 1000ppm, the preset data rate is 80MHz, the modulation scheme is QPSK, the window length of time deviation estimation is N =1024 symbols, and the signal-to-noise ratio is snr
The quantization bit number of the data signal is 8 bits.
And (3) performing time deviation correction simulation by using a simulation tool such as Matlab according to the set parameter values to obtain output data, wherein the output data is accurate and can be used as a standard value because the simulation has no error in the hardware implementation process. Then, the output data of the time deviation correction realized by adopting the existing FPGA feedback loop structure and the output data of the time deviation correction realized by the FPGA feedback loop structure provided by the invention are respectively obtained based on the set parameter values. And calculating the difference between the output data in the prior art and the simulated output data to obtain a parameter P1, and calculating the difference between the output data in the invention and the simulated output data to obtain a parameter P2. The result shown in fig. 8 can be obtained based on the parameters P1 and P2.
Based on fig. 8, it can be seen that the curve of the parameter P1 obtained according to the prior art is approximately vertically symmetrical with respect to the straight line where the ordinate value is-15, that is, the average value of the parameter P1 of the prior art is close to-15, and the minimum value of the parameter P1 is close to-25 and the maximum value is close to 10, that is, the fluctuation range of the parameter P1 is large, and then the difference between the output data of the prior art and the simulated standard value is large, that is, a large error exists in the prior art.
The curve of the parameter P2 obtained according to the present invention is approximately vertically symmetrical with respect to the straight line where the ordinate value is 0, that is, the average value of the parameter P2 of the present invention is close to 0, and the minimum value of the parameter P2 is close to-5 and the maximum value is close to 5, that is, the fluctuation range of the parameter P2 is small, then the difference between the output data of the present invention and the simulated standard value is small, that is, the error of the present invention is small.
In order to execute the corresponding steps in the above embodiments and various possible manners, an implementation manner of the FPGA is given below. It should be noted that the basic principle and the generated technical effect of the FPGA provided in this embodiment are the same as those of the foregoing embodiment, and for the sake of brief description, no part of this embodiment is mentioned, and corresponding contents in the foregoing embodiment may be referred to. The FPGA comprises:
the correction module is used for sequentially receiving M signal sections in the digital signal to be processed, which is sent by the signal conversion device, wherein M is a natural number greater than 1; carrying out time deviation correction on the ith signal segment to obtain the ith first signal segment, wherein i is a natural number which is more than 0 and less than M + 1;
the adjusting module is used for adjusting the ith first signal segment to obtain an ith second signal segment;
the estimation module is used for carrying out time deviation estimation on the ith second signal segment to obtain an (i + 1) th time deviation parameter; the (i + 1) th time deviation parameter is used for correcting the time deviation of the (i + 1) th signal segment by the correction module.
Optionally, the correction module is specifically configured to: acquiring an ith time deviation parameter; performing interpolation processing on all signal data in the ith signal segment based on the ith time deviation parameter and a first preset algorithm to obtain each interpolation point; and resampling the ith signal segment based on each interpolation point to obtain the ith first signal segment.
Optionally, the estimation module is specifically configured to: estimating the time deviation of the ith second signal segment based on a second preset algorithm to obtain an (i + 1) th initial deviation parameter; and smoothing the (i + 1) th initial deviation parameter to obtain an (i + 1) th time deviation parameter.
Optionally, the adjusting module is specifically configured to: obtaining an adjustment parameter based on the time delay parameter and a preset data rate; the time delay parameter represents the time length of processing a signal segment by the FPGA; the preset data rate represents the number of signal data received by the correction module in a preset unit time; the adjustment parameter represents the number of signal data to be adjusted; and adjusting the ith first signal segment based on the adjustment parameters to obtain the ith second signal segment.
Optionally, the adjusting module is specifically configured to: acquiring a preset clock frequency, a preset delay parameter and a preset data rate; wherein the preset clock frequency represents the reciprocal of the preset clock period; the preset delay parameter represents a multiple of a preset clock period used by the FPGA for processing a signal segment;
calculating based on a preset clock frequency, a preset delay parameter and a preset data rate according to a preset formula to obtain an adjustment parameter;
the preset formula is as follows:
t=k/clk；
n=floor(t*R)；
wherein k represents a preset delay parameter; clk represents a preset clock frequency; t represents a time delay parameter; r represents a preset data rate; n represents an adjustment parameter; floor denotes taking the integer downwards.
Optionally, the adjusting module is specifically configured to: and setting the first n signal data in the ith first signal segment to zero to obtain the ith second signal segment, wherein n is equal to the adjusting parameter.
It can be understood that the correction module and the estimation module in the FPGA provided in the embodiment of the present invention may be replaced with other functional modules according to actual applications, for example, the correction module is replaced with the module a, and the estimation module is replaced with the module B. The FPGA feedback loop structure provided by the embodiment of the invention is formed based on the module A, the module B and the adjusting module, and can be used for solving the phase deviation correction and the frequency deviation correction of a received signal in a communication receiving system. It should be noted that the module a and the module B are configured according to practical applications to implement corresponding functions.
Referring to fig. 9, which is a block schematic diagram of a communication receiving apparatus according to an embodiment of the present invention, a communication receiving apparatus 100 includes a signal conversion device 110 and an FPGA120, and the signal conversion device 110 is electrically connected to the FPGA 120.
The signal conversion device 110 is used for converting a received analog signal into a digital signal, and may include a sampling module and a matched filtering module. The sampling module is used for sampling the received analog signal, and optionally, the sampling module may be an ADC sampler. The matched filtering module is configured to perform noise suppression on the sampled signal, and optionally, the matched filtering module may be a root-raised cosine matched filter.
The FPGA120 is used to correct time offsets of the digital signals, which can also be understood as timing synchronization. The FPGA120 includes a correction module, an adjustment module, and an estimation module, and can perform the corresponding steps in the above embodiments.
It is to be understood that the structure shown in fig. 9 is merely a schematic structure of the communication receiving device, and the communication receiving device may include more or less components than those shown in fig. 9, or have a different configuration from that shown in fig. 9. The components shown in fig. 9 may be implemented in hardware, software, or a combination thereof.
In summary, the embodiment of the present invention provides a time offset correction method, an FPGA and a communication receiving device, where the FPGA is electrically connected to a signal conversion device and includes a correction module, an adjustment module and an estimation module; the correction module sequentially receives M signal segments in the digital signal to be processed, which is sent by the signal conversion device, wherein M is a natural number greater than 1; performing time deviation correction on the ith signal segment to obtain the ith first signal segment, wherein i is a natural number which is more than 0 and less than M + 1; then an adjusting module adjusts the ith first signal segment to obtain an ith second signal segment; and finally, the estimation module carries out time deviation estimation on the ith second signal segment to obtain an (i + 1) th time deviation parameter, and the (i + 1) th time deviation parameter is used for carrying out time deviation correction on the (i + 1) th signal segment by the correction module. The signal output by the correction module is adjusted by the adjusting module, so that the estimation module carries out time deviation estimation based on the adjusted signal, thereby reducing errors and improving the accuracy of calculation.
In the embodiments provided in the present invention, it should be understood that the disclosed apparatus and method can be implemented in other ways. The apparatus embodiments described above are merely illustrative, and for example, the flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
In addition, the functional modules in the embodiments of the present invention may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (8)
1. A time offset correction method is applied to an FPGA (field programmable gate array), the FPGA is electrically connected with a signal conversion device, the FPGA comprises a correction module, an adjustment module and an estimation module, and the method comprises the following steps:
the correction module sequentially receives M signal segments in the digital signal to be processed sent by the signal conversion device, wherein M is a natural number greater than 1;
the correction module performs time offset correction on the ith signal segment to obtain the ith first signal segment, wherein i is a natural number which is more than 0 and less than M + 1;
the adjusting module adjusts the ith first signal segment to obtain an ith second signal segment;
the estimation module carries out time deviation estimation on the ith second signal segment to obtain an (i + 1) th time deviation parameter; the i +1 th time deviation parameter is used for the correction module to carry out time deviation correction on the i +1 th signal segment;
the ith first signal segment comprises a plurality of signal data;
the step of adjusting the ith first signal segment by the adjusting module to obtain the ith second signal segment includes:
the adjusting module obtains an adjusting parameter based on the time delay parameter and a preset data rate;
the time delay parameter represents the time length of processing a signal segment by the FPGA; the preset data rate represents the number of signal data received by the correction module in a preset unit time; the adjustment parameter represents the number of signal data to be adjusted;
the adjusting module adjusts the ith first signal segment based on the adjusting parameter to obtain the ith second signal segment;
the step of obtaining the adjustment parameter by the adjustment module based on the time delay parameter and the preset data rate comprises the following steps:
the adjusting module acquires a preset clock frequency, a preset delay parameter and the preset data rate;
wherein the preset clock frequency represents the reciprocal of a preset clock period; the preset delay parameter represents a multiple of a preset clock period used by the FPGA for processing a signal segment;
the adjusting module calculates based on the preset clock frequency, the preset delay parameter and the preset data rate according to a preset formula to obtain the adjusting parameter;
the preset formula is as follows:
t=k/clk；
n=floor(t*R)；
wherein k represents a preset delay parameter; clk represents a preset clock frequency; t represents a time delay parameter; r represents a preset data rate; n represents an adjustment parameter; floor denotes the downward integer.
2. The method of claim 1, wherein the i-th signal segment includes a plurality of signal data therein;
the step of correcting the time deviation of the ith signal segment by the correction module to obtain the ith first signal segment comprises the following steps:
the correction module acquires an ith time deviation parameter;
the correction module performs interpolation processing on all signal data in the ith signal segment based on the ith time deviation parameter and a first preset algorithm to obtain each interpolation point;
and the correction module performs resampling processing on the ith signal segment based on each interpolation point to obtain the ith first signal segment.
3. The method according to claim 1, wherein the step of the estimation module performing time offset estimation on the ith second signal segment to obtain an i +1 th time offset parameter comprises:
the estimation module estimates the time deviation of the ith second signal segment based on a second preset algorithm to obtain an (i + 1) th initial deviation parameter;
and the estimation module carries out smoothing processing on the (i + 1) th initial deviation parameter to obtain the (i + 1) th time deviation parameter.
4. The method according to claim 1, wherein the step of adjusting, by the adjusting module, the ith first signal segment based on the adjustment parameter to obtain the ith second signal segment comprises:
and the adjusting module sets the first n signal data in the ith first signal segment to zero to obtain the ith second signal segment, wherein n is equal to the adjusting parameter.
5. The FPGA is characterized in that the FPGA is electrically connected with a signal conversion device and comprises a correction module, an adjustment module and an estimation module;
the correction module is used for sequentially receiving M signal segments in the digital signal to be processed sent by the signal conversion device, wherein M is a natural number greater than 1; carrying out time deviation correction on the ith signal segment to obtain the ith first signal segment, wherein i is a natural number which is more than 0 and less than M + 1;
the adjusting module is used for adjusting the ith first signal segment to obtain an ith second signal segment;
the estimation module is used for carrying out time deviation estimation on the ith second signal segment to obtain an (i + 1) th time deviation parameter; the (i + 1) th time deviation parameter is used for the correction module to carry out time deviation correction on the (i + 1) th signal segment;
the ith first signal segment includes a plurality of signal data, and the adjustment module is specifically configured to: obtaining an adjustment parameter based on the time delay parameter and a preset data rate; the time delay parameter represents the time length of processing a signal segment by the FPGA; the preset data rate represents the number of signal data received by the correction module in a preset unit time; the adjustment parameter represents the number of signal data to be adjusted; the adjusting module adjusts the ith first signal segment based on the adjusting parameter to obtain the ith second signal segment;
the adjustment module is specifically configured to: the adjusting module acquires a preset clock frequency, a preset delay parameter and the preset data rate; wherein the preset clock frequency represents the reciprocal of a preset clock period; the preset delay parameter represents a multiple of a preset clock period used by the FPGA for processing a signal segment; the adjusting module calculates based on the preset clock frequency, the preset delay parameter and the preset data rate according to a preset formula to obtain the adjusting parameter;
the preset formula is as follows:
t=k/clk；
n=floor(t*R)；
wherein k represents a preset delay parameter; clk represents a preset clock frequency; t represents a delay parameter; r represents a preset data rate; n represents an adjustment parameter; floor denotes the downward integer.
6. The FPGA of claim 5, wherein the ith signal segment includes a plurality of signal data therein; the correction module is specifically configured to:
acquiring an ith time deviation parameter;
performing interpolation processing on all signal data in the ith signal segment based on the ith time deviation parameter and a first preset algorithm to obtain each interpolation point;
and resampling the ith signal segment based on each interpolation point to obtain the ith first signal segment.
7. The FPGA of claim 5, wherein the estimation module is specifically configured to:
estimating the time deviation of the ith second signal segment based on a second preset algorithm to obtain an (i + 1) th initial deviation parameter;
and performing smoothing processing on the (i + 1) th initial deviation parameter to obtain the (i + 1) th time deviation parameter.
8. A communications receiving device comprising signal conversion means and an FPGA according to any one of claims 5 to 7.
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