CN113132285A - Digital demodulation system and method - Google Patents
Digital demodulation system and method Download PDFInfo
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- CN113132285A CN113132285A CN202110267486.5A CN202110267486A CN113132285A CN 113132285 A CN113132285 A CN 113132285A CN 202110267486 A CN202110267486 A CN 202110267486A CN 113132285 A CN113132285 A CN 113132285A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/26—Systems using multi-frequency codes
- H04L27/2601—Multicarrier modulation systems
- H04L27/2647—Arrangements specific to the receiver only
- H04L27/2655—Synchronisation arrangements
- H04L27/2656—Frame synchronisation, e.g. packet synchronisation, time division duplex [TDD] switching point detection or subframe synchronisation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/26—Systems using multi-frequency codes
- H04L27/2601—Multicarrier modulation systems
- H04L27/2647—Arrangements specific to the receiver only
- H04L27/2655—Synchronisation arrangements
- H04L27/2657—Carrier synchronisation
Abstract
The invention discloses a digital demodulation system and a method, comprising the following steps: the device comprises a symbol timing recovery module, a frame synchronization module, a carrier recovery module, a de-mapping module and a decoding module; the symbol timing recovery module is used for correcting the sampling error of the received data to obtain timing recovery data; the received data comprises I path data and Q path data which are in-phase and orthogonal; a frame synchronization module; the frame synchronization processing module is used for carrying out frame synchronization processing on the timing recovery data and outputting a frame head indicating signal when capturing a frame starting position; the carrier recovery module is used for realizing frequency offset recovery and phase offset recovery on the frame header indication signal based on a frequency offset estimation algorithm to obtain data after carrier recovery; the de-mapping module is used for realizing soft de-mapping on the input data to obtain soft information; wherein the input data is obtained based on the data after carrier recovery; and the decoding module is used for decoding the soft information and outputting a recovery bit stream. The scheme provided by the invention can effectively reduce the complexity of calculation and reduce the occupation of resources.
Description
Technical Field
The invention belongs to the technical field of wireless communication, and particularly relates to a digital demodulation system and a digital demodulation method.
Background
In a digital communication system, the position of a data frame needs to be obtained through a frame synchronization technology, and the accurately obtained position of the data frame directly influences subsequent demodulation and decoding work of data, and is very important for completing a communication process. To facilitate synchronization, a training data sequence for synchronization is typically inserted periodically in the data stream. The inserted training data sequence is generally divided into frame header data and pilot data; the frame header data is mainly used for realizing frame synchronization.
However, in the actual communication process, due to the long communication distance, signal fading, signal interference, and the influence of doppler effect, etc., frequency offset of the received signal is usually caused. Therefore, how to improve the detection probability of the digital demodulation system for the frame start position in this situation, and further ensure the overall performance of the system, is a problem to be solved in the art.
Disclosure of Invention
To solve the above problems in the prior art, the present invention provides a digital demodulation system and method. The technical problem to be solved by the invention is realized by the following technical scheme:
in a first aspect, an embodiment of the present invention provides a digital demodulation system, including: the device comprises a symbol timing recovery module, a frame synchronization module, a carrier recovery module, a de-mapping module and a decoding module;
the symbol timing recovery module is used for correcting a sampling error of received data to obtain timing recovery data; the receiving data comprises I path data and Q path data which are in-phase and orthogonal;
the frame synchronization module; the frame synchronization processing module is used for carrying out frame synchronization processing on the timing recovery data and outputting a frame header indicating signal when capturing a frame starting position;
the carrier recovery module is used for realizing frequency offset recovery and phase offset recovery of the frame header indicating signal based on a frequency offset estimation algorithm to obtain data after carrier recovery;
the de-mapping module is used for realizing soft de-mapping on the input data to obtain soft information; wherein the input data is obtained based on the data after carrier recovery;
and the decoding module is used for decoding the soft information and outputting a recovery bit stream.
Optionally, the frame synchronization module performs frame synchronization on the timing recovery data, and includes:
utilizing differential correlation calculation to the timing recovery data to obtain a differential correlation sequence;
acquiring a local correlation sequence of differential correlation information representing the SOF sequence; wherein the length of the differential correlation sequence is the same as that of the local correlation sequence;
carrying out phase judgment on each data in the differential correlation sequence to obtain a symbol sequence;
carrying out XOR processing on the local correlation sequence and the symbol sequence to obtain a decision value;
and comparing the judgment value with a preset threshold value to obtain a capture result of the frame starting position.
Optionally, the performing phase judgment on each data in the differential correlation sequence to obtain a symbol sequence includes:
for each differential correlation value in the differential correlation sequence, extracting a sign bit of the differential correlation value;
and forming a symbol sequence by each symbol bit obtained in sequence.
Optionally, the comparing the decision value with a preset threshold to obtain a capture result of the frame start position includes:
and when the judgment value is larger than a preset threshold value, determining that the frame starting position is captured.
Optionally, the carrier recovery module performs carrier recovery processing on the frame header indication signal, including:
performing coarse frequency offset estimation and elimination on the frame header indication signal to obtain coarse frequency offset recovery data;
performing fine frequency offset estimation and elimination on the coarse frequency offset recovery data to obtain fine frequency offset recovery data;
and carrying out phase offset estimation and elimination on the fine frequency offset recovery data to obtain the data after carrier recovery.
Optionally, the demapping module implements soft demapping, including:
determining a modulation mode, a coding rate and a constellation diagram;
calculating the ratio of the inner circle radius to the outer circle radius of the constellation diagram according to the coding rate, and determining a phase coordinate value according to each constellation point in the constellation diagram;
the constellation mapping module maps the binary vectors obtained by coding to constellation points according to the constellation map characteristics, wherein each constellation point corresponds to a 4-bit vector; the constellation mapping module is an inverse process corresponding to a soft demapping module of the receiver;
the soft demapping module compares the probability values of the bits corresponding to the 16 constellation points according to the characteristics of each bit in the constellation diagram, and excludes N constellation points with the minimum probability values, wherein N is larger than or equal to 1.
Optionally, the decoding module decodes the soft information, including:
initializing decoding information of the soft information;
obtaining the relation between multiplicative factor and signal-to-noise ratio through least square curve fitting;
and setting the maximum iteration times, carrying out decoding iteration on the decoding information until the iteration times reach the maximum iteration times, and outputting a recovery bit stream decoding result.
Optionally, the frame synchronization digital demodulation system further includes an equalization module, configured to implement nonlinear equalization processing on the carrier-recovered data and the frame header indication signal.
Optionally, the frame synchronization digital demodulation system further includes a digital automatic gain control module, configured to adjust the power of the input data.
In a second aspect, an embodiment of the present invention further provides a digital demodulation method, including:
correcting the sampling error of the received data to obtain timing recovery data; the receiving data comprises I path data and Q path data which are in-phase and orthogonal;
performing frame synchronization processing on the timing recovery data, and outputting a frame header indication signal when capturing a frame starting position;
frequency offset recovery and phase offset recovery are realized on the frame header indication signal based on a frequency offset estimation algorithm, and data after carrier recovery are obtained;
soft demapping is carried out on input data to obtain soft information; wherein the input data is obtained based on the data after carrier recovery;
and decoding the soft information and outputting a recovery bit stream.
The embodiment of the invention provides a digital demodulation system and a method, firstly correcting the sampling error of received data to obtain timing recovery data; then, frame synchronization processing is carried out on the timing recovery data, and a frame header indication signal is output when a frame starting position is captured; thirdly, performing frequency offset correction and phase offset correction on the frame head indicating signal; and finally, soft demapping and decoding are carried out on the input data, and a recovery bit stream is output. In the scheme, the timing recovery data is firstly subjected to differential correlation calculation, so that the frequency deviation resistance of the algorithm can be improved, and the detection probability of the frame starting position can be improved under the condition of frequency deviation. And the judgment value is obtained by only adopting the sign bit of the timing recovery data and the local correlation sequence for correlation, so that the calculation complexity can be effectively reduced, the resource occupation is reduced, and the hardware implementation of the algorithm is facilitated.
Of course, not all of the advantages described above need to be achieved at the same time in the practice of any one product or method of the invention.
The present invention will be described in further detail with reference to the accompanying drawings and examples.
Drawings
One or more embodiments are illustrated by way of example in the accompanying drawings, which correspond to the figures in which like reference numerals refer to similar elements and which are not to scale unless otherwise specified.
Fig. 1 is a block diagram of a digital demodulation system according to an embodiment of the present invention;
fig. 2 is a specific structural diagram of a symbol timing recovery module according to an embodiment of the present invention;
fig. 3 is a flowchart illustrating a frame synchronization method according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a frame synchronization process according to an embodiment of the present invention;
fig. 5 is a flowchart of a digital demodulation method according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In order to implement a digital demodulation system capable of improving the detection probability of the frame start position, the embodiment of the invention provides a digital demodulation system and a method.
In a first aspect, an embodiment of the present invention provides a digital demodulation system. Next, the system will be described first.
Referring to fig. 1, fig. 1 is a digital demodulation system provided in an embodiment of the present invention, including: a symbol timing recovery module 110, a frame synchronization module 120, a carrier recovery module 130, a demapping module 140, and a decoding module 150;
the symbol timing recovery module 110 is configured to correct a sampling error of received data to obtain timing recovery data; the received data comprises I path data and Q path data which are in-phase and orthogonal;
a frame synchronization module 120; the frame synchronization processing module is used for carrying out frame synchronization processing on the timing recovery data and outputting a frame head indicating signal when capturing a frame starting position;
the carrier recovery module 130 is configured to implement frequency offset recovery and phase offset recovery on the frame header indication signal based on a frequency offset estimation algorithm, so as to obtain data after carrier recovery;
a demapping module 140, configured to perform soft demapping on the input data to obtain soft information; wherein the input data is obtained based on the data after carrier recovery;
and a decoding module 150, configured to decode the soft information and output a recovered bit stream.
The Digital demodulation system of the embodiment of the present invention is applied to a receiver, and it should be noted that the receiver of the embodiment of the present invention includes, but is not limited to, a DVB-S2(Digital Video Broadcasting-Satellite-television Broadcasting, Second Generation Satellite Digital television Broadcasting) or a DVB-S2X (Digital Video Broadcasting-Satellite-television Broadcasting Extensions) receiver.
The following describes each module in the digital demodulation system according to the embodiment of the present invention:
(1) the symbol timing recovery module 110:
referring to fig. 2, fig. 2 is a specific structural diagram of a symbol timing recovery module according to an embodiment of the present invention.
The received data of the embodiment of the invention comprises in-phase and quadrature I path data and Q path data.
Specifically, the sampling clock generator 111 generates sampling pulses in cycles in which aliasing does not occur. The first sampler 112 generates a signal, and samples and outputs the band-limited input signal according to a sampling clock. The interpolator 113 generates and outputs an interpolation signal for interpolating the generated signal during an interpolation time interval. The data filter 114 filters the interpolation to output final strobe data. The timing error detector 115 detects a timing error from the strobe data. The loop filter 116 filters out noise components of the detected timing error. The controller 117 controls the operation of the interpolator 113 by using the filtered timing error, thereby achieving accurate timing recovery, resulting in timing recovery data.
(2) The frame synchronization module 120:
referring to fig. 3, fig. 3 is a flowchart illustrating a frame synchronization method according to an embodiment of the present invention.
Specifically, the frame synchronization module performs frame synchronization on the timing recovery data, and includes the following steps:
and S21, obtaining a differential correlation sequence by utilizing differential correlation calculation to the timing recovery data.
In an alternative embodiment, S21 may include S211 to S213.
And S211, performing conjugate calculation on the timing recovery data at the previous moment, and multiplying the conjugate calculation result by the timing recovery data at the current moment to obtain a differential correlation value at the current moment.
Please refer to fig. 4 for understanding the processing procedure of the embodiment of the present invention, and fig. 4 is a schematic diagram of the frame synchronization processing procedure of the embodiment of the present invention. Please refer to S21See the part inside the dashed box in the upper left corner of fig. 4, where k denotes the current time, rk-1Timing recovery data representing the last time, rkTiming recovery data representing the current time, rk+1Timing recovery data indicating the next time (c)*It is shown that the conjugate is found,
representing a multiplier and D a buffer.
The embodiment of the invention can store the timing recovery data at each moment. Therefore, the data r is recovered at the timing when the current time is acquiredkThen, the timing recovery data r of the last time can be adjustedk-1To r tok-1Obtaining the conjugation
Then r is further reducedkAnd
as two inputs to a multiplier to obtain a product
Will be provided with
As a differential correlation value at the current time.
It should be noted that complex conjugation is implemented in the FPGA, and only the imaginary signal needs to be inverted and added with 1, and the multiplication of the part needs to call a complex multiplier.
S212, deleting the first stored differential correlation value in the differential correlation sequence corresponding to the previous time, and sequentially shifting the subsequent differential correlation values to the deleted position to obtain a shifted sequence.
In the embodiment of the invention, the frame synchronization module continuously acquires the timing recovery data at each moment, and the timing recovery data at each moment can obtain a differential correlation value and is cached by using the cache D, so as to obtain a corresponding differential correlation sequence. The length of the differential correlation sequence corresponding to each time is fixed, and is specifically set according to the length of the synchronization sequence. Taking DVB-S2/DVB-S2X receiver as an example, the length of the differential correlation sequence is 25, i.e. the amount of data to be stored is 25 characters.
The differential correlation sequence at each time is buffered in a sliding window mode and moves along with time, and can be understood in a first-in first-out queue mode. For the current time, the sliding window deletes the difference correlation value stored first in the difference correlation sequence corresponding to the previous time by moving a position, and simultaneously sequentially shifts the difference correlation value after the original sequence deletion value to the deletion position by one position.
And S213, supplementing the difference correlation value of the current moment into the spare bits in the shifted sequence to obtain the difference correlation sequence.
The differential correlation sequence can be obtained by adding the differential correlation value at the current moment to the spare bits in the shifted sequence.
It can be understood that, by continuously buffering the differential correlation values at each time, the differential correlation sequences corresponding to each time are connected to form a serial array, and the differential correlation sequence at each time continuously moves in the array in the form of a sliding window.
And S22, acquiring a local correlation sequence of the differential correlation information which characterizes the SOF sequence.
In the embodiment of the present invention, the local correlation sequence is obtained by performing differential correlation calculation on an SOF sequence corresponding to the received data, and the specific process may include the following steps 1 to 3.
Referring to the part in the upper right corner of the dashed box in fig. 4, the SOF sequence in the embodiment of the present invention can be represented as:
SOF＝(sof1,sof2,...,sofS-1,sofS) Wherein SOF represents a specific number in the SOF sequenceAccording to the formula, the subscript of SOF represents the serial number of the data in the SOF sequence, S is the length of the SOF sequence, and S is a natural number greater than 1. Typically, SOF sequences are fixed characters, determined by the communication protocol. Thus, in case of a communication protocol determination, the corresponding SOF sequence can be known in advance. For example, in a DVB-S2/DVB-S2X receiver, the SOF sequence is a fixed symbol 18D2E82HEXAnd has a length of 26.
In the embodiment of the invention, the local correlation sequence is used as an important reference sequence of the frame synchronization module, the length is configurable, the local correlation sequence can adapt to various modulation types, and the universality of the frame synchronization module can be obviously improved.
And 2, calculating the conjugate value of the (i + 1) th data in the SOF sequence.
The conjugate value of the i +1 th data is expressed as
And 3, taking the product of the conjugate value of the (i + 1) th data and the ith data in the SOF sequence as the ith data in the local correlation sequence.
Let local correlation sequence be C ═ C1,...,cS-1) Wherein the ith data
Taking the example of a DVB-S2/DVB-S2X receiver, the length S of the SOF sequence is 26. Therefore, the length of the differential correlation sequence and the local correlation sequence corresponding to the current time is the same, and the length of the differential correlation sequence and the local correlation sequence at each time is 25. Through the steps 1 to 3, the local correlation sequence C can be obtained through calculation. In the actual processing, the calculations of step 1 to step 3 may be specifically performed when the process proceeds to S22. But since the SOF sequence is fixed. Therefore, in a preferred embodiment, before executing S21, the local correlation sequence C can be obtained in advance and stored accordingly through the above-mentioned calculation from step 1 to step 3, and then, when executingWhen the process goes to S22, only the stored local correlation sequence C needs to be retrieved, and repeated calculation is not needed, so that the calculation amount can be reduced, and the resource consumption can be reduced.
In an alternative embodiment, the SOF sequence is subjected to pi/2-BPSK modulation (BPSK). Therefore, as can be understood by those skilled in the art, the difference correlation value of two adjacent data in the SOF sequence is ± j, and therefore, the local correlation sequence only generates Q-way data. That is, the data in the obtained local correlation sequence only corresponds to ± j, and j referred to in the part represents a complex unit.
The rule of the differential correlation calculation performed to obtain the local correlation sequence in S22 is exactly opposite to the rule of the differential correlation calculation performed to obtain the differential correlation sequence in S21, and specifically shows the generation process of data at the same position in the two sequences, where the local correlation sequence is to calculate a conjugate value of data next to the current time, and the differential correlation sequence is to calculate a conjugate value of data previous to the current time. The two processing modes are opposite, and the purpose of simplifying the exclusive-or operation in the subsequent steps is to obtain Q-path data with opposite signs.
And S23, performing phase judgment on each data in the differential correlation sequence to obtain a symbol sequence.
As described above, the data in the local correlation sequence obtained in the embodiment of the present invention only corresponds to ± j, and therefore, it is necessary to correspondingly determine whether Q-path data corresponding to each data in the differential correlation sequence is greater than 0 or less than 0. In the embodiment of the invention, the step is to determine the quadrant of the data in the differential correlation sequence in a hard decision mode, so as to determine the sign bit corresponding to the data.
In an alternative embodiment, S23 may include S231 to S232:
s231, for each differential correlation value in the differential correlation sequence, extracting a sign bit of the differential correlation value.
As shown in fig. 4, sgn represents the extraction sign bit, having the sign + or-since the differential correlation value is complex. Thus, for a differential correlation value, 1 can be used to represent-0 represents +, i.e., the sign bit extracted is either 1 or 0.
And S232, forming a symbol sequence by each symbol bit obtained in sequence.
It is understood that the symbol sequence is composed of 0 or 1, and the length of the symbol sequence is consistent with the length of the differential correlation sequence corresponding to the current time and the length of the local correlation sequence. For the sign bit and the extraction process, please refer to the related prior art, which is not described herein.
Those skilled in the art can understand that the sign bit of the received data is extracted, and only 1 bit of data is needed to represent the received data, so that the occupation of resources can be reduced.
And S24, carrying out exclusive OR processing on the local correlation sequence and the symbol sequence to obtain a decision value.
Specifically, this step may include S241 and S242:
and S241, performing XOR processing on the data at the corresponding positions in the local correlation sequence and the symbol sequence to obtain a plurality of XOR processing results.
As shown in figure 4 of the drawings,
and indicating XOR processing, wherein if the data participating in the XOR processing are the same, the operation result is 0, and otherwise, the operation result is 1.
Taking the foregoing S as an example, after performing xor processing on the data at the corresponding position in the local correlation sequence and the symbol sequence, 25 xor processing results can be obtained.
S242, adding the plurality of xor processing results to obtain a decision value.
As shown in fig. 4, Σ represents the addition process. Taking the foregoing S as an example, after summing the 25 xor processing results, a sum can be obtained as the decision value.
In the art, calculating the correlation between a local sequence and a received sequence by using a correlation detector is a common synchronization method. The conventional correlation algorithm mainly includes an autocorrelation algorithm and a cross-correlation algorithm, the autocorrelation algorithm mainly uses a relationship between received sequences, and the cross-correlation algorithm uses a relationship between a local sequence and a received sequence, including a Differential Post-Detection Integration (DPDI) and the like. The correlation algorithm needs to perform a large number of complex multiplication operations, and the performance of the algorithm is generally improved along with the increase of complexity, so that a large number of complex multipliers are often required to be added to improve the performance of the algorithm, and a large amount of resources are generally occupied when the correlation algorithm is implemented on hardware such as an FPGA.
In order to reduce computing resources, the embodiment of the invention obtains the sign bit of the received signal in a hard decision mode, and only adopts a mode of correlating the sign bit of the received data with a local correlation sequence to accumulate and sum to obtain a decision value. Therefore, the resource occupation can be effectively reduced, the calculation complexity is reduced, and the hardware realization resources are reduced.
And S25, comparing the judgment value with a preset threshold value to obtain the capture result of the frame starting position at the current moment.
The preset threshold is determined from empirical values. For example, it may be set to 0.8 times or 0.9 times the length S of the SOF sequence. Comparing the decision value with a preset threshold, and obtaining the capturing result of the frame start position at the current time, which may include the following two types:
1) and when the judgment value is greater than the preset threshold value, determining that the frame starting position is captured at the current moment, and outputting a frame head indicating signal.
2) And when the judgment value is less than or equal to the preset threshold value, determining that the frame starting position is not captured at the current moment, and continuously detecting the received data at the next moment.
After determining that the frame start position is captured at the current time, the subsequent processing may be performed with reference to the related art, for example, in an alternative embodiment, after obtaining the capture result of the frame start position at the current time for the satellite communication system, the method may further include:
and calculating the number of delay clocks from the time when the received data at the current moment is acquired to the time when the comparison of the judgment value and the preset threshold value is completed, and delaying the received data by using the number of delay clocks.
The interval between frames in a satellite communication system is often not fixed, and a certain number of clocks are needed for a frame synchronization module to complete correlation calculation to obtain a decision value corresponding to the current time. The number of delay clocks determined in this step provides a reference for delay control of the received data at the current time and at the subsequent time. In the implementation process, according to the number of delay clocks, the internal counter of the fifo IP core is used, so that the read-write operation of the fifo is controlled, and the delay control is realized.
(3) The carrier recovery module 130:
specifically, the carrier recovery module 130 performs carrier recovery processing on the frame header indication signal, and includes the following steps:
and S31, performing coarse frequency offset estimation and elimination on the frame header indicating signal to obtain coarse frequency offset recovery data.
In an optional implementation manner, the coarse frequency offset estimation and cancellation uses an M & M frequency estimator, which can cope with large frequency offset.
Specifically, the estimation accuracy of the coarse estimation is improved by accumulating L consecutive pilot blocks, as shown in formula (1).
Wherein L is the number of consecutive pilot blocks, and N is L0/2，L0Is the pilot length, L036, w (M) is M&Smoothing function of M algorithm, Rl(m) is the correlation value r (m) of the l-th pilot block.
S32, fine frequency offset estimation and elimination are carried out on the coarse frequency offset recovery data, and fine frequency offset recovery data are obtained.
In an optional implementation manner, the fine frequency offset estimation and cancellation uses an L & R frequency estimator to correct residual frequency offset, so as to improve the accuracy of fine frequency offset cancellation.
Specifically, an L & R improvement algorithm, i.e., a manner of accumulating consecutive L pilot blocks, is used to improve the estimation accuracy of the fine estimation, as shown in formula (2).
And the fine frequency offset estimation and elimination adopts an L & R frequency estimator, and N is 18, so that the theoretical range of normalized residual frequency offset which can be processed by fine frequency offset elimination is +/-1/19. The coarse frequency offset estimation and the normalized residual frequency offset after the elimination obey gaussian distribution, and the probability Pe that the normalized residual frequency offset Δ fe after the coarse frequency offset elimination does not fall into the expected interval can be expressed as formula (3):
where σ is the standard deviation of the normalized residual frequency offset Δ fe.
Further, in order to obtain a proper margin, the standard deviation σ of the normalized residual frequency offset may be selected to be 0.001, which puts requirements on the accuracy of coarse frequency offset estimation and elimination. The fine frequency offset estimation and cancellation can normally operate only if the normalized frequency offset of the coarse frequency offset estimation and cancellation meets the requirement that the RMSE is less than 0.001.
And S33, performing phase offset estimation and elimination on the fine frequency offset recovery data to obtain data after carrier recovery.
It can be understood by those skilled in the art that the fine frequency offset recovery data still has residual frequency offset, phase noise and other influences, and needs to be further corrected to ensure reliable demodulation of the system.
In the embodiment of the invention, the pilot frequency auxiliary linear interpolation scheme is adopted to realize the phase recovery. The pilot-assisted interpolation technique derives the phase trajectory of the data symbols by means of linear interpolation using the estimated phases of two successive pilot blocks.
Specifically, with the maximum likelihood estimator, as shown in equation (4), the phase estimate of the pilot symbols can be obtained quickly.
Where L represents the L-th pilot block, LlIs the pilot length, and LlEqual to 90 (start of frame block) or 36 (pilot block), and c (k) is a known pilot symbol.
Next, as shown in equation (5), the phase estimation value is expanded to obtain the final phase estimation value of the l-th pilot block
Wherein the content of the first and second substances,
the function is a sawtooth type nonlinear function, the value of phi is ensured to be always within +/-2 pi, alpha is a parameter between 0 and 1, and optionally, in the embodiment of the invention, alpha is 1.
Considering the presence of residual frequency offset and phase noise, the phase estimated using equation (4) is only the average phase within the pilot block, and can be considered as the phase at the most intermediate pilot. In the linear interpolation process, in order to make the phase interpolation value of the data portion more accurate, it needs to be compensated, and the phase of the data portion can be obtained by equation (6):
wherein L isl-1Denotes the length, L, of the L-1 th pilot blocklDenotes the length, L, of the L-th pilot blocksIndicating the length of the data symbol between the two pilot blocks.
(4) The demapping module 140:
specifically, the demapping module implements soft demapping, including the following steps:
and S41, determining a modulation mode, a coding rate and a constellation diagram.
Optionally, the modulation scheme may be 8+8APSK, and the coding rate is 90/180, 96/180, 100/180, 18/30, or 20/30.
Correspondingly, the constellation diagram is composed of two concentric circles, the inner circle contains 8 constellation points, the outer circle contains 8 constellation points, wherein R1 represents the radius of the inner circle, R2 represents the radius of the outer circle, γ ═ R2/R1, and different encoding rates correspond to different γ values.
And S42, calculating the ratio of the inner circle radius to the outer circle radius of the constellation diagram according to the coding rate, and determining the phase coordinate value according to each constellation point in the constellation diagram.
In the embodiment of the invention, the phase coordinate value of the constellation point passes through a Gaussian white noise channel.
S43, the constellation mapping module maps the binary vectors obtained by coding to constellation points according to the characteristics of the constellation map, wherein each constellation point corresponds to a 4-bit vector; the constellation mapping module is the inverse process corresponding to the soft demapping module of the receiver.
S44, the soft de-mapping module compares the probability values of the bit corresponding to 16 constellation points according to the characteristics of each bit in the constellation diagram, and excludes m constellation points with the minimum probability values, wherein m is more than or equal to 1.
Optionally, the log-likelihood ratio of each bit of the constellation point includes: the LDPC coding and decoding or the Turbo coding and decoding are used in combination with an 8+8APSK modulation mode, soft information output by a receiver is sent to a decoder, and digital symbols 0 or 1 are determined bit by bit in the decoder; calculating the probability likelihood ratio of each bit symbol, and judging according to the likelihood ratio; the log-likelihood ratios of the bits are mapped based on a maximum a posteriori probability criterion.
(5) The decoding module 150:
specifically, the decoding module 150 decodes the soft information, which includes the following steps:
s51, decoding information of the soft information is initialized.
In the embodiment of the invention, the decoding information transmitted to the check node j by the variable node i is set as qijAnd the log-likelihood ratio information input by the decoder is L (Pi), and the initial message that i is transmitted to j is obtained: l (0) (q)ij)＝L(Pi)。
And S52, obtaining the relation between the multiplicative factor and the signal-to-noise ratio through least square curve fitting.
Optionally, S52 may include the following steps:
the method comprises the following steps: according to the characteristic that the value of the multiplicative factor is related to the signal-to-noise ratio, simulating the relationship between the signal-to-noise ratio and the multiplicative factor, and obtaining the corresponding relationship between the signal-to-noise ratio s and the multiplicative factor alpha(s) as follows: (0.5, 0.625), (0.75, 0.675), (1, 0.725), (1.25, 0.75), (1.5, 0.775), (1.75, 0.8), (2, 0.825), (2.25, 0.85), (2.5, 0.85);
step two: performing least square curve fitting on the corresponding relation in the step one to obtain a relation between the multiplicative factor and the signal-to-noise ratio: α(s) ═ 0.1s +0.6(s ≦ 2.5), and if s > 2.5, α(s) ═ 0.85;
s53, setting the maximum iteration times, decoding the decoded information until the iteration times reaches the maximum iteration times, and outputting the decoding result of the recovery bit stream.
Optionally, S53 may include the following steps:
the method comprises the following steps: updating check node messages with multiplicative factor α(s): let the decoding information transmitted from the check node j to the variable node i be rjiUpdating the check node information by combining the multiplicative factor alpha(s) and the minimum sum decoding algorithm to obtain the updating information L (l) (r) transmitted to the variable node i by the check node j during the decoding iteration of the first timeji) Comprises the following steps:
wherein i' represents the remaining variable nodes, V, adjacent to the check node j and excluding the ith variable nodej\ i represents the set of remaining variable nodes adjacent to check node j with the ith variable node removed, qi'jRepresents the decoding information transmitted by the variable node i' to the check node j, sgn (·) represents a sign function, and min (·) represents a minimum function.
Step two: updating the variable node message, namely obtaining the variable node i and transmitting the variable node i to the check when the decoding iteration is performed for the first timeUpdate information L (l) (q) of node jij) Comprises the following steps:
wherein j' represents the remaining check nodes adjacent to the variable node i with the jth check node removed, Ci\ j represents a set of remaining check nodes adjacent to variable node i with the jth check node removed, rj'iAnd indicating the decoding information transmitted to the variable node i by the check node j'.
Step three: setting the posterior probability information of variable node i as qiAccording to the l decoding iteration, the updated information L (l) (r) of the check node is obtainedji) And variable node update information L (l) (q)ij) Calculating the decision message L (l) (q) of the decoding of the first timei)：
Wherein, CiRepresenting a set of check nodes adjacent to variable node i.
Step four: the decision message L (l) (q) obtained from the decoding of the l timei) And (4) judging: if L (l) (q)i) If the decoding judgment result is more than 0, the first time decoding judgment result is 0; if L (l) (q)i) If the decoding result is less than or equal to 0, the first decoding judgment result is 1.
Step five: judging whether the maximum iteration number is reached: after the decoding iteration of the first time is finished, if the iteration time l reaches the preset maximum iteration time N, stopping the iteration and outputting a final decoding result; otherwise, returning to the first step to continue the iteration.
In an optional embodiment, the frame synchronization digital demodulation system further includes an equalization module, configured to implement a non-linear equalization process on the carrier-recovered data and the frame header indication signal.
It is to be understood that the equalization module is disposed after the carrier recovery module 130.
In an optional embodiment, the frame synchronization Digital demodulation system further includes a Digital Automatic Gain Control (DAGC) module, configured to adjust power of the input data.
It is understood that a digital automatic gain control module is disposed before the demapping module 140.
In the embodiment of the invention, firstly, the sampling error of the received data is corrected to obtain timing recovery data; then, frame synchronization processing is carried out on the timing recovery data, and a frame header indication signal is output when a frame starting position is captured; thirdly, performing frequency offset correction and phase offset correction on the frame head indicating signal; and finally, soft demapping and decoding are carried out on the input data, and a recovery bit stream is output. In the scheme, the timing recovery data is firstly subjected to differential correlation calculation, so that the frequency deviation resistance of the algorithm can be improved, and the detection probability of the frame starting position can be improved under the condition of frequency deviation. And the judgment value is obtained by only adopting the sign bit of the timing recovery data and the local correlation sequence for correlation, so that the calculation complexity can be effectively reduced, the resource occupation is reduced, and the hardware implementation of the algorithm is facilitated.
In a second aspect, an embodiment of the present invention further provides a digital demodulation method, and referring to fig. 5, fig. 5 is a flowchart of the digital demodulation method provided in the embodiment of the present invention, and may include the following steps:
s1, correcting the sampling error of the received data to obtain timing recovery data; the received data comprises I path data and Q path data which are in-phase and orthogonal;
s2, carrying out frame synchronization processing on the timing recovery data, and outputting a frame header indication signal when capturing a frame starting position;
s3, frequency offset recovery and phase offset recovery are realized on the frame head indicating signal based on a frequency offset estimation algorithm, and data after carrier recovery are obtained;
s4, implementing soft de-mapping on the input data to obtain soft information; wherein the input data is obtained based on the data after carrier recovery;
s5, decodes the soft information and outputs a recovered bit stream.
Optionally, performing frame synchronization on the timing recovery data, including:
carrying out differential correlation calculation on timing recovery data to obtain a differential correlation sequence;
acquiring a local correlation sequence of differential correlation information representing the SOF sequence; the length of the differential correlation sequence is the same as that of the local correlation sequence;
carrying out phase judgment on each data in the differential correlation sequence to obtain a symbol sequence;
carrying out XOR processing on the local correlation sequence and the symbol sequence to obtain a decision value;
and comparing the decision value with a preset threshold value to obtain a capture result of the frame starting position.
Optionally, the phase judgment is performed on each data in the differential correlation sequence to obtain a symbol sequence, and the method includes:
for each differential correlation value in the differential correlation sequence, extracting a sign bit of the differential correlation value;
and forming a symbol sequence by each symbol bit obtained in sequence.
Optionally, comparing the decision value with a preset threshold to obtain a capture result of the frame start position, where the capture result includes:
and when the judgment value is larger than a preset threshold value, determining that the frame starting position is captured.
Optionally, the carrier recovery processing is performed on the frame header indication signal, and includes:
carrying out coarse frequency offset estimation and elimination on the frame head indicating signal to obtain coarse frequency offset recovery data;
performing fine frequency offset estimation and elimination on the coarse frequency offset recovery data to obtain fine frequency offset recovery data;
and carrying out phase offset estimation and elimination on the fine frequency offset recovery data to obtain data after carrier recovery.
Optionally, implementing soft demapping includes:
determining a modulation mode, a coding rate and a constellation diagram;
calculating the ratio of the inner circle radius to the outer circle radius of the constellation diagram according to the coding rate, and determining a phase coordinate value according to each constellation point in the constellation diagram;
the constellation mapping module maps the binary vectors obtained by coding to constellation points according to the characteristics of a constellation diagram, wherein each constellation point corresponds to a 4-bit vector; the constellation mapping module is an inverse process corresponding to a soft demapping module of the receiver;
the soft de-mapping module compares the probability values of the bits corresponding to the 16 constellation points according to the characteristics of each bit in the constellation diagram, and excludes N constellation points with the minimum probability values, wherein N is more than or equal to 1.
Optionally, decoding the soft information includes:
initializing decoding information of the soft information;
obtaining the relation between multiplicative factor and signal-to-noise ratio through least square curve fitting;
and setting the maximum iteration times, carrying out decoding iteration on the decoded information until the iteration times reach the maximum iteration times, and outputting a decoding result of the recovery bit stream.
Optionally, after S3, a non-linear equalization process is performed on the carrier-recovered data and the frame header indication signal.
Optionally, before S4, the power of the input data is adjusted.
For details of the processing procedure of each step of the digital demodulation method, please refer to the digital demodulation system described in the first aspect, which is not described herein again.
In the scheme provided by the embodiment of the invention, firstly, the sampling error of the received data is corrected to obtain timing recovery data; then, frame synchronization processing is carried out on the timing recovery data, and a frame header indication signal is output when a frame starting position is captured; thirdly, performing frequency offset correction and phase offset correction on the frame head indicating signal; and finally, soft demapping and decoding are carried out on the input data, and a recovery bit stream is output. In the scheme, the timing recovery data is firstly subjected to differential correlation calculation, so that the frequency deviation resistance of the algorithm can be improved, and the detection probability of the frame starting position can be improved under the condition of frequency deviation. And the judgment value is obtained by only adopting the sign bit of the timing recovery data and the local correlation sequence for correlation, so that the calculation complexity can be effectively reduced, the resource occupation is reduced, and the hardware implementation of the algorithm is facilitated.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
All the embodiments in the present specification are described in a related manner, and the same and similar parts among the embodiments may be referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, for the system embodiment, since it is substantially similar to the method embodiment, the description is simple, and for the relevant points, reference may be made to the partial description of the method embodiment.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.
Claims (10)
1. A digital demodulation system, comprising: the device comprises a symbol timing recovery module, a frame synchronization module, a carrier recovery module, a de-mapping module and a decoding module;
the symbol timing recovery module is used for correcting a sampling error of received data to obtain timing recovery data; the receiving data comprises I path data and Q path data which are in-phase and orthogonal;
the frame synchronization module; the frame synchronization processing module is used for carrying out frame synchronization processing on the timing recovery data and outputting a frame header indicating signal when capturing a frame starting position;
the carrier recovery module is used for realizing frequency offset recovery and phase offset recovery of the frame header indicating signal based on a frequency offset estimation algorithm to obtain data after carrier recovery;
the de-mapping module is used for realizing soft de-mapping on the input data to obtain soft information; wherein the input data is obtained based on the data after carrier recovery;
and the decoding module is used for decoding the soft information and outputting a recovery bit stream.
2. The digital demodulation system of claim 1 wherein the frame synchronization module frame synchronizes the timing recovery data, comprising:
utilizing differential correlation calculation to the timing recovery data to obtain a differential correlation sequence;
acquiring a local correlation sequence of differential correlation information representing the SOF sequence; wherein the length of the differential correlation sequence is the same as that of the local correlation sequence;
carrying out phase judgment on each data in the differential correlation sequence to obtain a symbol sequence;
carrying out XOR processing on the local correlation sequence and the symbol sequence to obtain a decision value;
and comparing the judgment value with a preset threshold value to obtain a capture result of the frame starting position.
3. The digital demodulation system of claim 2 wherein the phase determining of each data in the differential correlation sequence to obtain a symbol sequence comprises:
for each differential correlation value in the differential correlation sequence, extracting a sign bit of the differential correlation value;
and forming a symbol sequence by each symbol bit obtained in sequence.
4. The digital demodulation system of claim 2, wherein the comparing the decision value with a preset threshold to obtain the capture result of the frame start position comprises:
and when the judgment value is larger than a preset threshold value, determining that the frame starting position is captured.
5. The digital demodulation system of claim 1, wherein the carrier recovery module performs carrier recovery processing on the frame header indication signal, and the carrier recovery processing comprises:
performing coarse frequency offset estimation and elimination on the frame header indication signal to obtain coarse frequency offset recovery data;
performing fine frequency offset estimation and elimination on the coarse frequency offset recovery data to obtain fine frequency offset recovery data;
and carrying out phase offset estimation and elimination on the fine frequency offset recovery data to obtain the data after carrier recovery.
6. The digital demodulation system of claim 1 wherein said demapping module implements soft demapping, comprising:
determining a modulation mode, a coding rate and a constellation diagram;
calculating the ratio of the inner circle radius to the outer circle radius of the constellation diagram according to the coding rate, and determining a phase coordinate value according to each constellation point in the constellation diagram;
the constellation mapping module maps the binary vectors obtained by coding to constellation points according to the constellation map characteristics, wherein each constellation point corresponds to a 4-bit vector; the constellation mapping module is an inverse process corresponding to a soft demapping module of the receiver;
the soft demapping module compares the probability values of the bits corresponding to the 16 constellation points according to the characteristics of each bit in the constellation diagram, and excludes N constellation points with the minimum probability values, wherein N is larger than or equal to 1.
7. The digital demodulation system of claim 1 wherein said decoding module decodes said soft information, comprising:
initializing decoding information of the soft information;
obtaining the relation between multiplicative factor and signal-to-noise ratio through least square curve fitting;
and setting the maximum iteration times, carrying out decoding iteration on the decoding information until the iteration times reach the maximum iteration times, and outputting a recovery bit stream decoding result.
8. The digital demodulation system of claim 1 wherein the frame synchronous digital demodulation system further comprises an equalization module for performing a non-linear equalization process on the carrier-recovered data and the frame header indicator signal.
9. The digital demodulation system of claim 1 or 8 wherein the frame-synchronous digital demodulation system further comprises a digital automatic gain control module for adjusting the power of the input data.
10. A digital demodulation method, characterized in that,
correcting the sampling error of the received data to obtain timing recovery data; the receiving data comprises I path data and Q path data which are in-phase and orthogonal;
performing frame synchronization processing on the timing recovery data, and outputting a frame header indication signal when capturing a frame starting position;
frequency offset recovery and phase offset recovery are realized on the frame header indication signal based on a frequency offset estimation algorithm, and data after carrier recovery are obtained;
soft demapping is carried out on input data to obtain soft information; wherein the input data is obtained based on the data after carrier recovery;
and decoding the soft information and outputting a recovery bit stream.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113783602A (en) * | 2021-08-31 | 2021-12-10 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | Satellite communication data quality improving device |
| CN114489565A (en) * | 2022-02-15 | 2022-05-13 | 中国计量科学研究院 | Phase unwrapping algorithm based on double counters |
| CN115242587A (en) * | 2022-07-27 | 2022-10-25 | 西安电子科技大学 | Data-aided carrier frequency offset estimation method in low signal-to-noise ratio environment |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113783602A (en) * | 2021-08-31 | 2021-12-10 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | Satellite communication data quality improving device |
| CN113783602B (en) * | 2021-08-31 | 2023-07-11 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | Satellite communication data quality improving device |
| CN114489565A (en) * | 2022-02-15 | 2022-05-13 | 中国计量科学研究院 | Phase unwrapping algorithm based on double counters |
| CN114489565B (en) * | 2022-02-15 | 2024-01-30 | 中国计量科学研究院 | Phase unwrapping algorithm based on double counters |
| CN115242587A (en) * | 2022-07-27 | 2022-10-25 | 西安电子科技大学 | Data-aided carrier frequency offset estimation method in low signal-to-noise ratio environment |
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