CN114489565B - Phase unwrapping algorithm based on double counters - Google Patents
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Abstract
The invention relates to the technical field of signal processing, in particular to a phase unwrapping algorithm based on double counters, which is used for calculating a difference value between front and rear phases, judging whether the difference value is larger than a limit value for phase truncation, if the difference value is larger than the limit value, adding 1 to the corresponding counter, judging the relative size of the counter, subtracting the counter with small value from the counter with large value, giving a result to the counter with large value, setting the counter with small value to 0, calculating the difference value of the two counters, and performing first-step compensation on the phase. Calculating the difference value between the current phase value and the back phase value and the difference value between the current phase value and the front phase value, comparing the difference result of the phase value with the threshold value, and subtracting the 2 times of the threshold value from the current phase value if the difference result of the numerical values is larger than the threshold value; if the numerical difference results are smaller than the threshold value, the current phase value is added with the threshold value which is 2 times, otherwise, the phase expansion algorithm is kept unchanged, the problems of low speed and high complexity of the phase expansion algorithm are solved, and the phase expansion algorithm is simultaneously suitable for an FPGA platform.
Description
Technical Field
The invention relates to the technical field of signal processing, in particular to a phase unwrapping algorithm based on double counters.
Background
The phase unwrapping is a classical signal processing problem, which refers to recovering the original phase value from the value interval (-pi, pi) or (0, 2 pi), when the phase is calculated by using the arctangent function, the actually extracted phase is the wrapped phase value wrapped in the phase interval of one period, and is not the actually obtained phase, and the wrapped phase is recovered to the actually continuous phase, namely the phase unwrapping.
Traditional algorithms assume packagesIs x w (n) the unwrapped phase is x u (n): let x be u (n)＝x w (n); calculating the difference of the data, namely, the first-order difference delta phase=x of the wrapped Phase signal w (n)－x w (n-1); if the data is delta Phase>Pi is x w (n) the current point and all subsequent points are subtracted by 2π; if the data is delta Phase<Pi is x u (n) the current point and all subsequent points are added with 2π.
The phase unwrapping algorithm was first proposed in paper Analysis ofthe phase unwrapping problem in 1982 by Kazuyoshi Itoh, the principle of which is described in detail below:
assuming the wrapped phase signal is x w (n) the unwrapped phase is x u (n), the phase may be unwrapped according to the following steps:
step 1: let x be u (n)＝x w (n)；
Step 2: calculate the difference Δphase=x w (n)-x w (n-1)；
Step 3: if the difference delta Phase>Pi is x u (n) the current point and all subsequent points are subtracted by 2π; if the difference delta Phase<-pi, then x u (n) the current point and all subsequent points are added with 2π;
step 4: repeating the above steps until x is traversed u (n)。
The corresponding MATLAB algorithm is described as follows:
the wrapped phase can be unwrapped according to the above steps.
The algorithm runs very slowly on a computer, and cannot be realized at all on an FPGA due to high space complexity.
Yet another algorithm in the prior art is as follows:
the core part of the phase unwrapping algorithm used by the phase unwrapping function in MATLAB is described as follows:
as above, assume thatWrapped phase signal is x w (n) the unwrapped phase is x u (n), the phase may be unwrapped according to the following steps:
step 1: let x be u (n)＝x w (n)；
Step 2: calculating a difference, namely a result dp_corr= [ x of dividing a wrapped phase signal first-order difference by 2pi w (n)-x w (n-1)]/2π；
Step 3: rounding the number of symbols dp_corr to obtain dp_corr_round;
step 4: adding the current phase to the sum of dp_corr_round by a factor of 2pi, i.e. x w (n)＝x w (n)+2π*dp_corr_round
Step 5: repeating the above steps until x is traversed u (n)。
The wrapped phase can be unwrapped according to the above steps.
The algorithm includes operations of taking, rounding and dividing in actual implementation, and cannot be implemented on hardware.
Therefore, a phase expansion algorithm based on double counters needs to be designed, and through the code design and the program flow design of MATLAB, the one-dimensional phase expansion algorithm on a software platform is modified to be suitable for an FPGA platform, the calculation speed is improved, the space complexity is reduced, and meanwhile, the method is suitable for a hardware platform, and the practicability is improved.
Disclosure of Invention
The invention aims to overcome the defects of the prior art, provides a phase expansion algorithm based on double counters, and improves a one-dimensional phase expansion algorithm on a software platform by designing a code design and a program flow of MATLAB so as to be suitable for an FPGA platform, improves the calculation speed, reduces the space complexity, is suitable for a hardware platform, and improves the practicability.
In order to achieve the above object, the present invention provides a phase unwrapping algorithm based on dual counters: the method is characterized by comprising a first big step and a second big step of an algorithm, and the first big step comprises the following steps:
s1: calculating a difference diff1=xu (k) -xu (k-1) between a previous phase and a next phase value and a difference diff2=xu (k-1) -xu (k) between a next phase and a previous phase value;
s2: judging whether diff1 and diff2 are larger than a limit value bound of phase truncation, if diff1 is larger than bound, adding 1 to the i jump counter; if diff2 is greater than bound, then add 1 to the j-Down counter; if the value of the counter is not met, judging the relative value of the counter values of i and j, subtracting the counter with small value from the counter with large value, assigning the calculated result to the counter with large value, and setting the counter with small value to 0;
s3: calculating a difference delta of the up-down jump counter, wherein delta=i-j;
s4: compensating the phase, and enabling xu (k-1) =xu (k-1) -2 (delta) to obtain a phase expansion result of the first large step;
the second step comprises the following steps:
s10: calculating a difference value diff3 between the current phase value my_phase_out (t) and the next phase value my_phase_out (t-1) and a difference value diff4 between the current phase value my_phase_out (t) and the previous phase value my_phase_out (t+1);
s20: judging the sizes of diff3, diff4 and bound, and subtracting a bound value which is 2 times from the current phase value my_phase_out (t) if both diff3 and diff4 are larger than bound; if diff3, diff4 are all smaller than-bound, then a bound value of 2 times is added to the current phase value my_phase_out (t); otherwise, remain unchanged.
The dual counter based phase unwrapping algorithm of: the algorithm of S2 may also be:
if diff1 is greater than bound, then add 1 to the i counter; if diff1 is less than-bound, then add 1 to the j counter; if the values do not meet the preset value, judging the relative values of the counter values of i and j, subtracting the counter with the small value from the counter with the large value, assigning the calculated result to the counter with the large value, and setting the counter with the small value to 0.
The encapsulating function source code realized on MATLAB by the algorithm is as follows:
ang is the phase where truncation occurs; the bound is a threshold value for judging phase truncation, and when the difference result is larger than bound or smaller than-bound, the phase truncation is judged to occur; the i is an up jump counter, and is a positive integer greater than or equal to 0; j is a positive integer which is larger than or equal to 0 and is a down jump counter; the xu is a phase where truncation occurs; the diff1 is xu (k) -xu (k-1), namely the difference value between the previous phase and the next phase in the first large-step phase expansion; the diff2 is xu (k-1) -xu (k), namely the difference value between the value of the latter phase and the value of the former phase in the first large-step phase expansion; the delta is the value of the upper jump counter minus the lower jump counter, and is an integer; the my_phase_out is the result after the first phase expansion; the diff3 is the difference value between the previous phase and the next phase value in the second large-step phase expansion, namely the value of the my_phase_out (t) -my_phase_out (t-1); the diff4 is the difference value between the value of the last phase and the value of the previous phase in the second large-step phase expansion, namely, the value of the next phase in the second large-step phase expansion is the value of the second large-step phase; the phase_out is the final output result of the phase unwrapping.
Compared with the prior art, the invention can obtain continuous phase expansion results by designing a 2-step phase expansion algorithm and a program flow and only using multiplication, addition and subtraction and counting operations, solves the problems of low calculation speed and high space complexity of the traditional phase expansion algorithm, can simultaneously apply the phase expansion algorithm to the FPGA, improves the instantaneity of the algorithm, can complete phase expansion by only needing one multiplier and two counters, and solves the problem that no IP core related to the phase expansion algorithm exists on the FPGA.
Drawings
Fig. 1 is a flow chart of the algorithm of the present invention.
Fig. 2 is a schematic waveform diagram of phase truncation of the present invention.
FIG. 3 is a graph showing the result of the first large step phase unwrapping according to the present invention.
FIG. 4 is a partially enlarged schematic illustration of the result of the first large step phase unwrapping according to the present invention.
Fig. 5 is a schematic diagram of the final phase unwrapping result after the second step of the present invention.
Fig. 6 is an original three-dimensional view of an embodiment of the present invention.
FIG. 7 is an original three-dimensional view of noise contained in an embodiment of the present invention.
Fig. 8 is a two-dimensional gray scale plan view containing noise according to the present invention.
Fig. 9 is a three-dimensional phase folding diagram obtained after arctangent of a three-dimensional image according to the present invention.
Fig. 10 is a two-dimensional gray scale of phase folding obtained by the present invention.
FIG. 11 is a three-dimensional schematic diagram of the invention with edge removed obtained by phase unwrapping the two-dimensional image lines by a phase unwrapping algorithm.
Detailed Description
The invention will now be further described with reference to the accompanying drawings.
Referring to fig. 1-11, the present invention provides a dual counter based phase unwrapping algorithm:
a truncated phase waveform is shown in fig. 2.
Comprising a first big step and a second big step of the algorithm, wherein the first big step comprises the following steps (as in fig. 3-4):
s1: calculating a difference diff1=xu (k) -xu (k-1) between a previous phase and a next phase value and a difference diff2=xu (k-1) -xu (k) between a next phase and a previous phase value;
s2: judging whether diff1 and diff2 are larger than a limit value bound of phase truncation, if diff1 is larger than bound, adding 1 to the i counter; if diff2 is greater than bound, then add 1 to the j counter; if the value of the counter is not met, judging the relative value of the counter values of i and j, subtracting the counter with small value from the counter with large value, assigning the calculated result to the counter with large value, and setting the counter with small value to 0;
s3: calculating a difference delta of the counter, wherein delta=i-j;
s4: compensating the phase, and enabling xu (k-1) =xu (k-1) -2 (delta) to obtain a phase expansion result of the first large step;
the second major step comprises the following steps (as shown in fig. 5):
s10: calculating a difference value diff3 between the current phase value my_phase_out (t) and the next phase value my_phase_out (t-1) and a difference value diff4 between the current phase value my_phase_out (t) and the previous phase value my_phase_out (t+1);
s20: judging the sizes of diff3, diff4 and bound, and subtracting a bound value which is 2 times from the current phase value my_phase_out (t) if both diff3 and diff4 are larger than bound; if diff3, diff4 are all smaller than-bound, then a bound value of 2 times is added to the current phase value my_phase_out (t); otherwise, remain unchanged.
The algorithm of S2 may also be:
if diff1 is greater than bound, then add 1 to the i counter; if diff1 is less than-bound, then add 1 to the j counter; if the values do not meet the preset value, judging the relative values of the counter values of i and j, subtracting the counter with the small value from the counter with the large value, assigning the calculated result to the counter with the large value, and setting the counter with the small value to 0.
As shown in fig. 1, the encapsulating function source code implemented on MATLAB by the algorithm is:
ang is the phase where truncation occurs; bound is a threshold value for judging phase truncation, and when the difference result is larger than bound or smaller than-bound, the phase truncation is judged to occur; i is an up jump counter, a positive integer greater than or equal to 0; j is a down jump counter, a positive integer greater than or equal to 0; xu is the phase where truncation occurs; diff1 is xu (k) -xu (k-1), namely the difference value between the previous phase and the next phase value in the first big step of phase expansion; diff2 is xu (k-1) -xu (k), i.e. the difference between the values of the last phase and the previous phase in the first big step of phase unwrapping; delta is the value of the upper jump counter minus the lower jump counter, and is an integer; the my_phase_out is the result after the first large phase unwrapping step; diff3 is my_phase_out (t) -my_phase_out (t-1), i.e. the difference between the values of the previous phase and the next phase in the second step of phase unwrapping; diff4 is the difference between the values of my_phase_out (t-1) -my_phase_out (t), i.e., the last phase and the previous phase in the second step of phase unwrapping; phase_out is the phase unwrapped final output result.
Example 1:
the algorithm is also applicable to the two-dimensional expansion problem, as shown in fig. 6, an original three-dimensional image constructed in MATLAB is added with noise as shown in fig. 7, a corresponding two-dimensional gray image containing noise is obtained as shown in fig. 8, a three-dimensional phase folding image obtained by arctangent of the above three-dimensional image is shown in fig. 9, the obtained phase folding two-dimensional image is shown in fig. 10, the phase expansion algorithm is applied to the rows and columns of the two-dimensional image, the obtained three-dimensional image is shown in fig. 11, and the data at the edge of the three-dimensional image is independently processed to recover the original image.
Example 2:
the algorithm reforms a one-dimensional phase unwrapping algorithm on a software platform to be suitable for an FPGA platform, and a part of Verilog codes are attached below to illustrate:
the above is a Verilog code segment, specifically speaking a core code implemented on an FPGA, and pi is a fixed point number constant corresponding to a circumference ratio pi; m, N, O, P, Q, L is the number of bits of the corresponding variable. The M, N, O, P, Q, L size can be modified as desired.
The clk is a system clock, when the unbrap_fig is effective when the reset signal is 0, dout_last_reg1 is effective when the data effective signal is 1, pi_2 is a constant number corresponding to 2pi, pi_2n is a constant number corresponding to 2pi×delta, phase_reg1 is a beat result of truncated phase, phase_reg2 is a truncated phase beat result of two beats, data_out_reg is a phase compensation result, data_out is a phase expansion result, and delta is i-j, namely a result of subtracting a down-jump counter by the up-jump counter.
While the embodiments of the present invention have been described above, the scope of the present invention is not limited to the above, and the present invention can be implemented by various modifications without departing from the gist of the present invention, but is included in the scope of protection of the present patent.
The invention solves the problems that the existing basic phase expansion algorithm is very slow to run on a computer and other improved phase expansion algorithms cannot be realized on an FPGA due to the inclusion of remainder, rounding and division operations, has the advantages of simple operation, less consumption resources, high calculation speed, low space and time complexity and the like, is not only suitable for software programming realization, but also can be transplanted to an FPGA platform very easily due to the fact that only multiplication, addition and subtraction and counting operations are used, and can completely solve the problem that no one-dimensional phase expansion algorithm IP core exists on the FPGA platform by setting the bit width of a counter and a multiplier and setting the size of a limit value bound value for judging phase interception.
Claims (3)
1. A phase unwrapping method based on double counters is characterized in that: the method is characterized in that the method comprises a first large step and a second large step, and is characterized in that the first large step comprises the following steps:
s1: calculating a difference diff1=xu (k) -xu (k-1) between a previous phase and a next phase value and a difference diff2=xu (k-1) -xu (k) between a next phase and a previous phase value;
s2: judging whether diff1 and diff2 are larger than a limit value bound of phase truncation, if diff1 is larger than bound, adding 1 to the i jump counter; if diff2 is greater than bound, then add 1 to the j-Down counter; if the value of the counter is not met, judging the relative value of the counter values of i and j, subtracting the counter with small value from the counter with large value, assigning the calculated result to the counter with large value, and setting the counter with small value to 0;
s3: calculating a difference delta of the up-down jump counter, wherein delta=i-j;
s4: compensating the phase, and enabling xu (k-1) =xu (k-1) -2 (delta) to obtain a phase expansion result of the first large step;
the second step comprises the following steps:
s10: calculating a difference value diff3 between the current phase value my_phase_out (t) and the next phase value my_phase_out (t-1) and a difference value diff4 between the current phase value my_phase_out (t) and the previous phase value my_phase_out (t+1);
s20: judging the sizes of diff3, diff4 and bound, and subtracting a bound value which is 2 times from the current phase value my_phase_out (t) if both diff3 and diff4 are larger than bound; if diff3, diff4 are all smaller than-bound, then a bound value of 2 times is added to the current phase value my_phase_out (t); otherwise, remain unchanged.
2. The dual counter based phase unwrapping method of claim 1, wherein: the method of S2 may also be:
if diff1 is greater than bound, then add 1 to the i counter; if diff1 is less than-bound, then add 1 to the j counter; if the values do not meet the preset value, judging the relative values of the counter values of i and j, subtracting the counter with the small value from the counter with the large value, assigning the calculated result to the counter with the large value, and setting the counter with the small value to 0.
3. The dual counter based phase unwrapping method of claim 1, wherein: the method is realized on MATLAB as the source codes of the packaging functions:
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112561861A (en) * | 2020-11-25 | 2021-03-26 | 中科融合感知智能研究院(苏州工业园区)有限公司 | Method and device for realizing binocular phase calculation algorithm |
| CN113054932A (en) * | 2021-03-09 | 2021-06-29 | 中国计量科学研究院 | One-dimensional phase unwrapping algorithm implemented on FPGA |
| CN113132285A (en) * | 2021-03-11 | 2021-07-16 | 西安科锐盛创新科技有限公司 | Digital demodulation system and method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112561861A (en) * | 2020-11-25 | 2021-03-26 | 中科融合感知智能研究院(苏州工业园区)有限公司 | Method and device for realizing binocular phase calculation algorithm |
| CN113054932A (en) * | 2021-03-09 | 2021-06-29 | 中国计量科学研究院 | One-dimensional phase unwrapping algorithm implemented on FPGA |
| CN113132285A (en) * | 2021-03-11 | 2021-07-16 | 西安科锐盛创新科技有限公司 | Digital demodulation system and method |
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