CN115378365A - Frequency multiplier circuit and frequency multiplier - Google Patents
Frequency multiplier circuit and frequency multiplier Download PDFInfo
- Publication number
- CN115378365A CN115378365A CN202210850942.3A CN202210850942A CN115378365A CN 115378365 A CN115378365 A CN 115378365A CN 202210850942 A CN202210850942 A CN 202210850942A CN 115378365 A CN115378365 A CN 115378365A
- Authority
- CN
- China
- Prior art keywords
- frequency
- unit
- circuit
- harmonic
- frequency doubling
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000001629 suppression Effects 0.000 claims abstract description 146
- 239000003990 capacitor Substances 0.000 claims abstract description 68
- 230000005540 biological transmission Effects 0.000 claims abstract description 58
- 238000010586 diagram Methods 0.000 description 34
- 238000004891 communication Methods 0.000 description 6
- 238000001914 filtration Methods 0.000 description 5
- 238000000034 method Methods 0.000 description 4
- 238000004088 simulation Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000002401 inhibitory effect Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000001228 spectrum Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B19/00—Generation of oscillations by non-regenerative frequency multiplication or division of a signal from a separate source
- H03B19/06—Generation of oscillations by non-regenerative frequency multiplication or division of a signal from a separate source by means of discharge device or semiconductor device with more than two electrodes
- H03B19/14—Generation of oscillations by non-regenerative frequency multiplication or division of a signal from a separate source by means of discharge device or semiconductor device with more than two electrodes by means of a semiconductor device
Landscapes
- Transmitters (AREA)
Abstract
The embodiment of the invention provides a frequency multiplier circuit and a frequency multiplier, relating to the field of frequency multipliers, wherein the frequency multiplier circuit comprises: a frequency doubling unit and a harmonic suppression circuit; the input end of the frequency doubling unit is connected with the radio frequency input port and used for receiving an input radio frequency signal so as to perform frequency doubling processing on the radio frequency signal, and the output end of the frequency doubling unit is connected with the radio frequency output port so as to output the radio frequency signal after the frequency doubling processing; wherein, harmonic suppression circuit includes: the frequency doubling unit comprises a transmission line, a first variable capacitor and a harmonic unit, wherein the output end of the frequency doubling unit is also connected with the first variable capacitor through the transmission line, the first variable capacitor is also connected with one end of the harmonic unit, and the other end of the harmonic unit is grounded. By adopting the invention, the reliability and the flexibility of the harmonic suppression circuit in the frequency doubling circuit can be enhanced.
Description
Technical Field
The invention relates to the field of frequency multipliers, in particular to a frequency multiplier circuit and a frequency multiplier.
Background
With the development of communication technology, wireless communication products are rapidly increased, so that the shortage of the original available frequency band occurs, and the development of a frequency band millimeter wave frequency band which is not used is urgently needed. The frequency multiplier can increase the working bandwidth in a frequency multiplication mode and is widely applied to the field of spread spectrum communication.
In order to prevent the frequency multiplier from generating large unwanted harmonic components and thus lowering the harmonic rejection ratio of the system signal, a harmonic network is usually used to perform harmonic rejection. However, the harmonic network in the related art can only suppress a single harmonic, and has a large occupied area and a poor suppression effect.
Disclosure of Invention
The embodiment of the invention provides a frequency multiplier circuit and a frequency multiplier, which can enhance the reliability and flexibility of a harmonic suppression circuit in the frequency multiplier circuit.
In a first aspect, an embodiment of the present invention provides a frequency multiplier circuit, where the frequency multiplier circuit includes: a frequency doubling unit and a harmonic suppression circuit; the input end of the frequency doubling unit is connected with a radio frequency input port for receiving an input radio frequency signal so as to perform frequency doubling processing on the radio frequency signal, and the output end of the frequency doubling unit is connected with a radio frequency output port for outputting the radio frequency signal after the frequency doubling processing;
wherein the harmonic rejection circuit comprises: the frequency multiplication circuit comprises a transmission line, a first variable capacitor and a harmonic unit, wherein the output end of the frequency multiplication unit is also connected with the first variable capacitor through the transmission line, the first variable capacitor is also connected with one end of the harmonic unit, and the other end of the harmonic unit is grounded.
Optionally, the frequency multiplier circuit further includes: a matching circuit; the radio frequency input port is connected with the input end of the frequency doubling unit through the matching circuit.
Optionally, the harmonic unit includes a second variable capacitor and an inductor, one end of the second variable capacitor connected in parallel with the inductor is one end of the harmonic unit, and the other end of the second variable capacitor connected in parallel with the inductor is the other end of the harmonic unit.
Optionally, if the number of the frequency doubling units is at least two, the at least two frequency doubling units are sequentially connected, and the number of the harmonic suppression circuits is at least one group;
and the output end of at least one frequency doubling unit in the at least two frequency doubling units is connected with the transmission line in the corresponding group of harmonic suppression circuits.
Optionally, if the number of the frequency doubling units is two and the number of the harmonic suppression circuits is one, the output end of any one of the two frequency doubling units is connected to one group of the harmonic suppression circuits.
Optionally, if the first frequency doubling unit is a differential frequency doubling unit, the number of the harmonic suppression circuits in the group is two, and both the two differential input ends of the first frequency doubling unit are connected to the radio frequency input port, the two differential output ends of the first frequency doubling unit are connected to transmission lines in the two harmonic suppression circuits in the group of harmonic suppression circuits.
Optionally, the first frequency doubling unit includes: the grid electrode of the first transistor and the grid electrode of the second transistor are two differential input ends of the first frequency doubling unit, the drain electrode of the first transistor and the drain electrode of the second transistor are two differential output ends of the first frequency doubling unit, and the source electrode of the first transistor and the source electrode of the second transistor are grounded.
Optionally, the first transistor and the second transistor are both N-channel MOS transistors.
Optionally, impedance values and physical lengths of transmission lines of two harmonic suppression circuits in one group of the harmonic suppression circuits are equal, and impedance values of harmonic units of two harmonic suppression circuits in one group of the harmonic suppression circuits are equal.
In a second aspect, an embodiment of the present invention further provides a frequency multiplier, where the frequency multiplier includes: a radio frequency input port, a frequency multiplier circuit comprising any of the first aspects, and a radio frequency output port; the input end of a frequency doubling unit in the frequency doubling circuit is connected with the radio frequency input port, and the output end of the frequency doubling unit in the frequency doubling circuit is connected with the radio frequency output port.
The embodiment of the invention provides a frequency doubling circuit and a frequency multiplier, wherein the frequency doubling circuit comprises a frequency doubling unit and a harmonic suppression circuit; the input end of the frequency doubling unit is connected with the radio frequency input port and used for receiving an input radio frequency signal so as to perform frequency doubling processing on the radio frequency signal, and the output end of the frequency doubling unit is connected with the radio frequency output port so as to output the radio frequency signal after the frequency doubling processing; wherein, harmonic suppression circuit includes: the frequency doubling unit comprises a transmission line, a first variable capacitor and a harmonic unit, wherein the output end of the frequency doubling unit is also connected with the first variable capacitor through the transmission line, the first variable capacitor is also connected with one end of the harmonic unit, and the other end of the harmonic unit is grounded. By using the frequency doubling circuit, the length requirement and the occupied area of a transmission line are reduced while the harmonic suppression of a frequency doubling unit is completed by the resonance suppression circuit, the situation that only a single resonance circuit is used for suppressing a specific certain harmonic is avoided, the number of harmonic suppression frequency points is increased, the harmonic suppression circuit is formed by using a variable capacitor, the harmonic suppression frequency points can meet the requirement of user conversion by adjusting the capacitor, and the reliability and the flexibility of the harmonic suppression circuit in the frequency doubling circuit are enhanced.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
Fig. 1 is a schematic diagram of a frequency multiplier circuit according to the present invention;
fig. 2 is a schematic diagram of another frequency multiplier circuit according to the present invention;
fig. 3 is a second schematic diagram of a frequency multiplier circuit according to the present invention;
fig. 4 is a third schematic diagram of a frequency multiplier circuit according to another embodiment of the present invention;
fig. 5 is a fourth schematic diagram of a frequency multiplier circuit according to the present invention;
fig. 6 is a fifth schematic diagram of a frequency multiplier circuit according to the present invention;
fig. 7 is a sixth schematic diagram of a frequency multiplier circuit according to the present invention;
fig. 8 is a seventh schematic diagram of another frequency multiplier circuit according to the present invention;
fig. 9 is an eighth schematic diagram of a frequency multiplier circuit according to another embodiment of the present invention;
FIG. 10 is a ninth schematic diagram of a frequency multiplier circuit according to another embodiment of the present invention;
fig. 11 is a tenth schematic diagram of another frequency multiplier circuit according to the present invention;
fig. 12 is a filtering simulation diagram of a harmonic suppression circuit according to the present invention;
fig. 13 is a schematic diagram of a frequency multiplier according to the present invention.
Icon: 1, a frequency doubling unit; 2, a radio frequency input port; 3, a radio frequency output port; 4, a frequency multiplier; 10, a frequency doubling unit; 11, a first frequency doubling unit; 12, a second frequency doubling unit; 20, a harmonic suppression circuit; 21, harmonic units; 30, a matching circuit; 31, an input matching circuit; 32, an output matching circuit; and 33, an interstage matching circuit.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
In the description of the present invention, the terms "first", "second", and the like, if any, are used only for distinguishing the description, and are not intended to indicate or imply relative importance.
It should be noted that the features of the embodiments of the present invention may be combined with each other without conflict.
Before explaining the present invention in detail, an application scenario of the present invention will be described.
As wireless communication technology is continuously developed along with the advancement of information technology, users have made higher demands on modern wireless communication, and it is expected that a communication system can perform data transmission at a higher rate with a larger bandwidth. However, the original available frequency band is becoming increasingly exhausted, so that the millimeter wave frequency band is drawing more and more attention, and the anti-interference capability and the penetration capability of the millimeter wave frequency band are both stronger. When a signal meeting the requirement is required to be acquired, the low-frequency signal source can be converted into a required millimeter wave frequency source in a frequency doubling mode.
For a frequency multiplier circuit, the core devices are nonlinear devices. When the nonlinear device is excited by a sine signal, each harmonic of the input signal can be obtained at the output end of the nonlinear device, and the effect of frequency multiplication can be achieved only by reserving the required harmonic signal and filtering out the unnecessary clutter signal.
In order to obtain a high-purity frequency multiplication signal at the output end of the frequency multiplication circuit, a harmonic suppression circuit is generally adopted at the output end of the frequency multiplication circuit. However, the conventional harmonic suppression circuit can only suppress a certain frequency point, and has poor flexibility and large occupied area. Meanwhile, the harmonic suppression point of the conventional harmonic suppression circuit is fixed after the processing is finished, so that a user cannot adjust the harmonic suppression point according to actual requirements, and the harmonic suppression effect is poor.
Based on this, the invention provides a frequency multiplier circuit and a frequency multiplier, wherein the frequency multiplier circuit comprises a frequency multiplier unit and a harmonic suppression circuit; the input end of the frequency doubling unit is connected with the radio frequency input port and used for receiving an input radio frequency signal so as to perform frequency doubling processing on the radio frequency signal, and the output end of the frequency doubling unit is connected with the radio frequency output port so as to output the radio frequency signal after the frequency doubling processing; wherein, harmonic suppression circuit includes: the output end of the frequency doubling unit is also connected with the first variable capacitor through the transmission line, the first variable capacitor is also connected with one end of the harmonic unit, and the other end of the harmonic unit is grounded, so that the reliability and the flexibility of a harmonic suppression circuit in the frequency doubling circuit are enhanced.
The following is an explanation by way of various embodiments in conjunction with the accompanying drawings. Fig. 1 is a schematic diagram of a frequency multiplier circuit according to the present invention. As shown in fig. 1, the frequency multiplier circuit 1 includes: frequency multiplication unit 10 and harmonic suppression circuit 20. The input end of the frequency doubling unit 10 is connected to the rf input port for receiving an input rf signal to perform frequency doubling processing on the rf signal, and the output end of the frequency doubling unit 10 is connected to the rf output port for outputting the rf signal after frequency doubling processing.
The frequency doubling unit 10 may enable the frequency of the output frequency-doubled radio-frequency signal to be a specific multiple of the input frequency, and the frequency doubling multiple achieved by the frequency doubling unit 10 is not specifically limited in this application. The frequency doubling unit 10 may be composed of a passive device (diode, etc.) or an active device (field effect transistor, etc.), so as to implement the function of frequency doubling by utilizing the nonlinear characteristics of the device. The frequency doubling unit 10 may include a push-push (push-push structure), a single-tube structure, an injection locking structure, and the like, which implement frequency doubling.
Generally, for the frequency multiplier circuit 1, the harmonic rejection ratio is one of the performance indicators of major concern. To achieve a desired harmonic rejection ratio, a harmonic rejection circuit is required. In the present embodiment, the harmonic suppression circuit 20 includes: the frequency multiplier comprises a transmission line TL1, a first variable capacitor C1 and a harmonic unit 21, wherein the output end of the frequency doubling unit 10 is further connected with the first variable capacitor C1 through the transmission line TL1, the first variable capacitor C1 is further connected with one end of the harmonic unit 21, and the other end of the harmonic unit 21 is grounded.
A transmission line is a dedicated cable or other structured conductor that transmits radio frequency signals. The structural form of the transmission line has a certain influence on the transmission of radio frequency signals, and simultaneously determines the size and the performance of the frequency multiplier circuit 1. In this application, the transmission line may optionally be a microstrip line, a stripline, a waveguide structure, or the like, in this embodiment, a microstrip line of a silicon-based process may be used as the transmission line TL1, and the length and the characteristic impedance of the transmission line TL1 are not specifically limited. For the harmonic suppression circuit 20, the adjustment of the harmonic suppression frequency point can be realized by changing the inductance value or the capacitance value, and since the inductance value cannot be continuously changed in the integrated circuit, the adjustment of the frequency suppression point of the harmonic suppression circuit 20 can be realized by using a variable capacitance. Alternatively, the harmonic cell 21 may include an inductance and a variable capacitance. In the present application, the harmonic suppression circuit 20 mainly functions as a filter, and passes a desired frequency and filters an undesired frequency.
In the present application, a silicon-based CMOS (Complementary Metal Oxide Semiconductor) process may be used to construct the frequency multiplier circuit 1, and a 65-nmCMOS process or a 180-nmCMOS process may be selected, which is not limited in the present application.
The working flow of the frequency multiplier circuit is explained by taking fig. 1 as an example. When a radio frequency signal is input from a radio frequency input port, enters an input end of a frequency doubling unit 10 in a frequency doubling circuit 1, reaches frequency doubling processing through the frequency doubling unit 10, outputs the radio frequency signal after the frequency doubling processing from an output end of the frequency doubling unit 10, and then the radio frequency signal after the frequency doubling processing finally reaches a radio frequency output port after being processed by a harmonic suppression circuit formed by a transmission line TL1, a first adjustable capacitor C1 and a harmonic unit 21.
Compared with the traditional circuit structure formed by only connecting a transmission line and a capacitor in series, the transmission line is the harmonic suppression circuit 20 in the application, so that the length of the transmission line can be effectively reduced, the layout area of the frequency doubling unit 10 can be effectively reduced, and the integration of the frequency doubling circuit 1 is facilitated.
For the frequency multiplier circuit 1 provided in fig. 1, the impedance of the harmonic suppression circuit 20 is set to Z L The impedance of the resonant network formed by the first variable capacitor and the harmonic unit 21 is Z X Characteristic impedance of transmission line TL1 is Z o When the physical length is d, the phase velocity in the medium is v, and the angular frequency is ω, the impedance of the harmonic suppression circuit 20 is Z obtained by the formula (1) L Relationships with the above parameters:
in this embodiment, the impedance Z of the resonant network can be adjusted continuously X Thereby causing the impedance Z of the harmonic suppression circuit 20 L While being as small as possible, the value of ω corresponds to a frequency magnitude that is a frequency suppression point desired by the user. In this embodiment, if Z is set L =0, when the remaining parameters are all taken into known quantities, a plurality of ω values can be solved, so as to correspond to a plurality of harmonic suppression frequency points, that is, in this embodiment, a single harmonic suppression circuit can provide a plurality of harmonic suppression points, thereby avoiding poor suppression effect caused by a single harmonic suppression point. Meanwhile, the impedance Z of the resonant network can be ensured by continuously adjusting the size of the variable capacitor X The value of (c) is changed, so that the value of ω is changed, and the harmonic suppression frequency point is made to continuously meet the requirement of a user.
In the embodiment, the resonance suppression circuit can reduce the length requirement and the floor area of the transmission line while finishing the harmonic suppression of the frequency doubling unit, avoid that only a single resonance circuit can only suppress a specific certain harmonic, increase the number of harmonic suppression frequency points, and use a variable capacitor to form the harmonic suppression circuit, so that the harmonic suppression frequency points can meet the requirement of user transformation by adjusting the capacitor, and the reliability and the flexibility of the harmonic suppression circuit are enhanced.
On the basis of the schematic diagram of the frequency multiplier circuit provided in fig. 1, the present application also provides a possible implementation manner of the frequency multiplier circuit. Fig. 2 is another schematic diagram of a frequency multiplier circuit according to the present invention. As shown in fig. 2, the frequency multiplier circuit 1 further includes: and a radio frequency input port of the matching circuit 30 is connected with the input end of the frequency doubling unit 10 through the matching circuit 30.
In the frequency multiplier circuit 1, the current and the voltage are transmitted like waves in a transmission line, and when a load or other network ports are met, a reflection phenomenon occurs, so that signals at an output end and signals at an input end are mixed, and radio frequency signals are deformed. In order to minimize reflections during transmission and maximize the reception of the rf signal by the frequency doubling unit 10, a matching circuit is needed. In this embodiment, the input end of the frequency doubling unit 10 is connected to the matching circuit 30, and the matching circuit here functions as an input matching circuit, so that the signal-to-noise ratio of the whole frequency doubling circuit can be improved. Alternatively, the matching circuit 30 may have a circuit structure such as an L-type, T-type, or pi-type matching circuit, which is not limited in this application.
In this embodiment, the matching circuit is added to reduce the loss of the radio frequency signal, transmit the radio frequency signal to the frequency doubling circuit to the maximum, suppress the leakage of the higher harmonic signal as much as possible, and assist the radio frequency signal to obtain higher frequency doubling efficiency.
Optionally, this embodiment also provides a possible implementation manner of the frequency multiplier circuit. Fig. 3 is a second schematic diagram of a frequency multiplier circuit according to another embodiment of the present invention. As shown in fig. 3, in the frequency doubling circuit 1, a radio frequency input port is connected to an input end of a frequency doubling unit 10 through an input matching circuit 31, and an output end of the frequency doubling unit 10 is connected to a radio frequency output port through an output matching circuit 32.
In this embodiment, matching circuits are connected to the input and output of the frequency multiplier unit 10. For the input matching circuit 31, the main role is to transmit the original rf signal to the frequency doubling unit 10 to the maximum; the main function of the output matching circuit 32 is to maximally transmit the frequency-doubled rf signal to the rf output port, so as to reduce the transmission loss of the rf signal at the output end.
When a radio frequency signal is input from the radio frequency input port, the radio frequency signal firstly enters the input end of the frequency doubling unit 10 in the frequency doubling circuit 1 through the input matching circuit 31, the frequency doubling unit 10 performs frequency doubling processing on the frequency, the radio frequency signal after the frequency doubling processing is output from the output end of the frequency doubling unit 10, and then the radio frequency signal after the frequency doubling processing is processed by the harmonic suppression circuit formed by the transmission line TL1, the first adjustable capacitor C1 and the harmonic unit 21 and finally reaches the radio frequency output port through the output matching circuit 32.
In this embodiment, the matching circuits are added to both the input end and the output end of the frequency doubling unit, so that the loss of the radio frequency signal in transmission is reduced, and the frequency doubling efficiency of the frequency doubling circuit is improved.
The present invention also provides a possible implementation of a frequency doubling circuit in order to clearly introduce the structure of the harmonic suppression circuit 20. Fig. 4 is a third schematic diagram of another frequency multiplier circuit according to the present invention. As shown in fig. 4, the harmonic unit 21 includes a second variable capacitor C2 and an inductor L1, one end of the second variable capacitor C2 connected in parallel with the inductor L1 is one end of the harmonic unit 21, and the other end of the second variable capacitor C2 connected in parallel with the inductor L1 is the other end of the harmonic unit 21. The specific parameters of the second capacitor and the inductor are not particularly limited in this application.
In the present embodiment, the impedance of the harmonic suppression circuit 20 is set to Z L The impedance of the resonant network formed by the first variable capacitor and the harmonic unit 21 is Z X The capacitance value of the first variable capacitor C1 is C 1 The capacitance value of the second variable capacitor is C 2 The inductance of the inductor L1 is L, and the characteristic impedance of the transmission line TL1 is Z o When the physical length is d, the phase velocity in the medium is v, and the angular frequency is ω, the impedance of the harmonic suppression circuit 20 can be obtained as Z by the formula (1) L Relationships with the above parameters:
in the above formula, the impedance of the resonant network formed by the first variable capacitor and the harmonic cell 21 is Z X This can be obtained by equation (2):
in this embodiment, the impedance Z of the resonant network can be adjusted by continuously adjusting the capacitance values of the first variable capacitor C1 and the second variable capacitor C2 X Thereby causing the impedance Z of the harmonic suppression circuit 20 L The frequency corresponding to the value of ω is set to be as small as possibleThe frequency rejection point desired by the user. In this embodiment, if Z is set L =0, when the remaining parameters are all taken into known quantities, a plurality of ω values can be solved, so as to correspond to a plurality of harmonic suppression frequency points, that is, in this embodiment, a single harmonic suppression circuit can provide a plurality of harmonic suppression points, thereby avoiding poor suppression effect caused by a single harmonic suppression point. Meanwhile, the impedance Z of the resonant network can be ensured by continuously adjusting the size of the variable capacitor X The value of (c) is changed, so that the value of ω is changed, and the harmonic suppression frequency point is made to continuously meet the requirement of a user.
In this embodiment, the structure of the harmonic unit 21 includes a variable capacitor and an inductor connected in parallel, and the harmonic unit 21 is further connected in series with a variable capacitor and a transmission line to form the harmonic suppression circuit 20, so as to reduce the length requirement of the transmission line and ensure the harmonic suppression effect.
On the basis of the schematic diagram of the frequency multiplier circuit provided in fig. 1, the present application also provides a possible implementation manner of the frequency multiplier circuit. Fig. 5 is a fourth schematic diagram of a frequency multiplier circuit according to another embodiment of the present invention. As shown in fig. 5, in the frequency multiplier circuit 1, the number of the frequency multiplier units 10 is at least two, and at least two of the frequency multiplier units 10 are connected in sequence. In this embodiment, in order to achieve the frequency doubling effect of high frequency doubling, the frequency doubling circuit 1 at least connects two frequency doubling units 10 in series, and the frequency doubling times finally achieved by the frequency doubling circuit 1 are the products of the respective frequency doubling times of the two frequency doubling units 10. For example, if two frequency doubling units 10 connected in series exist in the frequency doubling circuit 1, one of the frequency doubling units 10 is a frequency tripling frequency doubling unit 10, and the other frequency doubling unit 10 is a frequency doubling unit 10, the frequency doubling frequency that can be achieved by the frequency doubling circuit 1 finally is a frequency sextupole.
In this embodiment, there are at least two frequency doubling units 10, the number of the harmonic suppression circuits 20 is at least one group, and the output end of at least one frequency doubling unit 10 in the at least two frequency doubling units 10 is connected to the transmission line in the corresponding group of harmonic suppression circuits 20. As shown in fig. 4, the output end of one frequency doubling unit 10 is connected to the transmission lines in one set of harmonic suppression circuits 20, including TL1 and TL2, where TL1 and TL2 are two transmission lines in two harmonic suppression circuits 20 of the same circuit structure in one set of harmonic suppression circuits 20. The circuit structure of the harmonic suppression circuits 20 in the same group and the parameters of the devices in the circuit are the same. Alternatively, if there are three frequency doubling units 10 connected in series in the frequency doubling circuit 1, a group of transmission lines in the harmonic suppression circuit 20 is also connected to the output end of the second frequency doubling unit 10.
In this embodiment, a plurality of frequency doubling units are sequentially connected to form a frequency doubling circuit with high frequency doubling by matching with the harmonic suppression circuit, so as to realize high frequency doubling processing on the radio frequency signal.
Optionally, in this application, if the number of the frequency doubling units 10 is two and the number of the harmonic suppression circuits 20 is one, the output end of any one frequency doubling unit 10 of the two frequency doubling units 10 is connected to one group of the harmonic suppression circuits 20.
On the basis of the schematic diagram of the frequency multiplier circuit provided in fig. 1, the present application also provides a possible implementation manner of the frequency multiplier circuit. Fig. 6 is a fifth schematic diagram of another frequency multiplier circuit according to the present invention. As shown in fig. 6, in the present embodiment, the frequency multiplier circuit 1 includes: two frequency doubling units 10, a set of harmonic suppression circuits 20; if the number of the frequency doubling units 10 is two, the number of the harmonic suppression circuits 20 is one, in this embodiment, the output end of the first frequency doubling unit of the two frequency doubling units 10 is connected to one group of the harmonic suppression circuits 20. The first frequency doubling unit is a frequency doubling unit of which the input end is directly connected with the radio frequency input port.
Optionally, on the basis of the schematic diagram of the frequency multiplier circuit provided in fig. 1, the present application further provides a possible implementation manner of the frequency multiplier circuit. Fig. 7 is a sixth schematic diagram of another frequency multiplier circuit according to the present invention. As shown in fig. 7, in the present embodiment, the frequency multiplier circuit 1 includes: two frequency doubling units 10, a set of harmonic suppression circuits 20; if the number of the frequency doubling units 10 is two, the number of the harmonic suppression circuits 20 is one, and in this embodiment, the output end of the second frequency doubling unit of the two frequency doubling units 10 is connected to one group of the harmonic suppression circuits 20. The second frequency doubling unit is a frequency doubling unit whose output end is directly connected with the radio frequency input port after passing through a group of harmonic suppression circuits 20.
Alternatively, in order to clearly describe the circuit structure when two frequency doubling units are connected in sequence, the invention provides a possible implementation mode of the frequency doubling circuit. Fig. 8 is a seventh schematic diagram of another frequency multiplier circuit according to the present invention. As shown in fig. 8, the frequency multiplier circuit 1 includes: a first frequency doubling unit 11, a second frequency doubling unit 12, and a group of harmonic suppression circuits 20; if the first frequency doubling unit 11 is a differential frequency doubling unit, the number of the harmonic suppression circuits 20 in the group is two, and both the two differential input ends of the first frequency doubling unit 11 are connected to the radio frequency input port, the two differential output ends of the first frequency doubling unit 11 are connected to the transmission lines in the two harmonic suppression circuits 20 in the group of harmonic suppression circuits 20.
In this embodiment, for two sequentially connected frequency doubling units 10, a first frequency doubling unit 11 is a differential frequency doubling unit, that is, the first frequency doubling unit 11 is a frequency doubling unit with differential input and differential output, when a radio frequency signal is two differential signals with the same potential amplitude and opposite polarity, the radio frequency signal is input from two differential input ends of the first frequency doubling unit 11, frequency-doubled by the first frequency doubling unit 11, then input into a differential input end of a second frequency doubling unit 12 through transmission lines in two harmonic suppression circuits in a set of harmonic suppression circuits 20, and finally output from an output end of the second frequency doubling unit 12. The circuit structure of the same group of harmonic suppression circuits 20 and the parameters of each device in the circuit are the same, and the second frequency doubling unit 12 is a circuit structure with differential input and single output.
Optionally, in order to clearly describe the structure of the first frequency doubling unit 11, the present invention also provides a possible implementation manner of the frequency doubling circuit. Fig. 9 is an eighth schematic diagram of a frequency multiplier circuit according to another embodiment of the present invention. As shown in fig. 9, the first frequency multiplying unit 11 includes: the frequency multiplier comprises a first transistor M1 and a second transistor M2, wherein a gate of the first transistor M1 and a gate of the second transistor M2 are used as two differential input ends of a first frequency multiplier unit 11, a drain of the first transistor M1 and a drain of the second transistor M2 are used as two differential output ends of the first frequency multiplier unit 11, and a source of the first transistor M1 and a source of the second transistor M2 are grounded. The gates of the first transistor M1 and the second transistor M2 are used for receiving an input radio frequency signal, the sources are grounded, and when the voltage received by the gates meets the conduction requirement, the first transistor M1 and the second transistor M2 are turned on.
Optionally, in this embodiment, the first transistor M1 and the second transistor M2 are both N-channel MOS transistors.
As shown in fig. 9, the first frequency doubling unit 11 is a frequency multiplier with a push-push structure, where two differential signals with the same potential amplitude and opposite polarities can be injected into the gates of two identical transistors, and a radio frequency signal after frequency doubling processing is obtained at the drains of the two transistors. In the structure, the odd harmonic frequency multiplication gain of the frequency multiplication unit can be obviously improved, the inhibiting capability of even harmonic is increased, and higher frequency multiplication gain is realized.
Alternatively, for the harmonic suppression circuits 20 in the same frequency doubling circuit 1, the impedance values and the physical lengths of the transmission lines of the two harmonic suppression circuits 20 in one group of the harmonic suppression circuits 20 are equal, the impedance values of the harmonic units 21 of the two harmonic suppression circuits 20 in one group of the harmonic suppression circuits 20 are equal, and simultaneously, the capacitance values of the variable capacitors connected between the transmission lines of the two harmonic suppression circuits 20 and the harmonic units 21 in one group of the harmonic suppression circuits 20 are also equal, so that a plurality of harmonic suppression frequency points of the frequency doubling circuit 1 can be calculated by using the formula (1) and the formula (2).
Alternatively, if a plurality of harmonic suppression circuits 20 exist in one frequency multiplier circuit 1, the impedance value and the physical length of the transmission line of each harmonic suppression circuit 20 are equal, the impedance value of the included harmonic unit 21 is equal, and the capacitance value of the variable capacitance between the transmission line and the harmonic unit is also equal.
In one possible implementation, if the harmonic cell 21 is composed of a variable capacitor and an inductor connected in parallel, then for a set of harmonic suppression circuits 20, the capacitance values of the two variable capacitors included in the two harmonic cells 21 are equal, the inductance values of the two inductors included in the two harmonic suppression circuits 21 are equal, the impedance values and physical lengths of the transmission lines in the two harmonic suppression circuits 20 are equal, and the capacitance values of the variable capacitors connected between the transmission lines in the two harmonic suppression circuits 20 and the harmonic cells are also equal.
On the basis of the above embodiment, the present invention also provides a possible implementation manner of the frequency multiplier circuit. Fig. 10 is a ninth schematic diagram of a frequency multiplier circuit according to another embodiment of the present invention. As shown in fig. 10, the frequency multiplier circuit 1 includes: the input matching circuit 31, the first frequency multiplication unit 11, the interstage matching circuit 33, the second frequency multiplication unit 12 and the two harmonic suppression circuits 20.
Wherein, the first frequency doubling unit 11 includes: the first transistor M1 and the second transistor M2, a gate of the first transistor M1 and a gate of the second transistor M2 are used as two differential input ends of the first frequency doubling unit 11, a drain of the first transistor M1 and a drain of the second transistor M2 are two differential output ends of the first frequency doubling unit 11, a source of the first transistor M1 and a source of the second transistor M2 are grounded, and the first transistor M1 and the second transistor M2 are both N-channel MOS transistors. Optionally, the first frequency doubling unit 11 provides frequency doubling processing of triple frequency, and the second frequency doubling unit 12 provides frequency doubling processing of double frequency, so that the frequency doubling circuit 1 provides frequency doubling processing of six frequency doubling for the radio frequency signal.
A harmonic rejection circuit 20 comprising: the frequency doubling circuit comprises a transmission line TL1, a first variable capacitor C1, a second variable capacitor C2 and an inductor L1, wherein one end of the second variable capacitor C2, which is connected with the inductor L1 in parallel, is the end of a harmonic unit 21 and is connected with the first variable capacitor C1, the other end of the second variable capacitor C2, which is connected with the inductor L1 in parallel, is the other end of the harmonic unit 21 and is grounded, a differential output end of a first frequency doubling unit 11 is connected with the first variable capacitor C1 through the transmission line TL1, and the transmission line TL1 is further connected with a differential input end of an interstage matching circuit 33; the other harmonic rejection circuit 20 includes: another transmission line TL2, a third variable capacitor C3, a fourth variable capacitor C4 and an inductor L2, one end of the fourth variable capacitor C4 and the inductor L1 after being connected in parallel is the end of the harmonic unit 21 connected to the third variable capacitor C3, the other end of the fourth variable capacitor C4 and the inductor L1 after being connected in parallel is the other end of the harmonic unit 21 grounded, another differential output end of the first frequency doubling unit 11 is connected to the third variable capacitor C3 through another transmission line TL2, and another transmission line TL2 is further connected to another differential input end of the inter-stage matching circuit 33.
The differential output end of the interstage matching circuit 33 is further connected with the differential input end of the second frequency doubling unit 12, and the output end of the second frequency doubling unit 12 is connected with the radio frequency output port.
In this embodiment, a radio frequency signal is input into the frequency doubling circuit 1 from a radio frequency input port, a single-end input signal is converted into a differential signal by the input matching circuit 31 and input into the first frequency doubling unit 11 for first frequency doubling processing, then the differential signal reaches the input ends of the two harmonic suppression circuits 20 through the two differential output ends of the first frequency doubling unit 11, after the harmonic suppression processing, the differential signal reaches the second frequency doubling unit 12 through the inter-stage matching circuit 33 for second frequency doubling processing, and finally the processed radio frequency signal is transmitted to a radio frequency output port through the output end of the second frequency doubling unit 12.
In this embodiment, the impedance values and the physical lengths of TL1 and TL2 are equal, the capacitance value of the first variable capacitor C1 is equal to the capacitance value of the third variable capacitor C3, the capacitance value of the second variable capacitor C2 is equal to the capacitance value of the fourth variable capacitor C4, and the multiple harmonic suppression frequency points of the frequency multiplier circuit 1 can be calculated by using the formula (1) and the formula (2). Alternatively, suitable parameters may be selected such that the harmonic frequency rejection points are exactly at the fundamental and fifth harmonic frequencies output by the first frequency multiplying unit 11.
Optionally, on the basis of the schematic diagram of the frequency multiplier circuit provided in fig. 1, the present application also provides a possible implementation manner of the frequency multiplier circuit. Fig. 11 is a tenth schematic diagram of another frequency multiplier circuit according to the present invention. As shown in fig. 11, in the present embodiment, the frequency multiplier circuit 1 includes: two frequency doubling units 10, two sets of harmonic suppression circuits 20; if the number of the frequency doubling units 10 is two, the number of the harmonic suppression circuits 20 is two, and the output ends of the two frequency doubling units 10 are connected to one group of the harmonic suppression circuits 20. Optionally, in this embodiment, both of the two frequency doubling units are differential frequency doubling units, and provide differential input and differential output.
Optionally, in order to illustrate the harmonic suppression effect of the harmonic suppression circuit 20, the present invention further provides a filtering simulation diagram of the harmonic suppression circuit. FIG. 12 is a schematic view ofThe invention provides a filtering simulation diagram of a harmonic suppression circuit. As shown in fig. 12, the diagram is a simulation diagram of the filtering at the output end of the harmonic suppression circuit 20, at the frequency f 1 =10Ghz and f 2 In case of =50Ghz, the frequency multiplication loss can be made low, i.e. f 1 And f 2 Namely, two harmonic suppression frequency points of the frequency doubling circuit 1, two harmonic suppression frequency points exist in the frequency doubling circuit 1.
Alternatively, if desired f 1 And f 2 According to the harmonic suppression frequency desired by the user, the parameters of the variable capacitors included in the harmonic suppression circuit 20 can be continuously adjusted through the formula (1) and the formula (2), so that the obtained ω is 1 And ω 2 Consistent with the desired harmonic rejection frequency.
Optionally, on the basis of the frequency multiplier circuit 1 provided in the above embodiment, the present invention further provides a possible implementation manner of a frequency multiplier. Fig. 13 is a schematic diagram of a frequency multiplier according to the present invention. As shown in fig. 13, the frequency multiplier 4 includes: a radio frequency input port 2, a frequency multiplier circuit 1 including any of the above embodiments, and a radio frequency output port 3; the input end of a frequency doubling unit 10 in the frequency doubling circuit 1 is connected with the radio frequency input port 2, and the output end of the frequency doubling unit 10 in the frequency doubling circuit 1 is connected with the radio frequency output port 3.
By using the frequency multiplier, the length requirement and the floor area of a transmission line are reduced while the harmonic suppression of a frequency multiplication unit is completed by the resonance suppression circuit in the frequency multiplier, the situation that only a single resonance circuit is used for suppressing a specific certain harmonic is avoided, the number of harmonic suppression frequency points is increased, the harmonic suppression circuit is formed by using a variable capacitor, the harmonic suppression frequency points can meet the requirement of user conversion by adjusting the capacitor, and the reliability and the flexibility of the harmonic suppression circuit are enhanced.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are also within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
Claims (10)
1. A frequency multiplier circuit, characterized in that the frequency multiplier circuit comprises: a frequency doubling unit and a harmonic suppression circuit; the input end of the frequency doubling unit is connected with a radio frequency input port for receiving an input radio frequency signal so as to perform frequency doubling processing on the radio frequency signal, and the output end of the frequency doubling unit is connected with a radio frequency output port for outputting the radio frequency signal after the frequency doubling processing;
wherein the harmonic rejection circuit comprises: the frequency multiplication circuit comprises a transmission line, a first variable capacitor and a harmonic unit, wherein the output end of the frequency multiplication unit is also connected with the first variable capacitor through the transmission line, the first variable capacitor is also connected with one end of the harmonic unit, and the other end of the harmonic unit is grounded.
2. The frequency doubling circuit of claim 1, further comprising: a matching circuit; the radio frequency input port is connected with the input end of the frequency doubling unit through the matching circuit.
3. The frequency doubling circuit according to claim 1, wherein the harmonic unit includes a second variable capacitor and an inductor, one end of the second variable capacitor connected in parallel with the inductor is one end of the harmonic unit, and the other end of the second variable capacitor connected in parallel with the inductor is the other end of the harmonic unit.
4. The frequency multiplier circuit of claim 1, wherein if the number of the frequency multiplying units is at least two, at least two of the frequency multiplying units are connected in sequence, and the number of the harmonic suppression circuits is at least one group;
and the output end of at least one frequency doubling unit in the at least two frequency doubling units is connected with the transmission line in the corresponding group of harmonic suppression circuits.
5. The frequency multiplier circuit of claim 1, wherein if the number of the frequency multiplying units is two and the number of the harmonic suppression circuits is one, the output terminal of any one of the two frequency multiplying units is connected to one of the harmonic suppression circuits.
6. The frequency doubling circuit according to claim 5, wherein if the first frequency doubling unit is a differential frequency doubling unit, the number of the harmonic suppression circuits in a group is two, and both differential input terminals of the first frequency doubling unit are connected to the radio frequency input port, the two differential output terminals of the first frequency doubling unit are connected to transmission lines of two harmonic suppression circuits in a group of the harmonic suppression circuits.
7. The frequency multiplier circuit of claim 6, wherein the first frequency multiplier unit comprises: the grid electrode of the first transistor and the grid electrode of the second transistor are two differential input ends of the first frequency doubling unit, the drain electrode of the first transistor and the drain electrode of the second transistor are two differential output ends of the first frequency doubling unit, and the source electrode of the first transistor and the source electrode of the second transistor are grounded.
8. The frequency multiplier circuit of claim 7, wherein the first transistor and the second transistor are both N-channel MOS transistors.
9. The frequency doubling circuit of claim 5, wherein the impedance values and physical lengths of the transmission lines of two harmonic suppression circuits in a group of the harmonic suppression circuits are equal, and the impedance values of the harmonic elements of two harmonic suppression circuits in a group of the harmonic suppression circuits are equal.
10. A frequency multiplier, characterized in that the frequency multiplier comprises: a radio frequency input port, comprising a frequency multiplier circuit according to any of claims 1-9, and a radio frequency output port; the input end of a frequency doubling unit in the frequency doubling circuit is connected with the radio frequency input port, and the output end of the frequency doubling unit in the frequency doubling circuit is connected with the radio frequency output port.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210850942.3A CN115378365A (en) | 2022-07-19 | 2022-07-19 | Frequency multiplier circuit and frequency multiplier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210850942.3A CN115378365A (en) | 2022-07-19 | 2022-07-19 | Frequency multiplier circuit and frequency multiplier |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN115378365A true CN115378365A (en) | 2022-11-22 |
Family
ID=84062702
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210850942.3A Pending CN115378365A (en) | 2022-07-19 | 2022-07-19 | Frequency multiplier circuit and frequency multiplier |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115378365A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN118232842A (en) * | 2024-05-23 | 2024-06-21 | 西北工业大学 | Broadband injection locking frequency multiplier with variable frequency multiplication ratio |
-
2022
- 2022-07-19 CN CN202210850942.3A patent/CN115378365A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN118232842A (en) * | 2024-05-23 | 2024-06-21 | 西北工业大学 | Broadband injection locking frequency multiplier with variable frequency multiplication ratio |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10230348B2 (en) | Sub-network enhanced reflectionless filter topology | |
| CN107565201B (en) | A kind of microwave oscillator with low phase noise | |
| CN109245726B (en) | Double-push frequency multiplier suitable for extremely high frequency | |
| CN114514704B (en) | Broadband transmitter for millimeter wave wireless communication | |
| CN109449548B (en) | Reconfigurable multifunctional filter based on half-wave resonator | |
| CN110460310A (en) | A kind of ultra wide band higher harmonics inhibition Terahertz frequency multiplier | |
| US8686790B2 (en) | Distributed amplifier for band pass radio front-end | |
| CN115378365A (en) | Frequency multiplier circuit and frequency multiplier | |
| CN216903297U (en) | Quadrature coupler and radio frequency module | |
| CN113922780A (en) | Power divider applicable to Doherty PA | |
| CN103338016B (en) | A kind of lumped parameter there are harmonic restraining function 90 degree of orthocouplers | |
| CN117498807A (en) | Monolithic integrated harmonic quadrature down mixer based on novel multifunctional mixed junction | |
| CN108631734A (en) | A kind of millimeter wave broadband frequency mixer based on multiple coupled transmission line | |
| CN111884615A (en) | High-order broadband input impedance matching network and application thereof | |
| CN113794447B (en) | Active frequency multiplier, frequency multiplication amplifying circuit and MMIC chip | |
| CN116317956A (en) | Quadruple frequency device and frequency source | |
| EP0266198A2 (en) | A distributed balanced frequency multiplier | |
| CN203984356U (en) | Millimeter based on avalanche diode involves Terahertz ten fifth overtone frequency mixers | |
| Abata et al. | A V-band two pole high-pass filter for frequency quadrupler design | |
| JP2008054174A (en) | 90-degree hybrid circuit | |
| US20120146747A1 (en) | Millimeter-wave wideband frequency doubler | |
| CN114759336B (en) | Four-frequency power divider based on coupled line and design method thereof | |
| CN118249747B (en) | High harmonic rejection ratio broadband injection locking double-frequency multiplier | |
| CN114946080B (en) | Filtering circuit | |
| US20240072405A1 (en) | Compact balun with out-of-band spurious suppression |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |