CN115377099B - Negative pressure isolation device and process method and chip thereof - Google Patents
Negative pressure isolation device and process method and chip thereof Download PDFInfo
- Publication number
- CN115377099B CN115377099B CN202211064652.2A CN202211064652A CN115377099B CN 115377099 B CN115377099 B CN 115377099B CN 202211064652 A CN202211064652 A CN 202211064652A CN 115377099 B CN115377099 B CN 115377099B
- Authority
- CN
- China
- Prior art keywords
- well
- active region
- buried layer
- double
- diffusion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
- H01L27/0744—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common without components of the field effect type
- H01L27/075—Bipolar transistors in combination with diodes, or capacitors, or resistors, e.g. lateral bipolar transistor, and vertical bipolar transistor and resistor
- H01L27/0755—Vertical bipolar transistor in combination with diodes, or capacitors, or resistors
- H01L27/0772—Vertical bipolar transistor in combination with resistors only
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H11/00—Emergency protective circuit arrangements for preventing the switching-on in case an undesired electric working condition might result
- H02H11/006—Emergency protective circuit arrangements for preventing the switching-on in case an undesired electric working condition might result in case of too high or too low voltage
Abstract
The application provides a negative pressure isolation device, a process method and a chip thereof, wherein the negative pressure isolation device comprises a first buried layer, a first double diffusion well, a second buried layer and a second double diffusion well which are formed in a substrate in a ring shape, and a first well, a second well and first to fourth active areas which are correspondingly formed in the first buried layer, the first double diffusion well, the second buried layer and the second double diffusion well, wherein the first buried layer, the first well and the first active area form a first isolation ring, the first double diffusion well and the second active area form a second isolation ring, the second buried layer, the second well and the third active area form a third isolation ring, the second double diffusion well and the fourth active area form a fourth isolation ring, and a plurality of isolation rings are arranged between a negative pressure circuit and an internal circuit to isolate negative pressure signals, so that the negative pressure circuit is prevented from generating a low impedance path, and the safety of the chip is improved.
Description
Technical Field
The application belongs to the technical field of semiconductor devices, and particularly relates to a negative-pressure isolation device, a process method thereof and a chip.
Background
In conventional inductive driving circuits, such as DC-DC and motor driving, a state that a negative voltage appears at the intermediate switching point SW is often generated, and as the switching current increases, the negative voltage value also increases, and when the negative voltage value is smaller than a preset voltage, for example, -0.7V, the latch-up effect of the chip is more easily triggered, wherein the latch-up effect refers to a low impedance path generated between the power supply terminal V and the ground terminal GND due to the mutual influence of parasitic PNP and NPN bipolar BJTs, which results in chip damage.
Specifically, as shown in fig. 1, the negative voltage circuit includes a PNP transistor Q1, a first NPN transistor Q2, a second NPN transistor Q3, a first resistor R1, and a second resistor R2, when the negative voltage less than-0.7V output by the internal circuit is connected, the second NPN transistor Q3 is turned on, the negative voltage is input to the PNP transistor Q1, the PNP transistor Q1 is turned on, the power supply terminal V inputs a positive voltage to the first NPN transistor Q2, the first NPN transistor Q2 is turned on in a following manner, and a low impedance path is generated between the power supply terminal V and the ground terminal GND, resulting in chip damage.
Disclosure of Invention
The purpose of the application is to provide a negative pressure isolation device, and aims to solve the problem that a traditional negative pressure circuit has a latch-up effect triggering a chip, so that the chip is damaged.
A first aspect of an embodiment of the present application proposes a negative pressure isolation device, including:
a substrate;
forming a ring-shaped first buried layer, a first double-diffusion well, a second buried layer and a second double-diffusion well in the substrate, wherein the first double-diffusion well is positioned in the ring of the first buried layer, the second buried layer is positioned in the ring of the first double-diffusion well, the second double-diffusion well is positioned in the ring of the second buried layer, a negative pressure circuit is positioned in the ring of the second double-diffusion well, and an internal circuit is positioned outside the ring of the first buried layer;
a first well formed in the first buried layer, a first active region formed in the first well, the first well and the first active region being ring-shaped, the first active region being connected to a voltage terminal;
a second active region formed in the first double diffusion well, wherein the second active region is annular and is connected to the ground terminal;
a second well formed in the second buried layer, a third active region formed in the second well, the second well and the third active region being ring-shaped, the third active region being connected to the ground;
a fourth active region formed in the second double diffusion well, the fourth active region being annular, the fourth active region being connected to the ground;
the doping types of the first active region and the third active region are the same, the doping types of the second active region and the fourth active region are the same, and the doping types of the first active region and the second active region are opposite;
the doping types of the first double-diffusion well and the second double-diffusion well are the same, the doping types of the first buried layer and the second buried layer are the same, and the doping types of the first well and the second well are the same.
Optionally, the substrate is a P-type substrate;
the first double-diffusion well and the second double-diffusion well are double-diffusion P-type wells;
the first active region and the third active region are N-type active regions, and the second active region and the fourth active region are P-type active regions;
the first buried layer and the second buried layer are N-type buried layers;
the first well and the second well are an N-type deep injection well and an N-type deep injection well.
Optionally, the first double diffusion well, the second double diffusion well, the first active region, the second active region, the third active region, the fourth active region, the first buried layer, the second buried layer, the first well, and the second well are formed by ion implantation or diffusion.
Optionally, the internal circuit, the first buried layer, the first double diffusion well, the second buried layer, the second double diffusion well and the negative pressure circuit are arranged at equal intervals.
Optionally, the first buried layer, the first double diffusion well, the second buried layer and the second double diffusion well are square annular.
A second aspect of the embodiments of the present application proposes a chip comprising a negative voltage circuit, an internal circuit and a negative voltage isolation device as described above.
A third aspect of an embodiment of the present application provides a process method for a negative voltage isolation device, including:
forming a ring-shaped first buried layer, a first double-diffusion well, a second buried layer and a second double-diffusion well in a substrate, wherein the first double-diffusion well is positioned in the ring of the first buried layer, the second buried layer is positioned in the ring of the first double-diffusion well, the second double-diffusion well is positioned in the ring of the second buried layer, a negative pressure circuit is positioned in the ring of the second double-diffusion well, and an internal circuit is positioned outside the ring of the first buried layer;
forming a first well in the first buried layer, forming a first active region in the first well, wherein the first well and the first active region are annular, and the first active region is connected to a voltage terminal;
forming a second active region in the first double diffusion well, wherein the second active region is annular and is connected to the ground terminal;
forming a second well in the second buried layer, and forming a third active region in the second well, wherein the second well and the third active region are annular, and the third active region is connected to the ground terminal;
forming a fourth active region in the second double-diffusion well, wherein the fourth active region is annular and is connected to the ground terminal;
the doping types of the first active region and the third active region are the same, the doping types of the second active region and the fourth active region are the same, and the doping types of the first active region and the second active region are opposite;
the doping types of the first double-diffusion well and the second double-diffusion well are the same, the doping types of the first buried layer and the second buried layer are the same, and the doping types of the first well and the second well are the same.
Optionally, the substrate is a P-type substrate;
the first double-diffusion well and the second double-diffusion well are double-diffusion P-type wells;
the first active region and the third active region are N-type active regions, and the second active region and the fourth active region are P-type active regions;
the first buried layer and the second buried layer are N-type buried layers;
the first well and the second well are an N-type deep injection well and an N-type deep injection well.
Optionally, the first double diffusion well, the second double diffusion well, the first active region, the second active region, the third active region, the fourth active region, the first buried layer, the second buried layer, the first well, and the second well are formed by ion implantation or diffusion.
Optionally, the first buried layer, the first double diffusion well, the second buried layer and the second double diffusion well are square annular;
the internal circuit, the first buried layer, the first double diffusion well, the second buried layer, the second double diffusion well and the negative pressure circuit are arranged at equal intervals.
Compared with the prior art, the embodiment of the application has the beneficial effects that: in the negative pressure isolation assembly, the first buried layer, the first well and the first active region form a first isolation ring, the first double diffusion well and the second active region form a second isolation ring, the second buried layer, the second well and the third active region form a third isolation ring, the second double diffusion well and the fourth active region form a fourth isolation ring, and a plurality of isolation rings are arranged between the negative pressure circuit and the internal circuit to isolate negative pressure signals, so that the negative pressure circuit is prevented from generating a low-impedance passage, and the safety of the chip is improved.
Drawings
FIG. 1 is a schematic diagram of a conventional negative-voltage circuit;
FIG. 2 is a cross-sectional view of a negative pressure isolation device according to an embodiment of the present disclosure;
FIG. 3 is a top view block diagram of a negative pressure isolation device provided in an embodiment of the present application;
fig. 4 is a circuit structure diagram of a negative voltage isolation device and a negative voltage circuit provided in an embodiment of the present application;
fig. 5 is a schematic flow chart of a process method of the negative pressure isolation device provided in the embodiment of the application.
Detailed Description
In order to make the technical problems, technical schemes and beneficial effects to be solved by the present application more clear, the present application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the present application.
It is to be understood that the terms "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like indicate or are based on the orientation or positional relationship shown in the drawings, merely to facilitate description of the present application and simplify description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be configured and operated in a particular orientation, and therefore should not be construed as limiting the present application.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present application, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
A first aspect of the embodiments of the present application proposes a negative voltage isolation device, which is used to isolate a negative voltage circuit 3 from an internal circuit 2, to prevent a low impedance path from being generated, and to improve the safety and reliability of a chip.
As shown in fig. 2 and 3, the negative pressure isolation device includes:
a substrate 1;
forming a ring-shaped first buried layer 11, a first double diffusion well 12, a second buried layer 13 and a second double diffusion well 14 in the substrate 1, wherein the first double diffusion well 12 is positioned in the ring of the first buried layer 11, the second buried layer 13 is positioned in the ring of the first double diffusion well 12, the second double diffusion well 14 is positioned in the ring of the second buried layer 13, the negative voltage circuit 3 is positioned in the ring of the second double diffusion well 14, and the internal circuit 2 is positioned outside the ring of the first buried layer 11;
a first well 15 formed in the first buried layer 11, a first active region 17 formed in the first well 15, the first well 15 and the first active region 17 being annular, the first active region 17 being connected to a voltage terminal;
a second active region 18 formed in the first double diffusion well 12, the second active region 18 being annular, the second active region 18 being connected to the ground GND;
a second well 16 formed in the second buried layer 13, a third active region 19 formed in the second well 16, the second well 16 and the third active region 19 being annular, the third active region 19 being connected to the ground GND;
a fourth active region 20 formed in the second double diffusion well 14, the fourth active region 20 being annular, the fourth active region 20 being connected to the ground GND;
the doping type of the first active region 17 is the same as that of the third active region 19, the doping type of the second active region 18 is the same as that of the fourth active region 20, and the doping type of the first active region 17 is opposite to that of the second active region 18;
the doping type of the first double diffusion well 12 is the same as that of the second double diffusion well 14, the doping type of the first buried layer 11 is the same as that of the second buried layer 13, and the doping type of the first well 15 is the same as that of the second well 16.
In this embodiment, the first buried layer 11, the first well 15 and the first active region 17 form a first isolation ring, the first double diffusion well 12 and the second active region 18 form a second isolation ring, the second buried layer 13, the second well 16 and the third active region 19 form a third isolation ring, the second double diffusion well 14 and the fourth active region 20 form a fourth isolation ring, a plurality of isolation rings are disposed between the negative voltage circuit 3 and the internal circuit 2, the fourth isolation ring to the first isolation ring are located between the negative voltage circuit 3 and the internal circuit 2 from inside to outside, and isolate negative voltage signals, wherein doping types of the first active region 17 and the second active region 18 are opposite, doping types of the second active region 18 and the third active region 19 are opposite, doping types of the third active region 19 and the fourth active region 20 are opposite, the first active region 17 is connected to the power supply terminal V, the second active region 18, the third active region 19 and the fourth active region 20 are connected to the ground terminal GND, the first active region 17 and the second active region 18 and the third active region 19 are connected to the ground terminal GND, and the first active region 18 and the third active region 19 form an isolation ring, and the negative voltage transistor 1 and the negative voltage transistor 4 are formed as an equivalent isolation ring, and the isolation transistor 1 is formed between the negative voltage circuit and the negative voltage transistor 2 is formed, the equivalent isolation structure is formed, and the isolation transistor is formed between the negative voltage transistor and the isolation circuit and the negative voltage transistor circuit and the negative circuit and the equivalent circuit and the negative circuit and the negative circuit.
The negative voltage circuit 3 includes a PNP transistor Q1, a first NPN transistor Q2, a second NPN transistor Q3, a first resistor R1 and a second resistor R2, and an isolation transistor, for example, a third NPN transistor Q4 is connected between the negative voltage circuit 3 and the internal circuit 2, when the internal circuit 2 inputs a negative voltage smaller than-0.7V to the negative voltage circuit 3, the second NPN transistor Q3 is turned on, the base and the emitter, or the base and the collector of the isolation transistor input a negative voltage equal to each other, and by adjusting a distance between the isolation rings, a voltage difference of Vbe of the isolation transistor is smaller than a threshold on voltage, the isolation transistor is turned off, the PNP transistor Q1 and the first NPN transistor Q2 keep an off state, preventing the negative voltage circuit 3 from generating a low impedance path, and improving the safety of the chip.
The first double-diffusion well 12, the second double-diffusion well 14, the first active region 17, the second active region 18, the third active region 19, the fourth active region 20, the first buried layer 11, the second buried layer 13, the first well 15 and the second well 16 are formed by ion implantation or diffusion, and are all in a closed ring shape from the plane view of the layout, as shown in fig. 4, optionally, the first buried layer 11, the first double-diffusion well 12, the second buried layer 13 and the second double-diffusion well 14 are in a square ring shape, and each active region and each well follow to form a square ring structure.
Optionally, the substrate 1 is a P-type substrate 1;
the first double diffusion well 12 and the second double diffusion well 14 are double diffusion P-type wells;
the first active region 17 and the third active region 19 are N-type active regions, and the second active region 18 and the fourth active region 20 are P-type active regions;
the first buried layer 11 and the second buried layer 13 are N-type buried layers;
the first well 15 and the second well 16 are an N-type deep implant well and an N-well.
In this embodiment, the first isolation ring, the second isolation ring and the third isolation ring form a third NPN transistor Q4, the third NPN transistor Q4 is connected between the second NPN transistor Q3 and the power supply terminal V, when the internal circuit 2 inputs a negative voltage smaller than-0.7V to the negative voltage circuit 3, the second NPN transistor Q3 is turned on, the base and the emitter of the third NPN transistor Q4 input an equal negative voltage, by adjusting the interval between the isolation rings, the voltage difference of Vbe of the third NPN transistor Q4 is smaller than the threshold on voltage, the third NPN transistor Q4 is turned off, the PNP transistor Q1 and the first NPN transistor Q2 keep the off state, preventing the negative voltage circuit 3 from generating a low impedance path, and improving the chip security.
In order to further ensure that the third NPN transistor Q4 maintains an off state, and ensure that the resistances of the resistors formed at intervals of the isolation ring are close, optionally, the internal circuit 2, the first buried layer 11, the first double diffusion well 12, the second buried layer 13, the second double diffusion well 14 and the negative pressure circuit 3 are arranged at equal intervals, so that the fifth resistor R5 and the eighth resistor R8 in fig. 4 have equal resistances, the voltage difference between the third NPN transistor Q4 is ensured to be smaller than a threshold on voltage, and the third NPN transistor Q4 maintains an off state when a negative pressure is input.
Compared with the prior art, the embodiment of the application has the beneficial effects that: in the negative pressure isolation assembly, the first buried layer 11, the first well 15 and the first active region 17 form a first isolation ring, the first double diffusion well 12 and the second active region 18 form a second isolation ring, the second buried layer 13, the second well 16 and the third active region 19 form a third isolation ring, the second double diffusion well 14 and the fourth active region 20 form a fourth isolation ring, and a plurality of isolation rings are arranged between the negative pressure circuit 3 and the internal circuit 2 to isolate negative pressure signals, so that the negative pressure circuit 3 is prevented from generating a low impedance path, and the safety of a chip is improved.
The second aspect of the embodiment of the present application proposes a chip, which includes a negative voltage circuit 3, an internal circuit 2 and a negative voltage isolation device, where the specific structure of the negative voltage isolation device refers to the above embodiment, and since the chip adopts all the technical solutions of all the embodiments, the chip at least has all the beneficial effects brought by the technical solutions of the embodiments, and will not be described in detail herein.
A third aspect of the embodiments of the present application provides a process method of a negative voltage isolation device, as shown in fig. 5, where the process method includes the following steps:
s1, forming a ring-shaped first buried layer 11, a first double-diffusion well 12, a second buried layer 13 and a second double-diffusion well 14 in a substrate 1, wherein the first double-diffusion well 12 is positioned in the ring of the first buried layer 11, the second buried layer 13 is positioned in the ring of the first double-diffusion well 12, the second double-diffusion well 14 is positioned in the ring of the second buried layer 13, a negative voltage circuit 3 is positioned in the ring of the second double-diffusion well 14, and an internal circuit 2 is positioned outside the ring of the first buried layer 11;
s2, forming a first well 15 in the first buried layer 11, forming a first active region 17 in the first well 15, wherein the first well 15 and the first active region 17 are annular, and the first active region 17 is connected to a voltage terminal;
s3, forming a second active region 18 in the first double diffusion well 12, wherein the second active region 18 is annular, and the second active region 18 is connected to the ground GND;
s4, forming a second well 16 in the second buried layer 13, forming a third active region 19 in the second well 16, wherein the second well 16 and the third active region 19 are annular, and the third active region 19 is connected to the ground GND;
s5, forming a fourth active region 20 in the second double diffusion well 14, wherein the fourth active region 20 is annular, and the fourth active region 20 is connected to the ground GND;
the doping type of the first active region 17 is the same as that of the third active region 19, the doping type of the second active region 18 is the same as that of the fourth active region 20, and the doping type of the first active region 17 is opposite to that of the second active region 18;
the doping type of the first double diffusion well 12 is the same as that of the second double diffusion well 14, the doping type of the first buried layer 11 is the same as that of the second buried layer 13, and the doping type of the first well 15 is the same as that of the second well 16.
In this embodiment, the first buried layer 11, the first well 15 and the first active region 17 form a first isolation ring, the first double diffusion well 12 and the second active region 18 form a second isolation ring, the second buried layer 13, the second well 16 and the third active region 19 form a third isolation ring, the second double diffusion well 14 and the fourth active region 20 form a fourth isolation ring, a plurality of isolation rings are disposed between the negative voltage circuit 3 and the internal circuit 2, the fourth isolation ring to the first isolation ring are located between the negative voltage circuit 3 and the internal circuit 2 from inside to outside, and isolate negative voltage signals, wherein doping types of the first active region 17 and the second active region 18 are opposite, doping types of the second active region 18 and the third active region 19 are opposite, doping types of the third active region 19 and the fourth active region 20 are opposite, the first active region 17 is connected to the power supply terminal V, the second active region 18, the third active region 19 and the fourth active region 20 are connected to the ground terminal GND, the first active region 17 and the second active region 18 and the third active region 19 are connected to the ground terminal GND, and the first active region 18 and the third active region 19 form an isolation ring, and the negative voltage transistor 1 and the negative voltage transistor 4 are formed as an equivalent isolation ring, and the isolation transistor 1 is formed between the negative voltage circuit and the negative voltage transistor 2 is formed, the equivalent isolation structure is formed, and the isolation transistor is formed between the negative voltage transistor and the isolation circuit and the negative voltage transistor circuit and the negative circuit and the equivalent circuit and the negative circuit and the negative circuit.
The negative voltage circuit 3 includes a PNP transistor Q1, a first NPN transistor Q2, a second NPN transistor Q3, a first resistor R1 and a second resistor R2, and an isolation transistor, for example, a third NPN transistor Q4 is connected between the negative voltage circuit 3 and the internal circuit 2, when the internal circuit 2 inputs a negative voltage smaller than-0.7V to the negative voltage circuit 3, the second NPN transistor Q3 is turned on, the base and the emitter, or the base and the collector of the isolation transistor input a negative voltage equal to each other, and by adjusting a distance between the isolation rings, a voltage difference of Vbe of the isolation transistor is smaller than a threshold on voltage, the isolation transistor is turned off, the PNP transistor Q1 and the first NPN transistor Q2 keep an off state, preventing the negative voltage circuit 3 from generating a low impedance path, and improving the safety of the chip.
The first double-diffusion well 12, the second double-diffusion well 14, the first active region 17, the second active region 18, the third active region 19, the fourth active region 20, the first buried layer 11, the second buried layer 13, the first well 15 and the second well 16 are formed by ion implantation or diffusion, and are all in a closed ring shape from the plane view of the layout, as shown in fig. 4, optionally, the first buried layer 11, the first double-diffusion well 12, the second buried layer 13 and the second double-diffusion well 14 are in a square ring shape, and each active region and each well follow to form a square ring structure.
Optionally, the substrate 1 is a P-type substrate 1;
the first double diffusion well 12 and the second double diffusion well 14 are double diffusion P-type wells;
the first active region 17 and the third active region 19 are N-type active regions, and the second active region 18 and the fourth active region 20 are P-type active regions;
the first buried layer 11 and the second buried layer 13 are N-type buried layers;
the first well 15 and the second well 16 are an N-type deep implant well and an N-well.
In this embodiment, the first isolation ring, the second isolation ring and the third isolation ring form a third NPN transistor Q4, the third NPN transistor Q4 is connected between the second NPN transistor Q3 and the power supply terminal V, when the internal circuit 2 inputs a negative voltage smaller than-0.7V to the negative voltage circuit 3, the second NPN transistor Q3 is turned on, the base and the emitter of the third NPN transistor Q4 input an equal negative voltage, by adjusting the interval between the isolation rings, the voltage difference of Vbe of the third NPN transistor Q4 is smaller than the threshold on voltage, the third NPN transistor Q4 is turned off, the PNP transistor Q1 and the first NPN transistor Q2 keep the off state, preventing the negative voltage circuit 3 from generating a low impedance path, and improving the chip security.
In order to further ensure that the third NPN transistor Q4 maintains an off state, and ensure that the resistances of the resistors formed at intervals of the isolation ring are close, optionally, the internal circuit 2, the first buried layer 11, the first double diffusion well 12, the second buried layer 13, the second double diffusion well 14 and the negative pressure circuit 3 are arranged at equal intervals, so that the fifth resistor R5 and the eighth resistor R8 in fig. 4 have equal resistances, the voltage difference between the third NPN transistor Q4 is ensured to be smaller than a threshold on voltage, and the third NPN transistor Q4 maintains an off state when a negative pressure is input.
It should be understood that the sequence number of each step in the foregoing embodiment does not mean that the execution sequence of each process should be determined by the function and the internal logic of each process, and should not limit the implementation process of the embodiment of the present application in any way.
The above embodiments are only for illustrating the technical solution of the present application, and are not limiting; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present application, and are intended to be included in the scope of the present application.
Claims (10)
1. A negative pressure isolation device, comprising:
a substrate;
forming a ring-shaped first buried layer, a first double-diffusion well, a second buried layer and a second double-diffusion well in the substrate, wherein the first double-diffusion well is positioned in the ring of the first buried layer, the second buried layer is positioned in the ring of the first double-diffusion well, the second double-diffusion well is positioned in the ring of the second buried layer, a negative pressure circuit is positioned in the ring of the second double-diffusion well, and an internal circuit is positioned outside the ring of the first buried layer;
a first well formed in the first buried layer, a first active region formed in the first well, the first well and the first active region being ring-shaped, the first active region being connected to a voltage terminal;
a second active region formed in the first double diffusion well, wherein the second active region is annular and is connected to the ground terminal;
a second well formed in the second buried layer, a third active region formed in the second well, the second well and the third active region being ring-shaped, the third active region being connected to the ground;
a fourth active region formed in the second double diffusion well, the fourth active region being annular, the fourth active region being connected to the ground;
the doping types of the first active region and the third active region are the same, the doping types of the second active region and the fourth active region are the same, and the doping types of the first active region and the second active region are opposite;
the doping types of the first double-diffusion well and the second double-diffusion well are the same, the doping types of the first buried layer and the second buried layer are the same, and the doping types of the first well and the second well are the same;
the doping types of the first buried layer, the first well and the first active region are the same;
the doping types of the first double diffusion well and the second active region are the same;
the doping types of the second buried layer, the second well and the third active region are the same;
the doping type of the second double diffusion well and the fourth active region is the same.
2. The negative voltage isolation device of claim 1, wherein the substrate is a P-type substrate;
the first double-diffusion well and the second double-diffusion well are double-diffusion P-type wells;
the first active region and the third active region are N-type active regions, and the second active region and the fourth active region are P-type active regions;
the first buried layer and the second buried layer are N-type buried layers;
the first well and the second well are an N-type deep injection well and an N-type deep injection well.
3. The negative voltage isolation device of claim 1, wherein the first double diffusion well, the second double diffusion well, the first active region, the second active region, the third active region, the fourth active region, the first buried layer, the second buried layer, the first well, and the second well are formed by ion implantation or diffusion.
4. The negative voltage isolation device of claim 1, wherein the internal circuit, the first buried layer, the first double diffusion well, the second buried layer, the second double diffusion well, and the negative voltage circuit are disposed equidistant.
5. The negative voltage isolation device of claim 1, wherein the first buried layer, the first double diffusion well, the second buried layer, and the second double diffusion well are square ring-shaped.
6. A chip comprising a negative pressure circuit, an internal circuit, and the negative pressure isolation device according to any one of claims 1 to 5.
7. A process for a negative pressure isolation device, comprising:
forming a ring-shaped first buried layer, a first double-diffusion well, a second buried layer and a second double-diffusion well in a substrate, wherein the first double-diffusion well is positioned in the ring of the first buried layer, the second buried layer is positioned in the ring of the first double-diffusion well, the second double-diffusion well is positioned in the ring of the second buried layer, a negative pressure circuit is positioned in the ring of the second double-diffusion well, and an internal circuit is positioned outside the ring of the first buried layer;
forming a first well in the first buried layer, forming a first active region in the first well, wherein the first well and the first active region are annular, and the first active region is connected to a voltage terminal;
forming a second active region in the first double diffusion well, wherein the second active region is annular and is connected to the ground terminal;
forming a second well in the second buried layer, and forming a third active region in the second well, wherein the second well and the third active region are annular, and the third active region is connected to the ground terminal;
forming a fourth active region in the second double-diffusion well, wherein the fourth active region is annular and is connected to the ground terminal;
the doping types of the first active region and the third active region are the same, the doping types of the second active region and the fourth active region are the same, and the doping types of the first active region and the second active region are opposite;
the doping types of the first double-diffusion well and the second double-diffusion well are the same, the doping types of the first buried layer and the second buried layer are the same, and the doping types of the first well and the second well are the same;
the doping types of the first buried layer, the first well and the first active region are the same;
the doping types of the first double diffusion well and the second active region are the same;
the doping types of the second buried layer, the second well and the third active region are the same;
the doping type of the second double diffusion well and the fourth active region is the same.
8. The process of claim 7, wherein the substrate is a P-type substrate;
the first double-diffusion well and the second double-diffusion well are double-diffusion P-type wells;
the first active region and the third active region are N-type active regions, and the second active region and the fourth active region are P-type active regions;
the first buried layer and the second buried layer are N-type buried layers;
the first well and the second well are an N-type deep injection well and an N-type deep injection well.
9. The process of claim 7, wherein the first double diffusion well, the second double diffusion well, the first active region, the second active region, the third active region, the fourth active region, the first buried layer, the second buried layer, the first well, and the second well are formed by ion implantation or diffusion.
10. The process of claim 7, wherein the first buried layer, the first double diffusion well, the second buried layer, and the second double diffusion well are square ring-shaped;
the internal circuit, the first buried layer, the first double diffusion well, the second buried layer, the second double diffusion well and the negative pressure circuit are arranged at equal intervals.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211064652.2A CN115377099B (en) | 2022-08-31 | 2022-08-31 | Negative pressure isolation device and process method and chip thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211064652.2A CN115377099B (en) | 2022-08-31 | 2022-08-31 | Negative pressure isolation device and process method and chip thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN115377099A CN115377099A (en) | 2022-11-22 |
| CN115377099B true CN115377099B (en) | 2023-07-04 |
Family
ID=84069568
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211064652.2A Active CN115377099B (en) | 2022-08-31 | 2022-08-31 | Negative pressure isolation device and process method and chip thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115377099B (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102723304A (en) * | 2012-05-31 | 2012-10-10 | 日银Imp微电子有限公司 | Preparation method of N-trap high-voltage gate driving chip for directly driving power device |
| CN103839941A (en) * | 2012-11-20 | 2014-06-04 | 美国亚德诺半导体公司 | Junction-isolated blocking voltage devices with integrated protection structures and methods of forming same |
| CN109037336A (en) * | 2018-06-19 | 2018-12-18 | 上海艾为电子技术股份有限公司 | Nmos device and chip including nmos device |
| CN112928112A (en) * | 2021-01-27 | 2021-06-08 | 深圳市国微电子有限公司 | Low-trigger high-maintenance bidirectional SCR (selective catalytic reduction) protection device and process method thereof |
| CN114334956A (en) * | 2022-03-15 | 2022-04-12 | 成都市易冲半导体有限公司 | Isolation protection structure of alternating current power switch with extreme negative voltage resistant high-voltage pin |
-
2022
- 2022-08-31 CN CN202211064652.2A patent/CN115377099B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102723304A (en) * | 2012-05-31 | 2012-10-10 | 日银Imp微电子有限公司 | Preparation method of N-trap high-voltage gate driving chip for directly driving power device |
| CN103839941A (en) * | 2012-11-20 | 2014-06-04 | 美国亚德诺半导体公司 | Junction-isolated blocking voltage devices with integrated protection structures and methods of forming same |
| CN109037336A (en) * | 2018-06-19 | 2018-12-18 | 上海艾为电子技术股份有限公司 | Nmos device and chip including nmos device |
| CN112928112A (en) * | 2021-01-27 | 2021-06-08 | 深圳市国微电子有限公司 | Low-trigger high-maintenance bidirectional SCR (selective catalytic reduction) protection device and process method thereof |
| CN114334956A (en) * | 2022-03-15 | 2022-04-12 | 成都市易冲半导体有限公司 | Isolation protection structure of alternating current power switch with extreme negative voltage resistant high-voltage pin |
Also Published As
| Publication number | Publication date |
|---|---|
| CN115377099A (en) | 2022-11-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9147677B2 (en) | Dual-tub junction-isolated voltage clamp devices for protecting low voltage circuitry connected between high voltage interface pins and methods of forming the same | |
| US7868387B2 (en) | Low leakage protection device | |
| US6236087B1 (en) | SCR cell for electrical overstress protection of electronic circuits | |
| US8633509B2 (en) | Apparatus and method for transient electrical overstress protection | |
| US8637899B2 (en) | Method and apparatus for protection and high voltage isolation of low voltage communication interface terminals | |
| JP4209432B2 (en) | ESD protection device | |
| US9997510B2 (en) | Semiconductor device layout structure | |
| US8587071B2 (en) | Electrostatic discharge (ESD) guard ring protective structure | |
| JPH07506216A (en) | SCR protection structure and circuit with reduced trigger voltage | |
| US7999327B2 (en) | Semiconductor device, and semiconductor manufacturing method | |
| US9373682B2 (en) | Compact guard ring structure for CMOS integrated circuits | |
| US10262987B2 (en) | Electrostatic discharge protection circuit | |
| JP4209433B2 (en) | ESD protection device | |
| US10192863B2 (en) | Series connected ESD protection circuit | |
| US7777248B1 (en) | Semiconductor device for latch-up prevention | |
| KR101392587B1 (en) | High voltage electro-static discharge protection device | |
| US9029952B2 (en) | Semiconductor structure and method of manufacturing the same | |
| CN115377099B (en) | Negative pressure isolation device and process method and chip thereof | |
| US20180033878A1 (en) | Stucture for protecting an integrated circuit against electrostatic discharges | |
| CN103378139A (en) | Semiconductor structure and manufacturing method thereof | |
| US9263429B2 (en) | Semiconductor device and manufacturing method of the same | |
| CN211265471U (en) | Bidirectional thyristor electrostatic protection device | |
| JP2005223016A (en) | Semiconductor device | |
| US10249610B1 (en) | IGBT coupled to a reverse bias device in series | |
| JPH1074958A (en) | Semiconductor integrated circuit and its manufacture |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |