CN103378139A - Semiconductor structure and manufacturing method thereof - Google Patents
Semiconductor structure and manufacturing method thereof Download PDFInfo
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- CN103378139A CN103378139A CN2012101185237A CN201210118523A CN103378139A CN 103378139 A CN103378139 A CN 103378139A CN 2012101185237 A CN2012101185237 A CN 2012101185237A CN 201210118523 A CN201210118523 A CN 201210118523A CN 103378139 A CN103378139 A CN 103378139A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 35
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 9
- 239000012535 impurity Substances 0.000 claims abstract description 38
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 238000000034 method Methods 0.000 claims description 14
- 239000000463 material Substances 0.000 claims description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 7
- 229920005591 polysilicon Polymers 0.000 claims description 7
- 210000000746 body region Anatomy 0.000 abstract 3
- 230000015556 catabolic process Effects 0.000 description 8
- 230000000694 effects Effects 0.000 description 6
- 239000007943 implant Substances 0.000 description 6
- 238000002360 preparation method Methods 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 229910044991 metal oxide Inorganic materials 0.000 description 3
- 150000004706 metal oxides Chemical class 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 210000003323 beak Anatomy 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
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Abstract
The invention discloses a semiconductor structure and a manufacturing method of the semiconductor structure. The semiconductor structure comprises a substrate, a first conductivity type well region, a second conductivity type well region, a body region, a first doped region, a second doped region, a third doped region and a field plate. The first conductivity type well region and the second conductivity type well region are respectively formed in the substrate, the body region is formed in the second conductivity type well region, and the first doped region and the second doped region are formed in the first conductivity type well region and the body region respectively; the polarity of the second doped region and the polarity of the first doped region are the same, and the impurity concentration of the second doped region is larger than that of the first doped region; the third doped region is formed in the second conductivity type well region and located between the first doped region and the second doped region, and the polarity of the third doped region is opposite to the polarity of the first doped region; the field plate is formed on the surface region between the second doped region and the third doped region.
Description
Technical field
The invention relates to a kind of semiconductor structure and preparation method thereof, and a kind of semiconductor structure relevant for two-carrier junction transistors (Bipolar Junction Transistor, BJT) and preparation method thereof particularly.
Background technology
Double carrier transistor is one of important in recent years semiconductor element.It is by two groups of three contacts (three terminal) elements of forming of pn knot (junction) very closely, these three contacts are called emitter-base bandgap grading (emitter), base stage (base) and collector (collector), and wherein base stage is the intermediate contact in three contacts of double carrier transistor.Because double carrier transistor is to utilize simultaneously two kinds of carriers of electronics and hole to come conduction current, so the two-carrier element has the advantage that speed is fast and a larger electric current can be provided in a less space, therefore two-carrier complementary transistor (BiCMOS) structure of utilizing double carrier transistor and CMOS transistor (CMOS) to combine is suggested, in order to promote transistorized running speed.
Yet, when design two-carrier junction transistors, improve the impurity concentration of emitter-base bandgap grading for the injection efficiency that improves emitter-base bandgap grading, will certainly reduce the puncture voltage between emitter-base bandgap grading and the base stage, and reduce the performance of double carrier transistor.
Summary of the invention
The invention relates to a kind of semiconductor structure and preparation method thereof, in order to improving the current gain of common emitter circuit, and the puncture voltage of the PN junction when improving the reverse bias operation.
According to an aspect of the present invention, propose a kind of semiconductor structure, comprise the well region of a substrate, one first conductivity type, well region, this tagma, one first doped region, one second doped region, one the 3rd doped region and a field plate of one second conductivity type.The well region of the well region of the first conductivity type and the second conductivity type is formed in the substrate respectively.This tagma is formed in the well region of the second conductivity type.The first doped region and one second doped region be formed at respectively in the well region of the first conductivity type with this tagma in.The polarity of the second doped region is identical with the polarity of the first doped region, and the impurity concentration of the second doped region is greater than the impurity concentration of the first doped region.The 3rd doped region is formed at the well region of the second conductivity type, and between the first doped region and the second doped region.The polarity of the 3rd doped region is opposite with the polarity of the first doped region.Field plate is formed at the surf zone between the second doped region and the 3rd doped region.
According to a further aspect in the invention, propose a kind of manufacture method of semiconductor structure, comprise the following steps.One substrate is provided.Form respectively the well region of the well region of one first conductivity type and one second conductivity type in substrate.Form this tagma in the well region of the second conductivity type.Form respectively one first doped region and one second doped region in the well region and this tagma of the first conductivity type.The polarity of the second doped region is identical with the polarity of the first doped region, and the impurity concentration of the second doped region is greater than the impurity concentration of the first doped region.Form one the 3rd doped region in the well region of the second conductivity type, and between the first doped region and the second doped region.The polarity of the 3rd doped region is opposite with the polarity of the first doped region.Form the surf zone of one first field plate between the second doped region and the 3rd doped region.
For there is better understanding above-mentioned and other aspect of the present invention, embodiment cited below particularly, and cooperate appended graphicly, be described in detail below:
Description of drawings
Fig. 1～Fig. 3 illustrates respectively the generalized section according to three kinds of semiconductor structures of one embodiment of the invention.
Fig. 4 A～Fig. 4 C illustrates respectively the flow chart of the manufacture method of semiconductor structure.
Fig. 5～Fig. 7 illustrates respectively the generalized section according to three kinds of semiconductor structures of one embodiment of the invention.
Fig. 8 A～Fig. 8 C illustrates respectively the flow chart of the manufacture method of semiconductor structure.
Fig. 9～Figure 10 illustrates respectively the schematic diagram according to two kinds of protective circuits of one embodiment of the invention.
[main element symbol description]
100～102,200～202: semiconductor structure
110,210: substrate
121, the well region of 221: the first conductivity types
122, the well region of 222: the second conductivity types
123,223: this tagma
131,231: the first doped regions
132,232: the second doped regions
133,233: the three doped regions
136,236: field oxide
140,240: field plate (the first field plate)
141,241: field plate (the second field plate)
300,310,320: the two-carrier junction transistors
302:N type metal oxide semiconductor transistor
304:P type metal oxide semiconductor transistor
306: defeated in/out connection pad
Vdd: high potential
Vss: electronegative potential
B: base terminal
C: collector terminal
E: emitter-base bandgap grading end
Embodiment
Semiconductor structure of present embodiment and preparation method thereof, with the surf zone between field plate (the first field plate and/or the second field plate) covering P type doped region and the N-type doped region, for example cover between surf zone, base implant district and the collector doped region between emitter-base bandgap grading doped region and the base implant district surf zone or both, the junction breakdown voltage between junction breakdown voltage, base stage and the collector when improving the reverse bias operation between emitter-base bandgap grading and the base stage or both.In addition, increase field plate, can not only improve junction breakdown voltage, more can avoid the emitter-base bandgap grading doped region to engage with the exhaustion region of collector doped region and punch-through effect occurs.In addition, for the injection efficiency (injection efficiency) that improves emitter-base bandgap grading, the emitter-base bandgap grading doped region of high impurity concentration for example is formed in this tagma with ion implantation, to reduce the resistivity of emitter-base bandgap grading, make that carrier is easier to be flowed between emitter-base bandgap grading and the base stage, with the electric current of amplification collector terminal, and then the current gain (current gain) of raising common emitter (Common-emitter) amplifying circuit.
Below be to propose various embodiment to be elaborated, embodiment in order to as the example explanation, is not the scope in order to limit wish protection of the present invention only.
The first embodiment
Fig. 1～Fig. 3 illustrates respectively the generalized section according to three kinds of semiconductor structures of one embodiment of the invention.Please first with reference to Fig. 1, semiconductor structure 100 for example is the two-carrier junction transistors of common emitter, and it comprises the well region 121 of a substrate 110, one first conductivity type, well region 122, this tagma 123, one first doped region 131, one second doped region 132, one the 3rd doped region 133 and a field plate 140 of one second conductivity type.Substrate 110 for example is P type silicon substrate, and the well region 121 of the first conductivity type and the well region 122 of the second conductivity type for example are P type well region, and it is formed at respectively in the substrate 110.The first conductivity type is the P type for example, and the second conductivity type for example is N-type, but the present invention do not limited this, can the first conductivity type be N-type also, and the second conductivity type is the P type.
This tagma 123 for example is P type doped region, and it is formed in the well region 122 of the second conductivity type.This tagma 123 has a p type impurity concentration, is preferably the impurity concentration greater than the well region 121 of the first conductivity type.
In the well region 121 (for example P type well region) that the first doped region 131 and the second doped region 132 are formed at respectively the first conductivity type and this tagma 123, with as collector doped region and emitter-base bandgap grading doped region.The polarity of the second doped region 132 is identical with the polarity of the first doped region 131, the identical impurity of the polarity of for example mixing (for example p type impurity).But, because the impurity concentration in this tagma 123 is greater than the impurity concentration of the well region 121 of the first conductivity type, so the impurity concentration of the second doped region 132 also can be greater than the impurity concentration of the first doped region 131.The second doped region 132 is the P+ doped region for example, can be used as the contact zone of emitter-base bandgap grading end E, to reduce the resistivity of the second doped region 132.
In addition, the 3rd doped region 133 and is positioned at the surf zone of the well region 122 (for example for N-type well region) of the second conductivity type between the first doped region 131 and the second doped region 132, with as the base implant district.The polarity of the 3rd doped region 133 is opposite with the polarity of the first doped region 131, for example distinguishes doped N-type impurity and p type impurity, therefore can form the transistor of positive-negative-positive, but the present invention also can form the transistor of NPN knot not as limit.
Take the transistor of positive-negative-positive as example, when the knot of emitter-base bandgap grading end E and base terminal B applies forward voltage, and when the knot of collector terminal C and base terminal B applies revers voltage, the small carrier electric current of base terminal B of flowing through can make the electric current of collector terminal E be amplified, thereby electric current (Ib) ratio of the electric current of collector terminal C (Ic) and base terminal B can between 20～200, reach the effect of current gain.In the present embodiment, increase the impurity concentration in the emitter-base bandgap grading doped region, the resistance value of emitter-base bandgap grading doped region is descended, and under the electric current (Ib) of less base terminal B injects, amplify the electric current (Ic) of collector terminal C, so can improve the effect of current gain.
Then, please refer to Fig. 1, field plate 140 is formed at the surf zone between the second doped region 132 and the 3rd doped region 133, and covers the part surface zone in this tagma 123.Field plate 140 can directly overlay the well region surf zone that does not form field oxide 136.In one embodiment, the material of field oxide 136 for example is silicon dioxide, in order to isolate the first doped region 131 (for example collector doped region) and the 3rd doped region 133 (for example base implant district).The material of field plate 140 for example is polysilicon.Because field plate 140 can change Electric Field Distribution between the second doped region 132 and the 3rd doped region 133, strengthen the scope of exhaustion region, so the junction breakdown voltage (BVebo) between emitter-base bandgap grading end E and the base terminal B in the time of can improving reverse bias and operate.In addition, increase field plate 140, more can avoid the emitter-base bandgap grading doped region to engage with the exhaustion region of collector doped region and punch-through effect occurs.
Then, please refer to the semiconductor structure 101 of Fig. 2, field plate comprise be formed on the first field plate 140 between the second doped region 132 and the 3rd doped region 133 and be formed on the first doped region 131 and the 3rd doped region 133 between the second field plate 141.As mentioned above, the first field plate 140 can increase the junction breakdown voltage (BVebo) between emitter-base bandgap grading end E and the base terminal B.Equally, the second field plate 141 can increase the junction breakdown voltage (BVcbo) between collector terminal C and the base terminal B, and by increasing the first field plate 140 and the second field plate 141, also can avoid between the first doped region 131 and the second doped region 132 punch-through effect occuring.
Please refer to the semiconductor structure 102 of Fig. 3, field plate 141 only is formed between the first doped region 131 and the 3rd doped region 133, and the first field plate 140 that originally was formed between the second doped region 132 and the 3rd doped region 133 then replaces with field oxide 136.By field plate 141, also can reach increase the junction breakdown voltage (BVcbo) between collector terminal C and the base terminal B and avoid the first doped region 131 and the second doped region 132 between punch-through effect occurs.
Below introduce the manufacture method of semiconductor structure 100.Please refer to Fig. 4 A, form respectively the well region 122 of the well region 121 of one first conductivity type and one second conductivity type in this substrate 110, and form this tagma 123 in the well region 122 of the second conductivity type, this tagma 123 has the impurity concentration of the first conductivity type, is preferably the impurity concentration greater than the well region 121 of the first conductivity type.Please refer to Fig. 4 B, form a field oxide 136 in part surface zone, in order to isolated component and define position and the size at the first doped region 131 places.Then, form a field plate 140 in the part surface zone that does not form field oxide 136, accurately to define position and the size at the second doped region 132 and the 3rd doped region 133 places.Please refer to Fig. 4 C, carry out a doping process, injecting the first conductive-type impurity in the first doped region 131 and the second doped region 132, and inject the second conductive-type impurity in the 3rd doped region 133.The first conductivity type is the P type for example, and the second conductivity type for example is N-type, therefore can form the transistor of positive-negative-positive, but the present invention also can form the transistor of NPN knot not as limit.
Because the second doped region 132 is embedded in this tagma 123 of P type, so the impurity concentration of the second doped region 132 is higher with respect to the impurity concentration of the first doped region 131.In addition, field plate 140 and covers on the part surface zone in this tagma 123 between the second doped region 132 and the 3rd doped region 133.Yet field plate also can be formed between the first doped region 131 and the 3rd doped region 133, and field plate 141 does not as shown in Figures 2 and 3 repeat them here.
The second embodiment
Fig. 5～Fig. 7 illustrates respectively the generalized section according to three kinds of semiconductor structures of one embodiment of the invention.Please first with reference to Fig. 5, semiconductor structure 200 for example is the two-carrier junction transistors of common emitter, and it comprises the well region 221 of a substrate 210, one first conductivity type, well region 222, this tagma 223, one first doped region 231, one second doped region 232, one the 3rd doped region 233, a field oxide 236 and a field plate 240 of one second conductivity type.Present embodiment and the first embodiment difference are: form first a field oxide 236, form the field plate 240 that covers field oxide 236 again.Field oxide 236 is in order to isolated component and define position and the size at each doped region place, field oxide 236 is for example with the localized oxidation of silicon thing (local oxidation of silicon) of thermal oxidation method formation or the shallow ditch isolating member (shallow trench isolation, STI) that forms with etching.With respect to the first embodiment, because field plate 240 does not directly overlay the well region surf zone, the width dimensions of the 3rd doped region 233 (for example base implant district) is subject to easily the size variation (beak district) of field oxide 236 and can't accurately controls.But in the first embodiment, when field plate directly overlays the well region surf zone, the size of doped region can not be subject to the impact of field oxide 136 and make a variation, thus can accurately control the width dimensions in the 3rd doped region 133 (for example base implant district), to improve reliability.
In Fig. 5, field plate 240 is formed on the surf zone between the second doped region 232 and the 3rd doped region 233, to change the Electric Field Distribution between the second doped region 232 and the 3rd doped region 233, strengthen the scope of exhaustion region, so the junction breakdown voltage (BVebo) between emitter-base bandgap grading end E and the base terminal B in the time of can improving the reverse bias operation.In addition, the first field plate 240 among Fig. 6 and the second field plate 241, and the configuration mode of the field plate among Fig. 7 241 is similar to the first embodiment, does not repeat them here.
The manufacture method of relevant semiconductor structure 200, its step are identical with Fig. 4 A～Fig. 4 C haply.Please refer to Fig. 8 A, form respectively the well region 222 of the well region 221 of one first conductivity type and one second conductivity type in this substrate 210, and form this tagma 223 in the well region 222 of the second conductivity type, this tagma 223 has the first conductive-type impurity concentration, is preferably the impurity concentration greater than the well region 221 of the first conductivity type.Please refer to Fig. 8 B, form a field oxide 236 in part surface zone, in order to isolated component and define the first doped region 231 and position and the size at the 3rd doped region 233 places.Then, form a field plate 240 on the part surface zone on the field oxide 236 and this tagma 232, to define position and the size at the second doped region 232 places.Please refer to Fig. 8 C, carry out a doping process, injecting the first conductive-type impurity in the first doped region 231 and the second doped region 232, and inject the second conductive-type impurity in the 3rd doped region 233.The first conductivity type is the P type for example, and the second conductivity type for example is N-type, therefore can form the transistor of positive-negative-positive, but the present invention also can form the transistor of NPN knot not as limit.
Because the second doped region 232 is embedded in this tagma 223 of P type, so the impurity concentration of the second doped region 232 is higher with respect to the impurity concentration of the first doped region 231.In addition, field plate 240 and covers on the part surface zone in this tagma 223 between the second doped region 232 and the 3rd doped region 233.Yet field plate 240 also can be formed between the first doped region 231 and the 3rd doped region 233, and the field plate 241 such as Figure 6 and Figure 7 does not repeat them here.
Please refer to Fig. 9 to Figure 10, it illustrates respectively the schematic diagram according to two kinds of protective circuits of one embodiment of the invention.In Fig. 9, the emitter-base bandgap grading E of two-carrier junction transistors 300 and collector C are connected to high potential Vdd and electronegative potential Vss, and emitter-base bandgap grading E links to each other with base stage B.As mentioned above, two-carrier junction transistors 300 can be by increasing field plate, improving puncture voltage, thereby can be used as the clamped circuit of electrostatic discharge (ESD) protection between power supply.In addition, in Figure 10, two two-carrier junction transistors 310,320 are in parallel with P-type mos transistor 304 with N-type metal oxide semiconductor transistor 302 respectively, and the emitter-base bandgap grading E of the collector C of two-carrier junction transistors 310 and another two-carrier junction transistors 320 is connected to a defeated in/out connection pad 306.As mentioned above, this two two-carriers junction transistors 310,320 improves puncture voltage by field plate, thereby can be used as the ESD protection circuit of defeated in/out connection pad 306.
In sum, although the present invention discloses as above with preferred embodiment, so it is not to limit the present invention.The persond having ordinary knowledge in the technical field of the present invention, without departing from the spirit and scope of the present invention, when being used for a variety of modifications and variations.Therefore, protection scope of the present invention is when looking being as the criterion that the claim scope of enclosing defines.
Claims (10)
1. semiconductor structure comprises:
One substrate;
The well region of the well region of one first conductivity type and one second conductivity type is formed at respectively in this substrate;
One this tagma is formed in the well region of this second conductivity type;
One first doped region and one second doped region, be formed at respectively in the well region of this first conductivity type with this this tagma in, the polarity of this second doped region is identical with the polarity of this first doped region, and the impurity concentration of this second doped region is greater than the impurity concentration of this first doped region;
One the 3rd doped region be formed at the well region of this second conductivity type, and between this first doped region and this second doped region, the polarity of the 3rd doped region is opposite with the polarity of this first doped region; And
One first field plate is formed at the surf zone between this second doped region and the 3rd doped region.
2. semiconductor structure according to claim 1 more comprises one second field plate, is formed at the surf zone between this first doped region and the 3rd doped region, and the material of this second field plate is polysilicon.
3. semiconductor structure according to claim 2 more comprises a field oxide, is formed at the surf zone between this first doped region and the 3rd doped region, and this second field plate covers this field oxide.
4. semiconductor structure according to claim 1, more comprise a field oxide, be formed at the surf zone between this second doped region and the 3rd doped region, this first field plate covers this field oxide, and cover the part surface zone in this this tagma, the material of this first field plate is polysilicon.
5. semiconductor structure comprises:
One substrate;
The well region of the well region of one first conductivity type and one second conductivity type is formed at respectively in this substrate;
One this tagma is formed in the well region of this second conductivity type;
One first doped region and one second doped region, be formed at respectively in the well region of this first conductivity type with this this tagma in, the polarity of this second doped region is identical with the polarity of this first doped region, and the impurity concentration of this second doped region is greater than the impurity concentration of this first doped region;
One the 3rd doped region be formed at the well region of this second conductivity type, and between this first doped region and this second doped region, the polarity of the 3rd doped region is opposite with the polarity of this first doped region; And
One field plate is formed at the surf zone between this first doped region and the 3rd doped region, and the material of this field plate is polysilicon.
6. the manufacture method of a semiconductor structure, the method comprises:
One substrate is provided;
Form respectively the well region of the well region of one first conductivity type and one second conductivity type in this substrate;
Form this tagma in the well region of this second conductivity type;
Form respectively one first doped region and one second doped region in the well region and this this tagma of this first conductivity type, the polarity of this second doped region is identical with the polarity of this first doped region, and the impurity concentration of this second doped region is greater than the impurity concentration of this first doped region;
Form one the 3rd doped region in the well region of this second conductivity type, and between this first doped region and this second doped region, the polarity of the 3rd doped region is opposite with the polarity of this first doped region; And
Form the surf zone of one first field plate between this second doped region and the 3rd doped region.
7. method according to claim 6, more comprise and form the surf zone of one second field plate between this first doped region and the 3rd doped region, wherein form before this second field plate, more comprise and form the surf zone of a field oxide between this first doped region and the 3rd doped region, and form after this second field plate, this second field plate is covered in this field oxide, and the material of this second field plate is polysilicon.
8. method according to claim 6, wherein form before this first field plate, more comprise and form the surf zone of a field oxide between this second doped region and the 3rd doped region, and form after this first field plate, this first field plate is covered in this field oxide, and this first field plate covers the part surface zone in this this tagma, and the material of this first field plate is polysilicon.
9. the manufacture method of a semiconductor structure comprises:
One substrate is provided;
Form respectively the well region of the well region of one first conductivity type and one second conductivity type in this substrate;
Form this tagma in the well region of this second conductivity type;
Form respectively one first doped region and one second doped region in the well region and this this tagma of this first conductivity type, the polarity of this second doped region is identical with the polarity of this first doped region, and the impurity concentration of this second doped region is greater than the impurity concentration of this first doped region;
Form one the 3rd doped region in the well region of this second conductivity type, and between this first doped region and this second doped region, the polarity of the 3rd doped region is opposite with the polarity of this first doped region; And
Form the surf zone of a field plate between this first doped region and the 3rd doped region, the material of this field plate is polysilicon.
10. method according to claim 9 wherein forms before this field plate, comprises more forming the surf zone of a field oxide between this first doped region and the 3rd doped region, and form after this field plate that this field plate is covered in this field oxide.
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Cited By (4)
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| CN103489904A (en) * | 2012-06-11 | 2014-01-01 | 旺宏电子股份有限公司 | Semiconductor element, manufacturing method thereof and operating method thereof |
| CN104733516A (en) * | 2013-12-18 | 2015-06-24 | 旺宏电子股份有限公司 | Semiconductor element and manufacturing method thereof |
| CN107346784A (en) * | 2016-05-04 | 2017-11-14 | 旺宏电子股份有限公司 | Bipolar junction transistor |
| CN108878510A (en) * | 2017-05-10 | 2018-11-23 | 旺宏电子股份有限公司 | Semiconductor element |
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| US7132344B1 (en) * | 2004-12-03 | 2006-11-07 | National Semiconductor Corporation | Super self-aligned BJT with base shorted field plate and method of fabricating |
| US20100013458A1 (en) * | 2006-12-20 | 2010-01-21 | Marc Lany | Semiconductor Device For Measuring Ultra Small Electrical Currents And Small Voltages |
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| US4967253A (en) * | 1988-08-31 | 1990-10-30 | International Business Machines Corporation | Bipolar transistor integrated circuit technology |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103489904A (en) * | 2012-06-11 | 2014-01-01 | 旺宏电子股份有限公司 | Semiconductor element, manufacturing method thereof and operating method thereof |
| CN103489904B (en) * | 2012-06-11 | 2016-03-16 | 旺宏电子股份有限公司 | Semiconductor element, its manufacture method and method of operation thereof |
| CN104733516A (en) * | 2013-12-18 | 2015-06-24 | 旺宏电子股份有限公司 | Semiconductor element and manufacturing method thereof |
| CN107346784A (en) * | 2016-05-04 | 2017-11-14 | 旺宏电子股份有限公司 | Bipolar junction transistor |
| CN108878510A (en) * | 2017-05-10 | 2018-11-23 | 旺宏电子股份有限公司 | Semiconductor element |
| CN108878510B (en) * | 2017-05-10 | 2021-08-31 | 旺宏电子股份有限公司 | Semiconductor device with a plurality of semiconductor chips |
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