CN115377095A - Multi-finger MOS device, forming method and related structure - Google Patents

Multi-finger MOS device, forming method and related structure Download PDF

Info

Publication number
CN115377095A
CN115377095A CN202211124651.2A CN202211124651A CN115377095A CN 115377095 A CN115377095 A CN 115377095A CN 202211124651 A CN202211124651 A CN 202211124651A CN 115377095 A CN115377095 A CN 115377095A
Authority
CN
China
Prior art keywords
substrate
finger
mos
finger mos
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202211124651.2A
Other languages
Chinese (zh)
Inventor
宋璧若
李志国
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yangtze Memory Technologies Co Ltd
Original Assignee
Yangtze Memory Technologies Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yangtze Memory Technologies Co Ltd filed Critical Yangtze Memory Technologies Co Ltd
Priority to CN202211124651.2A priority Critical patent/CN115377095A/en
Publication of CN115377095A publication Critical patent/CN115377095A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

The embodiment of the invention provides a multi-finger MOS device, a forming method and a related structure. Wherein the MOS device comprises: a semiconductor substrate; a substrate contact frame disposed on the semiconductor substrate; and a plurality of single-finger MOS devices provided on a first substrate of the semiconductor substrate; the first substrate is a substrate in the space surrounded by the substrate contact frame in the semiconductor substrate; the single-finger MOS devices are uniformly arranged on the surface of the first substrate around a first blank area of the surface of the first substrate; the first blank area is located in the central area of the surface of the first substrate.

Description

Multi-finger MOS device, forming method and related structure
Technical Field
The invention relates to the technical field of memories, in particular to a multi-finger Metal Oxide Semiconductor (MOS) device, a forming method and a related structure.
Background
Electrostatic discharge is a natural phenomenon that is inevitable during the production, packaging and testing of integrated circuit chips. With the reduction of the process feature size of the integrated circuit and the development of various advanced processes, the situation that the integrated circuit chip is damaged by an ElectroStatic Discharge (ESD) phenomenon is more and more common, and the yield of the integrated circuit chip production is affected, so that more and more chip manufacturers pay attention to the design of the anti-ElectroStatic Discharge capability of the chip integrated circuit. At present, a multi-finger MOS transistor is widely applied to an ESD circuit, but the multi-finger MOS transistor has a problem of uneven turn-on, which may cause the ESD circuit to be burned out.
Disclosure of Invention
In view of the above, the present invention provides a multi-finger MOS device, a forming method and a related structure, wherein a plurality of single-finger MOS included in the MOS device are uniformly disposed on a substrate surrounding a central blank area of the substrate, so that a substrate resistance corresponding to each single-finger MOS in the plurality of single-finger MOS is balanced, thereby the MOS device can overcome the problem of non-uniform turn-on.
In order to achieve the purpose, the technical scheme of the invention is realized as follows:
in a first aspect, an embodiment of the present invention provides a multi-finger MOS device, including:
a semiconductor substrate;
a substrate contact frame disposed on the semiconductor substrate;
and a plurality of single-finger MOS devices provided on a first substrate of the semiconductor substrate; the first substrate is a substrate in a space surrounded by the substrate contact frame in the semiconductor substrate; the single-finger MOS devices are uniformly arranged on the surface of the first substrate around a first blank area of the surface of the first substrate; the first blank area is located in a central area of the surface of the first substrate.
In a second aspect, an embodiment of the present invention further provides an electrostatic clamp, including:
the transient sub-circuit is connected between a power supply pin and a grounding pin in parallel and is sequentially coupled with any one of the multi-finger Metal Oxide Semiconductor (MOS) devices, wherein the transient sub-circuit is used for sending a driving signal with a voltage value smaller than that of a power supply to the multi-finger MOS devices when static electricity is detected; the multi-finger MOS device discharges the static electricity under the driving of the driving signal.
In a third aspect, an embodiment of the present invention further provides an integrated circuit, including:
the high-voltage bonding pad is used for connecting a power supply voltage;
a low voltage pad for accessing a ground voltage;
and an electrostatic clamp as in any preceding claim; and the power pin of the electrostatic clamping circuit is electrically connected with the high-voltage bonding pad, and the grounding pin is electrically connected with the low-voltage bonding pad.
In a fourth aspect, an embodiment of the present invention further provides a method for forming a multi-finger metal oxide semiconductor MOS device, including:
forming a semiconductor substrate;
forming a substrate contact frame on the surface of the semiconductor substrate;
forming a plurality of single-finger MOS on the surface of a first substrate in the space surrounded by the substrate contact frame in the semiconductor substrate; the single-finger MOS surrounds a first blank area on the surface of the first substrate and is uniformly formed on the surface of the first substrate; the first blank area is located in the central area of the surface of the first substrate.
In a fifth aspect, an embodiment of the present invention further provides a memory, including: a memory array comprising memory cells;
and peripheral circuitry coupled to the memory array and configured to control the memory array;
the peripheral circuitry comprises the electrostatic clamp of any of the preceding claims; alternatively, the peripheral circuit comprises the integrated circuit described previously.
In a sixth aspect, an embodiment of the present invention further provides a storage system, including one or more of the foregoing memories; and a memory controller coupled to the memory; the memory controller to: various operation commands are sent to the memory.
The embodiment of the invention provides a multi-finger MOS device, a forming method and a related structure. Wherein, the multi-finger MOS device comprises: a semiconductor substrate; a substrate contact frame disposed on the semiconductor substrate; and a plurality of single-finger MOS devices provided on a first substrate of the semiconductor substrate; the first substrate is a substrate in a space surrounded by the substrate contact frame in the semiconductor substrate; the single-finger MOS devices are uniformly arranged on the surface of the first substrate around a first blank area of the surface of the first substrate; the first blank area is located in a central area of the surface of the first substrate. According to the multi-finger MOS device provided by the embodiment of the invention, a plurality of single-finger MOS contained in the MOS device are uniformly distributed on the substrate surrounding the central blank area of the substrate, so that the substrate resistance corresponding to each single-finger MOS in the single-finger MOS is balanced, and thus, the problem of uneven opening of the MOS device can be solved. In addition, the multi-finger MOS device is obtained simply and quickly, so that the multi-finger MOS device can be produced and used in large batch.
Drawings
Aspects of the present invention are best understood from the following detailed description of the embodiments when read in connection with the accompanying drawings. Note that in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
Fig. 1 is a schematic structural diagram of a multi-finger MOS device according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of another multi-finger MOS device provided in an embodiment of the present invention; a
Fig. 3 is a schematic diagram illustrating an electrostatic clamp according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a circuit connection of a single-finger MOS in the electrostatic clamp shown in FIG. 3 according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of an integrated circuit according to an embodiment of the present invention;
fig. 6 is a first flowchart illustrating a method for forming a multi-finger MOS device according to an embodiment of the present invention;
fig. 7 is a schematic flow chart of a method for forming a multi-finger MOS device according to an embodiment of the present invention;
FIG. 8 shows a schematic diagram of an exemplary memory containing peripheral circuitry;
FIG. 9 is a schematic diagram showing the organization of a memory array;
FIG. 10 illustrates a side view of a cross-section of an exemplary memory array containing strings of memory cells, in accordance with aspects of the present invention;
FIG. 11 illustrates a block diagram of an exemplary memory including a memory array and peripheral circuitry
FIG. 12 is a schematic structural diagram of a storage system according to an embodiment of the present invention;
FIG. 13 shows a block diagram of an exemplary system with memory in the related art;
FIG. 14 shows a schematic diagram of an exemplary memory card with memory;
fig. 15 shows a schematic diagram of an exemplary Solid State Disk (SSD) with memory.
Detailed Description
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, formation of a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. In addition, the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Furthermore, spatially relative terms such as "below … …", "below … …", "lower", "above … …", "upper", and the like may be used herein for ease of description to describe the relationship of one element or feature to another element or feature(s) as shown in the figures. Spatially relative terms are intended to encompass different orientations in use or operation of the device in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The technique of the present invention will be described in detail below with reference to the drawings.
Referring to fig. 1, a schematic structural diagram of a multi-finger MOS device provided in an embodiment of the present invention is shown. In fig. 1, the multi-finger MOS device 100 includes:
a semiconductor substrate 101;
a substrate contact frame 102 provided on the semiconductor substrate 101;
and a plurality of single-finger MOSs 103 provided on a first substrate 1011 of the semiconductor substrate 101; wherein the first substrate 1011 is a substrate in the semiconductor substrate in a space surrounded by the substrate contact frame 102; the plurality of single-finger MOS devices are uniformly arranged on the surface of the first substrate 1011 around a first blank area of the surface of the first substrate; the first clear area 1012 is located in a central region of the first substrate surface.
It should be noted that the multi-finger MOS device may correspond to a parallel connection of a plurality of single-finger MOS devices, where the single-finger MOS device may refer to an NPN junction or a PNP junction formed between each pair of source S and drain D.
In practical applications, the semiconductor substrate may be a P-type semiconductor substrate or an N-type semiconductor substrate.
In some embodiments, when the semiconductor substrate may be a P-type semiconductor substrate, the single-finger MOS may be an N-type MOS; when the semiconductor substrate can be an N-type semiconductor substrate, the single-finger MOS can be a P-type MOS. Wherein, the N-type MOS is also an MOS containing NPN junction; a P-type MOS is also a MOS comprising a PNP junction.
Specifically, when the single-finger MOS includes an NPN junction, the semiconductor substrate is a P-type semiconductor substrate, and the single-finger MOS may include: the N-type semiconductor drain region, the N-type semiconductor source region and the P-type semiconductor source terminal substrate contact region (namely the region where the substrate contact frame is located) are arranged on the surface of the semiconductor substrate, wherein the P-type source terminal substrate contact region and the N-type semiconductor source region are connected with source S metal, and the N-type semiconductor drain region is connected with drain D metal; the N-type semiconductor source region is arranged between the P-type semiconductor source end substrate contact region and the N-type semiconductor drain region, a gate oxide layer is arranged on the surface of the P-type semiconductor substrate between the N-type semiconductor source region and the N-type semiconductor drain region, and a polycrystalline silicon gate electrode G is arranged on the surface of the gate oxide layer.
When the single finger MOS includes a PNP junction, the semiconductor substrate is an N-type semiconductor substrate, and the single finger MOS may include: an N-type semiconductor source end substrate contact area (namely an area where a substrate contact frame is located), a P-type semiconductor source area and an N-type semiconductor drain area; the N-type semiconductor source end substrate contact area, the P-type semiconductor source area and the P-type semiconductor drain area are all located on the surface of the N-type semiconductor substrate, wherein the N-type source end substrate contact area and the P-type semiconductor source area are connected with a source S metal, and the P-type semiconductor drain area is connected with a drain D metal; the P-type semiconductor source region is arranged between the N-type semiconductor source end substrate contact region and the P-type semiconductor drain region, a gate oxide layer is arranged on the surface of the N-type semiconductor substrate between the P-type semiconductor source region and the P-type semiconductor drain region, and a polycrystalline silicon gate electrode G is arranged on the surface of the gate oxide layer.
In addition, it should be further noted that fig. 1 is a schematic diagram illustrating relations of parts included in a multi-finger MOS device provided by an embodiment of the present invention, and is not a structural diagram of a real implementation, for example, in some embodiments, an outermost edge of the substrate contact frame 102 may be coincident with an edge of the semiconductor substrate 101, or may be coincident with the edge of the semiconductor substrate, and is specifically designed according to an actual layout requirement. The number of the single-finger MOSs is not fixed to 55, but may include any realizable number more than 55 or less than 55, and therefore, the number of the single-finger MOSs is not limited in the present invention. Moreover, fig. 1 and subsequent drawings show the structure and connection relationship that the present invention intends to protect in the multi-finger MOS device, and other structures and connection relationships that are essential for forming the multi-finger MOS device are not shown in the present invention, which are similar to those in the related art and are not described herein again.
In the invention, the existing multi-finger MOS device is researched, and the single-finger MOS arranged at different positions of a semiconductor substrate has different sizes of corresponding substrate resistances for a plurality of single-finger MOS contained in the multi-finger MOS device. In general, in the multi-finger MOS device, the substrate resistance Rsub corresponding to the single-finger MOS disposed in the central region of the semiconductor substrate is the largest, and the resistance value of the substrate resistance corresponding to the single-finger MOS decreases as the disposition position is away from the central region. Based on this, the voltage Vsub divided from the power supply by the single finger MOS in the center region is the largest, and then the single finger MOS is turned on (i.e., turned on) first. This is the root cause of uneven turn-on of the MOS device.
Based on this, the embodiment of the present invention provides a multi-finger MOS device, which has a layout manner for a plurality of single-finger MOS devices included therein, in which a first blank region surrounding a first substrate 1011 is uniformly disposed on the surface of the first substrate 1011, and the first blank region is a central region of the surface of the first substrate. Therefore, one or more single-finger MOS originally positioned in the central area of the first substrate are removed, namely the possibly existing maximum substrate resistance or a plurality of larger substrate resistances are removed, so that the substrate resistance Rsub corresponding to each single-finger MOS in the multiple single-finger MOS devices is not different greatly, the single-finger MOS in the multiple single-finger MOS devices can be uniformly turned on, and the possibility of burning out the ESD circuit when the multiple-finger MOS devices are used in the ESD circuit is reduced.
Here, the first substrate is a substrate in a space surrounded by the substrate contact frame in the semiconductor substrate, that is, a part of the semiconductor substrate is covered by the substrate contact frame, the covered semiconductor substrate is not capable of disposing the single-finger MOS, and only the single-finger MOS is disposed on the surface of the semiconductor substrate in the substrate contact frame.
Based on the foregoing research, the substrate resistance corresponding to each single-finger MOS included in the multi-finger MOS device varies with the deployment position, and the substrate resistance corresponding to the single-finger MOS decreases as the deployment position of the single-finger MOS is away from the central region of the first substrate. Therefore, the problem of uneven opening of the multi-finger MOS device can be improved to a certain extent by adopting one or more single-finger MOS devices with the removing parts in the central area.
In some embodiments, the first blank area is not smaller than the area of the semiconductor substrate occupied by a gate oxide layer located between a semiconductor drain area and a semiconductor source area in the single-finger MOS.
Based on the previous research on the multi-finger MOS device, it can be known that the substrate resistance Rsub corresponding to the single-finger MOS disposed in the central region of the semiconductor substrate in the multi-finger MOS device is the largest, and the resistance value of the substrate resistance corresponding to the single-finger MOS is smaller as the disposition position is farther from the central region. Therefore, in the disposition of the single-finger MOS included in the multi-finger MOS device, one or more single-finger MOSs disposed in the central region of the first substrate is removed, so that the substrate resistances corresponding to the disposed single-finger MOSs do not differ greatly, and therefore, the minimum first blank region can be a region which is left by removing an NPN junction or a PNP junction, and then, the minimum area of the first blank region can be the area occupied by the gate oxide layer in the single-finger MOS. When the single-finger MOS is removed, the area of the first blank area is larger than the area occupied by the gate oxide layer in the single-finger MOS. The specific number of the first blank areas is determined according to the actual chip design.
Based on the foregoing description of the single finger in the multi-finger MOS device, the single-finger MOS may refer to an NPN junction or a PNP junction formed between each pair of the source S and the drain D, and thus, in some embodiments, in order to deploy more single-finger MOSs, the plurality of single-finger MOSs and a part of the single-finger MOSs in each group of the single-finger MOSs share a semiconductor drain region and a drain metal or a semiconductor source region and a source metal.
For example, the layout of the multi-finger MOS device 100 as illustrated in fig. 1, wherein two single-finger MOS in the AA box share a semiconductor drain region and a drain metal; two single finger MOS in BB frame share semiconductor source region and source metal.
In some embodiments, for better improvement, as shown in fig. 2, a schematic structural diagram of another multi-finger MOS device provided in an embodiment of the present invention is shown. In the multi-finger MOS device 100, the substrate contact frame 102 includes a plurality of sub-contact frames 1021; a group of single-finger MOS devices are arranged on the surface of the second substrate 1022 in the semiconductor substrate 101 in the space surrounded by each sub-contact frame 1021; the single-finger MOS in each group of the single-finger MOS is uniformly arranged on the surface of the second substrate 1022 around the second blank area 1023 of the corresponding surface of the second substrate; the second blank area 1023 is located in a central area of the second substrate surface.
The structure of the multi-finger MOS device described above can be understood as follows: the method comprises the steps of dividing a substrate contact frame 102 arranged on a semiconductor substrate 101 into a plurality of sub-contact frames 1021, uniformly arranging a group of single-finger MOS around a second blank area on the surface of a second substrate surrounded by each sub-contact frame 1021, namely, mixing the plurality of single-finger MOS arranged on the surface of the semiconductor substrate 101 into a plurality of groups, wherein each group of single-finger MOS is arranged on the part of the semiconductor substrate surrounded by the corresponding sub-contact frame, and the second blank area is reserved in the central area of each sub-contact frame, so that the substrate resistance corresponding to the single-finger MOS arranged on the semiconductor substrate is not greatly different, the single-finger MOS in the plurality of single-finger MOS can be uniformly turned on, and the possibility of burning out an ESD circuit when the multi-finger MOS device is used in the ESD circuit is reduced.
In some embodiments, there is no overlap region between the plurality of sub-contact frames.
In some embodiments, each of the plurality of sub-contact frames is connected to a low voltage pad for accessing a low voltage, wherein connection points of the sub-contact frames of the plurality of sub-contact frames to the low voltage pad are sequentially decreased from the sub-contact frame at a middle position to the sub-contact frame at an edge position.
It should be noted that the sub contact frames are independently arranged, and each sub contact frame is arranged between the sub contact framesThere is no overlap area between the frame edges of the contact frames. The connection point may be referred to as the block indicated at 104 in fig. 1. Since the parasitic resistance of the substrate contact frame 102 included in the multi-finger MOS device also affects its switching characteristics when the multi-finger MOS device is connected in operation in a circuit. The parasitic resistance is a part of the parasitic resistance of each one-finger MOS in the multi-finger MOS device (i.e., R described later) D1 +R S1 Or R D2 +R S2 Including the parasitic resistance of the substrate contact frame 102) whose magnitude is related to the distance between the high voltage pads or the low voltage pads and the number of connection points on the substrate contact frame 102. The farther from the high-voltage pad or the low-voltage pad, the greater the parasitic resistance; the greater the number of connection points on the substrate contact frame 102, the smaller the parasitic resistance that results from their parallel connection. Based on the characteristics, the substrate contact frame 102 is divided into a plurality of independent sub-contact frames, and the parasitic resistance corresponding to each sub-contact frame can be adjusted by adjusting the number of connection points on the sub-contact frames, so that each single-finger MOS in the multi-finger MOS device has a parasitic resistance with a similar size, and the multi-finger MOS device can improve the problem of uneven opening.
In some embodiments, the number of single-finger MOS groups corresponding to the sub-contact frames is equal to the number of single-finger MOS groups.
In order to make the multi-finger MOS devices in fig. 1 and fig. 2 identical, the total number of the sets of single-finger MOS including single-finger MOS corresponding to the sub-contact frames is equal to the number of the single-finger MOS included in the plurality of single-finger MOS. That is, if the multi-finger MOS devices in fig. 1 and fig. 2 are the same, the number of single-finger MOS devices used is the same, except that in fig. 1, a plurality of single-finger MOS devices are disposed on the surface of the semiconductor substrate in the same substrate contact frame; in fig. 2, after a plurality of single finger MOSs are divided into a plurality of groups, each group of single finger MOSs is disposed on the surface of the semiconductor substrate within one sub-contact frame.
In some embodiments, the second empty area is not smaller than the area of the semiconductor substrate occupied by a gate oxide layer located between the semiconductor drain region and the semiconductor source region in the single-finger MOS. It should be noted that the reason is as described above for the first blank area, and is not described herein again.
According to the multi-finger MOS device provided by the embodiment of the invention, a plurality of single-finger MOS contained in the MOS device are uniformly distributed on the substrate surrounding the central blank area of the substrate, so that the substrate resistance corresponding to each single-finger MOS in the single-finger MOS is balanced, and thus, the problem of uneven opening of the MOS device can be solved. In addition, the multi-finger MOS device provided by the embodiment of the invention can remove one or more single-finger MOS devices in the central region of the substrate through the existing multi-finger MOS device, and can also not arrange the single-finger MOS devices in the central region of the substrate during production, so that the multi-finger MOS device can be obtained in various and simple modes, and the multi-finger MOS device can be produced and used in large batch. The multi-finger MOS device provided by the embodiment of the invention can improve the problem of uneven opening, and only by changing the layout of the single-finger MOS contained in the multi-finger MOS device, no additional process or mask is needed.
Based on the foregoing inventive concept, an embodiment of the present invention further provides an electrostatic clamp circuit, as shown in fig. 3, where the electrostatic clamp circuit 300 may include: a transient sub-circuit 303 connected in parallel between the power pin 301 and the ground pin 302 and coupled in sequence, and the multi-finger MOS device 100 as described in any of the foregoing, wherein the transient sub-circuit 303 is configured to send a driving signal with a voltage value smaller than that of the power supply to the multi-finger MOS device 100 when static electricity is detected; the multi-finger MOS device discharges the static electricity under the driving of the driving signal.
In some embodiments, the transient subcircuit 303 may include: a capacitor 3031 and a resistor 3032 which are connected in series between the power supply pin and the grounding pin; when the multi-finger MOS device is an N-type MOS, the drain electrode of the multi-finger MOS device is connected with the power pin, the source electrode of the multi-finger MOS device is connected with the grounding pin, and the grid electrode of the multi-finger MOS device is connected with the connection position of the capacitor and the resistor.
In fig. 3, the arrows indicate the driving signals. The electrostatic clamp 300 operates according to the following principle: when the voltage pin 301 is connected to static electricity, the RC trigger circuit composed of the capacitor 3031 and the resistor 3032 generates the driving signal and sends the driving signal to the gate of the multi-finger MOS device 100. Since the voltage value of the driving signal is smaller than the voltage value of the power supply but larger than the threshold voltage of the multi-finger MOS device, the multi-finger MOS device is turned on, and the multi-finger MOS device discharges the static electricity.
In practical applications, the single-finger MOS included in the multi-finger MOS device connected to the electrostatic clamp has parasitic resistance, as shown in fig. 4, which illustrates a schematic circuit connection diagram of the single-finger MOS included in the multi-finger MOS device in the electrostatic clamp according to the embodiment of the present invention. In fig. 4, rsub denotes the substrate resistance of the single finger MOS; r S Representing the parasitic resistance (or called wiring resistance) between the source terminal of the single-finger MOS to the low-voltage bonding pad; r D Representing the parasitic resistance between the drain terminal of the single finger MOS to the high voltage pad. In different layout modes, in the multi-finger MOS device, the parasitic resistance corresponding to each single-finger MOS is also different. Different parasitic resistances also affect the discharge capability of the multi-finger MOS device.
Based on this, an embodiment of the present invention further provides an integrated circuit, as shown in fig. 5, where the integrated circuit 500 may include:
a high voltage pad 501 for accessing a power supply voltage;
a low voltage pad 502 for accessing a ground voltage;
and the electrostatic clamp 300 of any of the preceding claims disposed between the high voltage pad 501 and the low voltage pad 502; the power pin 301 of the electrostatic clamp 300 is electrically connected to the high voltage pad 501, and the ground pin 502 is electrically connected to the low voltage pad 402.
It should be noted that the layout of the electrostatic clamp Circuit 300 between the high-voltage pad and the low-voltage pad may be understood as that the high-voltage pad and the low-voltage pad are on the left and right sides or the upper and lower sides of the electrostatic clamp Circuit 300, wherein the closer distance to the high-voltage pad or the lower distance to the low-voltage pad may be determined according to an actual Printed Circuit Board (PCB) of an integrated Circuit. The electrostatic clamping circuit is arranged between the high-voltage bonding pad and the low-voltage bonding pad no matter the bonding pad is close to the bonding pad, so that in a discharge path of the electrostatic clamping circuit, each single-finger MOS in the contained multi-finger MOS device has parasitic resistance with similar size, each single-finger MOS has uniform discharge current, and the problem of uneven starting of the multi-finger MOS device is further improved.
For example, as in fig. 5, single-finger MOS1 and single-finger MOS2 are two single-finger MOSs included in the multi-finger MOS device. After the electrostatic clamping circuit containing the multi-finger MOS device is arranged between the high-voltage bonding pad and the low-voltage bonding pad, the parasitic resistance R between the corresponding drain end of the single-finger MOS1 and the high-voltage bonding pad D1 Less than parasitic resistance R between the corresponding drain terminal of the single finger MOS2 and the high-voltage bonding pad D2 (ii) a And the single-finger MOS1 corresponds to the parasitic resistance R between the source terminal and the low-voltage bonding pad S1 Greater than parasitic resistance R between corresponding source terminal and low-voltage bonding pad of single-finger MOS2 S2 Overall, the total parasitic resistance corresponding to the single-finger MOS1 is R D1 +R S1 The total parasitic resistance corresponding to the single finger MOS2 is R D2 +R S2 Similarly, the discharge current of each single-finger MOS in the multi-finger MOS device is uniform during electrostatic discharge, so that the problem of uneven turn-on of the multi-finger MOS device is further improved.
Fig. 6 is a schematic flow chart of a method for forming a multi-finger MOS device according to an embodiment of the present invention. As shown in fig. 6, the forming method may include:
s601: forming a semiconductor substrate;
s602: forming a substrate contact frame on the surface of the semiconductor substrate;
s603: forming a plurality of single-finger MOS on the surface of a first substrate in the space surrounded by the substrate contact frame in the semiconductor substrate; the single-finger MOS surrounds a first blank area on the surface of the first substrate and is uniformly formed on the surface of the first substrate; the first blank area is located in the central area of the surface of the first substrate.
In some embodiments, the substrate contact frame formed on the surface of the semiconductor substrate comprises a plurality of sub-contact frames; as shown in fig. 7, the forming method further includes:
s604: forming a group of single-finger MOS on the surface of the second substrate in the space surrounded by each sub-contact frame in the semiconductor substrate; the single-finger MOS in each group of the single-finger MOS surrounds the second blank area of the corresponding second substrate surface and is uniformly arranged on the second substrate surface; the second blank area is located in a central area of the surface of the second substrate.
It should be noted that the formation method described above is a multi-finger MOS device corresponding to the two structures. In practical application, there are two ways for forming the multi-finger MOS device with the above structure: one is to form the finally required multi-finger MOS device in steps S501 to S503 or in steps S501, S502, and S504 one by one based on a new semiconductor substrate; the other is based on the existing multi-finger MOS device, one or more single-finger MOS devices in the central area are removed to form the required multi-finger MOS device, or the multiple single-finger MOS devices contained in the multi-finger MOS device are divided into multiple groups of single-finger MOS devices, and then each group of single-finger MOS devices are framed by using independent sub contact frames to form the required multi-finger MOS device.
It should be understood that the above-mentioned forming method only describes the steps of the present invention that are mainly concerned, and other necessary steps, which have been described in detail in the foregoing structure description of the multi-finger MOS device, can be implemented in any realizable manner in the forming process, and are not described in detail herein.
An embodiment of the present invention further provides a memory, as shown in fig. 8, where the memory 800 includes: a memory array 801 for storing data; and peripheral circuitry 802 coupled to and for controlling the memory array 801; wherein the peripheral circuitry 802 comprises the electrostatic clamp of any of the preceding claims; alternatively, the peripheral circuit comprises the integrated circuit described above.
It should be noted that the foregoing describes only the structure of the peripheral circuit 802 and the relevant portions of the embodiments of the present invention. In practice, for the memory array 801 to be a NAND flash memory array, the memory cells 806 are provided in the form of an array of NAND memory cell strings 808, each NAND memory cell string 808 extending vertically above a substrate (not shown). In some embodiments, each NAND memory cell string 808 includes a plurality of memory cells 806 coupled in series and vertically stacked. Each memory cell 806 may hold a continuous analog value, e.g., a voltage or charge, that depends on the number of electrons trapped within the storage region of the memory cell 806. Each memory cell 806 may be a floating gate type memory cell including a floating gate transistor or a charge trapping type memory cell including a charge trapping transistor.
In some embodiments, each memory Cell 806 is a Single Level Cell (SLC) having two possible memory states and therefore can store one bit of data, e.g., a first memory state "0" may correspond to a first voltage range and a second memory state "1" may correspond to a second voltage range. In some embodiments, each memory Cell 806 is a Multi-Level Cell (MLC) capable of storing data for a single bit in a plurality of four memory states, e.g., an MLC may store two bits per Cell, three bits per Cell (also referred to as a triple Level Cell), or four bits per Cell (also referred to as a quad Level Cell).
As shown in fig. 8, each NAND memory cell string 808 can include a Source Select Gate (SSG) 810 at its source end and a Drain Select Gate (DSG) 812 at its drain end. The SSGs 810 and 812 may be configured to activate selected NAND memory cell strings 808 (columns of the array) during read and program (or write) operations. In some embodiments, the sources of NAND memory cell strings 808 in the same block 804 are coupled by the same Source Line (SL) 814 (e.g., a common SL). In other words, according to some embodiments, all of the NAND memory cell strings 808 in the same block 804 have an Array Common Source (ACS). According to some embodiments, the DSG812 of each NAND memory cell string 808 is coupled to a respective bit line 816, and data can be read from and written to the bit line 816 via an output bus (not shown). In some embodiments, each NAND memory cell string 808 is configured to be selected or deselected by applying a select voltage (e.g., above the threshold voltage of the transistor having the DSG 812) or a deselect voltage (e.g., 0 volts (V)) to the corresponding DSG812 via one or more DSG lines 813 and/or applying a select voltage (e.g., above the threshold voltage of the transistor having the SSG 810) or a deselect voltage (e.g., 0V) to the corresponding SSG810 via one or more SSG lines 815.
As shown in fig. 8, the NAND memory cell strings 808 may be organized into a plurality of blocks 804, each of the plurality of blocks 804 may have a common source line 814 (e.g., coupled to ground). In some embodiments, each block 804 is the basic unit of data with an erase operation, i.e., all storage cells 806 on the same block 804 are erased at the same time. To erase memory cells 806 in a selected block 804, a source line 814 coupled to the selected block 804 and to unselected blocks 804 in the same Plane (Plane) as the selected block 804 may be biased with an erase voltage (Vers), such as a high positive voltage of 20V or higher. It should be appreciated that in some examples, erase operations may be performed at a half block level, at a quarter block level, or at any suitable fraction of any suitable number of blocks or blocks. The memory cells 806 of the adjacent NAND memory cell strings 808 may be coupled by word lines 818, the word lines 818 selecting which row of memory cells 806 receive the read and program operations. In some embodiments, the memory cells 806 coupled to the same wordline 818 are referred to as a page 820. The page 820 is the basic unit of data for a program operation or a read operation, and the size of a page 820 in bits can be related to the number of NAND memory cell strings 808 coupled by word lines 818 in one block 804. Each word line 818 may include a plurality of control gates (gate electrodes) at each memory cell 806 in a respective page 820 and a gate line coupling the control gates.
The organization of the memory array 801 within the memory is shown in FIG. 9. The storage array 801 may be divided into several DIEs (or LUNs), each DIE having several planes (planes), each Plane having several blocks (blocks), each Block having several pages (pages), each Page corresponding to a word line (word), which connects thousands of storage units 806. Wherein the DIE/LUN is a basic unit for receiving and executing the operation command. As shown in FIG. 9, LUN0 and LUN1 can receive and execute different commands simultaneously (but still with certain limitations, different flash limitations of different vendors). However, in one LUN, only one command can be executed independently at a time, and it is impossible to perform read access to another Page while writing to one of the pages. A LUN is subdivided into several planes, 1 or 2 planes are common in the market, there are also flash memories of 4 planes, there are also flash memories of more than 4 planes, for example, flash memories containing 6 planes. It should be understood that how many planes a LUN includes may be more as technology evolves, and the invention is not limited. Each Plane has its own independent Cache buffer (Cache Register) and Page buffer (Page Register) that is equal in size to one Page. When a certain Page is written by a memory controller coupled with a memory, data is transmitted from the memory controller to a Cache Register of a Plane corresponding to the Page, and then the data in the whole Cache Register is written into a storage unit; in the reverse case, the data of the Page is read from the storage unit to the Cache Register and then transmitted to the memory controller as required. When reading data, the on-demand is that the data of the whole Page is not necessarily transmitted to the memory controller, and the data transmission is selected according to the demand. It should be kept in mind, however, that the unit of Page is used whether to read data from a memory cell to a Cache Register or to write data from a Cache Register to a memory cell. This is merely an exemplary description and is not intended to limit the present application.
FIG. 10 illustrates a side view of a cross section of an exemplary memory array 801 including NAND memory cell strings 808 in accordance with some aspects of the present invention. As shown in fig. 10, NAND memory cell strings 808 may extend vertically through the memory stack layers 1002 above the substrate 1001. Substrate 1001 may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.
Memory stack layer 1002 can include alternating gate conductive layers 1003 and gate-to-gate dielectric layers 1004. The number of pairs of gate conductive layers 1003 and gate-to-gate dielectric layers 1004 in memory stack 1002 may determine the number of memory cells 806 in memory array 801. The gate conductive layer 1003 may include a conductive material including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate conductive layer 1003 includes a metal layer, for example, a tungsten layer. In some embodiments, each gate conductive layer 1003 includes a doped polysilicon layer. Each gate conductive layer 1003 may include a control gate surrounding a memory cell 806 and may extend laterally at the top of memory stack 1002 as a DSG line 813, laterally at the bottom of memory stack 1002 as an SSG line 815, or laterally between DSG line 813 and SSG line 815 as a word line 818.
As shown in fig. 10, NAND memory cell string 808 includes a channel structure 1005 extending vertically through memory stack layers 1002. In some embodiments, the channel structure 1005 includes a channel hole filled with semiconductor material(s) and dielectric material(s). In some embodiments, the semiconductor channel comprises silicon, e.g., polysilicon. In some embodiments, the memory film is a composite dielectric layer that includes a tunneling layer, a storage layer (also referred to as a "charge trapping/storage layer"), and a blocking layer. The channel structure 1005 may have a cylindrical shape (e.g., a pillar shape). According to some embodiments, the semiconductor channel, the tunneling layer, the storage layer, and the blocking layer are radially disposed in this order from a center of the pillar toward an outer surface of the pillar. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The memory layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide/silicon oxynitride/silicon oxide (ONO).
Referring back to FIG. 8, peripheral circuitry 802 may be coupled to memory array 801 by bit lines 816, word lines 818, source lines 814, SSG lines 815, and DSG lines 813. Peripheral circuitry 802 may include any suitable analog, digital, and mixed-signal circuitry for facilitating operation of memory array 801 by applying voltage and/or current signals to and sensing voltage and/or current signals from each target memory cell 806 via bit line 816, word line 818, source line 814, SSG line 815, and DSG line 813. The peripheral circuitry 802 may include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. For example, fig. 11 shows some exemplary peripheral circuits, the peripheral circuits 802 including page buffers/sense amplifiers 1104, column decoders/bit line drivers 1106, row decoders/word line drivers 1108, voltage generators 1110, control logic unit 1112, registers 1114, interfaces 1116, and a data bus 1118. It should be understood that additional peripheral circuitry not shown in fig. 11 may also be included in some examples.
The page buffer/sense amplifier 1104 may be configured to read data from the memory array 801 and program (write) data to the memory array 801 according to control signals from the control logic unit 1112. In one example, the page buffer/sense amplifier 1104 may store a page of program data (write data) to be programmed into one page 820 of the memory array 801. In another example, the page buffer/sense amplifier 1104 may perform a program verify operation to ensure that data has been properly programmed into the memory cells 806 coupled to the selected word line 818. In yet another example, the page buffer/sense amplifier 1104 may also sense low-power signals from the bit line 816 that represent data bits stored in the memory cells 806 and amplify the small voltage swing to recognizable logic levels in a read operation. The column decoder/bit line driver 1106 may be configured to be controlled by the control logic unit 1112 and select one or more NAND memory cell strings 808 by applying a bit line voltage generated from the voltage generator 1110.
The row decoder/word line drivers 1108 may be configured to be controlled by the control logic unit 1112 and to select/deselect the blocks 804 of the memory array 801 and to select/deselect the word lines 818 of the blocks 804. The row decoder/wordline driver 1108 may also be configured to drive the wordline 818 using the wordline voltage generated from the voltage generator 1110. In some embodiments, row decoder/word line driver 1108 may also select/deselect and drive SSG lines 815 and DSG lines 813. As described in detail below, the row decoder/wordline driver 1108 is configured to perform an erase operation on the memory cells 806 coupled to the selected wordline 818(s). The voltage generator 1110 may be configured to be controlled by the control logic unit 1112 and to generate a word line voltage (e.g., a read voltage, a program voltage, a pass voltage, a local voltage, a verify voltage, etc.), a bit line voltage, and a source line voltage to be supplied to the memory array 801.
The control logic unit 1112 may be coupled to each of the peripheral circuits described above and configured to control the operation of each of the peripheral circuits. The registers 1114 may be coupled to the control logic unit 1112 and include status, command, and address registers for storing status information, command operation codes (OP codes), and command addresses for controlling the operation of each peripheral circuit. Interface 1116 may be coupled to control logic unit 1112 and act as a control buffer to buffer and relay control commands received from a host (not shown) to control logic unit 1112 and to buffer and relay status information received from control logic unit 1112 to the host. The interface 1116 may also be coupled to a column decoder/bit line driver 1106 via a data bus 1118, and acts as a data I/O interface and data buffer to buffer data and relay it to or from the memory array 801.
An embodiment of the present invention further provides a storage system, as shown in fig. 12, where the storage system 1200 includes: one or more of the aforementioned memories 800; and a memory controller 1201 coupled to the memory; the memory controller 1201 is configured to: various operation commands are sent to the memory.
In some embodiments, the storage system is a solid state disk, SSD, or memory card.
It should be noted that the storage system may be coupled to a host to form a data system, such as the data system shown in FIG. 13. The data system 1300 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual Reality (VR) device, augmented Reality (AR) device, or any other suitable electronic device having storage therein. As shown in fig. 13, data system 1300 may include a host 1308 and a storage system 1200, where storage system 1200 has one or more memories 800 and a memory controller 1201; the host 1308 may be a Processor of an electronic device, such as a Central Processing Unit (CPU) or a System on Chip (SoC), which may be an Application Processor (AP), for example. Host 1308 may be configured to send data to memory 800 or receive data from memory 800. Specifically, memory 800 may be any of the memories disclosed in the present invention. Such as Phase Change Random Access Memory (PCRAM), three-dimensional NAND flash Memory, and the like.
According to some embodiments, memory controller 1201 is coupled to memory 800 and host 1308. And is configured to control the memory 800. The memory controller 1201 may manage data stored in the memory 800 and communicate with the host 1308. In some embodiments, memory controller 1201 is designed to operate in a low duty cycle environment, such as in a Secure Digital (SD) card, compact Flash (CF) card, universal Serial Bus (USB) Flash drive, or other media for use in electronic devices in low duty cycle environments, such as personal computers, digital cameras, mobile phones, and the like. In some embodiments, the memory controller 1201 is designed to operate in a high duty cycle environment, such as a Solid State Drive (SSD) or an embedded multimedia Card (eMMC), where the SSD or eMMC is used as a data storage and enterprise storage array for mobile devices in a high duty cycle environment, such as smart phones, tablet computers, laptop computers, and the like. Memory controller 1201 may be configured to control operations of memory 800, such as read, erase, and program operations. The memory controller 1201 may also be configured to manage various functions with respect to data stored or to be stored in the memory 800, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, and the like. In some embodiments, the memory controller 1201 is further configured to process an Error Correction Code (ECC) with respect to data read from the memory 800 or written to the memory 800. The memory controller 1201 may also perform any other suitable functions, such as formatting the memory 800. The memory controller 1201 may communicate with external devices (e.g., host 1308) according to a particular communication protocol. For example, the memory controller 1201 may communicate with the external device via at least one of various Interface protocols, such as a USB protocol, an MMC protocol, a Peripheral Component Interconnect (PCI) protocol, a PCI Express (PCI-E, PCI Express) protocol, an Advanced Technology Attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a Small Computer System Interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI), an Integrated Drive Electronics (Integrated Drive Electronics) protocol, a Firewire protocol, and so forth. The memory controller 1201 and the one or more memories 800 may be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). That is, the storage system 1200 may be implemented and packaged into different types of end electronic products. In one example as shown in FIG. 14, a memory controller 1201 and a single memory 800 may be integrated into a memory card 1402. The memory card may include a PC card (PCMCIA), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, and the like. The memory card may also include a memory card connector 1404 that couples the memory card with a host (e.g., host 1308 in FIG. 13). In another example as shown in fig. 15, memory controller 1201 and plurality of memories 800 may be integrated into SSD 1502. The SSD may also include an SSD connector 1504 to couple the SSD with a host (e.g., host 1308 in fig. 15). In some embodiments, the storage capacity and/or operating speed of the SSD is greater than the storage capacity and/or operating speed of the memory card. In addition, the memory controller 1201 may also be configured to control erase, read, and write operations of the memory 800.
The above description is only for the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention.

Claims (16)

1. A multi-finger Metal Oxide Semiconductor (MOS) device, comprising:
a semiconductor substrate;
a substrate contact frame disposed on the semiconductor substrate;
and a plurality of single-finger MOS devices provided on a first substrate of the semiconductor substrate; the first substrate is a substrate in the space surrounded by the substrate contact frame in the semiconductor substrate; the single-finger MOS devices are uniformly arranged on the surface of the first substrate around a first blank area of the surface of the first substrate; the first blank area is located in the central area of the surface of the first substrate.
2. The MOS device of claim 1, wherein the substrate contact frame comprises a plurality of sub-contact frames; arranging a group of single-finger MOS on the surface of a second substrate in the space surrounded by each sub-contact frame in the semiconductor substrate; the single-finger MOS in each group of the single-finger MOS surrounds the second blank area of the corresponding second substrate surface and is uniformly arranged on the second substrate surface; the second blank area is located in a central area of the surface of the second substrate.
3. The MOS device of claim 2, wherein there is no overlap region between the plurality of sub-contact frames.
4. The MOS device of claim 2, wherein the total number of the groups of single-finger MOS containing single-finger MOS corresponding to the plurality of sub-contact frames is equal to the number of the groups of single-finger MOS containing single-finger MOS.
5. The MOS device of claim 2, wherein the first and second empty regions are not less than an area of the semiconductor substrate occupied by a gate oxide layer between a semiconductor drain region and a semiconductor source region in a single-finger MOS.
6. The MOS device of claim 2, wherein the plurality of single-finger MOSs and some of the single-finger MOSs in each group of the single-finger MOSs share a semiconductor drain region and a drain metal or a semiconductor source region and a source metal.
7. The MOS device of claim 2, wherein each of the plurality of sub-contact frames is connected to a low voltage pad for accessing a low voltage, wherein connection points of the sub-contact frames to the low voltage pad in the plurality of sub-contact frames are sequentially decreased from the sub-contact frame at the middle position to the sub-contact frame at the edge position.
8. The MOS device of claim 1, wherein when the semiconductor substrate is a P-type semiconductor substrate, the single-finger MOS is an N-type MOS; and when the semiconductor substrate is an N-type semiconductor substrate, the single-finger MOS is a P-type MOS.
9. An electrostatic clamp, comprising: a transient sub-circuit connected in parallel between the power supply pin and the ground pin and coupled in sequence, and the multi-finger Metal Oxide Semiconductor (MOS) device as claimed in any one of claims 1 to 8, wherein the transient sub-circuit is used for sending a driving signal with a voltage value smaller than that of the power supply to the multi-finger MOS device when static electricity is detected; the multi-finger MOS device discharges the static electricity under the driving of the driving signal.
10. The electrostatic clamp of claim 9, wherein the transient sub-circuit comprises: a capacitor and a resistor connected in series between the power pin and the ground pin; when the multi-finger MOS device is an N-type MOS, the drain electrode of the multi-finger MOS device is connected with the power pin, the source electrode of the multi-finger MOS device is connected with the grounding pin, and the grid electrode of the multi-finger MOS device is connected with the connection position of the capacitor and the resistor.
11. An integrated circuit, comprising:
a high voltage pad for accessing a power supply voltage;
a low voltage pad for accessing a ground voltage;
and the electrostatic clamp of any of claims 9 to 10; and the power pin of the electrostatic clamping circuit is electrically connected with the high-voltage bonding pad, and the grounding pin is electrically connected with the low-voltage bonding pad.
12. A method for forming a multi-finger Metal Oxide Semiconductor (MOS) device is characterized by comprising the following steps:
forming a semiconductor substrate;
forming a substrate contact frame on the surface of the semiconductor substrate;
forming a plurality of single-finger MOS on the surface of a first substrate in the space surrounded by the substrate contact frame in the semiconductor substrate; the single-finger MOS surrounds a first blank area on the surface of the first substrate and is uniformly formed on the surface of the first substrate; the first blank area is located in the central area of the surface of the first substrate.
13. The forming method according to claim 12, wherein the substrate contact frame formed on the surface of the semiconductor substrate includes a plurality of sub-contact frames;
forming a group of single-finger MOS on the surface of the second substrate in the space surrounded by each sub-contact frame in the semiconductor substrate; the single-finger MOS in each group of the single-finger MOS surrounds the second blank area of the corresponding second substrate surface and is uniformly arranged on the second substrate surface; the second blank area is located in the central area of the surface of the second substrate.
14. A memory, comprising: a storage array for storing data; and peripheral circuitry coupled to and for controlling the memory array; wherein the peripheral circuitry comprises the electrostatic clamp of any of claims 9 to 10; alternatively, the peripheral circuit comprises the integrated circuit of claim 11.
15. A storage system, comprising: one or more of the memories of claim 14;
and a memory controller coupled to the memory; the memory controller to: various operation commands are sent to the memory.
16. The storage system according to claim 15, wherein the storage system is a Solid State Disk (SSD) or a memory card.
CN202211124651.2A 2022-09-15 2022-09-15 Multi-finger MOS device, forming method and related structure Pending CN115377095A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202211124651.2A CN115377095A (en) 2022-09-15 2022-09-15 Multi-finger MOS device, forming method and related structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202211124651.2A CN115377095A (en) 2022-09-15 2022-09-15 Multi-finger MOS device, forming method and related structure

Publications (1)

Publication Number Publication Date
CN115377095A true CN115377095A (en) 2022-11-22

Family

ID=84071338

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202211124651.2A Pending CN115377095A (en) 2022-09-15 2022-09-15 Multi-finger MOS device, forming method and related structure

Country Status (1)

Country Link
CN (1) CN115377095A (en)

Similar Documents

Publication Publication Date Title
CN113196402B (en) Memory device and program operation thereof
US20240153544A1 (en) Current control circuit and discharge enable circuit for discharging bit lines of memory device and operation method thereof
CN113168879B (en) Open block based read offset compensation in read operations of memory devices
CN113421601B (en) Flash memory and operation method thereof
CN113168869B (en) Memory device and erase operation thereof
CN115377095A (en) Multi-finger MOS device, forming method and related structure
US12112802B2 (en) Memory device, the operation method thereof and memory system
US20240161827A1 (en) Memory device and operation method thereof, memory system, and operation method thereof
US20240170389A1 (en) Three-dimensional memory devices and system having the same
CN113921046B (en) Memory, reading method thereof and memory system
US11769559B2 (en) Methods of reducing program disturb by array source coupling in 3D NAND memory devices
US20240290388A1 (en) Memories, storage systems and electronic products
WO2021190448A1 (en) Memory device and program operation thereof
CN114400033A (en) Storage device and control method thereof
CN115346583A (en) Peripheral circuit for memory cell array and memory device
CN115588452A (en) Discharge circuit, discharge method, memory and storage system
CN118692541A (en) Memory operation method, memory system and electronic equipment
CN114613415A (en) Nonvolatile memory, memory system, and data erasing method of memory
CN118366522A (en) Memory device including page buffer, memory system including page buffer, and operating method thereof
CN115309337A (en) Memory operation method, memory and memory system
CN115033176A (en) Memory and operation method thereof, and memory system
CN113228186A (en) Negative gate stress operating machine memory device in multiple programming passes
CN115694171A (en) Charge pump circuit, memory and storage system
CN117999604A (en) Memory device, operation method, system and storage medium of memory device
CN114596893A (en) Memory device, memory system, and program operation method of memory device

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination