CN115033176A

CN115033176A - Memory and operation method thereof, and memory system

Info

Publication number: CN115033176A
Application number: CN202210624977.5A
Authority: CN
Inventors: 刘艳兰; 罗健
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2022-06-02
Filing date: 2022-06-02
Publication date: 2022-09-09

Abstract

The embodiment of the disclosure provides a memory, an operation method thereof and a memory system, wherein the memory comprises: a memory array and peripheral circuitry coupled with the memory array; the peripheral circuit includes: a master control unit and a slave control unit; wherein the slave control unit is configured to: receiving a first instruction; the first instruction instructs the slave control unit to enter a first state; when entering the first state, the slave control unit does not need to use a clock; turning off a clock of the slave control unit in response to the first instruction; and when the first state is determined to be finished, starting a clock of the slave control unit.

Description

Memory, operating method thereof and memory system

Technical Field

The present disclosure relates to the field of semiconductor technologies, and in particular, to a memory, an operating method thereof, and a memory system.

Background

Memory is a memory device used in modern information technology to hold information. As a typical nonvolatile semiconductor memory, a NAND (Not-And) flash memory has become a mainstream product in the storage market due to its high storage density, controllable production cost, appropriate erasing speed, And retention characteristics.

With the increasing demand for memory, how to reduce the power consumption of memory becomes one of the technical problems that needs to be solved urgently in the present stage in the field.

Disclosure of Invention

According to a first aspect of embodiments of the present disclosure, there is provided a memory, the memory including: a memory array and peripheral circuitry coupled with the memory array; the peripheral circuit includes: a master control unit and a slave control unit; wherein the slave control unit is configured to:

receiving a first instruction; the first instruction instructs the slave control unit to enter a first state; when entering the first state, the slave control unit does not need to use a clock;

turning off a clock of the slave control unit in response to the first instruction;

and when the first state is determined to be finished, starting a clock of the slave control unit.

In the above aspect, the slave control unit is configured to:

timing the first state with a clock of the master control unit;

and when the timing meets the preset duration, determining that the first state is finished.

In the above scheme, the peripheral circuit further includes: the clock generation module of the master control unit and the clock generation module of the slave control unit; the slave control unit comprises a polling module; the polling module comprises a first input port, a second input port and an output port; wherein the second input port is coupled to a clock generation module of the master control unit, and the output port is coupled to a clock generation module of the slave control unit;

the polling module is in an on state, the polling module configured to:

receiving the first instruction from the first input port;

in response to the first instruction, issuing an instruction to turn off a clock of a slave control unit from the output port to a clock generation module of the slave control unit;

and responding to the first instruction, timing the first state by using the clock of the master control unit input from the second input port, and when the timing meets the preset duration, sending an instruction for starting the clock of the slave control unit from the output port to the clock generation module of the slave control unit.

In the above solution, the polling module further includes a third input port; the master control unit comprises a polling control module coupled with a third input port of the polling module;

the polling module is configured to:

receiving an instruction of the polling control module from the third input port to control the polling module to be in an on state or an off state.

In the above scheme, the peripheral circuit further includes: a slave memory; the slave memory is coupled to the slave control unit;

the slave control unit is configured to:

in response to the first instruction, clock of the slave memory is turned off.

In the foregoing solution, the first instruction includes a wait instruction.

In the above scheme, the number of the slave control units includes one or more.

In the above scheme, the memory comprises a three-dimensional NAND-type memory.

According to a second aspect of embodiments of the present disclosure, there is provided a memory system including:

one or more memories as described in any of the above schemes; and

a memory controller coupled with and controlling the memory.

In the above scheme, the memory system includes a memory card or a solid state disk.

According to a third aspect of the embodiments of the present disclosure, there is provided an operating method of a memory, including:

receiving a first instruction; the first instruction indicates the slave control unit to enter a first state; when entering the first state, the slave control unit does not need to use a clock;

In the foregoing solution, the determining that the first state is ended includes:

timing the first state by using a clock of the main control unit;

In the foregoing solution, the receiving the first instruction includes:

a polling module receives the first instruction from a first input port;

the turning off the clock of the slave control unit in response to the first instruction includes:

the polling module responds to the first instruction and sends an instruction for closing the clock of the slave control unit from an output port to a clock generation module of the slave control unit;

when it is determined that the first state is finished, starting a clock of the slave control unit includes:

and the polling module responds to the first instruction, times the first state by using the clock of the master control unit input from the second input port, and sends an instruction for starting the clock of the slave control unit from the output port to the clock generation module of the slave control unit when the time meets the preset time length.

In the foregoing solution, the method further includes:

the polling module receives an instruction of a polling control module from a third input port so as to control the polling module to be in an on state or an off state.

In the foregoing solution, the turning off the clock of the slave control unit in response to the first instruction includes:

in response to the first instruction, clock of a slave memory coupled with the slave control unit is turned off.

In the foregoing solution, the first instruction includes a wait instruction.

The embodiment of the disclosure provides a memory, an operation method thereof and a memory system, wherein the memory comprises: a memory array and peripheral circuitry coupled with the memory array; the peripheral circuit includes: a master control unit and a slave control unit; wherein the slave control unit is configured to: receiving a first instruction; the first instruction instructs the slave control unit to enter a first state; when entering the first state, the slave control unit does not need to use a clock; turning off a clock of the slave control unit in response to the first instruction; and when the first state is determined to be finished, starting a clock of the slave control unit. In the embodiment of the disclosure, the clock of the slave control unit is turned off during the period that the clock of the slave control unit is not needed to be used, and the clock of the slave control unit is turned on again during the period that the clock of the slave control unit is needed to be used, so that certain power consumption caused by the fact that the clock of the slave control unit is in an on state when the clock of the slave control unit is not needed to be used can be avoided, and power can be saved.

Drawings

FIG. 1 is a schematic diagram of an exemplary system having a memory system according to an embodiment of the present disclosure;

FIG. 2a is a schematic diagram of an exemplary memory card with a memory system according to an embodiment of the present disclosure;

FIG. 2b is a schematic diagram of an exemplary solid state drive with a memory system according to an embodiment of the present disclosure;

FIG. 3a is a schematic diagram illustrating the distribution of memory cells in a three-dimensional NAND type memory according to one embodiment of the present disclosure;

FIG. 3b is a schematic diagram of an exemplary memory including peripheral circuitry according to one embodiment of the present disclosure;

FIG. 4 is a cross-sectional schematic diagram of a memory array including NAND memory strings, according to an embodiment of the present disclosure;

FIG. 5a is a first schematic diagram of an exemplary memory including a memory array and peripheral circuitry according to one embodiment of the present disclosure;

FIG. 5b is a second schematic diagram of an exemplary memory including a memory array and peripheral circuits according to one embodiment of the present disclosure;

FIG. 6 is a block diagram of a memory according to an embodiment of the present disclosure;

fig. 7 is a schematic flow chart illustrating an implementation of an operation method of a memory according to an embodiment of the disclosure.

Detailed Description

Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present disclosure. It will be apparent, however, to one skilled in the art, that the present disclosure may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order not to obscure the present disclosure; that is, not all features of an actual embodiment are described herein, and well-known functions and constructions are not described in detail.

In the drawings, the size of layers, regions, elements, and relative sizes may be exaggerated for clarity. Like reference numerals refer to like elements throughout.

It will be understood that when an element or layer is referred to as being "on" … …, "adjacent to … …," "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on … …," "directly adjacent to … …," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure. And the discussion of a second element, component, region, layer or section does not necessarily imply that the first element, component, region, layer or section is necessarily present in the disclosure.

Spatial relationship terms such as "under … …", "under … …", "below", "under … …", "above … …", "above", and the like, may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below … …" and "below … …" can encompass both an orientation of up and down. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

So that the manner in which the features and elements of the disclosed embodiments can be understood in detail, a more particular description of the disclosed embodiments, briefly summarized above, may be had by reference to the embodiments, some of which are illustrated in the appended drawings.

The memory in the embodiments of the present disclosure includes, but is not limited to, a three-dimensional NAND-type memory, and for the convenience of understanding, the three-dimensional NAND-type memory is taken as an example for description.

The three-dimensional NAND type memory is a main development direction in the current memory field, wherein memory cells are stacked in a direction perpendicular to a substrate, more memory cells can be formed in a smaller area, and the memory cells have larger storage capacity compared with a traditional two-dimensional memory. However, with the increasing demand for the density of the three-dimensional NAND memory, the problem of large power consumption of the memory has attracted much attention.

In order to solve one or more of the above problems, the embodiments of the present disclosure introduce a solution that may avoid unnecessary power consumption during the operation of a memory, thereby achieving an effect of saving power of the memory.

Fig. 1 illustrates a block diagram of an example system 100 with memory in accordance with some aspects of the present disclosure. System 100 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, Virtual Reality (VR) device, Augmented Reality (AR) device, or any other suitable electronic device having storage therein. As shown in fig. 1, system 100 may include a host 108 and a memory system 102, memory system 102 having one or more memories 104 and a memory controller 106. Host 108 may be a processor (e.g., a Central Processing Unit (CPU)) or a system on a chip (SoC) (e.g., an Application Processor (AP)) of an electronic device. Host 108 may be configured to send data to memory 104 or receive data from memory 104.

According to some embodiments, memory controller 106 is coupled to memory 104 and host 108, and is configured to control memory 104. Memory controller 106 may manage data stored in memory 104 and communicate with host 108. In some implementations, the memory controller 106 is designed for operation in a low duty cycle environment, such as a Secure Digital (SD) card, Compact Flash (CF) card, Universal Serial Bus (USB) flash drive, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, and so forth. In some implementations, the memory controller 106 is designed for operation in a high duty cycle environment SSD or embedded multimedia card (eMMC) that is used as a data store and enterprise storage array for mobile devices such as smart phones, tablet computers, laptop computers, and the like.

The memory controller 106 may be configured to control operations of the memory 104, such as read, erase, and program operations. The memory controller 106 may also be configured to manage various functions with respect to data stored or to be stored in the memory 104, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, and the like. In some implementations, the memory controller 106 is also configured to process Error Correction Codes (ECC) with respect to data read from the memory 104 or written to the memory 104. The memory controller 106 may also perform any other suitable functions, such as formatting the memory 104. The memory controller 106 may communicate with external devices (e.g., the host 108) according to a particular communication protocol. For example, the memory controller 106 may communicate with the external device via at least one of various interface protocols, such as a USB protocol, an MMC protocol, a Peripheral Component Interconnect (PCI) protocol, a PCI express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer system small interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, a Firewire protocol, and so forth.

The memory controller 106 and the one or more memories 104 may be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). That is, the memory system 102 may be implemented and packaged into different types of end electronic products. In one example as shown in FIG. 2a, the memory controller 106 and the single memory 104 may be integrated into a memory card 202. The memory card 202 may include a PC card (PCMCIA), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, and the like. Memory card 202 may also include a memory card connector 204 that couples memory card 202 with a host (e.g., host 108 in FIG. 1). In another example as shown in fig. 2b, the memory controller 106 and the plurality of memories 104 may be integrated into the SSD 206. SSD206 may also include SSD connector 208 that couples SSD206 with a host (e.g., host 108 in fig. 1). In some implementations, the storage capacity and/or operating speed of SSD206 is greater than the storage capacity and/or operating speed of memory card 202.

Fig. 3a is an exemplary structural diagram of a memory array of a three-dimensional NAND-type memory, which is composed of a plurality of memory cell rows staggered in parallel with gate isolation structures, as shown in fig. 3a, wherein every four memory cell rows are separated by the gate isolation structures and the upper select gate isolation structures, and each memory cell row comprises a plurality of memory cells. The gate isolation structures may include a first gate isolation structure and a second gate isolation structure, the first gate isolation structure may divide the memory array into a plurality of memory blocks (expressed in english as Block), the plurality of second gate isolation structures may divide the memory blocks into a plurality of Finger storage areas (expressed in english as Finger), and the upper selection gate isolation structure disposed in the middle of each Finger storage area may divide the Finger storage area into two parts, thereby dividing the Finger storage area into two memory slices (expressed in english as String). One memory block shown in fig. 3a contains 6 memory slices, and in practical applications, the number of memory slices in one memory block is not limited to this. The memory cells in a memory block coupled to a word line can be referred to as a Page (Page).

It should be noted that the number of rows of memory cells between the gate isolation structure and the upper select gate isolation structure shown in fig. 3a is only exemplary, and is not used to limit the number of rows of memory cells included in one finger storage area of the three-dimensional NAND-type memory in the present disclosure. In practical applications, the number of memory cell ranks contained in a finger memory area may be adjusted according to practical situations, such as 2, 4, 8, 16, etc.

Fig. 3b illustrates a schematic circuit diagram of an example memory 300 including peripheral circuitry, in accordance with some aspects of the present disclosure. Memory 300 may be an example of memory 104 in fig. 1. Memory 300 may include a memory array 301 and peripheral circuitry 302 coupled to memory array 301. The memory array 301 is illustrated as a three-dimensional NAND-type memory array in which the memory cells 306 are provided in the form of an array of NAND memory strings 308, each NAND memory string 308 extending vertically above a substrate (not shown). In some implementations, each NAND memory string 308 includes multiple memory cells 306 coupled in series and stacked vertically. Each memory cell 306 may hold a continuous analog value, e.g., a voltage or charge, that depends on the number of electrons trapped within the area of the memory cell 306. Each memory cell 306 may be a floating gate type memory cell including a floating gate transistor or a charge trapping type memory cell including a charge trapping transistor.

In some embodiments, each memory cell 306 is a Single Level Cell (SLC) that has two possible memory states and therefore can store one bit of data. For example, a first memory state "0" may correspond to a first voltage range, and a second memory state "1" may correspond to a second voltage range. In some embodiments, each memory cell 306 is a multi-level cell (MLC) capable of storing more than a single bit of data in more than four memory states. For example, MLCs may store two bits per cell, three bits per cell (also known as Triple Level Cells (TLC)), or four bits per cell (also known as Quadruple Level Cells (QLC)). Each MLC may be programmed to assume a range of possible nominal stored values. In one example, if each MLC stores two bits of data, the MLC may be programmed to assume one of three possible programming levels from the erased state by writing one of three possible nominal storage values to the cell. The fourth nominal storage value may be used for the erased state.

As shown in fig. 3b, each NAND memory string 308 may include a lower select gate (BSG)310 at its source end and an upper select gate (TSG)312 at its drain end. The BSGs 310 and TSGs 312 may be configured to activate selected NAND memory strings 308 during read and program operations. In some implementations, the sources of NAND memory strings 308 in the same memory block 304 are coupled by the same Source Line (SL)314 (e.g., a common SL). In other words, according to some embodiments, all NAND memory strings 308 in the same memory block 304 have an Array Common Source (ACS). According to some embodiments, the TSG312 of each NAND memory string 308 is coupled to a respective Bit Line (BL)316, from which bit line 316 data can be read or written via an output bus (not shown). In some implementations, each NAND memory string 308 is configured to be selected or deselected by applying a select voltage (e.g., higher than the threshold voltage of the transistor with the TSG 312) or a deselect voltage (e.g., 0V) to the corresponding TSG312 via one or more TSG lines 313 and/or by applying a select voltage (e.g., higher than the threshold voltage of the transistor with the BSG 310) or a deselect voltage (e.g., 0V) to the corresponding BSG310 via one or more BSG lines 315.

As shown in fig. 3b, the NAND memory strings 308 may be organized into a plurality of memory blocks 304, each of the plurality of memory blocks 304 may have a common source line 314 (e.g., coupled to ground). In some embodiments, each memory block 304 is the basic unit of data for an erase operation, i.e., all memory cells 306 on the same memory block 304 are erased at the same time. To erase memory cells 306 in selected memory block 304a, source line 314 coupled to selected memory block 304a and unselected memory block 304b in the same plane as selected memory block 304a may be biased with an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)). It should be appreciated that in some examples, the erase operation may be performed at a half memory block level, at a quarter memory block level, or at any suitable fractional level with any suitable number of memory blocks or memory blocks. The memory cells 306 of adjacent NAND memory strings 308 may be coupled by word lines 318, with the word lines 318 selecting which row of memory cells 306 is affected by the read and program operations. In some embodiments, each word line 318 is coupled to a page 320 of memory cells 306, the page 320 being the basic unit of data for a program operation. The size of a page 320 in bits may be related to the number of NAND memory strings 308 coupled by a word line 318 in one memory block 304. Each word line 318 may include a plurality of control gates (gate electrodes) at each memory cell 306 in a respective page 320 and a gate line coupling the control gates. In conjunction with FIG. 3a above, a page 320 includes a plurality of memory cells 306 separated by upper select gate isolation structures and gate isolation structures, the memory cells between the upper select gate isolation structures and gate isolation structures being arranged in rows of memory cells, each row of memory cells being parallel to a gate isolation structure and an upper select gate isolation structure. Where the memory cells in a memory slice sharing the same word line form a programmable (read/write) page.

Fig. 4 illustrates a cross-sectional schematic of an example memory array 301 including NAND memory strings 308, in accordance with some aspects of the present disclosure. As shown in fig. 4, the NAND memory string 308 may include a stacked structure 410, the stacked structure 410 including a plurality of gate layers 411 and a plurality of insulating layers 412 alternately stacked in sequence, and the memory string 308 vertically penetrating the gate layers 411 and the insulating layers 412. The gate layers 411 and the insulating layers 412 may be alternately stacked, and adjacent two gate layers 411 are separated by one insulating layer 412. The number of pairs of the gate layer 411 and the insulating layer 412 in the stacked structure 410 may determine the number of memory cells included in the memory array 401.

The constituent material of the gate layer 411 may include a conductive material. The conductive material includes, but is not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 411 includes a metal layer, e.g., a tungsten layer. In some embodiments, each gate layer 411 comprises a doped polysilicon layer. Each gate layer 411 may include a control gate surrounding a memory cell. The gate layer 411 at the top of the stacked structure 410 may laterally extend as an upper select gate line, the gate layer 411 at the bottom of the stacked structure 410 may laterally extend as a lower select gate line, and the gate layer 411 extending laterally between the upper and lower select gate lines may serve as a word line layer.

In some embodiments, the stacked structure 410 may be disposed on the substrate 401. The substrate 401 may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

In some embodiments, NAND memory string 308 includes a channel structure that extends vertically through stacked structure 410. In some embodiments, the channel structure includes a channel hole filled with semiconductor material(s) (e.g., as a semiconductor channel) and dielectric material(s) (e.g., as a memory film). In some embodiments, the semiconductor channel comprises silicon, e.g., polysilicon. In some embodiments, the memory film is a composite dielectric layer that includes a tunneling layer, a storage layer (also referred to as a "charge trapping/storage layer"), and a blocking layer. The channel structure may have a cylindrical shape (e.g., a pillar shape). According to some embodiments, the semiconductor channel, the tunneling layer, the storage layer, and the blocking layer are radially disposed in this order from a center of the pillar toward an outer surface of the pillar. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The memory layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide/silicon oxynitride/silicon oxide (ONO).

Referring back to fig. 3b, peripheral circuitry 302 may be coupled to memory array 301 through bit line 316, word line 318, source line 314, BSG line 315, and TSG line 313. Peripheral circuitry 302 may include any suitable analog, digital, and mixed-signal circuitry for facilitating operation of memory array 301 by applying and sensing voltage and/or current signals to and from each target memory cell 306 via bit line 316, word line 318, source line 314, BSG line 315, and TSG line 313. The peripheral circuitry 302 may include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. For example, fig. 5a shows some exemplary peripheral circuits, peripheral circuit 302 including page buffers/sense amplifiers 504, column decoders/bit line drivers 506, row decoders/word line drivers 508, voltage generators 510, control logic unit 512, registers 514, interfaces 516, and data bus 518. It should be understood that in some examples, additional peripheral circuitry not shown in fig. 5a may also be included.

The page buffer/sense amplifier 504 may be configured to read data from the memory array 301 and program (write) data to the memory array 301 according to control signals from the control logic unit 512. In one example, the page buffer/sense amplifier 504 may store a page of program data (write data) to be programmed into one page 320 of the memory array 301. In another example, the page buffer/sense amplifier 504 may perform a program verify operation to ensure that data has been properly programmed into the memory cells 306 coupled to the selected word line 318. In yet another example, page buffer/sense amplifier 504 may also sense low power signals from bit line 316 representing data bits stored in memory cells 306 and amplify small voltage swings to recognizable logic levels in a read operation. The column decoder/bit line driver 506 may be configured to be controlled by the control logic unit 512 and select one or more NAND memory strings 308 by applying bit line voltages generated from the voltage generator 510.

The row decoder/word line drivers 508 may be configured to be controlled by the control logic unit 512 and to select/deselect memory blocks 304 of the memory array 301 and to select/deselect word lines 318 of the memory blocks 304. The row decoder/word line driver 508 may also be configured to drive the word line 318 using the word line voltage generated from the voltage generator 510. In some embodiments, the row decoder/wordline driver 508 may also select/deselect and drive the BSG lines 315 and TSG lines 313. As described in detail below, the row decoder/word line driver 508 is configured to perform a programming operation on the memory cells 306 coupled to the selected word line(s) 318. The voltage generator 510 may be configured to be controlled by the control logic unit 512 and to generate a word line voltage (e.g., a read voltage, a program voltage, a pass voltage, a local voltage, a verify voltage, etc.), a bit line voltage, and a source line voltage to be supplied to the memory array 301.

In some embodiments, the program operation may include a plurality of steps, and for example, the program operation may include a bit line setting step, a program execution step, and a program recovery step. After the programming operation is carried out, a program verification operation is required to be carried out; after the program verification operation is performed, a program verification recovery operation needs to be performed. During the bit line setting step of performing the program operation, the voltage may be maintained at the ground voltage GND for unselected word lines. In the course of a program execution step of performing a program operation, a pass voltage Vpass may be applied to unselected word lines, and a program voltage Vpgm may be applied to a selected word line. Accordingly, the memory cell connected to the selected word line can be programmed. During the program recovery step of performing the program operation, the voltages applied to all the word lines may be lowered to the ground voltage GND.

In performing a program verify operation, a verify voltage Vvrf may be applied to a selected word line and a read voltage Vread may be applied to unselected word lines.

In performing the program verify recovery operation, a recovery operation of dropping the voltage to the ground voltage GND may be performed on both the unselected word lines and the selected word line.

The control logic unit 512 may be coupled to each of the peripheral circuits described above and configured to control the operation of each of the peripheral circuits. The registers 514 may be coupled to the control logic unit 512 and include a status register, a command register, and an address register for storing status information, a command operation code (OP code), and a command address for controlling the operation of each peripheral circuit. Interface 516 may be coupled to control logic unit 512 and act as a control buffer to buffer and relay control commands received from a host (not shown) to control logic unit 512, as well as to buffer and relay status information received from control logic unit 512 to the host. The interface 516 may also be coupled to the column decoder/bit line drivers 506 via a data bus 518 and act as a data I/O interface and data buffer to buffer data and relay it to or from the memory array 301.

The control logic unit 512 may include a master control unit and a slave control unit in the architecture of the three-dimensional NAND-type memory, that is, the master control unit and the slave control unit are also provided in a peripheral circuit to which the control logic unit 512 belongs. The master control unit controls a main flow of operation of each NAND chip, and the slave control unit controls a core Electrical Design Rule (EDR) waveform, an analog enable, and a Digital Analog Converter (DAC).

In controlling the use of the core electrical design rule waveform from the control unit, this is mostly done by executing wait instructions. In some electrical design rule operations, the waiting time reaches the millisecond level, just like the erase pulse, and how to reduce the power consumption becomes a problem to be solved in the semiconductor field.

Based on one or more of the above problems, an embodiment of the present disclosure provides a memory, including: a memory array and peripheral circuitry coupled with the memory array; the peripheral circuit includes: a master control unit and a slave control unit; wherein the slave control unit is configured to:

and when the end of the first state is determined, starting a clock of the slave control unit.

In some specific examples, the first instruction may be sent from the slave control unit to the slave control unit, from the memory controller to the slave control unit, or from the host directly to the slave control unit.

In some specific examples, the memory array is disposed on the same chip as the peripheral circuitry. In other specific examples, the memory array is disposed on an array chip, and the peripheral circuit is disposed on a different chip, specifically a chip implemented using Complementary Metal Oxide Semiconductor (CMOS) technology and referred to as a CMOS chip, and the array chip and the CMOS chip may be electrically coupled together using a bonding process. In some examples, a CMOS chip may be coupled with multiple array chips.

In some specific examples, the master control Unit includes a master Micro Control Unit (MCU) and the slave control Unit includes a slave micro control Unit.

FIG. 5b is a schematic diagram of an exemplary memory including a memory array and peripheral circuitry in accordance with another embodiment of the present disclosure. The master control unit and the slave control unit in fig. 5b correspond to the control logic unit 512 in fig. 5a, the master random access memory, the master read only memory, the slave random access memory, and the slave read only memory in fig. 5b correspond to the register 514 shown in fig. 5a, and the memory interface in fig. 5b corresponds to the interface 516 in fig. 5 a.

It should be noted that after entering the first state, only the clock of the slave control unit is turned off, and the power of the slave control unit is not turned off, because some functions of the slave control unit, such as accessing data in the slave memory, need to be maintained in a powered state, if the power of the slave control unit is turned off, when the slave control unit needs to be turned on, a certain time may be required to enter a required state, or a certain data loss exists, and therefore, after entering the first state, the power of the slave control unit is not turned off.

It can be understood that in the embodiment of the present disclosure, the clock of the slave control unit is turned off when the clock of the slave control unit is not needed to be used, and then turned on when the clock of the slave control unit is needed to be used, so that power can be effectively saved without affecting the operation of the slave control unit.

For how to determine that the first state ends, in some examples, the slave control unit may be utilized to determine.

In some embodiments, the slave control unit is configured to:

timing the first state using a clock of the master control unit;

Here, the preset time period may be set according to a time required for the first instruction to last. In some specific examples, the first state may be determined to end when the timing satisfies a preset duration when the timing is equal to a time that the first instruction needs to be maintained.

In some embodiments, the peripheral circuitry further comprises: the clock generation module of the master control unit and the clock generation module of the slave control unit; the slave control unit comprises a polling module; the polling module comprises a first input port, a second input port and an output port; wherein the second input port is coupled to a clock generation module of the master control unit, and the output port is coupled to a clock generation module of the slave control unit;

the polling module is in an on state, the polling module configured to:

receiving the first instruction from the first input port;

It can be understood that, in the embodiment of the present disclosure, a polling module is added in the slave control unit, and a first input port, a second input port, and an output port are set in the polling module, and interaction with the master control unit and the host is realized through these ports, so that after the slave control unit enters the first state, the clock of the slave control unit is turned off, and when the timing satisfies the preset time duration, the clock of the slave control unit is turned on.

In some embodiments, the polling module further comprises a third input port; the master control unit comprises a polling control module coupled with a third input port of the polling module;

the polling module is configured to:

and receiving an instruction of the polling control module from the third input port to control the polling module to be in an on state or an off state.

It will be appreciated that a polling control module provided in the master control unit may be used to control the on and off states of the polling module. When the user does not need to use the function of the polling module, the polling module can be in a closed state by using the polling control module arranged in the main control unit, and when the user needs to use the function of the polling module, the polling module can be in an open state by using the polling control module arranged in the main control unit. This allows for adjustment to different needs of the user.

In some embodiments, the peripheral circuitry further comprises: a slave memory; the slave memory is coupled to the slave control unit;

the slave control unit is configured to:

in response to the first instruction, clock of the slave memory is turned off.

In some specific examples, the slave memory may be part of a register as shown in fig. 5a, the register including a master memory and a slave memory, the slave memory including a slave random access memory and a slave read only memory.

It can be understood that, when entering the first state, the clock in the slave memory is not needed to be used, so that after receiving the first instruction, the clock in the slave memory can be turned off while the clock in the slave control unit is turned off, thereby avoiding a certain power consumption caused by the clock in the slave memory being in an on state during the period of not needing to be used, and further saving power.

In some embodiments, the first instruction comprises a wait instruction.

In some specific examples, the first instruction includes a longer operation by the master control unit, a clock of the slave control unit is not required to be used during the first instruction, and the first instruction includes a wait instruction, a watchdog, and is not limited thereto.

It can be understood that, when the master control unit needs to perform a long operation, and during the long operation, the clock of the slave control unit is in an idle state, if the clock of the slave control unit is always in an on state during the period of time, a large power consumption will be caused, and therefore the embodiment of the present disclosure turns off the clock of the slave control unit during the period of time, so as to save the power of the memory.

In some embodiments, the number of slave control units comprises one or more.

In some specific examples, the number of the slave control units includes a plurality, the data reading mode of the memory includes asynchronous multi-plane independent memory reading, and the peripheral circuit is configured to:

receiving a first instruction; the first instruction instructs the plurality of slave control units to enter a first state; when entering a first state, the plurality of slave control units do not need to use a clock;

turning off clocks of the plurality of slave control units in response to the first instruction;

and when the first state is determined to be finished, starting clocks of the plurality of slave control units.

In a three-dimensional NAND-type memory, one chip may include a plurality of dies that can independently perform NAND operations (e.g., read, write, and erase). Each die may include a plurality of storage planes, and each storage plane may include a plurality of memory cells stacked vertically to increase storage capacity per unit area, wherein the memory cells may be addressed from a shared word line. Asynchronous Multiple Plane Independent (AMPI) reading means that multiple memory planes in a chip can also perform Asynchronous Independent reading operation, and is an important way for accelerating random reading performance in a three-dimensional NAND-type memory, and in the Asynchronous multiple Plane Independent reading way, multiple slave control units are required for control.

It can be understood that, the embodiments of the present disclosure turn off the clock of the slave control unit when the clock of the slave control unit is not needed, and turn on the clock of the slave control unit when the clock of the slave control unit is needed, and when the data reading operation is performed in an asynchronous multi-plane independent reading manner, a plurality of slave control units are applied in the reading process, so that the power consumption of the clocks in the plurality of slave control units during the period of no need can be saved, thereby making the overall power consumption saving rate greater.

In some embodiments, the memory comprises a three-dimensional NAND-type memory.

The memory in the embodiments of the present disclosure is not limited to a three-dimensional NAND type memory. In the embodiment of the present disclosure, the Memory may be a semiconductor Memory, including but not limited to a three-dimensional NAND Flash Memory (NAND Flash Memory), a Vertical NAND Flash Memory (Vertical NAND Flash Memory), a NOR Flash Memory (NOR Flash Memory), a Dynamic Random Access Memory (DRAM), a Ferroelectric Random Access Memory (FRAM), a Magnetic Random Access Memory (MRAM), a Phase Change Random Access Memory (PCRAM), a Resistive Random Access Memory (RRAM), or a Nano Random Access Memory (NRAM).

The above embodiment is further explained with reference to fig. 6, and as shown in fig. 6, the peripheral circuit 302 includes: a master control unit 601, a slave control unit 602, a clock generation block 607 of the master control unit 601, and a clock generation block 608 of the slave control unit 602, a slave random access memory 605, and a slave read only memory 606; the slave control unit 602 comprises a polling module 603; the polling module 603 includes a first input port 611-1, a second input port 611-2, a third input port 611-3, and an output port 611-4; the master control unit 601 includes a polling control module 604.

The first input port 611-1 is configured to receive a first instruction, and specifically, may receive a signal Wait _ en from the first input port, and when the polling module 603 receives the first instruction from the first input port, the slave control unit 602 enters the first state.

The second input port 611-2 is coupled to the clock generation module 607 of the master control unit 601, and the first state is clocked by the clock of the master control unit 601 input from the second input port, specifically, the signal Slave _ mcu _ clk _ gt (Slave control unit clock signal) may be input from the second input port.

The third input port 611-3 is coupled to the polling control module 604, and receives an instruction of the polling control module 604 from the third input port 611-3, specifically, receives a signal Slave _ polling _ dis from the third input port (turns off the polling module of the Slave control unit), so as to control the polling module 603 to be in an on state, or receives a signal Slave _ polling _ en from the third input port (turns on the polling module of the Slave control unit), so as to control the polling module 603 to be in an off state.

The output port is coupled to the clock generation module of the Slave control unit 602, and after the polling module 603 receives the first instruction from the first input port, an instruction to turn off the clock of the Slave control unit 602 is sent from the output port to the clock generation module of the Slave control unit 602, specifically, a signal Slave _ mcu _ clk _ dis (turn off the clock of the Slave control unit) is sent from the output port, and when the timing satisfies the preset duration, an instruction to turn on the clock of the Slave control unit 602 is sent from the output port to the clock generation module of the Slave control unit 602, specifically, a signal Slave _ mcu _ clk _ en (turn on the clock of the Slave control unit) is sent from the output port.

The Slave ram 605 and the Slave rom 606 may turn off clocks of the Slave ram 605 and the Slave rom 606 in response to the first instruction, and particularly the Slave ram 605 and the Slave rom 606 may receive signals Slave _ ram _ clk _ dis (turn off clocks of the Slave ram) and Slave _ rom _ clk _ dis (turn off clocks of the Slave rom), so that clocks of the Slave ram 605 and the Slave rom 606 are in an off state, or signals Slave _ ram _ clk _ en (turn on clocks of the Slave ram) and Slave rom _ clk _ en (turn on clocks of the Slave rom), so that clocks of the Slave ram 605 and the Slave rom 606 are in an on state.

As can be seen from fig. 6, the peripheral circuit may further comprise a clock multiplexing control unit 610 and three clock terminals receiving source clock buffered clocks 609-1, 609-2, 609-3.

In the embodiment of the disclosure, based on the traditional use of tools, the clock gating is automatically added to save power, and the clock of the slave control unit is turned off according to the functional requirements, so that the most efficient energy saving can be realized.

The disclosed embodiment provides a memory, including: a memory array and peripheral circuitry coupled with the memory array; the peripheral circuit includes: a master control unit and a slave control unit; wherein the slave control unit is configured to: receiving a first instruction; the first instruction instructs the slave control unit to enter a first state; when entering the first state, the slave control unit does not need to use a clock; turning off a clock of the slave control unit in response to the first instruction; and when the first state is determined to be finished, starting a clock of the slave control unit. In the embodiment of the disclosure, the clock of the slave control unit is turned off during the period that the clock of the slave control unit is not needed to be used, and the clock of the slave control unit is turned on again during the period that the clock of the slave control unit is needed to be used, so that certain power consumption caused by the fact that the clock of the slave control unit is in an on state when the clock of the slave control unit is not needed to be used can be avoided, and power can be saved.

The disclosed embodiments also provide a memory system, which includes:

one or more memories as described in any of the above embodiments; and

a memory controller coupled with and controlling the memory.

Here, as to the specific structure and composition of the memory system, reference may be made to the related structure and composition of the memory system 102 in fig. 1 and fig. 2 a. For brevity, no further description is provided herein.

In some embodiments, the memory system comprises a memory card or a solid state disk.

Based on the foregoing memory, an embodiment of the present disclosure further provides an operating method of a memory, as shown in fig. 7, the method includes:

step 701: receiving a first instruction; the first instruction instructs the slave control unit to enter a first state; when entering the first state, the slave control unit does not need to use a clock;

step 702: turning off a clock of the slave control unit in response to the first instruction;

step 703: and when the first state is determined to be finished, starting a clock of the slave control unit.

In some embodiments, said determining that the first state is over comprises:

timing the first state by using a clock of the main control unit;

In some embodiments, the receiving a first instruction comprises:

a polling module receives the first instruction from a first input port;

and the polling module responds to the first instruction, clocks the first state by using the clock of the master control unit input from the second input port, and sends an instruction for starting the clock of the slave control unit from the output port to the clock generation module of the slave control unit when the clock meets the preset duration.

In some embodiments, the method further comprises:

In some embodiments, said turning off the clock of said slave control unit in response to said first instruction comprises:

in response to the first instruction, a clock of a slave memory coupled with the slave control unit is turned off.

In some embodiments, the first instruction comprises a wait instruction.

In some embodiments, the number of slave control units comprises one or more.

It should be appreciated that reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be understood that, in various embodiments of the present disclosure, the sequence numbers of the above-mentioned processes do not mean the execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The above-mentioned serial numbers of the embodiments of the present disclosure are merely for description and do not represent the merits of the embodiments.

The methods disclosed in the several method embodiments provided in this disclosure may be combined arbitrarily without conflict to arrive at new method embodiments.

The above description is only for the specific embodiments of the present disclosure, but the scope of the present disclosure is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present disclosure, and all the changes or substitutions should be covered within the scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A memory, comprising: a memory array and peripheral circuitry coupled with the memory array; the peripheral circuit includes: a master control unit and a slave control unit; wherein the slave control unit is configured to:

2. The memory according to claim 1, wherein the slave control unit is configured to:

timing the first state with a clock of the master control unit;

3. The memory of claim 2, wherein the peripheral circuitry further comprises: the clock generation module of the master control unit and the clock generation module of the slave control unit; the slave control unit comprises a polling module; the polling module comprises a first input port, a second input port and an output port; wherein the second input port is coupled to a clock generation module of the master control unit, and the output port is coupled to a clock generation module of the slave control unit;

the polling module is in an on state, the polling module configured to:

receiving the first instruction from the first input port;

4. The memory of claim 3, wherein the polling module further comprises a third input port; the master control unit comprises a polling control module coupled with a third input port of the polling module;

the polling module is configured to:

5. The memory of claim 1, wherein the peripheral circuitry further comprises: a slave memory; the slave memory is coupled to the slave control unit;

the slave control unit is configured to:

in response to the first instruction, clock of the slave memory is turned off.

6. The memory of claim 1, wherein the first instruction comprises a wait instruction.

7. The memory according to claim 1, wherein the number of slave control units comprises one or more.

8. The memory of claim 1, wherein the memory comprises a three-dimensional NAND-type memory.

9. A memory system, comprising:

one or more memories as claimed in any one of claims 1-8; and

a memory controller coupled with and controlling the memory.

10. The memory system of claim 9, wherein the memory system comprises a memory card or a solid state drive.

11. A method of operating a memory, comprising:

12. The method of operation of claim 11, wherein the determining that the first state is over comprises:

timing the first state by using a clock of the main control unit;

13. The method of operation of claim 12,

the receiving a first instruction comprises:

a polling module receives the first instruction from a first input port;

14. The method of operation of claim 13, further comprising:

15. The method of operation of claim 11,

16. The method of claim 11, wherein the first instruction comprises a wait instruction.

17. The operating method according to claim 11, wherein the number of slave control units comprises one or more.