CN115376889A - Epitaxial structure and preparation method thereof - Google Patents

Epitaxial structure and preparation method thereof Download PDF

Info

Publication number
CN115376889A
CN115376889A CN202211055872.9A CN202211055872A CN115376889A CN 115376889 A CN115376889 A CN 115376889A CN 202211055872 A CN202211055872 A CN 202211055872A CN 115376889 A CN115376889 A CN 115376889A
Authority
CN
China
Prior art keywords
layer
substrate
epitaxial
epitaxial layer
hole
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202211055872.9A
Other languages
Chinese (zh)
Inventor
邢琨
杨波
解光侠
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Zhuhai Ponawei Semiconductor Technology Co ltd
Original Assignee
Zhuhai Ponawei Semiconductor Technology Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Zhuhai Ponawei Semiconductor Technology Co ltd filed Critical Zhuhai Ponawei Semiconductor Technology Co ltd
Priority to CN202211055872.9A priority Critical patent/CN115376889A/en
Publication of CN115376889A publication Critical patent/CN115376889A/en
Priority to PCT/CN2023/115109 priority patent/WO2024046241A1/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
    • H01L21/02458—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02488—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/02502—Layer structure consisting of two layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/0254—Nitrides

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

Epitaxial structures and methods of making the same are provided. The preparation method of the epitaxial structure comprises the steps of forming a buffer layer, a mask layer, an epitaxial layer located in the first through hole and the second through hole and located on one side, away from the substrate, of the mask layer. When the epitaxial layer is positioned in the second through hole, the growth direction of the epitaxial layer is vertical to the arrangement direction of the substrate and the buffer layer, namely, the epitaxial layer is transversely extended. When the epitaxial layer is positioned in the first through hole, the growth direction of the epitaxial layer is parallel to the arrangement direction of the substrate and the buffer layer, namely longitudinal epitaxy. When the epitaxial layer is positioned on one side of the mask layer, which is far away from the substrate, the epitaxial layer grows in two arrangement directions which are parallel to and vertical to the substrate and the buffer layer simultaneously. According to the epitaxial layer manufacturing method, the mask layer with the first through hole is arranged, the second through hole communicated with the first through hole is arranged on the buffer layer, and the epitaxial layer is subjected to transverse/longitudinal/transverse epitaxy, so that the crystal defect density of the epitaxial layer is reduced, and the crystal quality of the epitaxial layer is improved.

Description

Epitaxial structure and preparation method thereof
Technical Field
The application belongs to the technical field of semiconductors, and particularly relates to an epitaxial structure and a preparation method thereof.
Background
In the semiconductor field, the crystal quality of an epitaxial structure is often one of the key indicators affecting device performance and reliability. However, the current mask method has a limited effect of improving the crystal quality, and the crystal defects which are not covered by the mask layer can extend longitudinally along the epitaxial layer until the top of the epitaxial layer. Therefore, the crystal defects not covered by the mask layer are more, which results in higher crystal defect density and lower crystal quality of the epitaxial layer.
Disclosure of Invention
In view of this, the first aspect of the present application provides a method for preparing an epitaxial structure, the method comprising:
providing a substrate;
forming a buffer layer on one side of the substrate;
epitaxially forming a mask layer on one side, away from the substrate, of the buffer layer, wherein the mask layer is provided with a plurality of first through holes formed in the epitaxial process, so that the buffer layer is exposed;
forming a plurality of second through holes penetrating through the buffer layer, exposing the substrate, and communicating the second through holes with the first through holes;
epitaxially forming an epitaxial layer which is positioned in the first through hole and the second through hole and is positioned on one side of the mask layer, which is far away from the substrate;
when the epitaxial layer is positioned in the second through hole, the growth direction of the epitaxial layer is vertical to the arrangement direction of the substrate and the buffer layer; when the epitaxial layer is positioned in the first through hole, the growth direction of the epitaxial layer is parallel to the arrangement direction of the substrate and the buffer layer; when the epitaxial layer is positioned on one side of the mask layer, which is far away from the substrate, the epitaxial layer grows in the arrangement directions parallel to and perpendicular to the substrate and the buffer layer simultaneously.
The first aspect of the present application provides a method for manufacturing an epitaxial structure, which has a simple process and high repeatability. First, a mask layer with a plurality of first through holes is formed on one side of the buffer layer, which is far away from the substrate. Subsequently, a plurality of second through holes communicating with the first through holes are formed in the buffer layer. And then, forming an epitaxial layer which is laterally extended in the second through hole, longitudinally extended in the first through hole and longitudinally extended and laterally extended outside the first through hole and the second through hole to obtain the epitaxial layer with lower crystal defect density. Wherein, the longitudinal epitaxy means that the direction of the epitaxial growth is parallel to the arrangement direction of the substrate and the buffer layer; lateral epitaxy means that the direction of epitaxial growth is perpendicular to the alignment direction of the substrate and the buffer layer.
Specifically, the buffer layer can provide a basis for forming the second through hole and subsequently forming an epitaxial layer with lower crystal defect density. The mask layer can provide a basis for forming a second via hole communicating with the first via hole. In the process of forming the epitaxial layer, the epitaxial layer is positioned in the second through hole, the first through hole and one side of the mask layer departing from the substrate, and can be subjected to epitaxial growth along the transverse direction, the longitudinal direction and the transverse direction respectively. The epitaxial layer with transverse/longitudinal/transverse epitaxy can reduce the probability of longitudinal extension of defects during epitaxial layer growth, and can also be understood as the probability of the defects penetrating through the epitaxial layer from bottom to top.
Therefore, according to the epitaxial layer manufacturing method, the mask layer with the first through hole is arranged, the second through hole communicated with the first through hole is arranged on the buffer layer, and the epitaxial layer is subjected to transverse/longitudinal/transverse epitaxy, so that the crystal defect density of the epitaxial layer is reduced, and the crystal quality of the epitaxial layer is improved.
The step of epitaxially forming an epitaxial layer located in the first through hole and the second through hole and located on the side of the mask layer departing from the substrate includes:
and the epitaxial layer in the second through hole is epitaxially grown from the side wall of the second through hole, which is close to the first through hole, along the arrangement direction vertical to the substrate and the buffer layer until the epitaxial layer is folded.
And a gap is formed between the epitaxial layer positioned in the second through hole and the bottom wall of the second through hole.
The step of epitaxially forming an epitaxial layer located in the first through hole and the second through hole and located on the side, away from the substrate, of the mask layer includes:
and the epitaxial layer positioned in the first through hole is epitaxially grown from the top surface of the epitaxial layer positioned in the second through hole along the arrangement direction parallel to the substrate and the buffer layer.
After the step of epitaxially forming an epitaxial layer located in the first through hole and the second through hole and located on the side of the mask layer departing from the substrate, the method further includes:
epitaxially forming a device function layer positioned on one side, away from the substrate, of the epitaxial layer; the device functional layer comprises at least one epitaxial layer which is stacked along the arrangement direction of the substrate and the buffer layer.
When the epitaxial layer formed in the second through hole is a III-V compound semiconductor and the epitaxial growth direction is perpendicular to the arrangement direction of the substrate and the buffer layer, the molar ratio of the group V source to the group III source satisfies the following condition: V/III is more than or equal to 500 and less than or equal to 1000, and the pressure of the reaction cavity meets the following conditions: p1 is more than or equal to 50torr and less than or equal to 100torr.
When the epitaxial layer formed in the first through hole and on the side of the mask layer, which is far away from the substrate, is a III-V compound semiconductor, and the epitaxial growth direction is parallel to the arrangement direction of the substrate and the buffer layer, the molar ratio of the V-group source to the III-group source meets the following conditions: V/III is more than 1000 and less than or equal to 3000, and the pressure of the reaction cavity meets the following conditions: p2 is more than 100torr and less than or equal to 500torr.
A second aspect of the present application provides an epitaxial structure, comprising:
a substrate;
the buffer layer is positioned on one side of the substrate, is provided with a plurality of second through holes and exposes the substrate;
the mask layer is positioned on one side, away from the substrate, of the buffer layer and is provided with a plurality of first through holes communicated with the second through holes; and
the epitaxial layer is positioned in the first through hole and the second through hole and is also positioned on one side of the mask layer, which is far away from the substrate;
when the epitaxial layer is positioned in the second through hole, the growth direction of the epitaxial layer is vertical to the arrangement direction of the substrate and the buffer layer; when the epitaxial layer is positioned in the first through hole, the growth direction of the epitaxial layer is parallel to the arrangement direction of the substrate and the buffer layer; when the epitaxial layer is positioned on one side, away from the substrate, of the mask layer, the growth direction of the epitaxial layer part is parallel to the arrangement direction of the substrate and the buffer layer, and the growth direction of the epitaxial layer part is perpendicular to the arrangement direction of the substrate and the buffer layer.
The epitaxial structure provided by the second aspect of the present application is composed of a substrate, a buffer layer, a mask layer, and an epitaxial layer. As the epitaxial layer can be epitaxially grown along the transverse direction, the longitudinal direction and the transverse direction in the second through hole, the first through hole and the side of the mask layer departing from the substrate, the probability of forming longitudinally extending crystal defects during the growth of the epitaxial layer can be reduced, so that the defect density of the epitaxial layer is reduced, and the crystal quality of the epitaxial layer is improved.
Wherein the buffer layer and the epitaxial layer comprise a homogenous material.
Wherein the dislocation density ρ of the epitaxial structure satisfies the following condition: 10 4 cm -2 ＜ρ≤10 9 cm -2 。
Drawings
In order to more clearly explain the technical solution in the embodiments of the present application, the drawings that are required to be used in the embodiments of the present application will be described below.
Fig. 1 is a process flow diagram of a method for fabricating an epitaxial structure according to an embodiment of the present disclosure.
Fig. 2 is a schematic diagram of an epitaxial structure corresponding to S200 in fig. 1.
Fig. 3 is a schematic view of an epitaxial structure corresponding to S300 in fig. 1.
Fig. 4 is a schematic diagram of an epitaxial structure corresponding to S400 in fig. 1.
Fig. 5 is a schematic view of an epitaxial structure corresponding to S500 in fig. 1.
Fig. 6 is a partially enlarged view of a portion of the epitaxial layer within the first via of fig. 5.
Fig. 7 is a partially enlarged view of a portion of the epitaxial layer in the second via of fig. 5.
Fig. 8 is a process flow diagram included in S500 in an embodiment of the present application.
Fig. 9 is a flowchart of a process included in S500 according to another embodiment of the present disclosure.
Fig. 10 is a process flow diagram of a method for fabricating an epitaxial structure in another embodiment of the present application.
Fig. 11 is a schematic view of an epitaxial structure corresponding to S600 in fig. 10.
Fig. 12 is a schematic diagram of a functional layer of the device corresponding to S600 in fig. 10.
Fig. 13 is a schematic structural diagram of an epitaxial structure according to an embodiment of the present application.
Description of reference numerals:
the structure comprises an epitaxial structure-1, a substrate-11, a buffer layer-12, a second through hole-121, a mask layer-13, a first through hole-131, an epitaxial layer-14 and a device function layer-15.
Detailed Description
The following is a preferred embodiment of the present application, and it should be noted that, for those skilled in the art, various modifications and embellishments can be made without departing from the principle of the present application, and these modifications and embellishments are also regarded as the scope of the present application.
In the semiconductor field, the crystal quality of epitaxial structures has a significant impact on device performance and reliability. At present, the method of improving the quality of the thin film crystal by adopting a mask method is a common epitaxial technical means. For example, MOCVD (Metal-organic Chemical Vapor Deposition) selective epitaxy (ELO epitaxy) based on a patterned substrate is one of the methods for improving the crystal quality and reducing the crystal defect density of group III nitrides (e.g., gaN, alN, etc.). The key mechanism is that the lateral extension of crystal materials is promoted by depending on a patterned substrate, the bending of penetrating defects is effectively realized, and the annihilation process of the defects is realized in the process of lateral combination of crystal seeds. Wherein, the crystal defect is meant to include point defect, line defect, surface defect, etc.
However, the current mask method has a limited effect on improving the quality of the crystal. This is because the crystal defects not covered by the mask layer can extend longitudinally with the epitaxial layer up to the top of the epitaxial layer. It is also understood that the penetration defects not covered by the mask layer are not masked, so that they can still penetrate the entire epitaxial layer. Therefore, the crystal defects of the parts which are not covered by the mask layer are more, and the crystal defect density of the epitaxial layer is higher, and the crystal quality is lower. Moreover, the traditional ELOG method is formed by performing micro-nano process (including silicon oxide mask deposition, a whole set of photoetching process and etching of the mask and the GaN template) and twice MOCVD epitaxy on a sapphire-based GaN template, and has the disadvantages of complicated preparation process, low repetition rate and poor uniformity in chips. Therefore, a technical method for preparing an epitaxial layer with high crystal quality, which has relatively simple process, high repeatability and good in-wafer uniformity, is needed.
In view of the above, in order to solve the above problems, the present application provides a method for fabricating an epitaxial structure. Referring to fig. 1-7 together, fig. 1 is a process flow diagram of a method for fabricating an epitaxial structure according to an embodiment of the present application. Fig. 2 is a schematic diagram of an epitaxial structure corresponding to S200 in fig. 1. Fig. 3 is a schematic view of an epitaxial structure corresponding to S300 in fig. 1. Fig. 4 is a schematic view of an epitaxial structure corresponding to S400 in fig. 1. Fig. 5 is a schematic view of an epitaxial structure corresponding to S500 in fig. 1. Fig. 6 is a partially enlarged view of a portion of an epitaxial layer within the first via of fig. 5. Fig. 7 is a partially enlarged view of a portion of the epitaxial layer in the second via of fig. 5.
It should be noted that the dimensions of the layers of the epitaxial structure in the schematic diagram of the epitaxial structure do not represent the actual dimensions of the epitaxial structure.
The present embodiment provides a method for manufacturing an epitaxial structure 1, where the method for manufacturing an epitaxial structure 1 includes S100, S200, S300, S400, and S500. The details of S100, S200, S300, S400, and S500 are as follows.
S100, a substrate 11 is provided.
The substrate 11 provided in this embodiment can provide a load bearing foundation for the preparation of other layers. The shape, material, and thickness of the substrate 11 are not limited in this application. Alternatively, the material of the substrate 11 includes, but is not limited to, sapphire, silicon, gallium nitride, gallium arsenide, aluminum nitride, indium phosphide, silicon carbide, and the like.
It should be noted that the epitaxial growth in the following of the present application includes lateral epitaxy and longitudinal epitaxy. Longitudinal epitaxy means that the direction of epitaxial growth is parallel to the arrangement direction of the substrate 11 and the buffer layer 12 (as shown by the direction D1 in fig. 2); lateral epitaxy means that the direction of epitaxial growth is perpendicular to the alignment direction of the substrate 11 and the buffer layer 12 (as shown by the direction D2 in fig. 2).
As shown in fig. 2, a buffer layer 12 is formed on one side of the substrate 11, S200.
The buffer layer 12 provided in this embodiment can provide a basis for forming the second via 121 and subsequently forming the epitaxial layer 14 having a low crystal defect density. The shape and material of the buffer layer 12 are not limited in this application. Optionally, the buffer layer 12 material is III-V. Still further alternatively, the material of the buffer layer 12 includes, but is not limited to, gaN, alN, inN, and the like. Preferably, the material of the buffer layer 12 is GaN. Optionally, the buffer layer 12 may include at least one material. The material of the buffer layer 12 includes AlN and GaN.
Optionally, the buffer layer 12 may be formed by, but not limited to, sputtering, atomic layer deposition, and/or epitaxy.
Alternatively, in the alignment direction of the substrate 11 and the buffer layer 12, the thickness d1 of the buffer layer 12 satisfies the following condition: d1 is more than or equal to 15nm and less than or equal to 3000nm. Preferably, the thickness d1 of the buffer layer 12 satisfies the following condition: d1 is more than or equal to 25nm and less than or equal to 1500nm. Still further preferably, the thickness d1 of the buffer layer 12 satisfies the following condition: d1 is more than or equal to 35nm and less than or equal to 500nm.
The substrate 11 has a growth surface on one side of which the buffer layer 12 is provided. The thickness of the buffer layer 12 may also be understood as the dimension of the buffer layer 12 perpendicular to the growth plane. A corresponding understanding can also be made with respect to the thicknesses of the layers described below.
Designing the thickness of the buffer layer 12 in the above range provides a basis for forming the second via 121 and subsequently forming the epitaxial layer 14 having a lower crystal defect density. If the thickness of the buffer layer 12 is too small, the buffer layer 12 is too thin, and the depth of the second through hole 121 is low, so that the buffer effect is not achieved, and the subsequent growth of the epitaxial layer 14 in the second through hole 121 is not facilitated. If the thickness of the buffer layer 12 is too large, the buffer layer 12 is too thick, which increases the manufacturing cost. Therefore, the optimal thickness of the buffer layer 12 is required to ensure the depth of the second through hole 121 to achieve the buffering effect, and reduce the manufacturing cost and avoid wasting material.
As shown in fig. 3, in S300, a mask layer 13 is epitaxially formed on a side of the buffer layer 12 away from the substrate 11, and the mask layer 13 has a plurality of first through holes 131 formed in the epitaxial process, so that the buffer layer 12 is exposed.
The mask layer 13 provided in this embodiment has the first through hole 131, and enables the epitaxial layer 14 to longitudinally extend in the first through hole 131, and provides a basis for forming the second through hole 121 communicating with the first through hole 131, so as to prepare for the subsequent preparation of the epitaxial layer 14 with a lower crystal defect density. The mask layer 13 may also be understood as a structure in which nano-pillar shaped holes are patterned. The shape and material of mask layer 13 are not limited in this application. Alternatively, the material of mask layer 13 includes, but is not limited to, silicon nitride, silicon oxide, silicon carbide, and the like. Preferably, the material of mask layer 13 is silicon nitride. The mask layer 13 covers at least part of the surface of the buffer layer 12 facing away from the substrate.
The mask layer 13 has a plurality of first through holes 131 formed in an epitaxial process and randomly distributed. Optionally, the size of the first via 131 is 50nm-500nm in a radial direction of the first via 131. The depth of the first via hole 131 is 0.4nm to 2.5nm in the axial direction of the first via hole 131. And, the distance between the adjacent first through holes 131 is 100nm to 200nm. The shape of the first through hole 131 includes, but is not limited to, circular, oval, near-circular, etc.
It should be noted that the first via 131 in this embodiment is formed by epitaxial growth, which further simplifies the growth process and can omit the step of etching the mask hole in the related art.
Optionally, in the arrangement direction of the substrate 11 and the buffer layer 12, the thickness d2 of the mask layer 13 satisfies the following condition: d2 is more than or equal to 0.4nm and less than or equal to 2.5nm. Preferably, the thickness d2 of the mask layer 13 satisfies the following condition: d2 is more than or equal to 0.6nm and less than or equal to 1.2nm.
Designing the thickness of the mask layer 13 to the above range ensures obtaining the mask layer 13 having the plurality of first through holes 131 in preparation for the subsequent preparation of the epitaxial layer 14. If the thickness of the mask layer 13 is too small, the mask layer 13 is too thin, and the depth of the first through hole 131 is insufficient, which is not favorable for the subsequent preparation of the epitaxial layer 14. If the thickness of the mask layer 13 is too large, the mask layer 13 becomes too thick, and the first via hole 131 cannot be formed, so that the epitaxial layer 14 cannot be prepared. Therefore, the thickness of the mask layer 13 is 0.4nm to 2.5nm, which ensures that the mask layer 13 with the plurality of first through holes 131 is obtained in preparation for the subsequent preparation of the epitaxial layer 14.
As shown in fig. 4, in S400, a plurality of second through holes 121 penetrating the buffer layer 12 are formed to expose the substrate 11, and the second through holes 121 communicate with the first through holes 131.
This embodiment has the second via hole 121 penetrating the buffer layer 12 to expose the substrate 11, and provides a basis for epitaxial growth of the epitaxial layer 14 from the second via hole 121. The present application does not limit the shape or size of the second through hole 121. Alternatively, dry etching (ICP) may be employed to form the second via 121. Further optionally, the gas used in the dry etching is Cl 2 Or Ar.
Optionally, in a radial direction of the second via hole 121, a size of the second via hole 121 is 50nm to 500nm. In the axial direction of the second via hole 121, the depth of the second via hole 121 is 15nm to 3000nm. And the distance between adjacent second through holes 121 is 100nm-500nm. The shape of the second through hole 121 includes, but is not limited to, a circle, an ellipse, a nearly circle, etc.
Optionally, the first through hole 131 and the second through hole 121 are disposed opposite to each other, and in the radial direction of the first through hole 131 and the second through hole 121, the sizes of the first through hole 131 and the second through hole 121 are equal.
In the present embodiment, the first through hole 131 and the second through hole 121 are disposed opposite to each other and have the same radial dimension, and it can also be understood that the second through hole 121 is etched from the bottom wall of the first through hole 131 and penetrates the buffer layer 12 to form a through hole exposing the substrate 11 and communicating with the first through hole 131. In other words, the first through hole 131 and the second through hole 121 have the same central axis and the same radial dimension, and the layers through which they penetrate are different. The first via 131 penetrates the mask layer 13, and the second via 121 penetrates the buffer layer 12. The arrangement of the first through hole 131 and the second through hole 121 provides enough growth space for the epitaxial layer 14 epitaxially grown from the second through hole 121 to the first through hole 131, and reduces the difficulty in the subsequent epitaxial layer 14 epitaxially grown from the second through hole 121 to the first through hole 131.
As shown in fig. 5, in S500, an epitaxial layer 14 located in the first through hole 131 and the second through hole 121 and located on a side of the mask layer 13 away from the substrate 11 is epitaxially formed;
as shown in fig. 6 and 7, when the epitaxial layer 14 is located in the second via hole 121, the growth direction of the epitaxial layer 14 is perpendicular to the arrangement direction of the substrate 11 and the buffer layer 12 (as shown by the direction D2 in fig. 7); when the epitaxial layer 14 is located in the first via 131, the growth direction of the epitaxial layer 14 is parallel to the alignment direction of the substrate 11 and the buffer layer 12 (as shown in the direction D1 in fig. 6); when the epitaxial layer 14 is located on the side of the mask layer 13 departing from the substrate 11, the epitaxial layer 14 grows in the direction parallel and perpendicular to the arrangement direction of the substrate 11 and the buffer layer 12.
The epitaxial layer 14 provided in this embodiment can reduce the probability of forming longitudinally extending defects by laterally extending in the second through hole 121, then longitudinally extending in the first through hole 131, and then longitudinally extending and laterally extending outside the first through hole 131 and the second through hole 121, so as to reduce the crystal defect density of the epitaxial layer 14 and improve the crystal quality of the epitaxial layer 14. The shape, material, and thickness of epitaxial layer 14 are not limited in this application. Alternatively, the thickness of epitaxial layer 14 can be based on device structure design requirements. Alternatively, epitaxial layer 14 includes, but is not limited to, silicon germanium, and compound semiconductors including, but not limited to, gaN, alN, inN, and the like. Preferably, the material of epitaxial layer 14 is GaN.
In one embodiment, the buffer layer 12 and the epitaxial layer 14 are made of a homogeneous material, which is better compatible with each other, and further improves the crystal quality of the epitaxial layer 14.
Optionally, in the alignment direction of the substrate 11 and the buffer layer 12, the thickness d3 of the epitaxial layer 14 satisfies the following condition: d3 is more than or equal to 0.3 mu m and less than or equal to 10 mu m. Preferably, the thickness d3 of the epitaxial layer 14 satisfies the following condition: d3 is more than or equal to 0.5 mu m and less than or equal to 5 mu m. The epitaxial layer 14 is formed to have a thickness from above the mask layer 13.
Designing the thickness of the epitaxial layer 14 to be within the above range not only ensures obtaining of the epitaxial layer 14 with low crystal defect density and high crystal quality, but also reduces the manufacturing cost. If the thickness of the epitaxial layer 14 is too small, the epitaxial layer 14 becomes too thin, which is not favorable for reducing the defect density of the epitaxial structure 1 and improving the crystal quality of the epitaxial layer 14. If the thickness of the epitaxial layer 14 is too large, the epitaxial layer 14 will be too thick, which increases the manufacturing cost. Therefore, the thickness of the epitaxial layer 14 is not more than 1 μm, which not only ensures the epitaxial layer 14 with low defect density and high crystal quality, but also reduces the manufacturing cost and avoids wasting materials.
Alternatively, metal Organic Chemical Vapor Deposition (MOCVD) may be employed to form the buffer layer 12 and/or the mask layer 13, the epitaxial layer 14.
The present embodiment provides a method for manufacturing an epitaxial structure 1, which is simple in process and includes first forming a mask layer 13 having a plurality of first through holes 131 on one side of a buffer layer 12. Subsequently, a plurality of second through holes 121 communicating with the first through holes 131 are formed in the buffer layer 12. Then, the epitaxial layer 14 is formed by laterally extending in the second via hole 121, longitudinally extending in the first via hole 131, and longitudinally and laterally extending outside the first via hole 131 and the second via hole 121, so as to obtain the epitaxial layer 14 with lower crystal defect density. It can also be understood that the epitaxial layer 14 grows laterally from the second via 121 until closed; then longitudinally grow in the first through hole 131 and simultaneously grow laterally and longitudinally outside the first through hole 131 and the second through hole 121 until they are connected to each other and finally closed, and a smooth and flat surface is achieved.
Specifically, in the process of forming the epitaxial layer 14, the epitaxial layer 14 can be epitaxially grown in the second via hole 121, in the first via hole 131, and on one side of the mask layer 13 in the lateral, vertical, and lateral directions, respectively. The laterally/longitudinally/laterally epitaxial layer 14 can reduce the probability of formation of longitudinally extending defects during growth of the epitaxial layer 14, and can also be understood as reducing the probability of defects penetrating the epitaxial layer 14 from bottom to top.
Therefore, in the present embodiment, by providing the mask layer 13 having the first through hole 131 and providing the second through hole 121 communicating with the first through hole 131 in the buffer layer 12, the epitaxial layer 14 is laterally/longitudinally/laterally extended, so that the crystal defect density of the epitaxial layer 14 is reduced and the crystal quality of the epitaxial layer 14 is improved.
Compared with the conventional MOCVD selective epitaxy (ELOG epitaxy) method for preparing the epitaxial structure 1, the preparation method of the epitaxial structure 1 provided by the embodiment simplifies the preparation process and reduces the preparation steps; the method has high repeatability, while the traditional method has complex process and low repeatability; and the epitaxial structure 1 prepared using the present embodiment has high uniformity. Therefore, the preparation method in this embodiment can not only prepare the epitaxial layer 14 with low crystal defect density and high crystal quality, but also simplify the preparation process and improve the repeatability and uniformity of the epitaxial structure 1 product.
Referring to fig. 7 and 8 together, fig. 8 is a process flow diagram included in S500 according to an embodiment of the present disclosure. S500, the step of epitaxially forming the epitaxial layer 14 located in the first through hole 131 and the second through hole 121 and located on a side of the mask layer 13 away from the substrate 11 includes:
s510, the epitaxial layer 14 in the second via hole 121 is epitaxially grown from the sidewall of the second via hole 121 close to the first via hole 131 along a direction perpendicular to the arrangement direction of the substrate 11 and the buffer layer 12 until being folded.
In this embodiment, the second via hole 121 penetrates the buffer layer 12 layer to expose the substrate 11, in other words, the sidewall of the second via hole 121 is the exposed buffer layer 12, and the bottom wall of the second via hole 121 is the exposed substrate 11. Therefore, the epitaxial layer 14 in the second via hole 121 can be epitaxially grown from the second via hole 121 near the sidewall of the first via hole 131, i.e., the buffer layer 12 exposed in the second via hole 121. It is also understood that the second via hole 121 has a certain depth compared to the first via hole 131, the epitaxial layer 14 located at the second via hole 121 is epitaxially grown from the sidewall in a direction perpendicular to the sidewall, and then the epitaxial layer 14 epitaxially grown from the sidewall is closed and then fills the second via hole 121.
Moreover, the growth direction of the epitaxial layer 14 in the second through hole 121 is perpendicular to the arrangement direction of the substrate 11 and the buffer layer 12, that is, the epitaxial layer 14 in the second through hole 121 is laterally extended, so that the probability that crystal defects penetrate through the epitaxial layer 14 from bottom to top is reduced, the crystal defect density of the epitaxial layer 14 is reduced, and the crystal quality of the epitaxial layer 14 is improved.
As shown in fig. 7, the surface of epitaxial layer 14 on the side close to substrate 11 in second via hole 121 is a convex surface that is convex in the direction away from substrate 11.
Referring to fig. 5 again, in one embodiment, the epitaxial layer 14 in the second via 121 has a gap from the bottom wall of the second via 121.
In this embodiment, the epitaxial layer 14 located in the second via hole 121 has a gap from the bottom wall of the second via hole 121, but it can also be understood that the epitaxial layer 14 located in the second via hole 121 has a gap from the substrate 11. Because the gap is formed between the epitaxial layer 14 and the substrate 11, the stress caused by lattice mismatch between the epitaxial layer 14 and the substrate 11 can be reduced, so that the cracking probability of the epitaxial structure 1 is reduced, and the reliability of the epitaxial structure 1 is improved.
Referring to fig. 6 and 9 together, fig. 9 is a flowchart of a process included in S500 according to another embodiment of the present disclosure. S500, the step of epitaxially forming the epitaxial layer 14 located in the first through hole 131 and the second through hole 121 and located on a side of the mask layer 13 away from the substrate 11 includes:
s520, the epitaxial layer 14 in the first via 131 is epitaxially grown from the top surface of the epitaxial layer 14 in the second via 121 along a direction parallel to the arrangement direction of the substrate 11 and the buffer layer 12.
In this embodiment, the first through hole 131 penetrates the mask layer 13 to expose the buffer layer 12, in other words, the sidewall of the first through hole 131 is the exposed mask layer 13, and the bottom of the first through hole 131 is communicated with the second through hole 121. Therefore, when the epitaxial layer 14 in the second via 121 is folded and epitaxially grown to the bottom of the first via 131, the epitaxial layer 14 in the first via 131 is epitaxially formed. The epitaxial growth of the epitaxial layer 14 in the first via 131 is performed from the top surface of the epitaxial layer 14 in the second via 121, and it can also be understood that the epitaxial growth is performed from the surface of the epitaxial layer 14 in the second via 121 exposed to the first via 131. Or it can be understood that, since the hole depth of the first via 131 is small, the epitaxial layer 14 located in the first via 131 is epitaxially grown directly from the top surface of the epitaxial layer located in the second via in a direction perpendicular to the top surface.
Moreover, the growth direction of the epitaxial layer 14 in the first through hole 131 is parallel to the arrangement direction of the substrate 11 and the buffer layer 12, that is, the epitaxial layer 14 in the first through hole 131 performs longitudinal epitaxy to match the epitaxial layer 14 in the second through hole 121, so as to reduce the probability that crystal defects penetrate through the epitaxial layer 14 from bottom to top, thereby reducing the crystal defect density of the epitaxial layer 14 and further improving the crystal quality of the epitaxial layer 14.
Referring to fig. 10-12 together, fig. 10 is a process flow chart of a method for fabricating an epitaxial structure according to another embodiment of the present application. Fig. 11 is a schematic diagram of an epitaxial structure corresponding to S600 in fig. 10. Fig. 12 is a schematic diagram of a functional layer of the device corresponding to S600 in fig. 10.
S500, after the step of epitaxially forming the epitaxial layer 14 located in the first through hole 131 and the second through hole 121 and located on the side of the mask layer 13 away from the substrate 11, the method further includes:
as shown in fig. 11 and 12, a device function layer 15 located on a side of the epitaxial layer 14 away from the substrate 11 is epitaxially formed S600; wherein the device function layer 15 includes at least one epitaxial layer 14 stacked along the arrangement direction of the substrate 11 and the buffer layer 12.
The device function layer 15 provided in this embodiment can perform various functions such as an optical waveguide, an edge-emitting laser, a power device, and the like in cooperation with the epitaxial layer 14. The shape, material, and thickness of the device functional layer 15 are not limited in this application. Alternatively, the material of the device functional layer 15 includes, but is not limited to, gaN, alN, inN, and the like.
Optionally, the device functional layer 15 is disposed on a side of the epitaxial layer 14 facing away from the substrate 11; or the device functional layer 15 is arranged in a partial region of the epitaxial layer 14 on the side facing away from the substrate 11.
In this embodiment, the device functional layer 15 is provided on at least a part of the surface of the epitaxial layer 14 on the side facing away from the substrate 11. It can also be understood that the device function layer 15 can be disposed on one side surface of the epitaxial layer 14 or a specific region of one side surface of the epitaxial layer 14 according to device requirements, so as to match with other devices, and improve applicability and integration of the device function layer 15.
Alternatively, metal Organic Chemical Vapor Deposition (MOCVD) may be employed to form the device functional layers 15, the epitaxial layers 14.
Since the device functional layer 15 may include one or more epitaxial layers 14, the crystal defect density of the device functional layer 15 may be reduced, thereby improving the crystal quality of the device functional layer 15. The epitaxial layer 14 has been described in detail above and will not be described in detail here. In fig. 12, only the epitaxial layer 14 is illustrated, and the other layers forming the epitaxial layer 14 are illustrated. Such as buffer layer 12, mask layer 13, etc., are not illustrated. The epitaxial layer 14 in the device functional layer 15 is also epitaxially grown in the lateral, longitudinal, and lateral directions, and thus has a low crystal defect density.
In one embodiment, when the epitaxial layer 14 formed in the second via 121 is a III-V compound semiconductor and the epitaxial growth direction is perpendicular to the alignment direction of the substrate 11 and the buffer layer 12, the molar ratio of the group V source to the group III source satisfies the following condition: V/III is more than or equal to 500 and less than or equal to 1000, and the pressure of the reaction cavity meets the following conditions: p1 is more than or equal to 50torr and less than or equal to 100torr.
In this embodiment, the epitaxial growth is performed under the conditions of a V/III ratio of 500to 1000 and a reaction chamber pressure of 50to 100torr, so that the lateral epitaxy can be promoted and the crystal quality of the epitaxial layer 14 can be improved.
In one embodiment, when the epitaxial layer 14 formed in the first via 131 and on the side of the mask layer 13 away from the substrate 11 is a III-V compound semiconductor and the epitaxial growth direction is parallel to the alignment direction of the substrate 11 and the buffer layer 12, the molar ratio of the group V source to the group III source satisfies the following condition: V/III is more than 1000 and less than or equal to 3000, and the pressure of the reaction cavity meets the following conditions: p2 is more than 100torr and less than or equal to 500torr.
In this embodiment, the epitaxial growth is performed under the conditions that the V/III ratio is 1000 to 3000 and the pressure of the reaction chamber is 100to 500torr, and the direction of the epitaxial growth of each layer is accelerated to be parallel to the arrangement direction of the substrate 11 and the buffer layer 12, thereby accelerating the growth rate.
In the present embodiment, the growth of the epitaxial layer 14 in a specific direction is promoted by adjusting the molar ratio of the group V source to the group iii source and the reaction chamber pressure. However, even if the molar ratio of the group V source to the group iii source and the reaction chamber pressure are outside the range of the present embodiment, the growth direction of the epitaxial layer 14 provided in the second via hole 121 is perpendicular to the arrangement direction of the substrate 11 and the buffer layer 12, and the growth direction of the epitaxial layer 14 provided in the first via hole 131 and on the side of the mask layer 13 away from the substrate 11 is parallel to the arrangement direction of the substrate 11 and the buffer layer 12.
In addition to the above-provided method for manufacturing the epitaxial structure 1, the present application also provides an epitaxial structure 1. The preparation method of the epitaxial structure 1 and the epitaxial structure 1 provided in the embodiment of the present application can achieve the technical effects of the present application, and both can be used together or separately, and the present application is not particularly limited thereto. For example, as an embodiment, the epitaxial structure 1 below may be prepared using the above preparation method of the epitaxial structure 1.
Referring to fig. 13, fig. 13 is a schematic structural diagram of an epitaxial structure according to an embodiment of the present application. The present application further provides an epitaxial structure 1 including a substrate 11, a buffer layer 12, a mask layer 13, and an epitaxial layer 14. The buffer layer 12 is located on one side of the substrate 11, and the buffer layer 12 is provided with a plurality of second through holes 121 and exposes the substrate 11. The mask layer 13 is located on a side of the buffer layer 12 away from the substrate 11, and the mask layer 13 has a plurality of first through holes 131 communicated with the second through holes 121. The epitaxial layer 14 is located in the first through hole 131 and the second through hole 121, and is also located on a side of the mask layer 13 away from the substrate 11.
When the epitaxial layer 14 is located in the second via 121, the growth direction of the epitaxial layer 14 is perpendicular to the arrangement direction of the substrate 11 and the buffer layer 12; when the epitaxial layer 14 is located in the first through hole 131, the growth direction of the epitaxial layer 14 is parallel to the arrangement direction of the substrate 11 and the buffer layer 12; when the epitaxial layer 14 is located on the side of the mask layer 13 departing from the substrate 11, the growth direction of part of the epitaxial layer 14 is parallel to the arrangement direction of the substrate 11 and the buffer layer 12, and the growth direction of part of the epitaxial layer 14 is perpendicular to the arrangement direction of the substrate 11 and the buffer layer 12. In other words, the epitaxial layer 14 is capable of simultaneous lateral growth and longitudinal growth.
The substrate 11, the buffer layer 12, the mask layer 13, and the epitaxial layer 14 are described in detail above, and will not be described herein again.
The epitaxial structure 1 in this embodiment is composed of a substrate 11, a mask layer 13, a buffer layer 12, and an epitaxial layer 14. In the epitaxial structure 1, the epitaxial layer 14 can be epitaxially grown in the second through hole 121, in the first through hole 131, and on one side of the mask layer 13 along the horizontal direction, the vertical direction, and the horizontal direction, so that the probability of forming a longitudinally extending defect during the growth of the epitaxial layer 14 can be reduced, the defect density of the epitaxial layer 14 is reduced, and the crystal quality of the epitaxial layer 14 is improved.
In one embodiment, the dislocation density ρ of the epitaxial structure 1 satisfies the following condition: 10 4 cm -2 ＜ρ≤10 9 cm -2 。
In one embodiment, a surface of the epitaxial layer 14 facing away from the substrate 11 is a polar surface, a semi-polar surface, or a non-polar surface. Preferably, a surface of the epitaxial layer 14 facing away from the substrate 11 is a semipolar surface.
According to the device design, the applicability of the epitaxial structure 1 can be improved by changing the polarity of the surface of the epitaxial layer 14 on the side away from the substrate 11, and the application range of the epitaxial structure 1 can be increased.
The foregoing detailed description has provided for the embodiments of the present application, and the principles and embodiments of the present application have been presented herein for purposes of illustration and description only and to facilitate understanding of the methods and their core concepts; meanwhile, for a person skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.

Claims (10)

1. A method for preparing an epitaxial structure, the method comprising:
providing a substrate;
forming a buffer layer on one side of the substrate;
epitaxially forming a mask layer on one side, away from the substrate, of the buffer layer, wherein the mask layer is provided with a plurality of first through holes formed in the epitaxial process, so that the buffer layer is exposed;
forming a plurality of second through holes penetrating through the buffer layer, exposing the substrate, and communicating the second through holes with the first through holes;
epitaxially forming an epitaxial layer which is positioned in the first through hole and the second through hole and is positioned on one side of the mask layer, which is far away from the substrate;
when the epitaxial layer is positioned in the second through hole, the growth direction of the epitaxial layer is vertical to the arrangement direction of the substrate and the buffer layer; when the epitaxial layer is positioned in the first through hole, the growth direction of the epitaxial layer is parallel to the arrangement direction of the substrate and the buffer layer; when the epitaxial layer is positioned on one side of the mask layer, which is far away from the substrate, the epitaxial layer grows in the arrangement directions which are parallel to and perpendicular to the substrate and the buffer layer at the same time.
2. The method for preparing an epitaxial structure according to claim 1, wherein the step of epitaxially forming an epitaxial layer in the first and second via holes and on a side of the mask layer away from the substrate comprises:
and the epitaxial layer in the second through hole is epitaxially grown from the side wall of the second through hole close to the first through hole along the arrangement direction vertical to the substrate and the buffer layer until the epitaxial layer is folded.
3. The method of claim 2, wherein the epitaxial layer in the second via has a gap from a bottom wall of the second via.
4. The method of claim 2, wherein the step of epitaxially forming an epitaxial layer in the first and second vias and on a side of the mask layer facing away from the substrate comprises:
and the epitaxial layer positioned in the first through hole is epitaxially grown from the top surface of the epitaxial layer positioned in the second through hole along the arrangement direction parallel to the substrate and the buffer layer.
5. The method of fabricating an epitaxial structure according to claim 1, wherein after the step of epitaxially forming an epitaxial layer in the first via and the second via and on a side of the mask layer facing away from the substrate, further comprising:
epitaxially forming a device function layer on one side, away from the substrate, of the epitaxial layer; the device functional layer comprises at least one epitaxial layer which is stacked along the arrangement direction of the substrate and the buffer layer.
6. The method of fabricating an epitaxial structure according to any one of claims 1 to 4 wherein when the epitaxial layer formed in the second via is a group III-V compound semiconductor and the epitaxial growth direction is perpendicular to the alignment direction of the substrate and the buffer layer, the molar ratio of group V source to group III source satisfies the following condition: V/III is more than or equal to 500 and less than or equal to 1000, and the pressure of the reaction cavity meets the following conditions: p1 is more than or equal to 50torr and less than or equal to 100torr.
7. The method according to any of claims 1 to 4, wherein when the epitaxial layer formed in the first via and on the side of the mask layer facing away from the substrate is a group III-V compound semiconductor and the epitaxial growth direction is parallel to the arrangement direction of the substrate and the buffer layer, the molar ratio of the group V source to the group III source satisfies the following condition: V/III is more than 1000 and less than or equal to 3000, and the pressure of the reaction cavity meets the following conditions: p2 is more than 100torr and less than or equal to 500torr.
8. An epitaxial structure, comprising:
a substrate;
the buffer layer is positioned on one side of the substrate, is provided with a plurality of second through holes and exposes the substrate;
the mask layer is positioned on one side, away from the substrate, of the buffer layer and is provided with a plurality of first through holes communicated with the second through holes; and
the epitaxial layer is positioned in the first through hole and the second through hole and is also positioned on one side of the mask layer, which deviates from the substrate;
when the epitaxial layer is positioned in the second through hole, the growth direction of the epitaxial layer is vertical to the arrangement direction of the substrate and the buffer layer; when the epitaxial layer is positioned in the first through hole, the growth direction of the epitaxial layer is parallel to the arrangement direction of the substrate and the buffer layer; when the epitaxial layer is positioned on the side, away from the substrate, of the mask layer, the growth direction of the epitaxial layer part is parallel to the arrangement direction of the substrate and the buffer layer, and the growth direction of the epitaxial layer part is perpendicular to the arrangement direction of the substrate and the buffer layer.
9. The epitaxial structure of claim 8, wherein the buffer layer and the epitaxial layer comprise a homogenous material.
10. The epitaxial structure of any one of claims 8 to 9, wherein the dislocation density p of the epitaxial structure satisfies the following condition: 10 4 cm -2 ＜ρ≤10 9 cm -2 。
CN202211055872.9A 2022-08-31 2022-08-31 Epitaxial structure and preparation method thereof Pending CN115376889A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN202211055872.9A CN115376889A (en) 2022-08-31 2022-08-31 Epitaxial structure and preparation method thereof
PCT/CN2023/115109 WO2024046241A1 (en) 2022-08-31 2023-08-26 Epitaxial structure and preparation method therefor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202211055872.9A CN115376889A (en) 2022-08-31 2022-08-31 Epitaxial structure and preparation method thereof

Publications (1)

Publication Number Publication Date
CN115376889A true CN115376889A (en) 2022-11-22

Family

ID=84069097

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202211055872.9A Pending CN115376889A (en) 2022-08-31 2022-08-31 Epitaxial structure and preparation method thereof

Country Status (2)

Country Link
CN (1) CN115376889A (en)
WO (1) WO2024046241A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024046241A1 (en) * 2022-08-31 2024-03-07 珠海庞纳微半导体科技有限公司 Epitaxial structure and preparation method therefor

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102427100A (en) * 2011-11-11 2012-04-25 郭磊 Semiconductor structure and forming method thereof
GB201507665D0 (en) * 2015-05-05 2015-06-17 Seren Photonics Ltd Semiconductor templates and fabrication methods
CN106960781A (en) * 2017-03-28 2017-07-18 刘志斌 A kind of gallium nitride film and preparation method thereof and graphene film and preparation method thereof
WO2021226839A1 (en) * 2020-05-12 2021-11-18 苏州晶湛半导体有限公司 Group iii nitride structure and manufacturing method therefor
CN115376889A (en) * 2022-08-31 2022-11-22 珠海庞纳微半导体科技有限公司 Epitaxial structure and preparation method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024046241A1 (en) * 2022-08-31 2024-03-07 珠海庞纳微半导体科技有限公司 Epitaxial structure and preparation method therefor

Also Published As

Publication number Publication date
WO2024046241A1 (en) 2024-03-07

Similar Documents

Publication Publication Date Title
JP4410972B2 (en) Method for manufacturing gallium nitride semiconductor layer
JP5117588B2 (en) Method for manufacturing nitride semiconductor crystal layer
US8129210B2 (en) Manufacturing method of microstructure
US7442999B2 (en) Semiconductor substrate, substrate for semiconductor crystal growth, semiconductor device, optical semiconductor device, and manufacturing method thereof
JP5627649B2 (en) Method for manufacturing nitride semiconductor crystal layer
US7339205B2 (en) Gallium nitride materials and methods associated with the same
US7687378B2 (en) Fabricating method of nitride semiconductor substrate and composite material substrate
KR101300069B1 (en) Nitride semiconductor layer-containing structure, nitride semiconductor layer-containing composite substrate and production methods of these
US8723296B2 (en) Stress compensation for large area gallium nitride or other nitride-based structures on semiconductor substrates
EP1583139A1 (en) Method for depositing a group III-nitride material on a silicon substrate and device therefor
WO2024046241A1 (en) Epitaxial structure and preparation method therefor
EP1059661A2 (en) Crack-free epitaxial semiconductor layer formed by lateral growth
KR20180088878A (en) Method for obtaining a semi-polar nitride layer on a crystalline substrate
CN218677040U (en) Epitaxial wafer
JPH07254561A (en) Pattern hetero epitaxial growth method and device
KR100773559B1 (en) Semiconductor device and method of fabricating the same
US20230053953A1 (en) Group iii nitride structures and manufacturing methods thereof
US7132351B2 (en) Method of fabricating a compound semiconductor layer
WO2022217542A1 (en) Semiconductor structure and manufacturing method therefor
JP4285928B2 (en) Method for forming semiconductor layer
WO2022194199A1 (en) Epitaxial structure of semiconductor device, preparation method therefor, and semiconductor device
US20240154059A1 (en) Method of controlling bow in a semiconductor structure, semiconductor structure, and semiconductor device
WO2021248693A1 (en) Semiconductor structure and preparation method therefor
WO2021237528A1 (en) Group iii nitride structure and preparation method therefor
US20220254633A1 (en) Semiconductor Layered Structure

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination