CN115374736A - Method for generating discrete loaded simulation memory model by converting binary file - Google Patents

Abstract

The invention discloses a method for generating a discrete loaded simulation memory model by converting a binary file, which extracts SREC file information and converts the SREC file information into HEX files of a plurality of VHX memory models, and specifically comprises the following steps: s1: linking an executable file of a system program into a loaded form; s2: converting the executable file in the loaded form into an SREC hexadecimal format file; s3: analyzing the SREC hexadecimal format file, extracting the type, the base address and the length of each segment of information, and converting the SREC hexadecimal format file into a hexadecimal format file of a VHX memory; s4: during chip simulation, the hexadecimal format file of the VHX memory is analyzed through a script, and the VHX memory is split and loaded into different memory simulation model files according to different loading addresses of different segments.

Description

Method for generating discrete loaded simulation memory model by converting binary file

Technical Field

The invention relates to the technical field of chip simulation, in particular to a method for generating a discrete loaded simulation memory model by converting a binary file, and more particularly to a method for generating a discrete loaded simulation memory model by converting a Motorola srec format binary file.

Background

The system program of the CPU chip needs to provide a self-loading flow loaded from the ROM to the RAM, and the loading process can be omitted by directly loading the symbol table of the executable file into the memory model in chip simulation so as to accelerate the chip simulation process.

The system test case of the chip is generally represented as a binary program and is linked into a text/. Roda/. Data/. Bss section according to the specification. Wherein the text field places code, the data field places read-only data, the data field places initialized data, and the bss field places uninitialized data. Since the system program of the chip does not include other programs executed before, it is necessary to provide a self-loading function to load the program into the corresponding CPU address space according to the linked segment space. Generally, a read-only ROM and a read-write RAM are required for executing a system program. In a non-simulated chip real operating environment, a system program is preset in a ROM by default (because RAM is a volatile storage medium, and therefore cannot be put in the RAM in advance), a self-loading process of the system program loads a readable and writable segment (data/. Bss segment) into the RAM, and sometimes even copies a read-only segment (text/. Data segment) into the RAM for execution. Since the loading process is a process of copying data from the ROM to the RAM, which takes a long time, an accelerated method is used to remove this process in chip simulation. The existing chip simulation generally adopts the following schemes:

1) All data are converted into a hexadecimal HEX format file which can be used by chip simulation in advance by using a RAM model, the HEX file (also called as a VHX hexadecimal format file, which is referred to as VHX format description below) is loaded into the RAM model through a readmemh function backgate of a Register Transfer Level (RTL), and a test program stored in the RAM model is executed by providing a RAM starting mode during simulation. The scheme can skip the self-loading process when the system program executes because the system program is loaded in advance. However, the text/rodata section in the file loaded in advance also occupies the space of the RAM, and the method cannot be used for simulating the scenes with small RAM designed at the limit of some chips. In addition, in the method, the program of the real scene is actually modified, the function of the executive program in the ROM cannot be tested during simulation, and certain test missing risks exist.

The VHX is a simulation memory model file dedicated for verilog, and can be loaded into a verilog memory model by a verilog system function $ readmemX, please refer to the following example of the VHX format file:

compared with the common HEX file, the VHX format file has an "@ offset" mark, and indicates an offset address of the memory model where a subsequent section of hexadecimally expressed data is located, so that discrete data content can be expressed by using a plurality of "@ offsets".

2) Data segments are not used as much as possible, and data is only manipulated within registers and on the stack. The technical scheme has the disadvantages that the test case is not a program of a real scene, the test case with strong functions can not be written for simulation, and the executed program only uses a part of functions of the CPU chip, so that the Bug of the CPU chip can not be completely detected in the simulation in many times, and the risk of missing the Bug exists.

Therefore, there is a need in the art for a method that can not only omit the loading process but also save the RAM overhead during simulation, but also can use a program in a real scene for testing.

Disclosure of Invention

In order to solve the problems, the invention provides a method for generating a discrete loaded simulation memory model by converting a binary file, and the method is characterized in that a discrete backdoor loading scheme is adopted, namely an off-line loader is realized, the binary program is divided into a ROM model and an RAM model, and the binary program can be directly loaded into the memory model without analyzing a symbol table, so that the loading process is omitted during simulation, the RAM expense is saved, and a program in a real scene can be used for simulation test.

In order to achieve the above object, the present invention provides a method for generating a discrete loaded emulated memory model by converting a binary file, which extracts SREC file information and converts the SREC file information into HEX files of multiple VHX memory models, specifically comprising:

step S1: linking an executable file of a system program into a loaded form;

step S2: converting the executable file in the loaded form into an SREC hexadecimal format file;

and step S3: analyzing the SREC hexadecimal format file, extracting the type, the base address and the length of each segment of information, and converting the SREC hexadecimal format file into a hexadecimal format file of a VHX memory;

and step S4: when the chip is simulated, the hexadecimal format file of the VHX memory is analyzed through the script, and the hexadecimal format file of the VHX memory is split and loaded into different memory simulation model files according to different loading addresses of different segments.

In an embodiment of the present invention, the linking method in step S1 is to process a link notebook, and specifically includes:

the link address is made the same as the load address by editing the linker script.

In an embodiment of the present invention, step S2 is to perform format conversion through a standard binary tool, where the standard binary tool includes obj copy.

In an embodiment of the present invention, the tool for performing the parsing in step S3 is an SREC parser.

In an embodiment of the present invention, wherein each segment in step S3 includes: text section,. Rodata section,. Data section, and.bss section.

In an embodiment of the present invention, the process of loading different memory model files in step S4 specifically includes:

and loading the hexadecimal format file of the split VHX memory into different memory simulation models through a back gate, wherein the back gate comprises a readmemh function of the RTL.

Compared with the prior art, the method for generating the discrete loaded simulation memory model by converting the binary file can be directly loaded into the memory model without analyzing the symbol table, saves the loading process and the RAM expense during simulation, can also use the program of a real scene to carry out simulation test, and reduces the risk caused by that part of the program cannot be detected during simulation.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 is a flow chart of an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without inventive effort based on the embodiments of the present invention, are within the scope of the present invention.

Generally, the operation of converting a binary file into an HEX file is a standard function of a linker and a loader, and is not described herein any more, but a normal HEX only converts the binary file into continuous HEX data content, and there is no address information therein, and a segment of a program cannot be distinguished. The SREC format is an HEX format created by motorola, which is different from a common binary format, and is used for converting a program into a discrete hexadecimal format, changing the program into a segment of hexadecimal, and can contain starting address and size information. However, since the address information in the SREC format is a link address and not a load address, that is, it is an offset of a program stored in a storage medium (e.g., ROM) and not an address used by the CPU last time, this embodiment is a tool for extracting file information in the SREC format and converting the file information into a plurality of files of the VHX memory model HEX to implement conversion of a binary file to generate a discrete loaded emulated memory model. Fig. 1 is a flowchart of an embodiment of the present invention, and as shown in fig. 1, the embodiment provides a method for generating a discrete loaded emulated memory model by converting a binary file, which extracts SREC file information and converts the SREC file information into a plurality of VHX memory model HEX files (HEX files for a Verilog HDL memory model), specifically including:

step S1: linking an executable file of a system program into a loaded form to realize off-line loading;

in this embodiment, the linking method in step S1 is to process a link pad, and specifically includes:

the link address is made the same as the load address by editing a linker script (e.g., an LDS script).

Step S2: converting the executable file in the loaded form into a Motorola SREC hexadecimal format file;

in the present embodiment, step S2 is to perform format conversion by a standard binary tool, which includes objcopy (GNU utility program).

And step S3: analyzing the SREC hexadecimal format file, extracting the type, the base address and the length of each segment of information, and converting the SREC hexadecimal format file into a hexadecimal format file of a VHX memory;

in this embodiment, the tool for performing the parsing in step S3 is an SREC parser.

In this embodiment, each segment in step S3 includes: text section,. Rodata section,. Data section, and.bss section.

At this time, the executable file is in a loaded form, the VHX format is in a standard format, and after the hexadecimal format of the VHX memory is generated, a readmemh function of the RTL can be called to automatically load, so that the base address of the link address is consistent with the loading address of the final symbol table, the base address and the loading address of the final symbol table can be directly loaded into the memory model without analyzing the symbol table, the generated hexadecimal format file of the VHX memory can be seen to be in a discrete form, and marks of '@ loading addresses' can be arranged in front of different segments.

And step S4: during chip simulation, the hexadecimal format file of the VHX memory is analyzed through a script, and the hexadecimal format file of the VHX memory is split and loaded into different memory simulation model files (HEX files) according to different loading addresses of different segments.

In this embodiment, the process of loading different memory model files in step S4 specifically includes:

and loading the hexadecimal format file of the split VHX memory into different memory simulation models through a back gate, wherein the back gate comprises a readmemh function of the RTL.

At this time, the. Text segment and the. Rodata segment can be left in the ROM memory model, and the. Data segment and the. Bss segment can be left in the RAM memory model.

Compared with the prior art, the method for generating the discrete loaded simulation memory model by converting the binary file can be directly loaded into the memory model without analyzing the symbol table, saves the loading process and the RAM expense during simulation, can also use the program of a real scene to carry out simulation test, and reduces the risk caused by that part of the program cannot be detected during simulation.

Those of ordinary skill in the art will understand that: the figures are merely schematic representations of one embodiment, and the blocks or flow diagrams in the figures are not necessarily required to practice the present invention.

Those of ordinary skill in the art will understand that: modules in the devices in the embodiments may be distributed in the devices in the embodiments according to the description of the embodiments, or may be located in one or more devices different from the embodiments with corresponding changes. The modules of the above embodiments may be combined into one module, or further split into multiple sub-modules.

Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, and not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.

Claims (6)

1. A method for generating a discrete loaded simulation memory model by converting a binary file extracts SREC file information and converts the SREC file information into HEX files of a plurality of VHX memory models, and is characterized by specifically comprising the following steps:

step S1: linking an executable file of a system program into a loaded form;

step S2: converting the executable file in the loaded form into an SREC hexadecimal format file;

and step S3: analyzing the SREC hexadecimal format file, extracting the type, the base address and the length of each segment of information, and converting the SREC hexadecimal format file into a hexadecimal format file of a VHX memory;

and step S4: when the chip is simulated, the hexadecimal format file of the VHX memory is analyzed through the script, and the hexadecimal format file of the VHX memory is split and loaded into different memory simulation model files according to different loading addresses of different segments.

2. The method according to claim 1, wherein the linking method in step S1 is to process a linking script, and specifically comprises:

the link address is made the same as the load address by editing the linker script.

3. The method for converting a binary file into a discrete loaded emulated memory model of claim 1, wherein step S2 is format converted by a standard binary tool, the standard binary tool comprising objcopy.

4. The method for converting a binary file into a discrete loaded emulated memory model of claim 1, wherein the tool for parsing in step S3 is an SREC parser.

5. The method for converting a binary file into a discrete loaded emulated memory model of claim 1, wherein each segment in step S3 comprises: a text segment, a data segment, and a bss segment.

6. The method according to claim 1, wherein the step S4 of loading the discrete loaded emulated memory model into the different memory model files comprises:

and loading the hexadecimal format file of the split VHX memory into different memory simulation models through a back gate, wherein the back gate comprises a readmemh function of the RTL.

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