CN115374040A - Reference potential generating apparatus - Google Patents
Reference potential generating apparatus Download PDFInfo
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- CN115374040A CN115374040A CN202211314560.5A CN202211314560A CN115374040A CN 115374040 A CN115374040 A CN 115374040A CN 202211314560 A CN202211314560 A CN 202211314560A CN 115374040 A CN115374040 A CN 115374040A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
- G06F13/4072—Drivers or receivers
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/36—Circuit design at the analogue level
- G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/017509—Interface arrangements
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0002—Serial port, e.g. RS232C
Abstract
The application relates to a reference potential generating device, which relates to the technical field of analog integrated circuit design and comprises: the device comprises a topology variable voltage output device, a common-mode signal acquisition device and a voltage signal mixing device. In implementation, the topology variable voltage output device selects one or more of the multilevel equipotential level signals to perform topology combination according to the control signal, and outputs the combined reference level to the voltage signal mixing device.
Description
Technical Field
The application relates to the technical field of analog integrated circuit design, in particular to reference potential generating equipment.
Background
With the development of the semiconductor industry, especially the development of the transmission interface, people have higher and higher requirements on the transmission rate, and the high-speed serial interface is replacing the traditional parallel transmission to become the mainstream of the new generation high-speed interface. In order to ensure the quality and amplitude of Signal transmission, a conventional universal serial interface such as PCI-Express (high speed serial computer extended bus standard), LVDS (Low Voltage Differential signaling), etc. mostly adopts dual ports, i.e. so-called Differential ports, to transmit data signals; for a high-speed serial interface with short distance and low loss among semiconductor chips, a single-port serial interface is gradually preferred due to lower power consumption and more saving of the number of packaged ports. The receiving end reference potential generating device is an indispensable component of the receiving end of the single-port serial interface.
The existing receiving end reference potential generating device mostly adopts a multi-stage voltage division structure with serially connected resistors to generate level values of a plurality of gears, and the level values are output by a voltage selection circuit, a voltage buffer and the like, the adjustable number of output gears of the reference level is small, the reference level value has fixity, and better judgment sensitivity and margin cannot be provided for a receiving judgment circuit.
Disclosure of Invention
In order to overcome the problems that the number of reference level output gears of the reference level generating equipment in the related art is small and the reference level value has fixity at least to a certain extent, the application provides the reference level generating equipment.
The scheme of this application is as follows:
a reference potential generating apparatus comprising:
the device comprises a topology variable voltage output device, a common-mode signal acquisition device and a voltage signal mixing device;
the topology variable voltage output device is used for selecting one or more level signals of the multilevel equipotential to perform topology combination according to the control signal, and outputting the combined reference level to the voltage signal mixing device;
the common-mode signal acquisition device is used for acquiring a dynamically-changed common-mode signal in a channel and outputting the common-mode signal to the voltage signal mixing device;
the voltage signal mixing device is used for superposing the reference level and the common-mode signal.
Preferably, the variable topology voltage output device includes: the device comprises a resistor array voltage division device and a topology variable voltage selection device;
the resistor array voltage division device comprises a multi-stage series resistor voltage division structure and is used for outputting a multi-stage equipotential level signal to the topology variable voltage selection device;
the topology variable voltage selection device is used for selecting one or more level signals of the multilevel equipotential to perform topology combination according to the control signal, and outputting the combined reference level to the voltage signal mixing device.
Preferably, the topology variable voltage selection device includes:
a decoder and a multi-stage series voltage transmission switch;
the multistage series voltage transmission switches correspond to the multistage equipotential level signals output by the multistage series resistance voltage division structure one by one;
the decoder is used for receiving the control signal and selecting the corresponding voltage transmission switch to be turned on according to the control signal.
Preferably, the reference level is an average of the selected one or more level signals.
Preferably, the voltage signal mixing apparatus includes:
at least two addend analog adders;
the addend analog adder superposes the reference level and the common-mode signal, so that the superposed reference level can be dynamically changed along with the common-mode signal.
Preferably, the apparatus further comprises:
a voltage signal buffer;
the voltage signal mixing device is used for outputting the superposed reference level to the voltage signal buffering device;
the voltage signal buffer device is used for enhancing the driving capability of the reference level.
Preferably, the voltage signal buffering means includes: a unity gain amplifier;
the gain range of the unit gain amplifier is 0.9-1.
Preferably, the apparatus further comprises:
a voltage signal stabilizer;
the voltage signal buffer device is used for outputting the enhanced reference level to the voltage signal voltage-stabilizing device;
and the voltage signal voltage stabilizing device is used for stabilizing and outputting the enhanced reference level.
The technical scheme provided by the application can comprise the following beneficial effects: the reference potential generating apparatus in the present application includes: the device comprises a topology variable voltage output device, a common-mode signal acquisition device and a voltage signal mixing device. During implementation, the topology variable voltage output device selects one or more of the level signals of the multilevel equipotential according to the control signal to perform topology combination, and outputs the combined reference level to the voltage signal mixing device. In the technical scheme of the application, the common-mode signal acquisition device is used for acquiring the dynamically-changed common-mode signal in the channel and outputting the common-mode signal to the voltage signal mixing device, and the voltage signal mixing device is used for superposing the reference level and the common-mode signal, so that the superposed reference level can dynamically change along with the common-mode signal. In summary, the technical solution in the present application can provide better decision sensitivity and margin for the receiving decision circuit.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and, together with the description, serve to explain the principles of the application.
Fig. 1 is a schematic structural diagram of a reference potential generating apparatus according to an embodiment of the present application;
FIG. 2 is a schematic structural diagram of a reference potential generating apparatus according to another embodiment of the present application;
fig. 3 is a schematic structural diagram of a resistor array voltage divider according to an embodiment of the present application;
fig. 4 is a schematic structural diagram of a topology variable voltage selection apparatus according to an embodiment of the present application;
fig. 5 is a schematic structural diagram of a reference potential generating apparatus according to another embodiment of the present application.
Reference numerals: a topology variable voltage output device-1; a resistor array voltage divider-11; topology variable voltage selection means-12; a common mode signal acquisition device-2; a voltage signal mixing device-3; a voltage signal buffer device-4; and voltage signal stabilizing device-5.
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. The following description refers to the accompanying drawings in which the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary examples do not represent all implementations consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.
Example one
Fig. 1 is a schematic structural diagram of a reference potential generating apparatus according to an embodiment of the present invention, and referring to fig. 1, the reference potential generating apparatus includes:
the device comprises a topology variable voltage output device 1, a common-mode signal acquisition device 2 and a voltage signal mixing device 3;
the topology variable voltage output device 1 is used for selecting one or more level signals of multilevel equipotential to perform topology combination according to the control signal, and outputting the combined reference level to the voltage signal mixing device 3;
the common-mode signal acquisition device 2 is used for acquiring a dynamically-changed common-mode signal in a channel and outputting the common-mode signal to the voltage signal mixing device 3;
the voltage signal mixing means 3 are arranged to superimpose the reference level and the common mode signal.
It should be noted that the technical solution in this embodiment belongs to the field of analog integrated circuit design in semiconductor chip design, and in particular relates to a receiving end reference potential generating device of a single-ended high-speed serial interface between semiconductor chips.
It should be noted that the common mode signal acquisition device 2 is used for acquiring a common mode signal dynamically changing with time in a channel. The common mode signal acquisition device 2 may be, but is not limited to, an RC filter, and the common mode signal acquisition device 2 extracts and outputs a level mean value of signals in a channel, that is, a common mode level signal.
It is to be understood that the reference potential generating apparatus in the present embodiment includes: the device comprises a topology variable voltage output device 1, a common-mode signal acquisition device 2 and a voltage signal mixing device 3. In implementation, the topology variable voltage output device 1 selects one or more of the multilevel equipotential level signals to perform topology combination according to the control signal, and outputs the combined reference level to the voltage signal mixing device 3. In addition, in the technical scheme of this embodiment, the common-mode signal acquisition device 2 is used for acquiring a dynamically changing common-mode signal in a channel and outputting the common-mode signal to the voltage signal mixing device 3, and the voltage signal mixing device 3 superimposes the reference level and the common-mode signal, so that the superimposed reference level can dynamically change along with the common-mode signal. In summary, the technical solution in this embodiment can provide better decision sensitivity and margin for the receiving decision circuit.
Referring to fig. 2 to 4, the variable topology voltage output apparatus includes: a resistor array voltage divider 11 and a topology variable voltage selector 12;
the resistor array voltage divider 11 comprises a multi-stage series resistor voltage dividing structure and is used for outputting a multi-stage equipotential level signal to the topology variable voltage selector 12;
the topology variable voltage selection device 12 is configured to select one or more level signals of the multilevel equipotential according to the control signal to perform topology combination, and output a reference level obtained by the topology combination to the voltage signal mixing device 3.
Referring to fig. 3, the resistor array voltage divider 11 includes a multi-stage series resistor voltage dividing structure, and can output a coarse-grained multi-stage equipotential level; one level of level can be output between every two resistors, the difference value between every two levels is Vr/n, vr is a reference voltage value, and n is the number of the resistors connected in series; the resistances of the resistor 1 to the resistor n are the same.
Referring to fig. 4, the topology variable voltage selection device 12 includes:
a decoder and a multi-stage series voltage transmission switch;
the multilevel series voltage transmission switches correspond to multilevel equipotential level signals output by the multilevel series resistance voltage division structure one by one;
the decoder is used for receiving the control signal and selecting the corresponding voltage transmission switch to be turned on according to the control signal.
The decoder converts the control signals into signals Sn-1 and Sn-2 \8230, S1 controls each voltage transmission switch respectively, and the voltage transmission switches can connect or disconnect input level signals; the decoder in this embodiment may output a plurality of high levels at the same time to control the voltage transmission switch, so as to select one or more of the level signals of the multilevel equipotential to perform topology combination.
For example, if the control signals are to control the voltage transmission switches Tn-1 and T1 to be turned on, and correspondingly, the decoder translates the control signals into signals Sn-1 and S1 to be at a high level, and the remaining signals are at a low level, so as to control the voltage transmission switches Tn-1 and T1 to be turned on, and if it is assumed that the resistance of the voltage transmission switch is much smaller than that of the single-stage resistor and the resistance of the n-2-stage series connection is much larger than that of the 2-stage resistor series connection, the calculation formula of the output level is approximately [ (n-1) × Vr/n + Vr/n ]/2= Vr/2. By turning on the voltage switches Tn-1 and T1, the series-connected n-level resistor networks can be recombined, all resistors are changed into resistors 1 and n which are connected in series, and the resistors are connected with the rest resistors in series in parallel, so that the topological structure of the original resistor network is changed, and a new level output value is obtained.
The voltage signal mixing device 3 includes:
at least two addend analog adders;
the added analog adder superposes the reference level and the common-mode signal, so that the superposed reference level can be dynamically changed along with the common-mode signal.
It can be understood that, in the present embodiment, the reference level and the common-mode signal are superimposed by at least two addend analog adders, so that the superimposed reference level can dynamically change with the common-mode signal.
Example two
Fig. 5 is a schematic structural diagram of a reference potential generating apparatus according to another embodiment of the present application, and referring to fig. 5, the reference potential generating apparatus further includes:
a voltage signal buffer 4;
the voltage signal mixing device 3 is used for outputting the superposed reference level to the voltage signal buffer device 4;
the voltage signal buffer 4 is used to enhance the driving capability of the reference level.
Further, the voltage signal buffering means 4 includes: a unity gain amplifier;
the gain of the unity gain amplifier ranges from 0.9 to 1.
It can be understood that the gain of the unity gain amplifier is approximately 1, and the signal driving capability can be enhanced and the output load capability can be improved without changing the level value of the input level.
Referring to fig. 5, the reference potential generating apparatus further includes:
a voltage signal stabilizer 5;
the voltage signal buffer device 4 is used for outputting the enhanced reference level to a voltage signal voltage-stabilizing device;
the voltage signal stabilizing device 5 is used for stabilizing and outputting the enhanced reference level.
In a specific practice, the voltage signal stabilizing device 5 may be, but is not limited to, an RC filter.
It is understood that the same or similar parts in the above embodiments may be mutually referred to, and the same or similar contents in other embodiments may be referred to for the contents which are not described in detail in some embodiments.
It should be noted that, in the description of the present application, the terms "first", "second", etc. are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. Further, in the description of the present application, the meaning of "a plurality" means at least two unless otherwise specified.
Any process or method descriptions in flow charts or otherwise described herein may be understood as representing modules, segments, or portions of code which include one or more executable instructions for implementing specific logical functions or steps of the process, and the scope of the preferred embodiments of the present application includes other implementations in which functions may be executed out of order from that shown or discussed, including substantially concurrently or in reverse order, depending on the functionality involved, as would be understood by those reasonably skilled in the art of the present application.
It should be understood that portions of the present application may be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, the various steps or methods may be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, any one or combination of the following technologies, which are well known in the art, may be used: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application specific integrated circuit having an appropriate combinational logic gate circuit, a Programmable Gate Array (PGA), a Field Programmable Gate Array (FPGA), or the like.
It will be understood by those skilled in the art that all or part of the steps carried by the method for implementing the above embodiments may be implemented by hardware related to instructions of a program, which may be stored in a computer readable storage medium, and when the program is executed, the program includes one or a combination of the steps of the method embodiments.
In addition, functional units in the embodiments of the present application may be integrated into one processing module, or each unit may exist alone physically, or two or more units are integrated into one module. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode. The integrated module, if implemented in the form of a software functional module and sold or used as a stand-alone product, may also be stored in a computer readable storage medium.
The storage medium mentioned above may be a read-only memory, a magnetic or optical disk, etc.
In the description herein, reference to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
Although embodiments of the present application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present application, and that variations, modifications, substitutions and alterations may be made to the above embodiments by those of ordinary skill in the art within the scope of the present application.
Claims (8)
1. A reference potential generating apparatus, comprising:
the device comprises a topology variable voltage output device, a common-mode signal acquisition device and a voltage signal mixing device;
the topology variable voltage output device is used for selecting one or more level signals of the multilevel equipotential to perform topology combination according to the control signal, and outputting the combined reference level to the voltage signal mixing device;
the common-mode signal acquisition device is used for acquiring a dynamically-changed common-mode signal in a channel and outputting the common-mode signal to the voltage signal mixing device;
the voltage signal mixing device is used for superposing the reference level and the common-mode signal.
2. The apparatus of claim 1, wherein the topology variable voltage output device comprises: the device comprises a resistor array voltage division device and a topology variable voltage selection device;
the resistor array voltage division device comprises a multi-stage series resistor voltage division structure and is used for outputting a multi-stage equipotential level signal to the topology variable voltage selection device;
the topology variable voltage selection device is used for selecting one or more level signals of the multilevel equipotential to perform topology combination according to the control signal, and outputting the combined reference level to the voltage signal mixing device.
3. The apparatus of claim 2, wherein the topology variable voltage selection means comprises:
a decoder and a multi-stage series voltage transmission switch;
the multistage series voltage transmission switches correspond to the multistage equipotential level signals output by the multistage series resistance voltage division structure one by one;
the decoder is used for receiving the control signal and selecting the corresponding voltage transmission switch to be turned on according to the control signal.
4. The apparatus of claim 1, wherein the reference level is an average of the selected one or more level signals.
5. The apparatus of claim 1, wherein the voltage signal mixing means comprises:
at least two analog adders for adding numbers;
the addend analog adder superposes the reference level and the common-mode signal, so that the superposed reference level can be dynamically changed along with the common-mode signal.
6. The apparatus of claim 1, further comprising:
a voltage signal buffer device;
the voltage signal mixing device is used for outputting the superposed reference level to the voltage signal buffering device;
the voltage signal buffer device is used for enhancing the driving capability of the reference level.
7. The apparatus of claim 1, wherein the voltage signal buffering means comprises: a unity gain amplifier;
the gain range of the unit gain amplifier is 0.9-1.
8. The apparatus of claim 1, further comprising:
a voltage signal stabilizer;
the voltage signal buffer device is used for outputting the enhanced reference level to the voltage signal voltage stabilizing device;
and the voltage signal voltage stabilizing device is used for stabilizing and outputting the enhanced reference level.
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| CN116841341A (en) * | 2023-09-01 | 2023-10-03 | 合肥智芯半导体有限公司 | Multi-voltage generating device, multi-voltage calibration system and chip device |
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