CN115373747A - Instruction expansion method, system and computer readable storage medium - Google Patents
Instruction expansion method, system and computer readable storage medium Download PDFInfo
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- CN115373747A CN115373747A CN202211009405.2A CN202211009405A CN115373747A CN 115373747 A CN115373747 A CN 115373747A CN 202211009405 A CN202211009405 A CN 202211009405A CN 115373747 A CN115373747 A CN 115373747A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30181—Instruction operation extension or modification
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
Abstract
The invention discloses an instruction extension method, an instruction extension system and a computer readable storage medium. The method comprises the following steps: generating an instruction to be expanded in a preset instruction set according to an algorithm to be realized and an instruction expansion rule; when the instruction to be expanded is called, entering an exception handling flow, and switching the execution environment of the processor from an operating system to OpenSBI in the exception handling flow; generating and calling an extended instruction function library corresponding to the instruction to be extended under the OpenSBI execution environment; and after the operation of the extended instruction function library is finished, exiting the exception handling process according to a preset instruction pointer, and switching the execution environment from OpenSBI to an operating system to finish instruction extension. The invention improves the performance when the instruction is expanded by using a software mode.
Description
Technical Field
The present invention relates to the field of processor design technologies, and in particular, to a method and a system for instruction extension and a computer-readable storage medium.
Background
The RISC-V instruction set architecture is proposed in 2010 by developers in Berkeley division of California university, has a simple instruction set architecture, is completely open source and free, can meet processors of various sizes from a microcontroller to a super computer, and is more and more widely applied to the field of microcontrollers of IoT (Internet of things) edge terminals, artificial intelligence, industrial control and the like.
As a brand-new instruction set architecture, the development of RISC-V in the industrial control field is in the early stage, the support of the RISC-V to the industrial control field depends on a reference instruction, and the ecology is not perfect. However, since RISC-V separates the base and extended instructions, customized modules and extensions can be made via the extended instructions. Aiming at specific or typical scenes of industrial control, the acceleration of the field of industrial control is met through instruction extension and instruction customization on the basis of a RISC-V open source architecture.
At present, a common method for extending an instruction is to support the instruction by modifying hardware, and corresponding modification needs to be made on a compiling tool chain. For each newly added custom extension instruction set, a user needs to implement corresponding support in a compiling tool chain, and two methods are commonly used: firstly, a program of an application layer uses an extended instruction by calling a newly defined data type and a built-in function of a compiler; second, the compiler is optimized to directly and automatically convert the intermediate code into corresponding extended instructions in the compilation stage.
However, the hardware is modified to support the extended instruction, the modification of the hardware and the compiler needs to be balanced through modeling, the development period is long, the difficulty in modifying the hardware and the software is high, the verification is complex, and the method is not suitable for rapid iterative development of versions.
Aiming at the defect of instruction extension by modifying a hardware mode, the instruction extension can be performed by a software mode. Extension is done by wrapping the functions to be implemented into function calls, but this approach has two drawbacks: firstly, the method is strongly related to an operating system, and recompilation and adaptation are needed when one operating system is replaced; secondly, the function realized by the method is generally realized based on a high-level language, and in a user flow, the hardware resource cannot be directly accessed, and the performance is not high.
Disclosure of Invention
The invention mainly aims to provide an instruction expansion method, an instruction expansion system and a computer-readable storage medium. The method aims to solve the problems of low universality and low performance caused by adopting a software mode to carry out instruction extension.
In order to achieve the above object, the present invention provides an instruction extension method, including the steps of:
generating an instruction to be expanded in a preset instruction set according to an algorithm to be realized and an instruction expansion rule;
when the instruction to be expanded is called, an exception handling flow is entered, and the execution environment of the processor is switched from an operating system to OpenSBI in the exception handling flow;
generating and calling an extended instruction function library corresponding to the instruction to be extended under the OpenSBI execution environment;
and after the operation of the extended instruction function library is finished, exiting the exception handling process according to a preset instruction pointer, and switching the execution environment from OpenSBI to an operating system to finish instruction extension.
Optionally, the step of generating the instruction to be expanded in the preset instruction set according to the algorithm to be implemented and the instruction expansion rule includes:
generating an instruction to be expanded corresponding to the algorithm to be realized according to the algorithm to be realized and an instruction expansion rule;
and allocating the instruction to be expanded in a reserved space in a preset instruction set, and generating an instruction code and an operation code macro definition corresponding to the instruction to be expanded, wherein the instruction to be expanded comprises the instruction code and the operation code macro definition.
Optionally, the step of entering an exception handling flow when the instruction to be expanded is called includes:
calling the instruction to be expanded, and suspending the current running program;
jumping to the PC address in the MTVEC register in the processor for execution, updating a plurality of preset CSR registers in the processor, and entering an exception handling flow.
Optionally, the switching an execution environment of the processor from an operating system to an OpenSBI in the exception handling process includes:
in the exception handling process, a preset function is called, and the execution environment of the processor is switched to a machine mode in OpenSBI from an operating system according to the preset function.
Optionally, after the step of generating and calling the extended instruction function library corresponding to the instruction to be extended in the OpenSBI execution environment, the method further includes:
and updating the PC address of the MEPC register in the processor, and using the PC address as a preset instruction pointer.
Optionally, the step of generating and calling an extended instruction function library corresponding to the instruction to be extended in the OpenSBI execution environment includes:
generating a library function corresponding to the instruction to be expanded under the OpenSBI execution environment;
and obtaining and calling a function library corresponding to the library function according to the library function.
Optionally, after the operation of the extended instruction function library is completed, exiting the exception handling process according to a preset instruction pointer, and switching the execution environment from OpenSBI to an operating system, where the step of completing instruction extension includes:
after the operation of the extended instruction function library is finished, executing the PC address of the MEPC register, and updating a plurality of preset CSR registers in the processor again;
and switching the execution environment from OpenSBI to a supervisor mode of an operating system according to the PC address of the MEPC register, and finishing instruction expansion.
Optionally, before the step of updating the PC address of the MEPC register in the processor and using the PC address as a preset instruction pointer, the method further includes:
and calling a preset registration function, and registering the extended instruction function library.
In addition, to achieve the above object, the present invention also provides an instruction expansion system, including: a memory, a processor and an instruction extension program stored on the memory and executable on the processor, the instruction extension program when executed by the processor implementing the steps of the instruction extension method as described above.
Furthermore, to achieve the above object, the present invention also provides a computer readable storage medium having stored thereon an instruction extension program, which when executed by a processor, implements the steps of the instruction extension method as described above.
The invention provides an instruction expansion method, a system and a computer readable storage medium, wherein the instruction expansion method comprises the following steps: generating an instruction to be expanded in a preset instruction set according to an algorithm to be realized and an instruction expansion rule; when the instruction to be expanded is called, entering an exception handling flow, and switching the execution environment of the processor from an operating system to OpenSBI in the exception handling flow; generating and calling an extended instruction function library corresponding to the instruction to be extended under the OpenSBI execution environment; and after the operation of the extended instruction function library is finished, exiting the exception handling process according to a preset instruction pointer, and switching the execution environment from OpenSBI to an operating system to finish instruction extension. Through the method, the invention utilizes OpenSBI of the resident memory in the machine mode to carry out extended instruction support through the machine privilege mode based on the RISC-V architecture. The extended instructions can be realized under the machine mode firmware (OpenSBI) by capturing the extended instructions to the machine mode, and the extended instructions are returned to the operating system after the extended library function is executed, so that the problems that when the operating system is replaced, compiling and adapting are required to be carried out again when the operating system is replaced, and the problem that the performance is not high because hardware resources cannot be directly accessed when the operating system is replaced due to the fact that the extended instructions are extended in a software mode are solved.
Drawings
FIG. 1 is a schematic diagram of an apparatus in a hardware operating environment according to an embodiment of the present invention;
FIG. 2 is a flowchart illustrating an instruction expanding method according to an embodiment of the invention.
The implementation, functional features and advantages of the present invention will be further described with reference to the accompanying drawings.
Detailed Description
It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Referring to fig. 1, fig. 1 is a schematic diagram of a hardware structure of an instruction expansion system provided in various embodiments of the present invention. The instruction expansion system comprises a communication module 01, a memory 02, a processor 03 and the like. Those skilled in the art will appreciate that the instruction expansion system shown in FIG. 1 may also include more or fewer components than shown, or combine certain components, or a different arrangement of components. The processor 03 is connected to the memory 02 and the communication module 01, respectively, and the memory 02 stores an instruction extension program, which is executed by the processor 03 at the same time.
The communication module 01 may be connected to an external device through a network. The communication module 01 may receive data sent by an external device, and may also send data, instructions, and information to the external device, where the external device may be an electronic device such as a mobile phone, a tablet computer, a notebook computer, and a desktop computer.
The memory 02 may be used to store software programs and various data. The memory 02 may mainly include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required for at least one function, and the like; the storage data area may store data or information created according to the use of the instruction expansion system, or the like. Further, the memory 02 may include high speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other volatile solid state storage device.
The processor 03, which is a control center of the instruction expansion system, connects various parts of the entire instruction expansion system by using various interfaces and lines, and executes various functions of the instruction expansion system and processes data by running or executing software programs and/or modules stored in the memory 02 and calling data stored in the memory 02, thereby integrally monitoring the instruction expansion system. Processor 03 may include one or more processing units; preferably, the processor 03 may integrate an application processor, which mainly handles operating systems, user interfaces, application programs, etc., and a modem processor, which mainly handles wireless communications. It will be appreciated that the modem processor described above may not be integrated into the processor 03.
Those skilled in the art will appreciate that the architecture of the instruction expansion system shown in FIG. 1 does not constitute a limitation of the instruction expansion system, and may include more or fewer components than shown, or some components in combination, or a different arrangement of components.
Various embodiments of the method of the present invention are presented in terms of the above-described hardware architecture.
Referring to fig. 2, fig. 2 is a flowchart illustrating an instruction expansion method according to a first embodiment of the present invention, where the instruction expansion method includes the following steps:
step S10, generating an instruction to be expanded in a preset instruction set according to an algorithm to be realized and an instruction expansion rule;
in this embodiment, the algorithm to be implemented may be an algorithm that needs to be expanded according to application analysis in the industrial control field; the instruction extension rule is a RISC-V instruction extension rule, the RISC-V instruction extension is standardized in the RISC-V instruction extension rule, and a person skilled in the art can extend the corresponding instruction according to the algorithm function and the extension rule which are required to be realized.
Specifically, in an embodiment, the step S10 further includes:
step A11, generating an instruction to be expanded corresponding to an algorithm to be realized according to the algorithm to be realized and an instruction expansion rule;
step A12, distributing the instruction to be expanded in a reserved space in a preset instruction set, and generating an instruction code and an operation code macro definition corresponding to the instruction to be expanded, wherein the instruction to be expanded comprises the instruction code and the operation code macro definition.
It should be noted that the RISC-V instruction set is divided into 6 types, such as R type, I type, S type, SB type, U type, UJ type, etc., each instruction has a code length of 32 bits, and low 7 bits in the code format are fixed as an operation code opcode for distinguishing different instructions. Instruction expansion can be performed using the reserved space in the RISC-V encoding space and the unused funct space in the above 6 instructions. Specifically, an operation code of the instruction to be expanded can be defined in the opcode for distinguishing the instruction to be expanded, and then the instruction code corresponding to the operation code is expanded in the unused funct space, the instruction formats of different types are different, and the instruction arranged according to the specific machine code has a special purpose. When the instruction is expanded, only the opcode of the lower order and the data of the corresponding area of the upper order are defined according to the RISC-V expansion instruction rule, and the binary code of the expansion instruction is corresponded. For example, an instruction to be expanded with a function of "multiply add" is expanded, and the instruction to be expanded with the "multiply add" function can be expanded by only defining an operation code of the multiply add instruction in an opcode and then defining corresponding data in a funct space.
Step 20, when the instruction to be expanded is called, entering an exception handling flow, and switching an execution environment of the processor from an operating system to OpenSBI in the exception handling flow;
in this embodiment, since the instruction to be extended is not registered, the instruction to be extended belongs to an Illegal instruction, and when the processor core runs to the Illegal instruction, the RISC-V architecture triggers an Illegal instruction exception, that is, the instruction enters an exception handling process. And switching the execution environment of the processor from the operating system to a machine mode in OpenSBI.
It should be noted that, in this embodiment, the RISC-V privileged mode M-mode is the highest-privilege mode that HART (hard thread) can execute, and has complete usage rights for memory, I/O, and some underlying functions necessary for configuring the system. The machine mode has the capability of intercepting and processing the exception, and can simulate the instruction function and the like which are lacked by RISC-V in the mode.
OpenSBI is an open source reference implementation that operates in M mode and provides a Supervisory Binary Interface (SBI) for the operating system of RISC-V platform, so that it can obtain and operate hardware information. RISC-V platforms and system-on-chip vendors can easily extend OpenSBI implementations to suit specific hardware configurations.
Specifically, the step S20 further includes:
step A21, calling the instruction to be expanded and suspending the current running program;
and step A22, jumping to a PC address in an MTVEC register in the processor for execution, updating a plurality of preset CSR registers in the processor, and entering an exception handling flow.
In this embodiment, the processor includes an MEPC register, an MTVAL register, an MSTATUS register, and an MCAUSE register, when the instruction to be expanded is called, first, the processor core terminates a currently running program, and stores a PC address of the currently running program in the MEPC register, then the processor starts execution from a PC address in the MTVEC register, and at the same time, the MCAUSE register is updated to a currently occurring exception type, the MEPC register is updated to a currently occurring exception instruction PC, and the MTVAL register is updated to an instruction code to be expanded that causes a current exception. The PC address is the address of the unit where the next instruction to be executed is located, the PC address is stored in an instruction counter in the processor, and after one instruction is executed, one byte is automatically added to the PC every time one instruction is executed, so that the program can be continuously executed. The preset CSR register comprises the MEPC register, the MTVAL register, the MSTATUS register and the MCAUSE register.
Step a23, in the exception handling process, a preset function is called, and an execution environment of the processor is switched from an operating system to a machine mode in the OpenSBI according to the preset function.
In this embodiment, the preset function is the sbi _ ecal _ init, and is configured to call an ecall instruction of the RISC-V, so that the execution of the CPU is transferred to an SEE environment with higher privilege, namely, an OpenSBI, and the call instruction expands a corresponding library function in the SEE environment, thereby implementing a function of expanding the function. It should be noted that in the art, the risc-v architecture defines 3 operating modes, which are also called privileged modes (privileged modes). The method comprises the following steps: machine mode (M mode for short); a supervision mode (super mode), referred to as S mode for short; and user mode (user mode), abbreviated U mode.
Step S30, generating and calling an extended instruction function library corresponding to the instruction to be extended under the OpenSBI execution environment;
in an embodiment, the step S30 further includes:
step a31, in the OpenSBI execution environment, generating a library function corresponding to the instruction to be extended;
and A32, obtaining and calling a function library corresponding to the library function according to the library function.
In this embodiment, the instruction to be expanded is packaged as a library function, and a set of library functions is obtained, that is, a library of instruction functions to be expanded corresponding to the instruction to be expanded. The function library may include a plurality of library functions corresponding to the instructions to be expanded.
In addition, in an embodiment, after the step S30, the method further includes:
step A301, updating a PC address of an MEPC register in the processor, and using the PC address as a preset instruction pointer.
In the present embodiment, due to the RISC-V definition, when an exception occurs, the value of the processor interrupt return address MEPC is updated to the address of the instruction to be extended PC at which the exception currently occurs. If the extended instruction function library call is executed, a return is made, and then execution is started from the PC address saved by the MEPC, because the address of the instruction to be extended is saved by the MEPC, so that a dead loop is caused (the instruction to be extended is executed repeatedly). Therefore, in the flow of the extended instruction in which the OpenSBI processing exception is executed, it is sufficient to change the MEPC to point to the next instruction and rewrite mcpc = mcpc + 4. So that the processor can be prevented from entering a loop of repeated execution of the instruction to be expanded after the execution of the function library of the expansion instruction is completed.
In addition, in an embodiment, before the step a301, the method further includes:
step A302, calling a preset registration function, and registering the extended instruction function library.
The preset registration function is the sbi _ trap _ handler, and the registration of the extended instruction function library can be performed through the function, so that the processor can call and execute the function to complete the extension of the instruction.
And step S40, after the operation of the extended instruction function library is completed, exiting the exception handling process according to a preset instruction pointer, and switching the execution environment from OpenSBI to an operating system to complete instruction extension.
In this embodiment, the preset instruction pointer is MEPC +4, after the call of the extended instruction function library is completed, the currently running program is stopped, the MRET instruction may be called to return to the S mode of the operating system, execution is started from the address defined in the CSR register MEPC, that is, MEPC +4, and the CSR register, including the MCAUSE register, is updated.
In addition, the invention is suitable for the instruction expansion of the existing chips of all RISC-V architectures, and particularly, the instruction expansion of the existing chips can be realized only by adding the support to the chips under the corresponding platform of OpenSBI.
The invention provides an instruction extension method, which comprises the following steps: generating an instruction to be expanded in a preset instruction set according to an algorithm to be realized and an instruction expansion rule; when the instruction to be expanded is called, an exception handling flow is entered, and the execution environment of the processor is switched from an operating system to OpenSBI in the exception handling flow; generating and calling an extended instruction function library corresponding to the instruction to be extended under the OpenSBI execution environment; and after the operation of the extended instruction function library is finished, exiting the exception handling process according to a preset instruction pointer, and switching the execution environment from OpenSBI to an operating system to finish instruction extension. Through the method, the invention utilizes OpenSBI of the resident memory in the machine mode to carry out extended instruction support through the machine privilege mode based on the RISC-V architecture. The extended instructions can be realized under the machine mode firmware (OpenSBI) by capturing the extended instructions to the machine mode, and the extended instructions are returned to the operating system after the extended library function is executed, so that the problems that when the operating system is replaced, compiling and adapting are required to be carried out again when the operating system is replaced, and the problem that the performance is not high because hardware resources cannot be directly accessed when the operating system is replaced due to the fact that the extended instructions are extended in a software mode are solved.
Furthermore, an embodiment of the present invention further provides a computer-readable storage medium, where the computer-readable storage medium has stored thereon an instruction extension program, and when executed by a processor, the instruction extension program implements the following operations:
generating an instruction to be expanded in a preset instruction set according to an algorithm to be realized and an instruction expansion rule;
when the instruction to be expanded is called, entering an exception handling flow, and switching the execution environment of the processor from an operating system to OpenSBI in the exception handling flow;
generating and calling an extended instruction function library corresponding to the instruction to be extended under the OpenSBI execution environment;
and after the operation of the extended instruction function library is finished, exiting the exception handling process according to a preset instruction pointer, and switching the execution environment from OpenSBI to an operating system to finish instruction extension.
Further, the instruction extension program when executed by the processor further implements the operations of:
the step of generating the instruction to be expanded in the preset instruction set according to the algorithm to be realized and the instruction expansion rule comprises the following steps:
generating an instruction to be expanded corresponding to the algorithm to be realized according to the algorithm to be realized and an instruction expansion rule;
and allocating the instruction to be expanded in a reserved space in a preset instruction set, and generating an instruction code and an operation code macro definition corresponding to the instruction to be expanded, wherein the instruction to be expanded comprises the instruction code and the operation code macro definition.
Further, the instruction extension program when executed by the processor further implements the operations of:
when the instruction to be expanded is called, the step of entering an exception handling flow comprises the following steps:
calling the instruction to be expanded, and suspending the current running program;
jumping to the PC address in the MTVEC register in the processor for execution, updating a plurality of preset CSR registers in the processor, and entering an exception handling process.
Further, the instruction extension program when executed by the processor further implements the operations of:
the step of switching the execution environment of the processor from the operating system to the OpenSBI in the exception handling process includes:
and in the exception handling process, calling a preset function, and switching the execution environment of the processor into a machine mode in OpenSBI from an operating system according to the preset function.
Further, the instruction extension program when executed by the processor further implements the operations of:
after the step of generating and calling the extended instruction function library corresponding to the instruction to be extended in the OpenSBI execution environment, the method further includes:
and updating the PC address of the MEPC register in the processor, and using the PC address as a preset instruction pointer.
Further, the instruction extension program when executed by the processor further implements the operations of:
the step of generating and calling an extended instruction function library corresponding to the instruction to be extended in the OpenSBI execution environment includes:
generating a library function corresponding to the instruction to be expanded in the OpenSBI execution environment;
and obtaining and calling a function library corresponding to the library function according to the library function.
Further, the instruction extension program when executed by the processor further implements the operations of:
after the operation of the extended instruction function library is completed, exiting the exception handling process according to a preset instruction pointer, and switching the execution environment from OpenSBI to an operating system, where the step of completing instruction extension includes:
after the operation of the extended instruction function library is finished, executing the PC address of the MEPC register, and updating a plurality of preset CSR registers in the processor again;
and switching the execution environment from OpenSBI to a supervisor mode of an operating system according to the PC address of the MEPC register, and finishing instruction expansion.
Further, the instruction extension program when executed by the processor further implements the operations of:
before the step of updating the PC address of the MEPC register in the processor and using the PC address as a preset instruction pointer, the method further includes:
and calling a preset registration function, and registering the extended instruction function library.
The specific embodiment of the computer-readable storage medium of the present invention is substantially the same as the embodiments of the instruction extension program, and is not described herein again.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or system. Without further limitation, an element defined by the phrases "comprising a," "8230," "8230," or "comprising" does not exclude the presence of other like elements in a process, method, article, or system comprising the element.
The above-mentioned serial numbers of the embodiments of the present invention are merely for description and do not represent the merits of the embodiments.
Through the description of the foregoing embodiments, it is clear to those skilled in the art that the method of the foregoing embodiments may be implemented by software plus a necessary general hardware platform, and certainly may also be implemented by hardware, but in many cases, the former is a better implementation. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium (e.g., ROM/RAM, magnetic disk, optical disk) as described above and includes instructions for causing a terminal device to execute the method according to the embodiments of the present invention.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, and all equivalent structures or equivalent processes performed by the present invention or directly or indirectly applied to other related technical fields are also included in the scope of the present invention.
Claims (10)
1. An instruction expansion method, characterized in that the instruction expansion method comprises the steps of:
generating an instruction to be expanded in a preset instruction set according to an algorithm to be realized and an instruction expansion rule;
when the instruction to be expanded is called, an exception handling flow is entered, and the execution environment of the processor is switched from an operating system to OpenSBI in the exception handling flow;
generating and calling an extended instruction function library corresponding to the instruction to be extended under the OpenSBI execution environment;
and after the operation of the extended instruction function library is finished, exiting the exception handling process according to a preset instruction pointer, and switching the execution environment from OpenSBI to an operating system to finish instruction extension.
2. The instruction expansion method of claim 1, wherein the step of generating the instruction to be expanded in the preset instruction set according to the algorithm to be implemented and the instruction expansion rule comprises:
generating an instruction to be expanded corresponding to the algorithm to be realized according to the algorithm to be realized and an instruction expansion rule;
and allocating the instruction to be expanded in a reserved space in a preset instruction set, and generating an instruction code and an operation code macro definition corresponding to the instruction to be expanded, wherein the instruction to be expanded comprises the instruction code and the operation code macro definition.
3. The instruction expansion method according to claim 1, wherein the step of entering an exception handling flow when the instruction to be expanded is called comprises:
calling the instruction to be expanded, and suspending the current running program;
jumping to the PC address in the MTVEC register in the processor for execution, updating a plurality of preset CSR registers in the processor, and entering an exception handling process.
4. The instruction expansion method according to claim 3, wherein the step of switching an execution environment of a processor from an operating system to OpenSBI in the exception handling flow comprises:
and in the exception handling process, calling a preset function, and switching the execution environment of the processor into a machine mode in OpenSBI from an operating system according to the preset function.
5. The instruction extension method according to claim 3, wherein after the step of generating and calling the extended instruction function library corresponding to the instruction to be extended in the OpenSBI execution environment, the method further includes:
and updating the PC address of the MEPC register in the processor, and using the PC address as a preset instruction pointer.
6. The instruction extension method according to claim 1, wherein the step of generating and calling an extended instruction function library corresponding to the instruction to be extended in the OpenSBI execution environment includes:
generating a library function corresponding to the instruction to be expanded in the OpenSBI execution environment;
and obtaining and calling a function library corresponding to the library function according to the library function.
7. The instruction extension method according to claim 5, wherein after completing the execution of the extended instruction function library, exiting the exception handling process according to a preset instruction pointer, and switching the execution environment from OpenSBI to an operating system, the step of completing instruction extension includes:
after the operation of the extended instruction function library is finished, executing the PC address of the MEPC register, and updating a plurality of preset CSR registers in the processor again;
and switching the execution environment from OpenSBI to a supervisor mode of an operating system according to the PC address of the MEPC register, and finishing instruction expansion.
8. The instruction expansion method of claim 1, wherein prior to the step of updating the PC address of the MEPC register in the processor and using the PC address as a preset instruction pointer, further comprising:
and calling a preset registration function to register the extended instruction function library.
9. An instruction expansion system, characterized in that the instruction expansion system comprises: memory, a processor and an instruction extension program stored on the memory and executable on the processor, which when executed by the processor implements the steps of the instruction extension method of any one of claims 1 to 7.
10. A computer-readable storage medium, characterized in that the computer-readable storage medium has stored thereon an instruction extension program which, when executed by a processor, implements the steps of the instruction extension method of any one of claims 1 to 7.
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