CN106970825B

CN106970825B - ARM7 simulation target machine implementation method based on GDB configurable framework

Info

Publication number: CN106970825B
Application number: CN201710141004.5A
Authority: CN
Inventors: 吴翔虎; 陶永超; 曲明成
Original assignee: Shenzhen Academy of Aerospace Technology
Current assignee: Shenzhen Academy of Aerospace Technology
Priority date: 2017-03-10
Filing date: 2017-03-10
Publication date: 2020-07-14
Anticipated expiration: 2037-03-10
Also published as: CN106970825A

Abstract

The invention provides an ARM7 simulation target machine implementation method based on a GDB configurable framework, wherein a host machine operated by a simulation target machine is based on a Windows system, a processor simulation kernel and simulation external equipment are provided in the form of a dynamic link library D LL, the GDB loads a processor simulation kernel D LL, and the processor simulation kernel loads a simulation peripheral D LL.

Description

ARM7 simulation target machine implementation method based on GDB configurable framework

Technical Field

The invention relates to the technical field of embedded systems, in particular to a realization method of an ARM7 simulation target machine.

Background

At present, embedded systems have gone into the lives of people unconsciously, such as smart phones, smart refrigerators, high-intelligent automobiles, and the like. In these terminals, the shadow of the embedded system exists. The embedded system is a special computer system which takes application as a center, takes computer technology as a basis, and has strict requirements on software and hardware cutting, functions, reliability, cost, volume and power consumption.

The development of the embedded system comprises two parts of hardware and software, the development of the hardware is usually prior to the development of the software, and the design, the manufacturing and the debugging process of the hardware usually consume a large amount of time, which inevitably leads to the delay of the initial node of the software development and causes the delay of the whole development progress. Therefore, the cooperative development of software and hardware related methods and theories has been the direction of efforts in academia and industry. Therefore, the simulation target machine based on the specific architecture enters the sight of people, and can simulate a hardware environment by software and provide hardware resource simulation required by running of test codes, so that after the requirement of hardware is provided, software can be developed and debugged without real hardware leaving factory. However, such simulation environments are often very costly and have a single system, such as an ARM architecture, a SPARC architecture, and an X86 architecture, each architecture has its own independent set of simulation environment, and thus, the architecture is not universal, and very inconvenient to use, and a great burden is imposed on enterprise development cost.

Disclosure of Invention

In order to solve the problems in the prior art, the invention firstly optimizes and reforms the traditional GDB structure, so that the GDB structure increases the support for configurability on the basis of providing file analysis and debugging functions, has a universal framework and supports various system structures; then, on the basis of a GDB configurable framework, a method for realizing ARM7 simulation of a target machine is provided.

In order to achieve the purpose, the invention is realized by the following technical scheme:

an ARM7 simulation target machine implementation method based on a GDB configurable framework is characterized in that a host machine running by the simulation target machine is based on a Windows system, a processor simulation kernel and simulation external equipment are provided in the form of a dynamic link library D LL, the GDB loads the processor simulation kernel D LL, and the processor simulation kernel loads simulation external equipment D LL, and the method comprises the following steps:

and (3) optimizing the universality of the GDB:

firstly, transforming a functional layer of the GDB, performing universality expansion on a data structure related to a target structure in the GDB to enable the GDB to support various target structures, simultaneously, completely changing tightly coupled parts of data interaction and function calling into a universal calling interface, extracting a simulator and separating the simulator from the GDB, and providing the simulator in a dynamically loadable dynamic link library form;

then, transforming a target abstract layer of the GDB to make the GDB capable of analyzing various executable file structures;

the simulation target layer of the GDB is reformed, the simulation target layer is directly pulled out from the GDB, the GDB can only access a general interface, the realization of the function and the interface of the simulator is provided by a general simulation eukaryotic body in a dynamic link mode, and the universality optimization of the GDB on the simulation access of the instruction set is completed;

the method comprises the steps of realizing an instruction set simulator module of an ARM7 architecture under a configurable framework of a GDB, constructing a simulation kernel of an ARM7 simulation target machine, and specifically determining the following basic operations of 1) updating operation of a three-stage pipeline, 2) condition code judgment of an instruction, 3) shifting operation, 4) A L U operation, 5) register access and 6) memory access according to the characteristics of an ARM7 processor architecture and an instruction set, wherein the simulation of most instruction execution logic can be completed through the basic operations.

Drawings

FIG. 1 is a schematic diagram of the overall structure of the simulation target machine system of the present invention;

FIG. 2 is a GDB hierarchy diagram;

FIG. 3 is a schematic diagram of the association between a configurable GDB and a simulation kernel;

FIG. 4 is a diagram of a generic interface of a configurable GDB with an emulation core;

FIG. 5 is a schematic diagram of an executable file parsing execution process;

FIG. 6 is a flowchart of an ARM7 kernel emulation function;

fig. 7 is a schematic diagram of an immediate shift process.

Detailed description of the preferred embodiments

The present invention will be described in further detail with reference to the following detailed description and accompanying drawings.

The main function of the simulation target machine designed by the invention is to simulate the processing capacity of processors such as ARM7 and the like to an instruction set. After the simulator obtains the executable program file, the code segment, the data segment and the like of the application program are loaded into the virtual memory of the simulator through the analysis of the GDB, and then the simulator can fetch, decode and execute in the memory, so that the running effect on a real ARM7 processor can be simulated. Meanwhile, the whole simulation environment also provides a plurality of simulation peripherals which work together with the processor simulation kernel to build the simulation environment required by the user.

The overall structure of the simulation target machine system is shown in figure 1, a host machine for running the simulation target machine is based on a Windows system, a processor simulation kernel and simulation external equipment are provided in a form of a dynamic link library D LL, a GDB loads the processor simulation kernel D LL, and a processor simulation kernel loads a simulation peripheral D LL.

GDB (the GNU Project Debuger) is a powerful program debugging tool under UNIX published by GNU open source organizations. Generally, the GDB mainly performs the following four functions:

1) and starting the debugged program, and optionally operating the program according to the customized requirement.

2) The program being debugged may be allowed to stall at the specified debug breakpoint.

3) When a program is stopped, what happens in the program at that time can be checked.

4) Dynamically changing the execution environment of the program.

The GDB has many functional layers, and communication control is performed between the layers by using a certain protocol, the chromatographic structure analysis of the GDB is shown in fig. 2, and the GDB can be roughly divided into 5 layers: the device comprises an I/O abstraction layer, a control layer, a functional layer, a target abstraction layer and a simulation target layer. The I/O abstraction layer mainly processes information interaction operations such as GDB command cycle and the like; the control layer mainly carries out operations such as command analysis, expression analysis, information extraction and the like; the functional layer is used for responding to specific commands and comprises a large number of processing functions and corresponding structures; the target abstract layer is used for carrying out operations such as symbol analysis and the like on the executable file; the simulation target layer at the bottom layer is used for performing simulation execution on the executable program to generate a result.

However, the conventional GDB can only complete the configuration of one architecture in the initial configuration stage, and cannot satisfy the general support for all architectures, so that the conventional GDB needs to be optimized and modified to increase the support for configurability on the basis of providing file parsing and debugging functions, has a general framework, supports multiple architectures, i.e., replaces the simulation target layer with the target simulation kernel, and finds the architecture-dependent part in each upper layer thereof to perform consistent modification. The GDB is associated with the instruction set emulator core as shown in figure 3.

The specific optimization and modification method comprises the following steps:

1) functional layer: i.e., GDB logic functions, this hierarchy contains some data structure settings, function implementations, etc. associated with the target architecture. The original GDB can only load an instruction set simulator (or called target core and simulated eukaryotic) with a target system structure, data interaction between the GDB and the simulator is called a tight coupling state, or called a function call relationship, and can not support various structures, and the GDB debugging and analyzing function and the simulator are coupled and compiled, and finally become an execution file, and can not be expanded. Only one target core can be used for one finished GDB, and the universality of the GDB is limited. The invention firstly modifies the functional layer of GDB, expands the data structure related to the target structure in GDB to make it able to support multiple target structures, and changes the tightly coupled part of data interaction and function call into a general call interface, extracts the simulator and separates it from GDB, and provides it in dynamic link library form capable of dynamic loading. Thus, the GDB after modification is an access universal interface, and is not required to be compiled together with a target core, and the structure of the GDB is separated from that of a single debugger. The interaction between the simulator and the function call and the data is completed through a universal interface, as shown in figure 4.

Therefore, the functional layer of the GDB completes the improvement of the universality. In summary, there are 2 main aspects: 1) the data structure related to the GDB and the target structure is expanded to support various structures; 2) the function call tightly coupled part is entirely changed into a call to the general purpose interface.

2) The target abstract layer carries out operations such as symbol analysis and the like on the executable file, the original GDB can only analyze the file structure corresponding to the structure of the target simulator because only one target simulator can be supported, and the GDB can analyze various executable file structures such as an E L F file, a COFF file and the like.

3) Simulating a target layer: the layer is used as an instruction set simulator in the original GDB structure and needs to be compiled together with the GDB, the layer is directly extracted from the GDB, the GDB can only access a general interface, the realization of the function and the interface of the simulator is provided by a general simulated eukaryotic body in a dynamic link mode, and the universality optimization of the GDB on the instruction set simulation access is completed.

The above is a brief description of the general optimization of GDB. The optimization method and the target machine interface standard under the general framework are an innovation of the invention and are core technologies.

And next, an instruction set simulator module of an ARM7 architecture is realized under a configurable framework of the GDB, and a simulation kernel of an ARM7 simulation target machine is constructed.

The ARM processor has 37 32-bit registers, including: 31 general purpose registers containing a Program Counter (PC); 6 status registers, but only 12 bits of them are used. These registers are grouped by mode, each mode using its own registers.

ARM7 supports 7 processor modes, with most applications executing in user mode. When the processor is operating in user mode, the executing program cannot access certain protected system resources, nor can it change mode unless an exception occurs. This allows the operating system to control the use of system resources. The other modes than the user mode are called privileged modes. Privileged mode has free access to system resources and changes modes.

The ARM7 instruction set is very rich, such as conditional execution instructions, branch and branch chaining instructions, soft interrupt instructions, data processing instructions, multiply instructions, data transfer instructions, multi-register transfer instructions, and so forth.

The simulator of the invention aims to simulate a real ARM7 hardware environment, reasonably and completely simulate registers, working modes and all instructions of the simulator, and provides the simulation in the form of a dynamic link library D LL. GDB carries out symbol analysis on an executable program file, and then information such as code segments, data segments and the like is loaded into a virtual memory of a simulation core, the simulation core carries out instruction fetching in the memory and then decoding execution, the process is shown in figure 5, and the whole simulation process is shown in figure 6:

fig. 6 shows a case where the emulation core receives a call of a continuous execution command under a normal condition, and further performs instruction fetching and decoding execution according to the current program counter PC value. In the above flow, the normal exit of the program is not indicated, but the simulation flow is exited only when a breakpoint instruction is encountered.

Typically, the execution of an instruction requires several hardware operations, such as reading operands, computing the result, and writing the result back to a register. The present invention also utilizes the above features in describing the instruction functionality. First, the basic hardware operations (e.g., pipelining) are described in C language. Then, after the decoding is completed, the operation corresponding to the instruction is selected according to the type of the instruction, and the operations are sequenced according to the dependency relationship among the operations, that is, all the operations and the time relationship of the operations are determined.

In light of the features of the ARM7 processor architecture and instruction set, the present invention defines several basic operations:

1) three stage pipeline update operation

Function definition: voidupdatePipe ()

Instruction fetching is required before the instruction is executed. Since ARM7 supports a three stage pipeline, most of the instructions to be executed are in the pipeline, and the pipeline is updated after the instructions that need to be executed this time are fetched.

2) Condition code determination for instructions

Function definition: pool charge ()

The condition code judgment of the instruction judges whether the instruction is executed according to the condition flag bit in the CPSR by the high-order 4-bit condition code in the ARM instruction coding. Since condition codes have 16 coding formats in common, it is possible to define an array of function pointers of length 16, with a decision being made for each case specific function. In addition, the function is directly positioned through the value of the upper 4 bits, and the running consumption can be reduced.

3) Shift operation

Function definition: UNIT32shiftOperand (UNIT32, UNIT8)

Firstly, judging the representation form of a second operand in an instruction, acquiring operation data if the representation form is an immediate mode, and setting a C condition mark in the CPSR; if in register form or register shift form, the particular shift function is selected based on the shift operand.

4) A L U operation

Function definition: basic operation

A L U is used to perform fixed-point arithmetic, logical operation and various shift operations on binary information.

5) Register access

Function definition: boul GetReg (UNIT32nRegID, UNIT32 pValue)

bool SetReg(UNIT32nRegID,UNIT32nVAlue)

The register is read through a specific function, and the register number is directly given. This requires the emulator to uniformly number all registers in advance.

6) Memory access

Function definitions the function definition is the function definition of the pool GetMen (UNIT32Addr, UNIT32n L ength,

UNIT32*pBuff,UNIT32nDataSize)

bool SetMem(UNIT32Addr,UNIT32nLength,

UNIT32*pBuff,UNIT32nDataSize)

the memory access is performed by a specific function. Information such as the start address of the access, the data width, etc. needs to be given. The function will then place the data in the designated buffer as required.

Through the above basic operations, simulation of most instruction execution logic can be completed. Taking data processing as an example, fig. 7 follows.

Similarly, various exception modes are defined in the simulator, and vector entry addresses of various exceptions are set, which are defined as follows:

meanwhile, a function ARMul _ Abort () for processing various exceptions is also realized, and the pseudo code thereof is realized as follows:

in order to capture the abnormity, the invention is provided with an abnormity entrance at three positions. These three positions are:

1) before the simulator fetches instructions: for catching reset exceptions, fast interrupt exceptions, and general interrupt exceptions.

2) After the simulator fetches and decodes, before executing: for catching undefined instruction exceptions and prefetch termination exceptions.

3) In the execution of the simulator instruction: for capturing software interrupt exceptions and data termination exceptions.

The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.

Claims

1. A realization method of an ARM7 simulation target machine based on a GDB configurable framework is characterized in that a host machine operated by the simulation target machine is based on a Windows system, a processor simulation kernel and simulation external equipment are provided in a dynamic link library D LL form, the GDB loads the processor simulation kernel D LL, and the processor simulation kernel loads simulation peripheral equipment D LL, and the method comprises the following steps:

and (3) optimizing the universality of the GDB:

and an instruction set simulator module for realizing an ARM7 architecture under a configurable framework of the GDB, and constructing a simulation kernel of an ARM7 simulation target machine, specifically:

according to the characteristics of an ARM7 processor architecture and an instruction set, the method comprises the following operations of 1) updating operation of a three-stage pipeline, 2) condition code judgment of an instruction, 3) shifting operation, 4) A L U operation, 5) register access and 6) memory access, and the simulation of instruction execution logic is completed through the operations.

2. The method as claimed in claim 1, wherein the instruction set emulator emulates a real ARM7 hardware environment, reasonably and completely emulates registers, operating modes and all instructions of the ARM7 hardware environment, and provides the emulations in the form of a dynamic link library D LL, the GDB performs symbol analysis on an executable program file, then code segment information and data segment information are loaded into a virtual memory of the emulation core, and the emulation core performs instruction fetching in the memory and then decoding execution.

3. The method of claim 1, wherein: the function definition of the update operation of the three-stage pipeline is as follows: before the instruction is executed, the instruction fetching operation is required; the instruction to be executed is in the three-stage pipeline, and after the instruction needing to be executed at this time is obtained, the three-stage pipeline is updated.

4. The method of claim 1, wherein: the function definition of the condition code judging operation of the instruction is as follows: the method comprises the following steps of (1) carrying out cool charge () to define a function pointer array with the length of 16, and judging by adopting a special function in each case; the function is directly positioned through the value of the upper 4 bits, and the running consumption is reduced.

5. The method of claim 1, wherein: the function of the shift operation defines: the UNIT32shiftOperand (UNIT32, UNIT8) firstly judges the representation form of a second operand in the instruction, acquires operation data if the representation form is an immediate number mode, and sets a C condition mark in the CPSR; if in register form or register shift form, the particular shift function is selected based on the shift operand.

6. The method of claim 1, wherein said A L U operation essentially completes fixed point arithmetic operations, logical operations, and various shifting operations on binary information.

7. The method of claim 1, wherein: various exception modes are defined in the instruction set emulator, and vector entry addresses of various exceptions are set.

8. The method of claim 7, wherein: in order to capture the abnormity, abnormity inlets are arranged at three positions; these three positions are: 1) before the simulator fetches instructions: for catching reset exceptions, fast interrupt exceptions, and general interrupt exceptions; 2) after the simulator fetches and decodes, before executing: for catching undefined instruction exceptions and prefetch termination exceptions; 3) in the execution of the simulator instruction: for capturing software interrupt exceptions and data termination exceptions.