CN115373499B

CN115373499B - Reset circuit and electronic device

Info

Publication number: CN115373499B
Application number: CN202211311478.7A
Authority: CN
Inventors: 李明良
Original assignee: Honor Device Co Ltd
Current assignee: Honor Device Co Ltd
Priority date: 2022-10-25
Filing date: 2022-10-25
Publication date: 2023-04-14
Anticipated expiration: 2042-10-25
Also published as: CN115373499A; CN117930949A

Abstract

The application provides a reset circuit and electronic equipment, relates to the circuit field. Reset circuit in this application sets up in electronic equipment, includes: the first charging circuit, the second charging circuit and the reset signal output circuit; the first charging circuit is used for charging the second charging circuit in the process of being electrically connected with the charger and disconnected from the charger for N times continuously, N is an integer larger than 1, and the time length of the first charging circuit from the electrical connection with the charger to the disconnection for N times continuously is less than 1 minute; a second charging circuit for outputting a control signal to the reset signal output circuit; and the reset signal output circuit is used for outputting a reset signal when detecting that the voltage value of the control signal exceeds a preset threshold value. By adopting the reset circuit in the application, the reset signal is generated in the process of repeatedly electrically connecting the charger and the electronic equipment, the electronic equipment is triggered to reset, the physical key in the electronic equipment is not required to be relied on, and meanwhile, the cost of the electronic equipment is also reduced.

Description

Reset circuit and electronic device

Technical Field

The present application relates to the field of circuits, and in particular, to a reset circuit and an electronic device.

Background

With the development of intelligent terminals, the intelligent terminals are increasingly used by users. During the operation of the intelligent terminal (such as an intelligent watch and a bracelet), a fault (such as program running) may occur, so that the intelligent terminal is halted, and the intelligent terminal needs to be reset to recover the operation of the intelligent terminal. At present, the intelligent terminal is reset in various modes, one mode is that a watchdog circuit is arranged in the intelligent terminal, and a reset signal is output through the watchdog circuit so as to reset the intelligent terminal. The other mode is that a reset key is arranged on the intelligent terminal, and when a user presses the reset key, the MCU is triggered to carry out reset operation.

However, the cost of the watchdog circuit is high, and corresponding software configuration is required, which increases the cost of the intelligent terminal. And another mode of resetting the intelligent terminal needs to rely on a reset key, and if the intelligent terminal is not provided with the reset key, the intelligent terminal cannot realize the reset function through the reset key.

Disclosure of Invention

In order to solve the technical problem, the application provides a reset circuit and an electronic device, so that in the process of repeatedly electrically connecting a charger and the electronic device, a reset signal is generated to trigger the electronic device to perform reset operation, the electronic device does not need to rely on an entity key in the electronic device, and meanwhile, the cost of the electronic device is also reduced.

In a first aspect, the present application provides a reset circuit disposed in an electronic device, the reset circuit including: the first charging circuit, the second charging circuit and the reset signal output circuit; the first charging circuit is used for charging the second charging circuit in the process of being electrically connected with the charger and disconnected from the charger for N times, wherein N is an integer larger than 1, and the time length of the first charging circuit from the electrical connection with the charger to the disconnection for N times is less than 1 minute; a second charging circuit for outputting a control signal to the reset signal output circuit; and the reset signal output circuit is used for outputting a reset signal when the voltage value of the control signal is detected to exceed a preset threshold value, and the reset signal is used for triggering a microprocessor in the electronic equipment to carry out reset operation.

Like this, through the operation that the charger is connected to the disconnection from the electricity with first charging circuit in succession many times for first charging circuit can postpone to charge for the second charging circuit, avoids appearing the charger and is connected the problem that just triggers the operation that resets with the electronic equipment electricity, simultaneously, because first charging circuit is continuous N times and the charger is less than 1 minute from being connected to the time of disconnection, can avoid the problem of the time overlength of charging to the second charging circuit, improves the user and carries out the use of the operation that resets and experience. Meanwhile, due to the fact that the charger needs to be plugged and pulled for many times, the voltage of the second charging circuit is gradually increased, the voltage of the control signal output by the second charging circuit is also gradually increased, when the voltage value of the control signal of the second charging circuit exceeds a preset threshold value, the reset signal output circuit can be triggered to output the reset signal, the reset circuit does not adopt a watchdog circuit, and does not need to rely on physical keys in the electronic equipment, the cost of the electronic equipment is reduced, and meanwhile, the application scenes of the reset circuit are increased.

According to a first aspect, a first charging circuit comprises: the first capacitor, the discharge component and the first diode; the second charging circuit includes: a second capacitor and a first resistor; the first end of the first capacitor is electrically connected with the anode of the first diode and the first end of the discharge assembly; the second end of the discharge assembly is grounded; the cathode of the first diode is electrically connected with the first end of the second capacitor and the first end of the first resistor; the first end of the second capacitor is electrically connected with the input end of the reset signal output circuit; the second end of the second capacitor is electrically connected with the second end of the first resistor; the second end of the first resistor is grounded; the output end of the reset signal output circuit is electrically connected with the reset end of the microprocessor; the second end of the first capacitor and the second end of the discharging assembly are used for being electrically connected with the charger.

Therefore, at the moment that the first capacitor is connected with the charger, because the voltage at the two ends of the first capacitor cannot suddenly change, pulse voltage is formed at the first end of the first capacitor and can charge the second capacitor, when the first capacitor is disconnected with the charger, the first capacitor releases the discharge amount through the discharge assembly, the voltage at the two ends of the first capacitor is reduced, and the pulse voltage used for charging the second capacitor is generated at the moment that the first capacitor is connected with the charger next time. For example, a discharging component (e.g., a discharging component including a fourth resistor) may form a discharging loop with an equivalent resistor (e.g., a third resistor) in a charging management circuit of the electronic device, or the first capacitor may form a discharging loop with the discharging component (e.g., a third resistor and a fourth resistor). Because the first charging circuit comprises the first diode and the cathode of the first diode is electrically connected with the first end of the second capacitor, the second capacitor can not be discharged reversely when the first capacitor is disconnected with the charger; meanwhile, the first resistor in the second charging circuit can release the electric quantity in the second capacitor, so that the accumulated electric quantity when the charger normally charges the electronic equipment every time is avoided, and the problem of false triggering of reset operation can be avoided.

According to a first aspect, the first charging circuit further comprises: a second resistor; the first end of the second resistor is electrically connected with the cathode of the first diode, and the second end of the second resistor is electrically connected with the first end of the second capacitor and the first end of the second resistor. In this way, the second resistor is added in the first charging circuit, so that the current flowing into the second capacitor can be limited, and the speed of charging the second capacitor by the first capacitor can be controlled through the second resistor. Through the second resistance that sets up, can also keep apart first electric capacity and reset signal output circuit's effect, avoid first electric capacity to the second electric capacity in-process of charging, the problem of spurious triggering reset signal output circuit has promoted reset circuit's anti-ESD (Electro-Static discharge)'s performance.

According to a first aspect, the first charging circuit further comprises: a second resistor; the first end of the second resistor is electrically connected with the first end of the first capacitor, and the second end of the second resistor is electrically connected with the anode of the first diode. In this way, the second resistor is added in the first charging circuit, so that the current flowing into the second capacitor can be limited, and the speed of charging the second capacitor by the first capacitor can be controlled through the second resistor. Through the second resistance who sets up, can keep apart first electric capacity and reset signal output circuit's effect, avoid first electric capacity to the second electric capacity in-process of charging, the problem of spurious triggering reset signal output circuit has promoted reset circuit's anti-ESD (Electro-Static discharge)'s performance.

According to a first aspect, a discharge assembly comprises: a third resistor and a fourth resistor; the first end of the fourth resistor is electrically connected with the first end of the first capacitor; the second end of the fourth resistor is electrically connected with the first end of the third resistor; the second end of the third resistor is electrically connected with the second end of the first capacitor; the first end of the third resistor is grounded. Like this, this first electric capacity, third resistance and fourth resistance can form the return circuit that discharges, and the third resistance that sets up can increase the speed of discharging to first electric capacity for next time when this first electric capacity contacts with the charger, the both ends voltage of this first electric capacity is littleer, can charge for the second electric capacity more efficiently.

According to a first aspect, a discharge assembly comprises: a third resistor and a second diode; the second end of the third resistor is electrically connected with the second end of the first capacitor; the first end of the third resistor is grounded and is electrically connected with the input end of the second diode; the output end of the second diode is electrically connected with the first end of the first capacitor. In this way, the discharge component may include a third resistor and a second diode, so that the first capacitor, the third resistor and the second diode may form a pair discharge loop to reduce the voltage across the first capacitor; meanwhile, the problem that negative voltage occurs to the first capacitor after power failure can be avoided.

According to a first aspect, a first charging circuit comprises: the first capacitor, the discharge component and the first diode; the second charging circuit includes: a second capacitor and a first resistor; the first end of the first capacitor is electrically connected with the input end of the first diode and the first end of the discharge assembly; the second end of the discharge assembly is grounded; the output end of the first diode is electrically connected with the first end of the second capacitor and the first end of the first resistor; the first end of the second capacitor is electrically connected with the input end of the reset signal output circuit; the second end of the second capacitor is electrically connected with the second end of the first resistor; the second end of the first resistor is grounded; the output end of the reset signal output circuit is electrically connected with the reset end of the microprocessor; the second end of the first capacitor and the second end of the discharging assembly are used for being electrically connected with the charger.

Therefore, at the moment that the first capacitor is connected with the charger, because the voltage at the two ends of the first capacitor cannot suddenly change, pulse voltage is formed at the first end of the first capacitor and can charge the second capacitor, when the first capacitor is disconnected with the charger, the first capacitor releases the discharge amount through the discharge assembly, the voltage at the two ends of the first capacitor is reduced, and the pulse voltage used for charging the second capacitor is generated at the moment that the first capacitor is connected with the charger next time. The second end of the discharging component (for example, the discharging component comprises the fourth resistor) is grounded, so that a discharging loop can be formed by the second end of the discharging component and an equivalent resistor (for example, the third resistor) in a charging management circuit of the electronic equipment, a new component does not need to be additionally arranged, and the cost of a reset circuit is reduced.

According to a first aspect, a discharge assembly comprises: a fourth resistor; the first end of the fourth resistor is electrically connected with the first end of the first capacitor; the second end of the fourth resistor is electrically connected with the first end of the third resistor, and the third resistor is an equivalent resistor of a charging management circuit in the electronic equipment; the second end of the third resistor is electrically connected with the second end of the first capacitor; the first end of the third resistor is grounded. Therefore, the equivalent resistor of the charging management circuit of the electronic equipment can be used as the third resistor, so that a device does not need to be additionally arranged in the reset electronics, and the cost of the reset resistor can be saved.

According to a first aspect, a discharge assembly comprises: a second diode; the second end of the first capacitor is electrically connected with the second end of a third resistor, and the third resistor is an equivalent resistor of a charging management circuit in the electronic equipment; the first end of the third resistor is grounded and is electrically connected with the input end of the second diode; the output end of the second diode is electrically connected with the first end of the first capacitor. Therefore, the equivalent resistor of the charging management circuit of the electronic equipment can be used as the third resistor, so that a device does not need to be additionally arranged in the reset electronic, and the cost of the reset resistor can be saved.

According to a first aspect, a reset signal output circuit includes: an N-type metal oxide semiconductor (NMOS) transistor; the grid electrode of the NMOS transistor is used as the input end of the reset signal output circuit; the drain electrode of the NMOS transistor is used as the output end of the reset signal output circuit; the source electrode of the NMOS transistor is electrically connected with the second end of the first resistor. Therefore, the reset signal output circuit is realized by adopting the NMOS transistor, so that the reset signal output circuit is simple, and the cost of the reset signal output circuit is reduced.

According to a first aspect, a reset signal output circuit includes: a not circuit; the input end of the NOT circuit is used as the input end of the reset signal output circuit; and the output end of the NOT circuit is used as the output end of the reset signal output circuit. Therefore, the reset signal output circuit can adopt a non-circuit, and the input signal and the output signal of the non-circuit are opposite to each other, so that the MCU can be triggered to carry out reset operation.

According to a first aspect, a reset signal output circuit includes: a comparator; the negative input end of the comparator is used as the input end of the reset signal output circuit; a positive input end of the comparator is electrically connected with a reference voltage, and the voltage value range of the reference voltage is 0.5V to 1V; the output end of the comparator is used as the output end of the reset signal output circuit, wherein the reset end of the microprocessor is triggered by a low level signal. In this way, the positive input end of the comparator is electrically connected with a reference voltage, and the voltage value range of the reference voltage is 0.5V-1V, namely, when the comparator detects that the voltage of the negative input end is less than that of the positive input end, a high level is output; when the comparator detects that the voltage of the negative input end is greater than the voltage of the positive input end, a low level signal is output, and because the reset end of the MCU is triggered by the low level signal, when the reset end of the MCU receives the low level signal, the MCU is triggered to carry out reset operation. The comparator is used as the reset signal output circuit, so that the mode is simple, and the problem of false triggering is not easy to occur.

According to the first aspect, the fourth resistor has a smaller resistance than the first resistor. Therefore, the resistance value of the fourth resistor is smaller than that of the first resistor, so that when the first capacitor charges the second capacitor, the electric quantity consumed by the fourth resistor is larger than that consumed by the second capacitor, and the problem that the first capacitor is full of electric quantity of the second capacitor for the first time is avoided.

According to the first aspect, the time period from the electrical connection to the disconnection of the first charging circuit and the charger ranges from 1 second to 5 seconds. Therefore, when the time from the electric connection to the disconnection of the first charging circuit and the charger is longer than 5 seconds, the reset circuit can be conducted to output the reset signal for too long, and the use experience of a user is reduced.

In a second aspect, the present application provides an electronic device comprising: the reset circuit and the microprocessor of the first aspect and any implementation manner of the first aspect correspond, and a reset signal output end of the reset circuit is electrically connected to a reset end of the microprocessor.

According to a second aspect, the electronic device is a smart watch, a smart bracelet or a smart card machine.

According to the second aspect, no button is provided on the smart watch or the smart bracelet.

Implementation manners of the second aspect correspond to any one of the implementation manners of the first aspect and the first aspect, respectively. For technical effects corresponding to the implementation manner of the second aspect, reference may be made to the technical effects corresponding to any one of the implementation manners of the first aspect and the first aspect, and details are not described here.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the description of the embodiments of the present application will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without inventive exercise.

FIG. 1 is a schematic diagram of an exemplary illustrative electronic device;

fig. 2 is a schematic diagram illustrating a structure of a reset circuit;

FIG. 3 is a circuit schematic diagram of an exemplary reset circuit;

FIG. 4a is a schematic diagram illustrating an exemplary connection of an analog charger to a smart watch;

FIG. 4b is a schematic diagram illustrating yet another analog charger coupled to a smart watch;

FIG. 5 is a circuit schematic diagram illustrating the inclusion of a second resistor in the first charging circuit;

fig. 6 is a circuit schematic diagram exemplarily showing that the first charging circuit includes the second resistor;

fig. 7 is a circuit schematic diagram exemplarily showing that a third resistor is further included in the reset circuit;

FIG. 8 is a circuit schematic diagram illustrating an exemplary reset circuit including a comparator;

FIG. 9 is a circuit schematic diagram illustrating an exemplary reset circuit including a NOT circuit;

FIG. 10 is a diagram illustrating an example of detecting voltages at various positions using an oscilloscope;

FIG. 11 is a waveform diagram illustrating 4 detection points in a scene;

FIG. 12 is a waveform diagram illustrating 4 detection points in a scene;

FIG. 13 is a waveform diagram illustrating 4 detection points in a scene;

fig. 14 is a waveform diagram of 4 detection points in an exemplary scenario.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some, but not all, embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

The electronic device in the embodiment of the application can be wearable electronic device, such as smart watch, bracelet, etc., and certainly, the electronic device can also be other devices, such as card machine (portable card machine), etc. The embodiment of the present application does not limit the specific form of the electronic device. For convenience of description, the electronic device is exemplified as a smart watch hereinafter.

Fig. 1 is a schematic diagram of an exemplary electronic device.

As shown in fig. 1, the smart watch 100 may include a motherboard, a display screen, a battery, and the like. The motherboard may be integrated with a Microprocessor (MCU), an internal memory, a charging circuit, and the like. Certainly, the smart watch may further include other components, and other circuit structures may also be integrated on the motherboard, which is not limited in this embodiment of the present application. The charging circuit of the intelligent watch comprises a power management circuit and a charging management circuit. The power management circuit is connected with the lithium battery, the charging management circuit and the microprocessor. The internal memory in the smart watch may be used to store computer executable program code, which may include instructions. The microprocessor executes various functional applications and data processing of the mobile phone by executing instructions stored in the internal memory. The microprocessor, the internal memory, the charging circuit and the like integrated on the mainboard comprise one or more chips.

The charging management circuit is configured to receive a charging input from a charger. The charger may be a wired charger, and the charging management circuit may receive a charging input of the wired charger through the USB interface.

The power management circuit receives the input from the battery and/or the charging management circuit and supplies power to the microprocessor, the internal memory, the external memory, the display screen, the wireless communication module, and the like.

At present, the intelligent watch is more and more widely applied, and the intelligent watch has the problem of crash caused by program runaway in the operation process. Generally, the entity keys can be arranged in the intelligent watch, and a user can press the entity keys for a long time, so that the reset circuit inputs a reset signal to the MCU in the intelligent watch and triggers the MCU to reset. The reset signal may refer to a signal for triggering reset; and assuming that the reset signal is a low-level signal, triggering to perform reset operation when a reset terminal in the MCU receives the low-level signal. However, this reset mode relies on physical keying. As shown in fig. 1, the smart watch in fig. 1 is not provided with a physical button, and when the smart watch has a program runaway fault, the smart watch cannot generate a reset signal through the physical button. In one example, since no physical keys are provided in the smart watch 100, a watchdog circuit may be further provided in the smart watch, and the watchdog chip is electrically connected to the microprocessor in the smart watch 100. When the intelligent watch is in a normal running state, the MCU inputs a dog feeding signal to the input end of the watchdog circuit at regular time, and the watchdog circuit receives the dog feeding signal and does not output a reset signal. When the MCU crashes, the MCU cannot continuously send a dog feeding signal to the watchdog circuit, and the watchdog circuit outputs a reset signal because the watchdog circuit does not timely receive the dog feeding signal, so that the MCU is triggered to perform reset operation.

Because the watchdog circuit is with high costs, lead to the cost-push of this intelligent wrist-watch, be unfavorable for this intelligent wrist-watch's popularization. If the smart watch is provided with the entity key, the entity key can be pressed by a user to output a reset signal, and the MCU is triggered to perform reset operation, however, the method cannot be applied to the smart watch shown in FIG. 1.

The embodiment of the application provides a reset circuit, and this reset circuit's signal output part can be connected with MCU's in the intelligent wrist-watch reset end electricity, and this reset circuit's input is connected with the charger electricity. When the charger and the reset circuit are connected for a plurality of times, the reset circuit can be triggered to output a reset signal to the reset end of the MCU, so that the MCU is triggered to carry out reset operation. The reset circuit in this example does not need to set a watchdog circuit and does not need to rely on an entity key in the electronic device, so that the reset circuit is low in cost, and the application scene of the reset circuit in the smart watch is improved.

Fig. 2 is a schematic diagram illustrating a structure of an exemplary reset circuit.

The smart watch includes an MCU and a reset circuit, and the reset circuit 10 includes a first charging circuit, a second charging circuit 102, and a reset signal output circuit 103. The first end of the first charging circuit is connected to the first end of the second charging circuit, and the second end of the first charging circuit and the third end of the first charging circuit 101 are used to electrically connect to a charger. The second end of the first charging circuit 101 may also be connected to the ground of the smart watch. The second terminal of the second charging circuit is grounded (i.e., electrically connected to the ground of the smart watch), and the first terminal of the second charging circuit 102 is also electrically connected to the first terminal of the reset signal output circuit. The second terminal of the RESET signal output circuit 103 is grounded, and the third terminal of the RESET signal output circuit 103 is electrically connected to the RESET terminal (i.e., RESET terminal) of the MCU.

In this example, the ground means that the circuit or the component is electrically connected to the ground in the smart watch.

The first charging circuit 101 is used for charging the second charging circuit in the process of being electrically connected with the charger and disconnected from the charger for N times, wherein N is an integer larger than 1, and the time length of the first charging circuit from being electrically connected with the charger to being disconnected from the charger for N times is less than 1 minute. And the second charging circuit 102 is configured to detect that the voltage reaches a preset threshold within a preset time period, and output a control signal to the reset signal output circuit, where the preset time period is less than 1 minute. And the reset signal output circuit 103 is used for outputting a reset signal after receiving the control signal, wherein the reset signal is used for triggering a microprocessor in the electronic equipment to carry out reset operation.

Specifically, when the smart watch crashes and needs to be reset, the user may electrically connect the charger to the second terminal and the third terminal of the first charging circuit 101 in the reset circuit, so that the charger may charge the first charging circuit 101. After a first interval duration, the user disconnects the electrical connection between the charger and the first charging circuit 101 in the reset circuit, and the first interval duration may be 1 to 10 seconds, such as 1 second, 2 seconds, 5 seconds, 8 seconds, 10 seconds, and the like. The user repeats the above-described steps of electrically connecting the charger to the first charging circuit 101N times, and disconnecting the electrical connection of the charger to the first charging circuit 101 after the first interval duration. N is an integer greater than 1, for example, N can be 2, 4, 6, 8, and the like.

The first charging circuit 101 may charge the second charging circuit 102 during N times of the process from being electrically connected to being disconnected from the charger. When the voltage of the second charging circuit 102 reaches a preset threshold, a control signal is output to the reset signal output circuit 103. The reset signal output circuit 103 outputs a reset signal to the reset terminal of the MCU after receiving the control signal.

It should be noted that the second terminal and the third terminal of the first charging circuit 101 in the reset circuit may be used as input terminals for electrically connecting the smart watch and the charger. Meanwhile, the second terminal and the third terminal of the first charging circuit 101 may also be used as input terminals of a charging management circuit in the smart watch, that is, the o1 terminal and the o2 terminal in fig. 2 are also electrically connected to the input terminals of the charging management circuit, respectively.

In this example, because need charger and first charging circuit to connect to the operation of disconnection from the electricity in succession many times, can avoid user's maloperation to lead to the smart watch to reset the operation, simultaneously, in this example, need not to use the watchdog circuit also need not to rely on the entity button in the smart watch, reduced the cost of smart watch, improved the application scene of reset circuit simultaneously.

Fig. 3 is a circuit schematic diagram of an exemplary reset circuit. As shown in fig. 3, the first charging circuit 101 in the reset circuit includes: a first capacitor (e.g., C1 in fig. 3), a discharge component, and a first diode (e.g., D3 in fig. 3). The second charging circuit 102 includes: a second capacitor (e.g., C2 in fig. 3) and a first resistor (e.g., R1 in fig. 3). The reset signal output circuit in this example is illustrated by taking an NMOS transistor (e.g., Q1 in fig. 3) as an example.

Specifically, the discharging component in the first charging circuit 101 is used to discharge the first capacitor, and the discharging component may include one or more resistors, and may further include a resistor and a diode. Alternatively, in this example, the discharge component is illustrated by taking a resistor as an example, as shown by a resistor R4 in fig. 3. A first end of the first capacitor C1 is electrically connected to the anode of the first diode D3 and a first end of the resistor R4; the second terminal of the resistor R4 is grounded. A cathode of the first diode D3 is electrically connected to a first end of the second capacitor C2 and a first end of the first resistor R1; the second end of the first resistor R1 is grounded; the first end of the second capacitor C2 is electrically connected with the grid electrode of the NMOS transistor Q1, and the drain electrode of the NMOS transistor Q1 is electrically connected with the reset end of the microprocessor; the source of the NMOS transistor Q1 is grounded. The second end of the second capacitor C2 is electrically connected with the second end of the first resistor R1; the second end of the first capacitor C1 and the second end of the resistor R4 are used for electrically connecting with a charger. In this example, the capacitance values of the first capacitor C1 and the second capacitor C2 may be set according to practical applications, for example, to reduce the time for charging the second capacitor, the capacitance value of the second capacitor is smaller than that of the first capacitor, for example, the capacitance value of the first capacitor is 10 microfarads; the second capacitor has a capacitance of 2.2 microfarads.

The operation of the reset circuit of fig. 3 will be described in detail with reference to fig. 4 a. Fig. 4a is a schematic diagram illustrating an example of an analog charger coupled to a smart watch.

As shown in fig. 4a, the battery and the resistor R5 are used to simulate a charger, the operation of closing the switch S1 is used to simulate the action of a user to electrically connect the charger with the first charging circuit 101, and the operation of opening the switch S1 is used to simulate the action of a user to electrically disconnect the charger from the first charging circuit 101. The resistor R3 is used for indicating an equivalent resistor in a charging management circuit of the intelligent watch; the second end of the third resistor R3 is electrically connected to the second end of the first capacitor C1; the first end of the third resistor R3 is grounded and is electrically connected to the second end of the resistor R4.

As shown in fig. 4a, at time t1, the user electrically connects the charger to the charging input terminal of the smart watch (i.e., the charger is inserted into a charging hole provided in the smart watch), that is, the charger is electrically connected to the first charging circuit 101 in the reset circuit. At the time t1, the switch S1 is closed, the battery charges the first capacitor C1, and since the voltage across the capacitor cannot change abruptly, at the instant when the switch S1 is closed at the time t1, the charging voltage is applied to the first end of the first capacitor C1, and a pulse voltage is formed at the first end of the first capacitor C1. The pulse voltage formed at the first terminal of the first capacitor C1 charges the second capacitor C2 through the first diode D3. In this example, since the discharging component includes the resistor R4, when the first capacitor C1 charges the second capacitor C2, a part of the current is shunted to the resistor R4. In this example, when the discharging component includes the resistor R4, the resistor R4 can control the amount of electricity charged to the second capacitor C2 each time, so as to avoid the problem of fully charging the second capacitor C2 at a time. Optionally, the resistance value of the resistor R4 is smaller than the resistance value of the first resistor R1. When the resistance of the resistor R4 is smaller than the resistance of the first capacitor R1, the current flowing to the second capacitor C2 can be further reduced, and the problem that the second capacitor C2 is charged fully quickly can be avoided, for example, in this example, the resistor R4 can be set to 5K Ω, and the first resistor R1 is larger than the resistor R4, such as 10K Ω, 20K Ω, 50K Ω, and the like, and in this example, the first resistor R1 is set to 5M Ω. With the increase of the closing time of the switch S1, the voltage across the first capacitor C1 continuously decreases, so that the first capacitor C1 cannot continuously charge the second capacitor C2.

At time t2, the switch S1 is turned off, and the first capacitor C1, the third resistor R3 and the resistor R4 form a discharge circuit 1 due to the presence of the resistor R4 and the equivalent third resistor R3: C1-R3-R4-C1. The third resistor R3 and the resistor R4 can release the electric quantity in the first capacitor C1 to reduce the voltage between the first terminal and the second terminal of the first capacitor C1. At time t2, when the switch S1 is turned off, the second capacitor C2 and the first resistor R1 form a discharge circuit 2: C2-R1-C2. The discharging loop 2 can consume the electric quantity on the second capacitor C2, and can avoid the problem that the voltage of the second capacitor gradually rises to trigger the reset signal output circuit to output the reset signal by mistake when a user uses the charger for charging for a long time. Alternatively, a first resistor with a large resistance may be selected to reduce the discharge speed of the second capacitor C2, and in this example, the first resistor R1 may be set to a resistance of the order of mega ohms, for example, the resistance of the first resistor R1 is 5M Ω.

Meanwhile, the first end of the second capacitor C2 is electrically connected to the gate of the Q1, the electric quantity of the second capacitor C2 is small, and the output voltage does not satisfy the conduction condition of the Q1, for example, the output voltage of the second capacitor C2 is 0.7V for the first time. The turn-on voltage of the NMOS transistor Q1 is not satisfied (e.g., the turn-on voltage is 1.2V), and the NMOS transistor is not turned on. Wherein, the voltage of the reset end of the MCU defaults to a high level.

Alternatively, the turn-on voltage of Vgs (i.e., gate-source voltage) of each NMOS transistor is different, and the turn-on voltage of the NMOS transistor Q1 may be adjusted by a voltage dividing resistor at the time of application. Normally, the on condition of the NMOS transistor is that the voltage difference of Vgs ranges from 0.6 to 1.2v, in this example, the voltage dividing resistance is increased, so that the adjusted on voltage of the NMOS transistor Q1 may be 1.2V. Fig. 4b shows a circuit schematic of the reset circuit after adding a voltage dividing resistor. As shown in fig. 4b, a voltage dividing resistor R6 is added. A first end of the first capacitor C1 is electrically connected to the anode of the first diode D3 and a first end of the resistor R4; the second terminal of the resistor R4 is grounded. A cathode of the first diode D3 is electrically connected to a first end of the second capacitor C2 and a first end of the voltage-dividing resistor R6; the second end of the voltage dividing resistor R6 is electrically connected to the gate of the NMOS transistor Q1, the second end of the voltage dividing resistor R6 is electrically connected to the first end of the first resistor R1, the second end of the first resistor R1 is grounded, and the second end of the second capacitor C2 is grounded. The drain electrode of the NMOS transistor Q1 is electrically connected with the reset end of the microprocessor; the source of the NMOS transistor Q1 is grounded. The second end of the first capacitor C1 and the second end of the resistor R4 are used for being electrically connected with a charger. Due to the arrangement of the divider resistor R6, the on-state voltage of the NMOS transistor Q1 can be adjusted, and the resistance value of the divider resistor may be the same as that of the first resistor.

Alternatively, if a voltage dividing resistor is provided for the NMOS transistor Q1, the voltage dividing resistor may also be used as a discharge resistor of the second capacitor C2, that is, the voltage dividing resistor may be used as the first resistor R1.

In this example, the cathode of the first diode D3 is electrically connected to the first end of the second capacitor C2, so that the problem that the second capacitor C2 cannot be charged due to the reverse discharge of the second capacitor C2 can also be avoided. The difference between time t1 and time t2 may range from [1,5], which in this example is 1 second for time t1 and time t 2. Optionally, with the increase of the off-time of the switch S1, the electric quantity stored in the first capacitor C1 decreases, and the voltage across the first capacitor C1 decreases, which is beneficial to charging the second capacitor C2 by the first capacitor C1 next time.

At time t3, the switch S1 is closed again, and since the first capacitor C1 is discharged at time t2 to time t3, the voltage between the first end and the second end of the first capacitor C1 decreases, and at the moment when the switch S1 is closed, the charging voltage is applied to the first end of the first capacitor C1 again, so as to form a pulse voltage at the first end of the first capacitor C1. At time t3, the pulse voltage charges the second capacitor C2 again through the first diode D3. Optionally, the duration between t2 and t3 may be greater than the duration between t1 and t2, or may be less than or equal to the duration between t1 and t2, which is not limited in this example.

At time t4, the switch S1 is opened, and the first capacitor C1, the third resistor R3 and the resistor R4 form a discharge circuit 1 due to the presence of the resistor R4 and the equivalent third resistor R3: C1-R3-R4-C1. The current in the first capacitor C1 can be discharged through the resistor R4 to reduce the voltage between the first terminal and the second terminal of the first capacitor C1. At time t4, when the switch S1 is turned off, the second capacitor C2 and the first resistor R1 form a discharge loop 2: C2-R1-C2.

In the present example, assuming that the switch S1 is operated from closed to open 4 times, the voltage of the second capacitor C2 gradually reaches a preset threshold, which may be the on-voltage of Vgs in Q1. For example, when the switch S1 is closed for the fourth time, the voltage of the second capacitor C2 reaches the turn-on voltage of Vgs in the NMOS transistor Q1, so that the NMOS transistor Q1 is turned on, the drain voltage of the NMOS transistor is decreased, that is, the drain of the NMOS transistor Q1 outputs a low-level signal, and the reset terminal of the MCU receives the low-level reset signal, and triggers the MCU to perform the reset operation. In this example, the reset terminal of the MCU is triggered by a low level signal. Since the NMOS transistor Q1 is turned on, the electric energy in the second capacitor C2 is continuously consumed, and the voltage of the second capacitor C2 continuously decreases. When the voltage input to the gate of the NMOS transistor Q1 by the second capacitor C2 is a low voltage (i.e., the voltage of the Vgs is less than the turn-on voltage), the drain voltage of the NMOS transistor Q1 changes from a low level to a high level again.

It should be noted that after the fourth switch S1 is closed, the switch S1 and the first capacitor C1 may be electrically disconnected after a time period of t1 to t 2. Alternatively, the switch S1 may not be electrically connected to the first capacitor C1.

The reset circuit in the example is simple, the second capacitor is charged through the process of continuously connecting the charger and the first charging circuit from electricity to disconnection for multiple times, when the voltage of the second capacitor reaches the conduction voltage of the NMOS transistor, the NMOS transistor Q1 outputs low level, and along with the conduction of the NMOS transistor Q1, the NMOS transistor Q1 outputs a reset signal to trigger the MCU to perform reset operation, the output reset signal of the reset circuit does not depend on a physical key, the cost is far less than that of a watchdog circuit, and the cost of electronic equipment is reduced.

In some embodiments, the first charging circuit 101 may further include: a second resistor. The first end of the second resistor is electrically connected with the cathode of the first diode, and the second end of the second resistor is electrically connected with the first end of the second capacitor and the first end of the second resistor. Fig. 5 schematically shows a circuit diagram including a second resistor in the first charging circuit.

As shown in fig. 5, the first charging circuit 101 in the reset circuit includes: a first capacitor (e.g., C1 in fig. 5), a discharge component, a first diode (e.g., D3 in fig. 5), and a second resistor (e.g., R2 in fig. 5). The second charging circuit 102 includes: a second capacitor (e.g., C2 in fig. 5) and a first resistor (e.g., R1 in fig. 5). The reset signal output circuit in this example is explained taking an NMOS transistor (e.g., Q1 in fig. 5) as an example.

Specifically, the discharge device is illustrated as including a resistor, as shown by a resistor R4 in fig. 5. A first end of the first capacitor C1 is electrically connected to an anode of the first diode D3 and a first end of the resistor R4; the second terminal of the resistor R4 is grounded. A cathode of the first diode D3 is electrically connected to a first end of a second resistor R2, and a second end of the second resistor R2 is electrically connected to a first end of the second capacitor C2 and a first end of the first resistor R1; the second end of the first resistor R1 is grounded; the first end of the second capacitor C2 is electrically connected with the grid electrode of the NMOS transistor Q1, and the drain electrode of the NMOS transistor Q1 is electrically connected with the reset end of the microprocessor; the source of the NMOS transistor Q1 is grounded. The second end of the second capacitor C2 is electrically connected with the second end of the first resistor R1; the second end of the first capacitor C1 and the second end of the resistor R4 are used for being electrically connected with a charger. Wherein, resistance R3 is used for instructing the equivalent resistance in the charge management circuit of this smart watch. The second end of the third resistor R3 is electrically connected to the second end of the first capacitor C1; the first end of the third resistor R3 is grounded and electrically connected to the second end of the resistor R4.

In this example, similar to fig. 4a, the battery and the resistor R5 are used to simulate a charger, the operation of closing the switch S1 is used to simulate the action of a user electrically connecting the charger to the first charging circuit 101, and the operation of opening the switch S1 is used to simulate the action of a user electrically disconnecting the charger from the first charging circuit 101.

At time t1, the user electrically connects the charger to the charging input terminal of the smart watch, that is, the charger is electrically connected to the first charging circuit 101 in the reset circuit. At the time t1, the switch S1 is closed, the battery charges the first capacitor C1, and at the instant when the switch S1 is closed, the charging voltage is applied to the first end of the first capacitor C1, so as to form a pulse voltage at the first end of the first capacitor C1. The pulse voltage formed at the first end of the first capacitor C1 charges the second capacitor C2 through the first diode D3 and the second resistor R2. In this example, the second resistor R2 is added to the first charging circuit 101, so that the resistance of the branch consisting of the first diode D3, the second resistor R2 and the first capacitor C1 is increased, and thus the current in the branch can be reduced, and the speed of charging the second capacitor C2 by the first capacitor C1 can be controlled. In this example, the second resistance may be set to 120K Ω.

In addition, because a glitch may exist in the pulse voltage generated by the first capacitor C1, which may cause the problem of false triggering of the NMOS transistor Q1, the first capacitor C1 and the NMOS transistor Q1 may be isolated by the arranged second resistor R2, so as to avoid the problem of false triggering of the NMOS transistor Q1 to be turned on in the process of charging the first capacitor C1 to the second capacitor C2, and improve the ESD (Electro-Static discharge) prevention performance of the reset circuit.

In this example, the functions of the resistor R4 and the first resistor R1 are the same as those in fig. 4a, and reference may be made to the related description in fig. 4a, which is not repeated herein.

The process of turning off the switch S1 at the time t2 by the reset circuit in fig. 5 is similar to the related description in fig. 4a, and may refer to the related description in fig. 4a, and is not repeated here. Similarly, the process of generating the reset signal by the reset circuit in fig. 5 is similar to the process of outputting the reset signal by the reset circuit in fig. 4a, and reference may be made to the related description in fig. 4a, and details are not repeated here.

In some embodiments, the first terminal of the second resistor may also be electrically connected to the first terminal of the first capacitor, and the second terminal of the second resistor is electrically connected to the anode of the first diode. Fig. 6 is a circuit diagram exemplarily showing that the second resistor is included in the first charging circuit.

As shown in fig. 6, the first charging circuit 101 in the reset circuit includes: a first capacitor (e.g., C1 in fig. 6), a discharge component, a first diode (e.g., D3 in fig. 6), and a second resistor (e.g., R2 in fig. 6). The second charging circuit 102 includes: a second capacitor (e.g., C2 in fig. 6) and a first resistor (e.g., R1 in fig. 6). The reset signal output circuit in this example is described by taking an NMOS transistor (e.g., Q1 in fig. 6) as an example.

The operation principle of the reset circuit in fig. 6 is the same as that of the reset circuit in fig. 5, and reference may be made to the description in fig. 5, which is not repeated herein.

In some embodiments, the discharge assembly comprises: a third resistor and a fourth resistor; the first end of the fourth resistor is electrically connected with the first end of the first capacitor; the second end of the fourth resistor is electrically connected with the first end of the third resistor; the second end of the third resistor is electrically connected with the second end of the first capacitor; the first end of the third resistor is grounded. In this example, the discharge element includes a third resistor R3 and a fourth resistor R4 as an example. Fig. 7 schematically shows a circuit diagram further including a third resistor in the discharge assembly. As shown in fig. 7, the second end of the third resistor R3 is electrically connected to the second end of the first capacitor C1, and the first end of the third resistor R3 is grounded. A first end of the first capacitor C1 is electrically connected to the anode of the first diode D3 and a first end of the resistor R4; the second terminal of the resistor R4 is grounded. A cathode of the first diode D3 is electrically connected to a first end of a second resistor R2, and a second end of the second resistor R2 is electrically connected to a first end of the second capacitor C2 and a first end of the first resistor R1; the second end of the first resistor R1 is grounded; the first end of the second capacitor C2 is electrically connected with the grid electrode of the NMOS transistor Q1, and the drain electrode of the NMOS transistor Q1 is electrically connected with the reset end of the microprocessor; the source of the NMOS transistor Q1 is grounded. The second end of the second capacitor C2 is electrically connected with the second end of the first resistor R1; the second end of the first capacitor C1 and the second end of the resistor R4 are used for electrically connecting with a charger.

In this example, the third resistor R3 may discharge the first capacitor C1 when the charger is disconnected from the first capacitor C1, so as to further increase the discharging speed of the first capacitor C1, and ensure that the first capacitor C1 can continue to charge the second capacitor C2 when the charger is electrically connected to the first capacitor C1 next time.

At time t1, the user electrically connects the charger to the charging input terminal of the smart watch, that is, the charger is electrically connected to the first charging circuit 101 in the reset circuit. At time t1, at the instant when the switch S1 is closed, the charging voltage is applied to the first end of the first capacitor C1, and a pulse voltage is formed at the first end of the first capacitor C1. The pulse voltage charges the second capacitor C2 through the first diode D3 and the second resistor R2. In this example, the resistor R4 may be set to 5K Ω, and the first resistor R1 may be set to 5M Ω. With the increase of the closing time of the switch S1, the voltage is gradually formed at the two ends of the first capacitor C1, and the second capacitor C2 is no longer charged.

In this example, when the charger charges the first capacitor C1, a part of the current flows through the fourth resistor, which can reduce the voltage for charging the first capacitor, and also can avoid the problem that the first capacitor C1 quickly charges the second capacitor C2 with electricity or erroneously triggers the NMOS transistor Q1 to turn on.

At time t2, switch S1 is open, forming a discharge circuit 1 due to the presence of resistor R4 and third resistor R3: C1-R3-R4-C1. The resistor R4 and the third resistor R3 can accelerate the discharging of the electric quantity in the first capacitor C1, so as to reduce the voltage between the first end and the second end of the first capacitor C1. At time t2, when the switch S1 is turned off, the second capacitor C2 and the first resistor R1 form a discharge circuit 2: C2-R1-C2. The discharge circuit 2 may consume the charge on the second capacitor C2. Alternatively, the resistance of the third resistor R3 may be the same as the resistance of the resistor R4, for example, the resistance of the third resistor R3 is 5K Ω.

The process of generating the reset signal by the reset circuit in fig. 6 is similar to the process of outputting the reset signal by the reset circuit in fig. 4a, and can refer to the related description in fig. 4a, and the details are not repeated here.

In some embodiments, the discharge assembly may further include a third resistor R3 and a second diode D4. The anode of the second diode D4 is grounded, and the cathode of the second diode D4 is electrically connected to the first end of the first capacitor C1. The second diode D4 can discharge the first capacitor C1 when the charger is electrically disconnected from the first capacitor C1, thereby avoiding a negative voltage at the first end of the first capacitor C1. The structure of the reset circuit is shown in fig. 8.

The first charging circuit 101 in the reset circuit includes: a first capacitor (e.g., C1 in fig. 8), a discharge element, a first diode (e.g., D3 in fig. 8), and a second resistor (e.g., R2 in fig. 8). The second charging circuit 102 includes: a second capacitor (e.g., C2 in fig. 8) and a first resistor (e.g., R1 in fig. 8). The reset signal output circuit in this example is explained taking a comparator (e.g., Q1 in fig. 8) as an example.

Specifically, the second end of the third resistor R3 is electrically connected to the second end of the first capacitor C1, and the first end of the third resistor R3 is grounded. A first end of the first capacitor C1 is electrically connected to an anode of the first diode D3 and a cathode of the second diode D4; the anode of the second diode D4 is electrically connected to the first end of the third resistor R3. A cathode of the first diode D3 is electrically connected to a first end of a second resistor R2, and a second end of the second resistor R2 is electrically connected to a first end of a second capacitor C2 and a first end of a first resistor R1; the second end of the first resistor R1 is grounded; the first end of the second capacitor C2 is electrically connected to the negative input terminal of the comparator 103. The second end of the second capacitor C2 is electrically connected to the second end of the first resistor R1. The positive input end of the comparator 103 is electrically connected with the reference voltage Vref, and the output end of the comparator 103 is electrically connected with the reset end of the MCU. The reference voltage can be provided by a device meeting the voltage value of the reference voltage in the intelligent watch, and the voltage value range of the reference voltage is 0.5V to 1V. The first end and the second end of the third resistor R3 may be used for electrically connecting with a charger.

The operation of the reset circuit will be described in detail below.

At time t5, the user electrically connects the charger to the charging input terminal of the smart watch, that is, the charger is electrically connected to the first charging circuit 101 in the reset circuit. At time t5, the switch S1 is closed, and at the instant when the switch S1 is closed, the charging voltage is applied to the first end of the first capacitor C1, forming a pulse voltage at the first end of the first capacitor C1. The pulse voltage formed at the first end of the first capacitor C1 charges the second capacitor C2 through the first diode D3 and the second resistor R2. In this example, since the diode is a one-way conducting device, when the first capacitor C1 charges the second capacitor C2, the current flows to the second capacitor C2.

The negative input terminal of the comparator 103 is electrically connected to the second terminal of the second resistor R2, and the comparator detects that the voltage at the negative input terminal is compared with the reference voltage, and at this time, the voltage at the negative input terminal is smaller than the reference voltage, and the output terminal of the comparator outputs a high level.

At time t6, switch S1 is open, and due to the presence of second diode D4, discharge circuit 1 is formed: C1-R3-D4-C1. The second diode D4 and the third resistor R3 can discharge the electric quantity in the first capacitor C1 to reduce the voltage between the first terminal and the second terminal of the first capacitor C1. At time t6, when the switch S1 is turned off, the second capacitor C2 and the first resistor R1 form a discharge circuit 2: C2-R1-C2. The discharge circuit 2 may consume the charge on the second capacitor C2.

Meanwhile, the first end of the second capacitor C2 is electrically connected to the negative input end of the comparator 103, the voltage value output by the second capacitor C2 is small, and if the comparator detects that the voltage at the negative input end is smaller than the reference voltage, the comparator 103 outputs a high level. In this example, the reference voltage may be 0.7V.

Along with the increase of the off-duration of the switch S1, the third resistor R3 and the second diode D4 consume the stored electric quantity in the first capacitor C1, and the voltage at the two ends of the first capacitor C1 decreases, which is beneficial to charging the second capacitor C2 next time.

At time t7, the switch S1 is closed again, and since the first capacitor C1 is discharged at time t6 to time t7, the voltage between the first end and the second end of the first capacitor C1 decreases, and at the moment when the switch S1 is closed, the charging voltage is applied to the first end of the first capacitor C1 again, so as to form a pulse voltage at the first end of the first capacitor C1. At time t7, the pulse voltage charges the second capacitor C2 again through the first diode D3 and the second resistor R2. Optionally, the time between t6 and t7 can be longer than the time between t5 and t 6.

At time t8, switch S1 is open, forming a discharge circuit 1 due to the presence of second diode D4: C1-R3-D4-C1. The second diode D4 and the third resistor R3 can discharge the electric quantity in the first capacitor C1 to reduce the voltage between the first terminal and the second terminal of the first capacitor C1. At time t8, when the switch S1 is turned off, the second capacitor C2 and the first resistor R1 form a discharge circuit 2: C2-R1-C2.

In the present example, assuming that the switch S1 is operated from closed to open for 4 times, the voltage of the second capacitor C2 reaches a preset threshold, which may be a value greater than the reference voltage (e.g., the preset threshold is 0.8V). The comparator compares the voltage of the negative input end with a reference voltage, and if the voltage of the negative input end is higher than the reference voltage, the output end of the comparator outputs a low-level signal. The reset end of the MCU receives a low-level reset signal and triggers the MCU to execute reset operation. In this example, the reset signal of the reset terminal of the MCU is a low level signal. As the amount of electricity in the second capacitor C2 decreases, the comparator outputs a high level signal when it detects that the voltage at the negative input terminal is less than the reference voltage.

It should be noted that the comparator may use an existing comparator circuit or comparator chip.

In some embodiments, the reset signal output circuit 103 may also be a non-circuit, an input terminal of the non-circuit is electrically connected to the first terminal of the second capacitor, and an output terminal of the non-circuit 103 is electrically connected to the reset terminal of the MCU.

The first charging circuit 101 in the reset circuit includes: a first capacitor (e.g., C1 in fig. 9), a discharge element, a first diode (e.g., D3 in fig. 9), and a second resistor (e.g., R2 in fig. 9). The second charging circuit 102 includes: a second capacitor (e.g., C2 in fig. 9) and a first resistor (e.g., R1 in fig. 9). The reset signal output circuit 103 may be a non-circuit, and the non-circuit 103 may be an inverter.

Specifically, the second end of the third resistor R3 is electrically connected to the second end of the first capacitor C1, and the first end of the third resistor R3 is grounded. A first end of the first capacitor C1 is electrically connected to an anode of the first diode D3 and a cathode of the second diode D4; the anode of the second diode D4 is electrically connected to the first end of the third resistor R3. A cathode of the first diode D3 is electrically connected to a first end of a second resistor R2, and a second end of the second resistor R2 is electrically connected to a first end of a second capacitor C2 and a first end of a first resistor R1; the second end of the first resistor R1 is grounded; a first end of the second capacitor C2 is electrically connected to an input end of the not circuit 103. The second end of the second capacitor C2 is electrically connected to the second end of the first resistor R1. The output end of the not circuit 103 is electrically connected with the reset end of the MCU.

The operation of the reset circuit will be described in detail below.

At time t5, the user electrically connects the charger to the charging input terminal of the smart watch, that is, the charger is electrically connected to the first charging circuit 101 in the reset circuit. At time t5, at the instant when the switch S1 is closed, the charging voltage is applied to the first end of the first capacitor C1, and a pulse voltage is formed at the first end of the first capacitor C1. The pulse voltage charges the second capacitor C2 through the first diode D3 and the second resistor R2. In this example, since the second diode D4 is a unidirectional device, when the first capacitor C1 charges the second capacitor C2, the current flows to the second capacitor.

The input terminal of the not circuit 103 is electrically connected to the second terminal of the second resistor R2 and the first terminal of the second capacitor C2, and the voltage obtained by the not circuit 103 is lower than a preset threshold (for example, the preset threshold is 0.7V), and at this time, the not circuit 103 outputs a high level. In this example, the high level may be 2 to 5v.

At time t6, switch S1 is open, forming a discharge circuit 1 due to the presence of second diode D4: C1-R3-D4-C1. The second diode D4 and the third resistor R3 can discharge the electric quantity in the first capacitor C1 to reduce the voltage between the first terminal and the second terminal of the first capacitor C1. At time t6, when the switch S1 is turned off, the second capacitor C2 and the first resistor R1 form a discharge circuit 2: C2-R1-C2. The discharge circuit 2 may consume the charge on the second capacitor C2.

Meanwhile, the first end of the second capacitor C2 is electrically connected to the input end of the not circuit 103, the second capacitor C2 has a small electric quantity, and the output voltage is small, and if the output voltage is 0.25V, the not circuit 103 outputs a high level.

Along with the increase of the off-time of the switch S1, the third resistor R3 and the second diode D4 consume the stored electric quantity in the first capacitor C1, and the voltage at the two ends of the first capacitor C1 decreases, which is beneficial to charging the second capacitor C2 next time.

At the time t7, the switch S1 is closed again, and since the first capacitor C1 is discharged at the time t6 to t7, the voltage between the first end and the second end of the first capacitor C1 decreases, and at the moment when the switch S1 is closed, the charging voltage is applied to the first end of the first capacitor C1 again, and a pulse voltage is formed at the first end of the first capacitor C1. At time t7, the pulse voltage charges the second capacitor C2 again through the first diode D3 and the second resistor R2. Optionally, the time between t6 and t7 can be longer than the time between t5 and t 6.

At time t8, switch S1 is open, and due to the presence of second diode D4, discharge circuit 1 is formed: C1-R3-D4-C1. The second diodes D4 and R3 can discharge the electric quantity in the first capacitor C1 to reduce the voltage between the first terminal and the second terminal of the first capacitor C1. At time t8, when the switch S1 is turned off, the second capacitor C2 and the first resistor R1 form a discharge circuit 2: C2-R1-C2.

In the present example, it is assumed that the voltage of the second capacitor C2 exceeds a preset threshold (e.g. 0.7V) after 4 operations from closing to opening of the switch S1. When the inverter detects that the voltage at the input end is 1V and is greater than a preset threshold, the output end of the inverter 103 outputs a low level (the range of a low level signal is 0 to 0.25v), and the MCU is triggered to perform a reset operation. In this example, the reset signal of the reset terminal of the MCU is a low level signal. When the comparator detects that the voltage of the negative input end is less than the reference voltage, the comparator outputs a high level signal.

Fig. 10 is a schematic diagram illustrating exemplary detection of voltages at various positions using an oscilloscope.

The first charging circuit 101 in the reset circuit includes: a first capacitor (e.g., C1 in fig. 10), a discharge component, a first diode (e.g., D3 in fig. 10), and a second resistor (e.g., R2 in fig. 10). The second charging circuit 102 includes: a second capacitor (e.g., C2 in fig. 10) and a first resistor (e.g., R1 in fig. 10). The reset signal output circuit 103 will be described by taking an NMOS transistor as an example.

Specifically, the second end of the third resistor R3 is electrically connected to the second end of the first capacitor C1, and the first end of the third resistor R3 is grounded. A first end of the first capacitor C1 is electrically connected to an anode of the first diode D3 and a first end of the resistor R4; the second terminal of the resistor R4 is grounded. A cathode of the first diode D3 is electrically connected to a first end of a second resistor R2, and a second end of the second resistor R2 is electrically connected to a first end of the second capacitor C2 and a first end of the first resistor R1; the second end of the first resistor R1 is grounded; the first end of the second capacitor C2 is electrically connected with the grid electrode of the NMOS transistor Q1, and the drain electrode of the NMOS transistor Q1 is electrically connected with the reset end of the microprocessor; the source of the NMOS transistor Q1 is grounded. The second end of the second capacitor C2 is electrically connected with the second end of the first resistor R1; the second end of the first capacitor C1 and the second end of the resistor R4 are used for being electrically connected with a charger.

Due to the capacitance that may be present in the loop of the charge management circuit of the smartwatch, in this example, the capacitance that may be present in the charge management circuit is simulated by a third capacitor C3. The first end of the third capacitor C3 is electrically connected to the first end of the third resistor R3, and the second end of the third capacitor C3 is grounded.

In this example, the oscilloscope adopts a four-channel oscilloscope, where an a channel of the oscilloscope is used to measure a signal input by the charger, and a detection point of the a channel may be connected to a position between the first end of the third capacitor C3 and the second end of the third resistor R3. The channel B of the oscilloscope is used for measuring the output signal of the first diode D3, and the detection point of the channel B can be connected to the cathode of the first diode D3. The C channel of the oscilloscope is used for measuring the grid voltage of the NMOS transistor, and the detection point of the C channel can be connected with the grid of the NMOS transistor Q1. The D channel of the oscilloscope is used for measuring the drain voltage of the NMOS transistor, the detection point of the D channel can be connected to the drain of the NMOS transistor Q1, and the G end of the oscilloscope is grounded.

FIGS. 11-14 show waveforms of 4 detection points under different scenarios.

Fig. 11 is a waveform diagram illustrating 4 detection points in the case where the time period for which the charger is electrically connected to the first charging circuit is longer than the time period for which the charger is electrically disconnected from the first charging circuit.

Specifically, as shown in fig. 11, the abscissa is used to indicate the time, and each grid time is 1 second; the ordinate is used to indicate the voltage, wherein the voltage per cell (Div) differs for different detection points. In this example, each grid (Div) in the waveform of the detection point of the a channel represents 5V; each grid (Div) in the waveform of the detection point of the B channel represents 5V; each grid (Div) in the waveform of the detection point of the C channel represents 1V; each grid (Div) in the waveform of the detection point of the D channel represents 5V. As shown in fig. 11, the time period for the first time of electrically connecting the charger to the first capacitor in the smart watch is 0.7 seconds, and after 0.7 seconds, the user disconnects the charger from the first capacitor, and the disconnection time period is less than 0.7 seconds (for example, 0.05 seconds). As can be seen from fig. 11, when the charger goes through a process of being electrically connected to the first capacitor and being disconnected from the first capacitor, the second terminal (i.e., the voltage of the gate) of the second capacitor C2 increases. Through 8 times of repeated processes of electrical connection and disconnection with the first capacitor, the charger continuously increases the gate voltage of the NMOS transistor Q1 through the reset circuit, and reaches the on voltage of the NMOS transistor Q1 (for example, the on voltage is 1.2V) at 7.3 seconds, and the drain of the NMOS transistor Q1 outputs a reset signal (as shown by a thin solid line in fig. 11), so as to trigger the MCU to perform the reset operation.

In fig. 11, the disconnection time between the charger and the first capacitor C1 may cause insufficient discharge of the first capacitor C1, thereby increasing the plugging/unplugging times of the charger.

Fig. 12 is a waveform diagram illustrating 4 detection points in the case where the time period for which the electrical connection between the charger and the first charging circuit is electrically disconnected is shorter than the time period for which the electrical connection between the charger and the first charging circuit is electrically disconnected.

Specifically, as shown in fig. 12, the abscissa is used to indicate time, each grid of time being 1 second; the ordinate is used to indicate the voltage, wherein the voltage per cell (Div) differs for different detection points. In this example, each grid (Div) in the waveform of the detection point of the a channel represents 5V; each grid (Div) in the waveform of the detection point of the B channel represents 5V; each grid (Div) in the waveform of the detection point of the C channel represents 1V; each grid (Div) in the waveform at the detection point of the D channel represents 5V. As shown in fig. 12, the time period for the first time of the charger being electrically connected to the first capacitor in the smart watch is 0.2 seconds, and after 0.2 seconds, the user disconnects the charger from the first capacitor, and the disconnection time period is greater than 0.2 seconds (for example, 0.8 seconds). As can be seen from fig. 12, when the charger goes through a process of once electrically connecting to disconnecting from the first capacitor, the second terminal (i.e., the voltage of the gate) of the second capacitor C2 increases. After the charger repeats the process from electrical connection to disconnection with the first capacitor 4 times, the gate voltage of the NMOS transistor Q1 continuously rises through the reset circuit, and reaches the on voltage of the NMOS transistor Q1 (for example, the on voltage is 1.2V) at the 4.2 th second, and the drain of the NMOS transistor Q1 outputs a reset signal (as shown by a thin solid line in fig. 12), thereby triggering the MCU to perform the reset operation.

It should be noted that, in this example, after the voltage output by the second capacitor reaches the preset threshold, the charger is still repeatedly electrically connected to and disconnected from the first capacitor, that is, the first capacitor continuously charges the second capacitor, so that after 4.2 seconds in fig. 12, the drain of the NMOS transistor outputs a low level signal.

Fig. 13 is a waveform diagram illustrating 4 detection points in the case where the time period for which the charger is electrically connected to the first charging circuit is equal to the time period for which the charger is electrically disconnected from the first charging circuit.

Specifically, as shown in fig. 13, the abscissa is used to indicate time, and each grid time is 1 second; the ordinate is used to indicate the voltage, wherein the voltage per cell (Div) differs for different detection points. In this example, each grid (Div) in the waveform of the detection point of the a channel represents 5V; each grid (Div) in the waveform of the detection point of the B channel represents 5V; each grid (Div) in the waveform of the detection point of the C channel represents 1V; each grid (Div) in the waveform at the detection point of the D channel represents 5V. As shown in fig. 13, the time duration of the second electrical connection between the charger and the first capacitor in the smart watch is 0.5 seconds, and after 0.5 seconds, the user disconnects the charger from the first capacitor, and the disconnection time duration is equal to 0.5 seconds (for example, 0.5 seconds). As can be seen from fig. 13, when the charger is electrically connected to the first capacitor for the second time, the second terminal (i.e., the voltage of the gate) of the second capacitor C2 increases. From the second time, the charger repeats the operations of electrically connecting to disconnecting the first capacitor 4 times, the gate voltage of the NMOS transistor Q1 in the reset circuit continuously rises, and reaches the on voltage of the NMOS transistor Q1 (for example, the on voltage is 1.2V) at the 5.4 th second, and the drain of the NMOS transistor Q1 outputs a reset signal (as shown by a thin solid line in fig. 13), thereby triggering the MCU to perform the reset operation.

Fig. 14 is a waveform diagram exemplarily showing 4 detection points in the case where the charger and the first charging circuit are electrically connected m times in 1 second, where m is an integer greater than 2.

Specifically, as shown in fig. 14, the abscissa is used to indicate time, and each grid time is 1 second; the ordinate is used to indicate the voltage, wherein the voltage per cell (Div) differs for different detection points. In this example, each grid (Div) in the waveform of the detection point of the a channel represents 5V; each grid (Div) in the waveform of the detection point of the B channel represents 5V; each grid (Div) in the waveform of the detection point of the C channel represents 1V; each grid (Div) in the waveform of the detection point of the D channel represents 5V. As shown in fig. 14, the charger is electrically connected to the first capacitor in the smart watch 4 times in 1 second, and the drain of the NMOS transistor Q1 outputs a reset signal (indicated by a thin solid line in fig. 14), thereby triggering the MCU to perform a reset operation.

The charger is connected and disconnected with the first charging circuit in a quick electric mode, if the charger is connected with the first charging circuit m times in one second, m is an integer larger than 2, the mode of plugging and unplugging the charger enables the output of reset signals to be more stable, and the anti-interference capacity is high.

The term "and/or" herein is merely an association describing an associated object, meaning that three relationships may exist, e.g., a and/or B, may mean: a exists alone, A and B exist simultaneously, and B exists alone.

The terms "first" and "second," and the like in the description and in the claims of the embodiments of the present application, are used for distinguishing between different objects and not for describing a particular order of the objects. For example, the first target object and the second target object, etc. are specific sequences for distinguishing different target objects, rather than describing target objects.

In the embodiments of the present application, words such as "exemplary" or "for example" are used to mean serving as an example, instance, or illustration. Any embodiment or design described herein as "exemplary" or "e.g.," is not necessarily to be construed as preferred or advantageous over other embodiments or designs. Rather, use of the word "exemplary" or "such as" is intended to present concepts related in a concrete fashion.

In the description of the embodiments of the present application, the meaning of "a plurality" means two or more unless otherwise specified. For example, a plurality of processing units refers to two or more processing units; the plurality of systems refers to two or more systems.

Any contents of the respective embodiments of the present application, and any contents of the same embodiment, can be freely combined. Any combination of the above is within the scope of the present application.

While the present embodiments have been described with reference to the accompanying drawings, it is to be understood that the invention is not limited to the precise embodiments described above, which are meant to be illustrative and not restrictive, and that various changes may be made therein by those skilled in the art without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. A reset circuit provided in an electronic device, the reset circuit comprising: the first charging circuit, the second charging circuit and the reset signal output circuit;

the first charging circuit is used for charging the second charging circuit in the process of being electrically connected with the charger and disconnected from the charger for N times, wherein N is an integer larger than 1, and the time length of the first charging circuit from being electrically connected with the charger to being disconnected from the charger for N times is less than 1 minute;

the first charging circuit includes: the first capacitor, the discharge component and the first diode; when the discharge assembly comprises three connecting ends, the first end of the first capacitor is electrically connected with the anode of the first diode and the first end of the discharge assembly, the second end of the discharge assembly is grounded, and the third end of the discharge assembly is electrically connected with the second end of the first capacitor; when the discharge assembly comprises two connecting ends, the first end of the first capacitor is electrically connected with the anode of the first diode and the first end of the discharge assembly, and the second end of the discharge assembly is grounded; the cathode of the first diode is used as the output end of the first charging circuit, and the second end of the first capacitor and the second end of the discharging component are used for being electrically connected with the charger;

the second charging circuit is used for outputting a control signal to the reset signal output circuit;

the reset signal output circuit is used for outputting a reset signal when the voltage value of the control signal is detected to exceed a preset threshold value, and the reset signal is used for triggering a microprocessor in the electronic equipment to carry out reset operation.

2. The reset circuit of claim 1, wherein the second charging circuit comprises: a second capacitor and a first resistor;

a cathode of the first diode is electrically connected with a first end of the second capacitor and a first end of the first resistor;

the first end of the second capacitor is electrically connected with the input end of the reset signal output circuit;

the second end of the second capacitor is electrically connected with the second end of the first resistor;

the second end of the first resistor is grounded;

the output end of the reset signal output circuit is electrically connected with the reset end of the microprocessor.

3. The reset circuit of claim 2, wherein when the discharging component comprises three connection terminals, the first charging circuit further comprises: a second resistor;

the first end of the second resistor is electrically connected with the cathode of the first diode, and the second end of the second resistor is electrically connected with the first end of the second capacitor and the first end of the second resistor.

4. The reset circuit of claim 2, wherein when the discharging component includes three connection terminals, the first charging circuit further comprises: a second resistor;

the first end of the second resistor is electrically connected with the first end of the first capacitor, and the second end of the second resistor is electrically connected with the anode of the first diode.

5. The reset circuit according to claim 2, wherein when the discharge element includes three connection terminals, the discharge element includes: a third resistor and a fourth resistor;

the first end of the fourth resistor is electrically connected with the first end of the first capacitor;

the second end of the fourth resistor is electrically connected with the first end of the third resistor;

the second end of the third resistor is electrically connected with the second end of the first capacitor;

the first end of the third resistor is grounded;

the first end of the fourth resistor is used as the first end of the discharge component, the first end of the third resistor is used as the second end of the discharge component, and the second end of the third resistor is used as the third end of the discharge component.

6. The reset circuit of claim 2, wherein when the discharge element includes three connection terminals, the discharge element includes: a third resistor and a second diode;

the first end of the third resistor is grounded and is electrically connected with the anode of the second diode;

a cathode of the second diode is electrically connected with a first end of the first capacitor;

the cathode of the second diode is used as the first end of the discharge component, the first end of the third resistor is used as the second end of the discharge component, and the second end of the third resistor is used as the third end of the discharge component.

7. The reset circuit of claim 2, wherein when the discharge element includes two connection terminals, the discharge element includes: a fourth resistor;

a second end of the fourth resistor is electrically connected to a first end of a third resistor, and the third resistor is an equivalent resistor of a charging management circuit in the electronic device;

the first end of the third resistor is grounded;

the first end of the fourth resistor is used as the first end of the discharge component, and the second end of the fourth resistor is used as the second end of the discharge component.

8. The reset circuit of claim 2, wherein when the discharge element includes two connection terminals, the discharge element includes: a second diode;

a second end of the first capacitor is electrically connected with a second end of a third resistor, and the third resistor is an equivalent resistor of a charging management circuit in the electronic equipment;

the first end of the third resistor is grounded and is electrically connected with the input end of the second diode;

the output end of the second diode is electrically connected with the first end of the first capacitor;

the output end of the second diode is used as the first end of the discharge component, and the input end of the second diode is used as the second end of the discharge component.

9. The reset circuit according to any one of claims 2 to 8, wherein the reset signal output circuit comprises: an N-type metal oxide semiconductor (NMOS) transistor;

the grid electrode of the NMOS transistor is used as the input end of the reset signal output circuit;

the drain electrode of the NMOS transistor is used as the output end of the reset signal output circuit;

and the source electrode of the NMOS transistor is electrically connected with the second end of the first resistor.

10. The reset circuit according to any one of claims 2 to 8, wherein the reset signal output circuit includes: a not circuit;

the input end of the NOT circuit is used as the input end of the reset signal output circuit;

and the output end of the NOT circuit is used as the output end of the reset signal output circuit.

11. The reset circuit according to any one of claims 2 to 8, wherein the reset signal output circuit comprises: a comparator;

the negative input end of the comparator is used as the input end of the reset signal output circuit;

the positive input end of the comparator is electrically connected with a reference voltage, and the voltage value range of the reference voltage is 0.5V to 1V;

the output end of the comparator is used as the output end of the reset signal output circuit, wherein the reset end of the microprocessor is triggered by a low-level signal.

12. The reset circuit according to claim 5 or 7, wherein the fourth resistor has a smaller resistance than the first resistor.

13. The reset circuit according to any one of claims 1 to 8, wherein the first charging circuit and the charger are electrically connected to and disconnected from each other for a period of time in a range of 1 second to 5 seconds.

14. An electronic device, comprising: the reset circuit and microprocessor of any one of claims 1-13, wherein the reset signal output of the reset circuit is electrically connected to a reset terminal of the microprocessor.

15. The electronic device of claim 14, wherein the electronic device is a smart watch, a smart bracelet, or a smart card machine.

16. The electronic device of claim 15, wherein no keys are disposed on the smart watch or smart bracelet.