CN115361513A - Single-electron reading circuit and method based on composite dielectric grid photosensitive detector - Google Patents

Abstract

The invention discloses a single electron readout circuit and method based on a composite dielectric grid photosensitive detector. Its photosensitive detector includes a photosensitive transistor and a readout transistor formed on the same substrate. These two transistors share a composite dielectric gate. The composite dielectric gate includes a bottom dielectric layer, a charge coupling layer, a top dielectric layer and a control gate. The readout circuit includes a correlated double sampling circuit, an amplifying circuit and a quantization circuit. The correlated double sampling circuit is used to sample the drain current of the read transistor, and the amplifying circuit is used to amplify the voltage signal output by the correlated double sampling circuit. The quantized circuit It is used for single-bit quantization of the voltage signal output by the amplifier circuit. The present invention provides a low-noise, high-gain, high-frame-rate readout circuit and method based on a composite dielectric grating photosensitive detector, which can realize single-electron level readout and solve high-performance imaging for high-resolution low-illuminance scenes question.

Description

Single electron readout circuit and method based on composite dielectric grid photosensitive detector

technical field

The invention relates to a readout method of a photosensitive detector array, in particular to a single-electron-level low-noise, high-gain, high-frame-rate readout circuit and method based on a composite dielectric grid photosensitive detector.

Background technique

Photosensitive detectors play an extremely important role in daily life and in the field of national defense and security. At present, the mainstream photosensitive detectors are divided into two categories: CCD and CMOS-APS. With the development of CMOS technology, CMOS-APS occupies The vast majority of the market share, but as the pixel size becomes smaller and smaller, the sensitivity and full well capacity of CMOS-APS are getting lower and lower, resulting in a significant decrease in signal-to-noise ratio, low dynamic range, and poor imaging quality.

In order to solve the problem of low signal-to-noise ratio of small pixels, the photosensitive detector based on composite dielectric gate improves the signal-to-noise ratio by expanding the full well capacity under small pixel size. Since ordinary photosensitive detectors based on composite dielectric grids do not require high sensitivity in order to detect large full-well signal quantities, a longer exposure time is required for photosensitive detection under extremely low illumination, which easily leads to excessive dark current accumulation. drown out the signal.

Contents of the invention

In view of the fact that none of the existing photosensitive detectors can meet the imaging requirements under extremely low illumination, especially in scenes requiring high resolution, in order to solve the problem of high-performance imaging for high-resolution low-illuminance scenes, the present invention is based on composite media The grid photosensitive detector provides a low-noise, high-gain, high-frame-rate readout circuit and method thereof, which can realize single-electron level readout.

The technical scheme that the present invention adopts is as follows:

A single-electron readout circuit based on a composite dielectric gate photodetector. The photosensitive detector includes a photosensitive transistor and a read transistor formed on the same substrate. These two transistors share a composite dielectric gate. The composite dielectric gate includes a bottom layer dielectric layer, charge coupling layer, top dielectric layer and control gate; the readout circuit includes a correlated double sampling circuit, an amplification circuit and a quantization circuit, and the correlated double sampling circuit is used for sampling the drain current of the read transistor, so The amplifying circuit is used to amplify the voltage signal output by the correlated double sampling circuit, and the quantization circuit is used to perform single-bit quantization on the voltage signal output by the amplifying circuit.

Further, the thickness of the top dielectric layer is greater than 10 nm, and the size of the composite dielectric gate is less than 500 nm.

Further, the amplifying circuit adopts a charge transfer amplifying circuit.

Further, the quantization circuit adopts a single-bit ADC or a D-latch circuit.

Further, when multiple photosensitive detectors form an array structure, the array structure is divided into multiple sub-arrays, and each sub-array shares one readout circuit.

The present invention also provides a readout method of the above-mentioned single electron readout circuit based on the composite dielectric grating photosensitive detector, comprising the following steps:

(1) Reset: add a voltage of -4V to the control gate, and add a voltage of -3V to the substrate to reset the electrons collected by the photosensitive transistor of the photosensitive detector, and read the reset signal by the relevant double sampling circuit;

(2) Exposure: Add a voltage of 0V to the control gate and a voltage of -3V to the substrate. When there is light, when the energy of photoelectrons is greater than the forbidden band width of silicon, an electron-hole pair will be excited. Under the action of the electric field in the region, the phototransistor collects the generated photoelectrons, the potential of the phototransistor will change, and the charge coupling layer coupled to the composite dielectric gate changes the potential of the charge coupling layer, thereby changing the threshold voltage for turning on the read transistor, the threshold voltage The amount of change is U=Q/C, where Q is the amount of charge of the collected photoelectrons, and C is the capacitance of the top dielectric grid; the exposure signal is read by the relevant double sampling circuit;

(3) Reading: In the reading stage, the control grid is applied with a voltage of 2 to 5V, and the substrate is applied with a voltage of -3 to 0V. The wells are all in the linear region; the drain of the read transistor is given a constant voltage, the source is given a constant voltage of 0V, and the drain current is read out by the relevant double sampling circuit.

Further, after the photosensitive detector is reset, the correlated double sampling circuit samples the drain current through the reset signal sampling capacitor, and outputs the voltage signal VOUTR of the reset signal; after the photosensitive detector is exposed, the drain current is sampled through the exposure signal sampling capacitor The electrode current is sampled, and the voltage signal VOUTS of the exposure signal is output. The difference between the two voltage signals VOUTS-VOUTR is the signal amount corresponding to the photoelectrons collected after exposure.

The detector of the present invention realizes high gain at the device level, so that the overall signal-to-noise ratio of the signal transmission link is improved, which is beneficial to the improvement of imaging quality. Since the signal collection capacity of the photosensitive detector is far below the full well capacity in low-illuminance imaging environments or extremely high frame rate imaging conditions, the high-gain output from charge to voltage satisfies the dynamic range of analog circuits, reducing circuit Difficulty of design. In the post-stage circuit, the present invention adopts correlated double sampling circuit to reduce reset noise, shot noise, etc., and further improves the signal-to-noise ratio; Active input, so there is a great advantage in power consumption; and in the 1bit quantization requirements, the requirements for the amplification accuracy of the amplifier circuit in the readout circuit of different arrays are low, so the advantages of the charge transfer amplifier circuit can be fully utilized , in the quantization circuit, only 1-bit quantization is required for low illumination or extremely high frame rate requirements, so single-bit ADC or D-latch can be used for high frame rate quantization. Through the optimization from the device to the readout circuit, compared with the readout mode of the slope voltage scanning device threshold adopted by the traditional photosensitive detector based on the composite dielectric gate, the circuit readout method of the present invention makes the noise lower than 0.2e -, only 2% of the traditional solution; the charge-to-voltage conversion gain reaches 1mv/e-, which is 4 times that of the traditional solution; the frame rate can reach 1000fps, while the traditional solution is only 3fps.

Description of drawings

FIG. 1 is a schematic structural diagram of a photosensitive detector based on a composite dielectric grating in an embodiment of the present invention;

Fig. 2 is a structural schematic diagram of a reading transistor of a composite dielectric gate photosensitive detector;

FIG. 3 is a schematic structural diagram of an m×n pixel sub-array sharing a readout circuit;

Fig. 4 is the module schematic diagram of readout circuit;

Fig. 5 is a schematic structural diagram of a correlated double sampling circuit;

6 is a schematic structural diagram of a charge transfer amplifier circuit;

Figure 7 is a schematic diagram of the structure of D-latch;

Fig. 8 is a module schematic diagram of an m * n photosensitive sensor sub-array and a readout circuit;

FIG. 9 is a structural schematic diagram of an M×N photosensitive sensor array integrated with (M/n)×(N/n) readout circuits.

Detailed ways

This embodiment utilizes a photosensitive detector based on a composite dielectric gate as shown in Figure 1, and its structure is: it includes two parts: a photosensitive transistor 101 and a read transistor 103 formed on the same P-type semiconductor substrate, and these two parts share a A composite dielectric gate, wherein the composite dielectric gate includes a bottom dielectric layer 107 , a charge coupling layer 106 , a top dielectric layer 104 and a control gate 105 from bottom to top. Wherein, the photosensitive transistor 101 is used for sensing light and converting the light signal into an electrical signal, and the reading transistor 103 is used for reading the electrical signal. The structure of the reading transistor 103 is shown in FIG. 2 , and further includes a drain 201 and a source 202 .

According to the capacitance formula: C=ε _r S/4πkd, where C is the capacitance, ε _r is the dielectric constant, S is the facing area between the two electrode plates, k is the Coulomb constant, and d is the distance between the capacitor plates. If the area of the composite dielectric gate is small and the thickness is large, a small composite dielectric gate capacitance can be obtained. According to the formula C=Q/U, where C is the capacitance, Q is the amount of charge, and U is the voltage. At this time, a charge The amount can be converted into a larger voltage amount, thereby increasing the sensitivity of the photodetector. Therefore, the capacitance of the composite dielectric grid can be reduced to improve sensitivity by increasing the thickness of the top dielectric layer 104 and reducing the size of the composite dielectric grid, such as increasing the thickness of the top dielectric layer 104 to be greater than 10 nm, and reducing the size of the composite dielectric grid to 500nm, the capacitance of the composite dielectric gate can be made less than 0.15fF, and the conversion gain from charge to voltage under this condition, that is, the sensitivity can be greater than 1mV/e-.

The photosensitive transistor 101 of the photosensitive detector is used to convert light signals into photoelectrons, and the two exhibit a linear relationship. The photoelectrons generated by the substrate 102 are coupled to the charge-coupled layer 106, and converted into voltage through capacitance, thereby changing the threshold value of the read transistor 103 Voltage. When a fixed gate voltage is given, the drain 201 current will vary due to the threshold voltage, and the gray value of the photosensitive detector can be calculated by collecting the current signal. For a large array of photosensitive detectors, the large array of photosensitive detectors is divided into multiple sub-arrays, and each sub-array shares a readout circuit (as shown in Figure 3), so that the photosensitive detector array can be read out in parallel to achieve a high frame rate.

During the exposure process, the photoelectrons collected by the phototransistor 101 are coupled to the charge-coupled layer 106 of the composite dielectric gate at the interface between silicon and silicon dioxide, changing the potential of the charge-coupled layer 106 of the composite dielectric gate, thereby changing the threshold voltage of the read transistor 103, During the signal reading process, a positive bias pulse is applied to the control gate 105, and the magnitude of the current of the drain 201 will change with the change of the threshold voltage, so as to determine whether to collect photoelectrons.

The readout circuit of this embodiment is shown in FIG. 4 , including a correlated double sampling circuit 401 , an amplification circuit 402 and a quantization circuit 403 . During the sampling process of the correlated double sampling circuit 401, it is necessary to reset the signal sampling capacitor 501 and the reset signal sampling capacitor 502 first, and read the drain 201 current I _R of the photosensitive detector after reset and the drain current I R after exposure respectively. The current I _S of pole 201 charges the reset signal sampling capacitor 502 and the signal sampling capacitor 501 , and the voltage difference between them is the signal amount generated by the collected photoelectrons. In the amplifying circuit 402, a charge transfer amplifying circuit is used, which has the advantage of low power consumption and can reduce the overall power consumption of a large-scale photosensitive detector array. In the quantization circuit 403, single-bit quantization is performed on the output signal of the amplification circuit 402, and a single-bit ADC or D-latch601 can be used to increase the speed and reduce the area of the readout circuit, which has the advantages of effectively reducing power consumption and having high speed , which can meet the imaging requirements under low illumination conditions.

This embodiment provides a single-electron-level readout method with low noise, high gain, and high frame rate based on a composite dielectric grating photosensitive detector:

(1) Reset: Add the voltage of -4V to the control gate 105, add the voltage of -3V to the P-type substrate 102, reset the electrons collected by the MOS-C part photosensitive transistor 101 of the photosensitive detector, and switch to read mode, the reset signal is read by the correlated double sampling circuit;

(2) Exposure: Add a voltage of 0V to the control grid 105, and a voltage of -3V to the P-type substrate 102. When there is light, the energy of photoelectrons is greater than the forbidden band width of silicon, and an electron-hole pair will be excited , under the action of the electric field in the depletion region, the phototransistor 101 will collect the generated photoelectrons, the potential of the phototransistor 101 will change, and the charge coupling layer 106 coupled to the composite dielectric gate will change the potential of the charge coupling layer 106, thereby changing the opening Read the threshold voltage of the transistor 103, the variation of the threshold voltage is U=Q/C, wherein Q is the charge amount of the collected photoelectrons, and C is the capacitance of the top layer dielectric gate 104, and switch to the read mode, by the correlation double sampling circuit Read the exposure signal;

(3) Read: During the readout phase, the gate voltage can be 2-5V, such as adding a bias voltage of 3V to the control gate 105, and the substrate can be -3-0V, such as adding -3V to the P-type substrate 102 The bias voltage, gate voltage and substrate voltage need to meet the requirement that the reading transistor of the photodetector is in the linear region under both empty well and full well. The constant voltage is 0V, and the current of the drain 201 is read out by the correlated double sampling circuit 401 .

The VIN input terminal of the relevant double sampling circuit is connected to the drain 201 of the composite dielectric gate reading transistor 103. After reset, the current of the drain 201 is read, as shown in FIG. 5 , through the reset signal sampling capacitor CR502 of the relevant double sampling circuit The current of the drain 201 is sampled, and the voltage signal VOUTR of the reset signal is output. After the exposure, the current of the drain 201 is read, and the current of the drain 201 is sampled through the exposure signal sampling capacitor CS501 of the relevant double sampling circuit, and the voltage signal VOUTS of the signal is output. The difference between the two, VOUTS-VOUTR, is the signal amount corresponding to the photoelectrons collected after exposure. Using a correlated double sampling circuit can effectively reduce reset noise and shot noise.

The signals VOUTR and VOUTS output by the correlated double sampling circuit are input to the input terminals in1 and in2 of the charge transfer amplifier circuit shown in Figure 6, and the capacitor C1 and the capacitor C2 are charged by closing the switch S1, and the output is charged by closing the switch S2. The terminals out1 and out2 are pre-charged, and the voltage signal is output to out1 and out2 by opening the switch S1. After being amplified by the charge transfer amplifier, its gain is C2/C1. Because the charge-transfer amplifier charges only when the switch is closed, it effectively reduces power consumption.

The quantization circuit can use a D-latch circuit as shown in FIG. 7 . The output out1 and out2 of the charge transfer amplifier are used as the input of the D-latch circuit for single-bit quantization. Single-bit quantization can greatly improve the quantization speed, so that the photosensitive detector has an extremely short exposure time, which meets the requirements of The need for single-photon imaging during the exposure time.

Since the size of the photosensitive detector is extremely small and the size of the readout circuit is relatively large, in order to save chip area, a sub-array 801 composed of multiple photosensitive detectors can be used to share a form of a readout circuit 802 , as shown in FIG. 8 .

For the photosensitive detector array, in order to realize high-speed readout, if the photosensitive detector array is composed of M×N photosensitive detectors, each m×n photosensitive detector sub-array 901 shares a readout circuit 902, as shown in FIG. 9 , then there are (M/n)×(N/n) photosensitive detector subarrays and readout circuits, and the photosensitive detector subarray 901 corresponds to the readout circuit 902 one-to-one, compared with only one readout circuit , the readout speed is accelerated by (M/n)×(N/n) times, realizing fast readout at a high frame rate.

Claims (8)

1. The single-electron reading circuit based on the composite dielectric gate photosensitive detector comprises a photosensitive transistor and a reading transistor which are formed on the same substrate, wherein the two transistors share a composite dielectric gate which comprises a bottom dielectric layer, a charge coupling layer, a top dielectric layer and a control gate; the readout circuit is characterized by comprising a correlated double sampling circuit, an amplifying circuit and a quantizing circuit, wherein the correlated double sampling circuit is used for sampling the drain current of the reading transistor, the amplifying circuit is used for amplifying a voltage signal output by the correlated double sampling circuit, and the quantizing circuit is used for carrying out single-bit quantization on the voltage signal output by the amplifying circuit.

2. The single-electron readout circuit based on the composite dielectric gate photosensitive detector as claimed in claim 1, wherein the thickness of the top dielectric layer is greater than 10nm, and the size of the composite dielectric gate is less than 500nm.

3. The single-electron readout circuit based on the composite dielectric gate photosensitive detector as claimed in claim 1, wherein the amplification circuit is a charge transfer amplification circuit.

4. The single-electron readout circuit based on the composite dielectric gate photosensitive detector as claimed in claim 1, wherein the quantization circuit is a single-bit ADC or D-latch circuit.

5. The single-electron readout circuit based on the composite dielectric gate photosensitive detector of claim 1, wherein when the photosensitive detector is a plurality of photosensitive detectors, the array structure is divided into a plurality of sub-arrays, and each sub-array shares one readout circuit.

6. A method for reading out a single-electron reading out circuit based on a composite dielectric gate photosensitive detector as claimed in any one of claims 1 to 5, comprising the steps of:

(1) Resetting: applying a voltage of-4V to the control grid and a voltage of-3V to the substrate, resetting electrons collected by a photosensitive transistor of the photosensitive detector, and reading a reset signal by a related double sampling circuit;

(2) Exposure: the voltage of 0V is applied to the control grid, the voltage of-3V is applied to the substrate, when the energy of photoelectrons is larger than the forbidden bandwidth of silicon under illumination, an electron hole pair is excited, the generated photoelectrons are collected by the photosensitive transistor under the action of an electric field of a depletion region, the potential of the photosensitive transistor is changed, and the photosensitive transistor is coupled to the charge coupling layer of the composite dielectric grid to change the potential of the charge coupling layer, so that the threshold voltage for starting the reading transistor is changed; reading the exposure signal by a correlated double sampling circuit;

(3) Reading: in the reading stage, 2-5V of voltage is applied to the control grid, and-3-0V of voltage is applied to the substrate, and the voltages of the control grid and the substrate need to meet the requirement that a reading transistor of the photosensitive detector is in a linear region under an empty well and a full well; the drain of the read transistor is supplied with a constant voltage, the source is supplied with a constant voltage of 0V, and the drain current is read by the correlated double sampling circuit.

7. A readout method according to claim 6, wherein in step (2), the threshold voltage of the read transistor varies by an amount of U = Q/C, where Q is the charge amount of collected photoelectrons and C is the capacitance of the top dielectric gate.

8. The readout method according to claim 6, wherein the correlated double sampling circuit samples the drain current through the reset signal sampling capacitor after the photosensitive detector is reset, and outputs a voltage signal VOUTR of the reset signal; after the photosensitive detector is exposed, the drain current is sampled through an exposure signal sampling capacitor, a voltage signal VOUTS of an exposure signal is output, and the difference VOUTS-VOUTR of the two voltage signals is the signal quantity corresponding to photoelectrons collected after exposure.

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