CN115361002B

CN115361002B - Signal generation control circuit for timer

Info

Publication number: CN115361002B
Application number: CN202211277326.XA
Authority: CN
Inventors: 张跃玲; 万海军; 束克留; 韩兴成
Original assignee: Suzhou Powerlink Microelectronics Inc
Current assignee: Suzhou Powerlink Microelectronics Inc
Priority date: 2022-10-19
Filing date: 2022-10-19
Publication date: 2023-03-24
Anticipated expiration: 2042-10-19
Also published as: CN115361002A

Abstract

The invention discloses a signal generation control circuit for a timer, which comprises: the trigger circuit comprises a first input trigger circuit, a second input trigger circuit, a third input trigger circuit, a selector, a trigger controller and an encoder. The signal generation control circuit for the timer according to the embodiment of the present invention can be used as generation of a count clock of the timer which needs to be generated by register configuration, and can have a variety of clock source mode selections. Besides enabling starting, resetting initialization and the like of the software configuration timer, the method can also trigger the enabling and resetting characteristics of the hardware trigger circuit when external input events occur in the characteristic mode. And the internally designed low pass filter may be programmed to configure the characteristics of the selected low pass filtering process for the external signal.

Description

Signal generation control circuit for timer

Technical Field

The present invention relates to the field of integrated circuits, and more particularly, to a signal generation control circuit for a timer.

Background

With the development of the SOC/MCU integration technology, the popularity of MCU products and driving motor control is increasing. The timer is used as an important device for controlling time, the requirement on a required clock signal is higher and higher along with the increase of functional requirements, and the existing clock signal has a single form and cannot meet the requirement of the timer at all.

The information disclosed in this background section is only for enhancement of understanding of the general background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art that is already known to a person skilled in the art.

Disclosure of Invention

The invention aims to provide a signal generation control circuit for a timer, which can generate clock signals in different forms to meet the requirements of the timer.

To achieve the above object, an embodiment of the present invention provides a signal generation control circuit for a timer, including:

the first input trigger circuit generates a driving signal based on filtering, polarity selection and edge detection of an external clock input signal;

the second input trigger circuit generates a logic driving signal based on polarity selection, pre-frequency division and filtering of an external trigger input signal;

a third input trigger circuit generating a selection signal based on selecting the internal trigger input signal;

the selector is used for selecting the driving signal, the logic driving signal and the selection signal to output a trigger signal; and

a trigger controller, the trigger controller comprising:

an enable signal generation circuit that generates a first enable signal for enabling the timer based on an edge signal of the trigger signal in the trigger mode;

a gate signal generation circuit that generates a second enable signal for enabling the timer based on the first enable signal or based on the trigger signal if the first enable signal is active;

a reset signal generating circuit which generates a reset signal for resetting the timer based on an edge signal of the trigger signal;

the clock signal generating circuit is used for generating a clock signal for the timer to work based on the trigger signal, the logic driving signal, the counting clock signal output by the encoder and the internal clock signal;

the signal generation control circuit further comprises an encoder which generates a direction count signal and a count clock signal for the timer to work based on the driving signal and the configuration bit sms.

In one or more embodiments of the present invention, the first input trigger circuit includes a first low pass filter, a first edge detection circuit, a first inverter, a first selector, a second low pass filter, a second edge detection circuit, a second inverter, and a second selector;

the first low-pass filter is used for receiving a first external clock input signal, the first low-pass filter is simultaneously connected with the first edge detection circuit, the first input end of the first selector is connected with the first edge detection circuit, the second input end of the first selector is connected with the output end of the first phase inverter, the input end of the first phase inverter is connected with the first edge detection circuit, the selection control end of the first selector is connected with the configuration bit, and the output end of the first selector is connected with the first input end of the selector;

the second low-pass filter is used for receiving a second external clock input signal, the second low-pass filter is simultaneously connected with the second edge detection circuit, the first input end of the second selector is connected with the second edge detection circuit, the second input end of the second selector is connected with the output end of the second phase inverter, the input end of the second phase inverter is connected with the second edge detection circuit, the output end of the second selector is connected with the second input end of the selector, the third input end of the selector is used for receiving a logic driving signal, the fourth input end of the selector is used for receiving a selection signal, and the selection control end of the selector is connected with the configuration bit.

In one or more embodiments of the present invention, the second input trigger circuit includes a third inverter, a fourth selector, a frequency division counter, a fifth selector, a third low pass filter, a sampling frequency division clock counter, a sixth selector, a first D flip-flop, and a seventh selector;

the first input end of the fourth selector is used for receiving an external trigger input signal, the second input end of the fourth selector is connected with the output end of a third inverter, the input end of the third inverter is used for receiving an external trigger input signal, the selection control end of the fourth selector is connected with a configuration bit, the output end of the fourth selector is connected with a frequency division counter, the input end of the fifth selector is connected with the frequency division counter, the selection control end of the fifth selector is connected with the configuration bit, the output end of the fifth selector is connected with a third low-pass filter, the input end of the sixth selector is connected with a sampling frequency division clock counter, the selection control end of the sixth selector is connected with the configuration bit, the D input end of the first D flip-flop is connected with the output end of the sixth selector, the first input end of the seventh selector is connected with the Q output end of the first D flip-flop, the second input end of the seventh selector is used for receiving an internal clock signal, the selection control end of the seventh selector is connected with the configuration bit, the output end of the seventh selector is connected with the third low-pass filter to output a sampling clock signal, and drive the third low-pass filter.

In one or more embodiments of the present invention, the third low pass filter includes a fourth inverter, a first and gate, an eighth selector, a fifth inverter, a second and gate, a ninth selector, a tenth selector, an eleventh selector, a second D flip-flop, a sixth inverter, a third and gate, a twelfth selector, a seventh inverter, a fourth and gate, a thirteenth selector, a fourteenth selector, a fifteenth selector, and a third D flip-flop;

a first input end of the eighth selector is used for receiving a high level signal, a second input end of the eighth selector is connected with a Q output end of the second D flip-flop, the selection control end of the eighth selector is connected with the first comparison signal, the output end of the eighth selector is connected with the first input end of the eleventh selector, a first input end of the ninth selector is used for receiving a low level signal, a second input end of the ninth selector is connected with a Q output end of the second D flip-flop, the selection control end of the ninth selector is connected with the first comparison signal, the output end of the ninth selector is connected with the first input end of the tenth selector, a second input terminal of the tenth selector is connected to the Q output terminal of the second D flip-flop, an input terminal of the fifth inverter is connected to an output terminal of the fifth selector, the output end of the fifth inverter is connected with the second input end of the second AND gate, the first input end of the second AND gate is connected with the Q output end of the second D flip-flop, the output end of the second AND gate is connected with the selection control end of a tenth selector, the second input end of the eleventh selector is connected with the output end of the tenth selector, the input end of the fourth inverter is connected with the Q output end of the second D trigger, the first input end of the first AND gate is connected with the output end of the fifth selector, the second input end of the first AND gate is connected with the output end of the fourth inverter, the selection control end of the eleventh selector is connected with the output end of the first AND gate, the output end of the eleventh selector is connected with the D input end of the second D trigger, and the clock control end of the second D trigger is connected with the input end of the seventh selector;

a first input terminal of the twelfth selector is configured to receive an initial value of a count of the third low-pass filter, the second input end of the twelfth selector is connected with the second comparison signal, the selection control end of the twelfth selector is connected with the first comparison signal, an output end of the twelfth selector is connected with a first input end of a fifteenth selector, a first input end of the thirteenth selector is used for receiving a counting initial value of a third low-pass filter, the second input end of the thirteenth selector is connected with the second comparison signal, the selection control end of the thirteenth selector is connected with the first comparison signal, an output end of the thirteenth selector is connected with a first input end of a fourteenth selector, a second input end of the fourteenth selector is connected with a Q output end of the third D flip-flop, the input end of the seventh inverter is connected with the output end of the fifth selector, the output end of the seventh inverter is connected with the second input end of the fourth AND gate, a first input end of the fourth AND gate is connected with a Q output end of the second trigger, an output end of the fourth AND gate is connected with a selection control end of the fourteenth selector, a second input end of the fifteenth selector is connected with an output end of the fourteenth selector, an input end of the sixth inverter is connected with a Q output end of the second D flip-flop, the first input end of the third AND gate is connected with the output end of the fifth selector, the second input end of the third AND gate is connected with the output end of the sixth inverter, and the selection control end of the fifteenth selector is connected with the output end of the third AND gate, the output end of the fifteenth selector is connected with the D input end of the third D trigger, and the time control end of the third D trigger is connected with the input end of the seventh selector.

In one or more embodiments of the present invention, the third input trigger circuit includes a third selector, a first input terminal of the third selector is configured to receive the first internal trigger input signal, a second input terminal of the third selector is configured to receive the second internal trigger input signal, a third input terminal of the third selector is connected to the first edge detection circuit, a selection control terminal of the third selector is connected to the configuration bit ts, and an output terminal of the third selector is connected to a fourth input terminal of the selector.

In one or more embodiments of the present invention, the enable signal generating circuit includes a fifth and gate, a fourth D flip-flop, a sixteenth selector, a seventeenth selector, an eighteenth selector, and a fifth D flip-flop;

the first input end of the fifth and gate is connected with a configuration bit sms, the second input end of the fifth and gate is used for receiving a rising edge signal of a trigger signal, the D input end of the fourth D flip-flop is connected with the output end of the fifth and gate, the Q output end of the fourth D flip-flop is connected with the second input end of the sixteenth selector, the D input end of the fourth D flip-flop is connected with the first input end of the sixteenth selector, the selection control end of the sixteenth selector is connected with the configuration bit, the first input end of the seventeenth selector is connected with a high level signal, the second input end of the seventeenth selector is connected with a low level signal, the selection control end of the seventeenth selector is connected with the output end of the sixteenth selector, the first input end of the eighteenth selector is a data write-in end, the second input end of the eighteenth selector is connected with the output end of the seventeenth selector, the selection control end of the eighteenth selector is a data write-in end, the output end of the eighteenth selector is connected with the D flip-flop, the fifth D flip-flop is used for receiving a clock signal, and enabling the Q output end of the fifth flip-flop to output signal.

In one or more embodiments of the present invention, the gate signal generating circuit includes a sixth and gate, a sixth D flip-flop, a nineteenth selector, a twentieth selector, a seventh D flip-flop, and an eighth D flip-flop;

the first input end of the sixth and gate is used for receiving a trigger signal, the second input end of the sixth and gate is used for receiving a first enable signal, the D input end of the sixth D flip-flop is connected with the output end of the sixth and gate, the clock control end of the sixth D flip-flop is used for receiving an internal clock signal, the Q output end of the sixth D flip-flop is connected with the second input end of the nineteenth selector, the D input end of the sixth D flip-flop is connected with the first input end of the nineteenth selector, the selection control end of the nineteenth selector is connected with the configuration bit msm, the output end of the nineteenth selector is connected with the first input end of the twentieth selector, the second input end of the twentieth selector is used for receiving a first enable signal, the selection control end of the twentieth selector is connected with the configuration bit sms, the D input end of the seventh D flip-flop is connected with the output end of the twentieth selector, the Q output end of the seventh D flip-flop is connected with the D input end of the eighth D flip-flop, and the eighth D flip-flop is used for outputting a second enable signal.

In one or more embodiments of the present invention, the reset signal generating circuit includes a twenty-first selector, a ninth D flip-flop, a twenty-second selector, and a first or gate;

the first input end of the twenty-first selector is used for receiving a rising edge signal of a trigger signal, the second input end of the twenty-first selector is connected with a low level signal, the selection control end of the twenty-first selector is connected with a configuration bit sms, the D input end of the ninth D flip-flop is connected with the output end of the twenty-first selector, the clock control end of the ninth D flip-flop is connected with an internal clock signal, the first input end of the twenty-second selector is connected with the output end of the twenty-first selector, the second input end of the twenty-second selector is connected with the Q output end of the ninth D flip-flop, the selection control end of the twenty-second selector is connected with the configuration bit msm, the first input end of the first OR gate is connected with the output end of the twenty-second selector, the second input end of the first OR gate is a data writing end, and the output end of the first OR gate is used for outputting a reset signal.

In one or more embodiments of the present invention, the clock signal generation circuit includes a tenth D flip-flop, an eleventh D flip-flop, an eighth inverter, a seventh and gate, a twenty-third selector, and an eighth and gate;

a D input end of the tenth D flip-flop is configured to receive a trigger signal, a Q output end of the tenth D flip-flop is connected to a D input end of an eleventh D flip-flop, an input end of the eighth inverter is connected to a Q output end of the eleventh D flip-flop, a first input end of the seventh and gate is connected to a Q output end of the tenth D flip-flop, a second input end of the seventh and gate is connected to an output end of the eighth inverter, an output end of the seventh and gate is configured to output a rising edge signal of the trigger signal, and a first input end of the twenty-third selector is configured to receive a logic driving signal, the second input end of the twenty-third selector is connected with the output end of a seventh AND gate, the third input end of the twenty-third selector is connected with the encoder, the fourth input end of the twenty-third selector is used for receiving an internal clock signal, the output end of the twenty-third selector is connected with the first input end of an eighth AND gate, the output end of the twenty-third selector is connected with the clock control ends of a seventh D trigger and an eighth D trigger, the second input end of the eighth AND gate is used for receiving a second enable signal, and the output end of the eighth AND gate is used for outputting a clock signal.

In one or more embodiments of the present invention, the encoder comprises a fifteenth D trigger, a sixteenth D trigger, a seventeenth D trigger, an eighteenth D trigger, a seventeenth inverter, an eighteenth inverter, a nineteenth inverter, a twentieth inverter, a twenty-first AND gate, a twenty-second AND gate, a twenty-third AND gate, a twenty-fourth AND gate, a second OR gate, a third OR gate, a fourth OR gate, a forty-first selector, a ninth inverter, a ninth AND gate, a tenth inverter, a tenth AND gate, an eleventh inverter, an eleventh AND gate, a twelfth inverter, a twelfth AND gate, a thirteenth inverter, a fourteenth inverter, a thirteenth AND gate, a fourteenth AND gate, a fifteenth AND gate, a sixteenth AND gate, a twenty-fourth selector, a twenty-fifth selector, a twenty-sixth selector, a twenty-seventh selector, a twelfth D trigger, a seventeenth AND gate, a fifteenth AND gate, a fourteenth selector, a twenty-fourth selector, a twenty-fifth selector, a twenty-sixth selector, a twenty-seventh selector, a twenty-fourth D trigger, a seventeenth inverter, a sixteenth and a sixteenth selector a fifteenth inverter, a sixteenth inverter, a seventeenth and, eighteenth and, nineteenth and, twentieth and, twenty-eighth selector, a twenty-ninth selector, a thirtieth selector, a thirty-eleventh selector, a thirteenth flip-flop, a twenty-first inverter, a twenty-second inverter, a twenty-third inverter, a twenty-fourth inverter, a twenty-fifth and, a twenty-sixth and, a twenty-seventh and, a twenty-eighth and, a twenty-ninth and, a thirty-eighth and, a thirty-eleventh and, a thirty-second selector, a thirty-third selector, a thirty-fourth selector, a thirty-fifth selector, a thirty-sixth selector, a thirty-seventh selector, a thirty-eighth selector, a thirty-ninth selector, a fourteenth and a forty selector;

the D input end of the fifteenth D flip-flop is configured to receive a second driving signal, the D input end of the sixteenth D flip-flop is connected to the Q output end of the fifteenth D flip-flop, the clock control ends of the fifteenth D flip-flop and the sixteenth D flip-flop are configured to receive an internal clock signal, the input end of the seventeenth inverter is connected to the Q output end of the fifteenth D flip-flop, the first input end of the twenty-first and-gate is connected to the output end of the seventeenth inverter, the second input end of the twenty-first and-gate is connected to the Q output end of the sixteenth D flip-flop, the input end of the eighteenth inverter is connected to the Q output end of the sixteenth D flip-flop, the first input end of the twenty-second and-gate is connected to the Q output end of the fifteenth D flip-flop, the second input end of the twenty-second and-gate is connected to the output end of the eighteenth inverter, the first input end of the second or-gate is connected to the output end of the twenty-second and-gate, and the second input end of the twenty-gate is connected to the output end of the twenty-second and-gate;

a D input end of the seventeenth D flip-flop is used for receiving a first driving signal, a D input end of the eighteenth D flip-flop is connected with a Q output end of the seventeenth D flip-flop, clock control ends of the seventeenth D flip-flop and the eighteenth D flip-flop are used for receiving an internal clock signal, an input end of the nineteenth inverter is connected with a Q output end of the seventeenth D flip-flop, a first input end of the twenty-third and gate is connected with an output end of the nineteenth inverter, the second input end of the twenty-third AND gate is connected with the Q output end of an eighteenth D trigger, the input end of the twentieth inverter is connected with the Q output end of the eighteenth D trigger, the first input end of the twenty-fourth AND gate is connected with the Q output end of the seventeenth D trigger, the second input end of the twenty-fourth AND gate is connected with the output end of the twentieth inverter, the first input end of the third OR gate is connected with the output end of the twenty-third AND gate, and the second input end of the third OR gate is connected with the output end of the twenty-fourth AND gate;

a first input end of the fourth or gate is connected with an output end of the third or gate, a second input end of the fourth or gate is connected with an output end of the second or gate, a first input end of the forty-first selector is connected with an output end of the second or gate, a second input end of the forty-first selector is connected with an output end of the third or gate, a third input end of the forty-first selector is connected with an output end of the fourth or gate, a fourth input end of the forty-first selector is connected with a low level signal, a selection control end of the forty-first selector is connected with a configuration bit sms, and an output end of the forty-first selector is used for outputting a counting clock signal;

the input end of the ninth inverter is connected with the Q output end of an eighteenth D trigger, the first input end of the ninth inverter is connected with a first driving signal, the second input end of the ninth inverter is connected with the output end of the ninth inverter, the input end of the tenth inverter is connected with the first driving signal, the first input end of the tenth inverter is connected with the output end of the tenth inverter, the second input end of the tenth inverter is connected with the Q output end of the eighteenth D trigger, the input end of the eleventh inverter is connected with the Q output end of the sixteenth D trigger, the first input end of the eleventh inverter is connected with a second driving signal, the second input end of the eleventh inverter is connected with the output end of the eleventh inverter, the input end of the twelfth inverter is connected with the second driving signal, the first input end of the twelfth inverter is connected with the output end of the twelfth inverter, and the second input end of the twelfth inverter is connected with the Q output end of the sixteenth D trigger;

the first input end of the thirteenth AND gate is connected with the output end of the tenth AND gate, the second input end of the thirteenth AND gate is connected with the second driving signal, the first input end of the twenty-fourth selector is used for receiving a low level signal, the second input end of the twenty-fourth selector is connected with the Q output end of the twelfth D flip-flop, the selection control end of the twenty-fourth selector is connected with the output end of the thirteenth AND gate, the input end of the thirteenth inverter is connected with the second driving signal, the first input end of the fourteenth AND gate is connected with the output end of the tenth AND gate, the selection control end of the twenty-fifth selector is connected with the output end of the fourteenth AND gate, the first input end of the twenty-fifth selector is used for receiving a high level signal, and the second input end of the twenty-fifth selector is connected with the output end of the twenty-fourth selector, the input end of the fourteenth inverter is connected with the second driving signal, the first input end of the fifteenth and-gate is connected with the output end of the ninth and-gate, the second input end of the fifteenth and-gate is connected with the output end of the fourteenth inverter, the selection control end of the twenty-sixth selector is connected with the output end of the fifteenth and-gate, the first input end of the twenty-sixth selector is connected with the low level signal, the second input end of the twenty-sixth selector is connected with the output end of the twenty-sixth selector, the first input end of the sixteenth and-gate is connected with the output end of the ninth and-gate, the second input end of the sixteenth and-gate is connected with the second driving signal, the first input end of the twenty-seventh selector is used for receiving the high level signal, and the second input end of the twenty-seventh selector is connected with the output end of the twenty-sixth selector, a D input end of the twelfth D trigger is connected with an output end of the twenty-seventh selector, and a clock control end of the twelfth D trigger is used for receiving an internal clock signal;

the input end of the fifteenth inverter is connected with a first driving signal, the first input end of the seventeenth and gate is connected with the output end of the twelfth and gate, the second input end of the seventeenth and gate is connected with the output end of the fifteenth inverter, the first input end of the twenty-eighth selector is connected with a low level signal, the second input end of the twenty-eighth selector is connected with the Q output end of the thirteenth D trigger, the selection control end of the twenty-eighth selector is connected with the output end of the seventeenth and gate, the first input end of the eighteenth and gate is connected with the output end of the twelfth and gate, the second input end of the eighteenth and gate is connected with the first driving signal, the first input end of the twenty-ninth selector is connected with a high level signal, and the second input end of the twenty-ninth selector is connected with the output end of the twenty-eighth selector, the selection control end of the twenty-ninth selector is connected with the output end of the eighteenth AND gate, the first input end of the nineteenth AND gate is connected with the output end of the eleventh AND gate, the second input end of the nineteenth AND gate is connected with the first driving signal, the first input end of the thirtieth selector is connected with the low level signal, the second input end of the thirtieth selector is connected with the output end of the twenty-ninth selector, the first input end of the twentieth AND gate is connected with the output end of the eleventh AND gate, the input end of the sixteenth inverter is connected with the first driving signal, the second input end of the twentieth AND gate is connected with the output end of the sixteenth inverter, the first input end of the thirty-eleventh selector is connected with the high level signal, and the second input end of the thirty-eighth selector is connected with the output end of the thirtieth selector, a D input end of the thirteenth D flip-flop is connected to an output end of the thirty-first selector, and a clock control end of the thirteenth D flip-flop is configured to receive an internal clock signal;

the input end of the twenty-first inverter is connected with a first driving signal, the first input end of the twenty-fifth and gate is connected with the output end of the twelfth and gate, the second input end of the twenty-fifth and gate is connected with the output end of the twenty-first inverter, the first input end of the thirty-second selector is connected with a low level signal, the second input end of the thirty-second selector is connected with the Q output end of the fourteenth D trigger, the selection control end of the thirty-second selector is connected with the output end of the twenty-fifth and gate, the first input end of the twenty-sixth and gate is connected with the output end of the twelfth and gate, the second input end of the twenty-sixth and gate is connected with the first driving signal, the first input end of the thirty-third selector is connected with a high level signal, and the second input end of the thirty-third selector is connected with the output end of the thirty-second selector, the selection control end of the thirty-third selector is connected with the output end of a twenty-sixth AND gate, the first input end of the twenty-seventh AND gate is connected with a first driving signal, the second input end of the twenty-seventh AND gate is connected with the output end of an eleventh AND gate, the first input end of the thirty-fourth selector is connected with a low level signal, the second input end of the thirty-fourth selector is connected with the output end of a thirty-third selector, the selection control end of the thirty-fourth selector is connected with the output end of a twenty-seventh AND gate, the input end of a twenty-second inverter is connected with a first driving signal, the first input end of a twenty-eighth AND gate is connected with the output end of an eleventh AND gate, the second input end of the twenty-eighth AND gate is connected with the output end of a twenty-second inverter, and the first input end of the thirty-fifth selector is connected with a high level signal, the second input end of the thirty-fifth selector is connected with the output end of the thirty-fourth selector, the selection control end of the thirty-fifth selector is connected with the output end of the twenty-eighth AND gate, the first input end of the twenty-ninth AND gate is connected with the output end of the tenth AND gate, the second input end of the twenty-ninth AND gate is connected with the second driving signal, the first input end of the thirty-sixth selector is connected with the low level signal, the second input end of the thirty-sixth selector is connected with the output end of the thirty-fifth selector, the selection control end of the thirty-sixth selector is connected with the output end of the twenty-ninth AND gate, the input end of the twenty-third inverter is connected with the second driving signal, the first input end of the thirty-AND gate is connected with the output end of the tenth AND gate, and the second input end of the thirty-AND gate is connected with the output end of the twenty-third inverter, a first input end of the thirty-seventh selector is connected with a high level signal, a second input end of the thirty-seventh selector is connected with an output end of the thirty-sixth selector, a selection control end of the thirty-seventh selector is connected with an output end of the thirty-seventh and gate, an input end of the twenty-fourth inverter is connected with a second driving signal, a first input end of the thirty-eleventh and gate is connected with an output end of the twenty-fourth inverter, a second input end of the thirty-eleventh and gate is connected with an output end of the ninth and gate, a first input end of the thirty-eighth selector is connected with a low level signal, a second input end of the thirty-eighth selector is connected with an output end of the thirty-seventh selector, a selection control end of the thirty-eighth selector is connected with an output end of the thirty-eleventh and gate, and a first input end of the thirty-second and gate is connected with an output end of the ninth and gate, a second input end of the thirty-second and gate is connected with the second driving signal, a first input end of the thirty-ninth selector is connected with the high level signal, a second input end of the thirty-ninth selector is connected with an output end of the thirty-eighth selector, a selection control end of the thirty-ninth selector is connected with an output end of the thirty-second and gate, a D input end of the fourteenth D flip-flop is connected with an output end of the thirty-ninth selector, and a clock control end of the fourteenth D flip-flop is used for receiving the internal clock signal;

a first input end of the fortieth selector is connected with a Q output end of the thirteenth D flip-flop, a second input end of the fortieth selector is connected with a Q output end of the twelfth D flip-flop, a third input end of the fortieth selector is connected with a Q output end of the fourteenth D flip-flop, a fourth input end of the fortieth selector is connected with a low level signal, a selection control end of the fortieth selector is connected with a configuration bit sms, and an output end of the fortieth selector is used for outputting a direction count signal.

Compared with the prior art, the signal generation control circuit for the timer according to the embodiment of the invention can be used for generating the counting clock of the timer which needs to be generated through register configuration, and can be provided with various clock source mode selections.

Besides enabling starting, resetting initialization and the like of the software configuration timer, the method can also trigger the enabling and resetting characteristics of the hardware trigger circuit when external input events occur in the characteristic mode. And the internally designed low pass filter may be programmed to configure the characteristics of the low pass filtering process selected for the external signal.

And an encoder mode is internally designed, and a counting clock and a counting direction in the encoder mode are generated according to the edge change of the externally input signal.

The circuit can be integrated in an MUC/SoC circuit and used as a control trigger circuit of a basic counting unit, and has the advantages of low power consumption, strong universality, small occupied area and cost saving.

Drawings

Fig. 1 is a system schematic diagram of a signal generation control circuit according to an embodiment of the present invention.

Fig. 2 is a partial schematic diagram of a signal generation control circuit according to an embodiment of the present invention.

Fig. 3 is a circuit schematic of a second input trigger circuit according to an embodiment of the present invention.

Fig. 4a is a schematic circuit diagram of a part of a third low-pass filter according to an embodiment of the invention.

Fig. 4b is another circuit schematic of a portion of a third low pass filter according to an embodiment of the invention.

Fig. 5 is a circuit schematic diagram of an enable signal generating circuit according to an embodiment of the present invention.

Fig. 6 is a circuit schematic diagram of a gate signal generating circuit according to an embodiment of the present invention.

Fig. 7 is a circuit schematic of a reset signal generating circuit according to an embodiment of the present invention.

Fig. 8 is a circuit schematic of a clock signal generating circuit according to an embodiment of the present invention.

Fig. 9a is a first partial circuit diagram of a first circuit schematic of an encoder according to an embodiment of the present invention.

Fig. 9b is a second partial circuit diagram of the first circuit schematic of an encoder according to an embodiment of the invention.

Fig. 9c is a third partial circuit diagram of the first circuit schematic of an encoder according to an embodiment of the present invention.

Fig. 10 is a second circuit schematic of an encoder according to an embodiment of the present invention.

Fig. 11 is a third circuit schematic of an encoder according to an embodiment of the present invention.

FIG. 12 is a fourth circuit schematic of an encoder according to an embodiment of the present invention.

Fig. 13 is a fifth circuit schematic of an encoder according to an embodiment of the present invention.

Fig. 14 is a sixth circuit schematic of an encoder according to an embodiment of the present invention.

FIG. 15a is a signal waveform diagram corresponding to an encoding mode according to an embodiment of the present invention.

FIG. 15b is a signal waveform diagram corresponding to the second encoding mode according to an embodiment of the invention.

FIG. 15c is a signal waveform diagram corresponding to coding mode three according to an embodiment of the present invention.

Detailed Description

Specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings, but it should be understood that the scope of the present invention is not limited to the specific embodiments.

Throughout the specification and claims, unless explicitly stated otherwise, the word "comprise", or variations such as "comprises" or "comprising", will be understood to imply the inclusion of a stated element or component but not the exclusion of any other element or component.

As shown in fig. 1, a signal generation control circuit for a timer includes: the trigger circuit comprises a first input trigger circuit, a second input trigger circuit, a third input trigger circuit, a selector, a trigger controller and an encoder.

The first input trigger circuit generates a first driving signal ti1fp1 and a second driving signal ti2fp2 based on filtering, polarity selection and edge detection of a first external clock input signal ti1 and a second external clock input signal ti 2.

As shown in fig. 2, the first input trigger circuit includes a first low pass filter, a first edge detection circuit, a first inverter, a first selector, a second low pass filter, a second edge detection circuit, a second inverter, and a second selector.

The first low pass filter is used for receiving a first external clock input signal ti1, and is simultaneously connected with the first edge detection circuit. The first input end of the first selector is connected with the first edge detection circuit, the second input end of the first selector is connected with the output end of the first phase inverter, the input end of the first phase inverter is connected with the first edge detection circuit, the selection control end of the first selector is connected with the configuration bit cc1p of the register, and the output end of the first selector is connected with the first input end of the selector. The first selector and the first inverter are used for polarity selection.

The second low-pass filter is used for receiving a second external clock input signal ti2, and is connected with the second edge detection circuit at the same time. The first input end of the second selector is connected with the second edge detection circuit, the second input end of the second selector is connected with the output end of the second phase inverter, the input end of the second phase inverter is connected with the second edge detection circuit, and the output end of the second selector is connected with the second input end of the selector. The third input end of the selector is used for receiving the logic driving signal etrf output by the second input trigger circuit, the fourth input end of the selector is used for receiving the selection signal output by the third input trigger circuit, and the selection control end of the selector is connected with the configuration bit sms of the register. The second selector and the second inverter are used for polarity selection.

As shown in fig. 1, the second input trigger circuit generates a logic driving signal etrf based on polarity selection, prescaler, and filtering of an external trigger input signal etr.

As shown in fig. 3, the second input flip-flop circuit includes a third inverter, a fourth selector, a frequency division counter, a fifth selector, a third low pass filter, a sampling frequency division clock counter, a sixth selector, a first D flip-flop, and a seventh selector.

The first input end of the fourth selector is used for receiving an external trigger input signal etr, the second input end of the fourth selector is connected with the output end of the third inverter, the input end of the third inverter is used for receiving the external trigger input signal etr, the selection control end of the fourth selector is connected with the configuration bit etp of the register, and the output end of the fourth selector is connected with the frequency division counter. The input end of the fifth selector is connected with the frequency division counter, the selection control end of the fifth selector is connected with the configuration bit stps of the register, and the output end of the fifth selector is connected with the third low-pass filter to output a signal etrp. The input end of the sixth selector is connected with the sampling frequency division clock counter, the selection control end of the sixth selector is connected with the configuration bit etf of the register, and the D input end of the first D trigger is connected with the output end of the sixth selector. A first input end of the seventh selector is connected to the Q output end of the first D flip-flop, a second input end of the seventh selector is configured to receive the internal clock signal clk _ per, a selection control end of the seventh selector is connected to the configuration bit etf of the register, an output end of the seventh selector is connected to the third low-pass filter to output the sampling clock signal sampling _ clk, and meanwhile, the third low-pass filter outputs the logic driving signal etrf to the third input end of the selector.

As shown in fig. 4a, 4b and 3, further, the third low pass filter includes a fourth inverter, a first and gate, an eighth selector, a fifth inverter, a second and gate, a ninth selector, a tenth selector, an eleventh selector, a second D flip-flop, a sixth inverter, a third and gate, a twelfth selector, a seventh inverter, a fourth and gate, a thirteenth selector, a fourteenth selector, a fifteenth selector and a third D flip-flop.

A first input end of the eighth selector is configured to receive a high-level signal 1' b1, a second input end of the eighth selector is connected to the Q output end of the second D flip-flop, a selection control end of the eighth selector is connected to a first comparison signal, the first comparison signal is "1" if the output signal of the Q output end of the third D flip-flop is "0", and an output end of the eighth selector is connected to the first input end of the eleventh selector.

A first input terminal of the ninth selector is configured to receive the low-level signal 1' b0, a second input terminal of the ninth selector is connected to the Q output terminal of the second D flip-flop, a selection control terminal of the ninth selector is connected to the first comparison signal, and an output terminal of the ninth selector is connected to the first input terminal of the tenth selector. The second input end of the tenth selector is connected with the Q output end of the second D flip-flop, the input end of the fifth inverter is connected with the output end of the fifth selector to receive the signal etrp, the output end of the fifth inverter is connected with the second input end of the second and gate, the first input end of the second and gate is connected with the Q output end of the second D flip-flop, the output end of the second and gate is connected with the selection control end of the tenth selector, and the second input end of the eleventh selector is connected with the output end of the tenth selector.

The input end of the fourth inverter is connected with the Q output end of the second D flip-flop, the first input end of the first AND gate is connected with the output end of the fifth selector to receive the signal etrp, the second input end of the first AND gate is connected with the output end of the fourth inverter, and the selection control end of the eleventh selector is connected with the output end of the first AND gate. An output end of the eleventh selector is connected to a D input end of the second D flip-flop, and a clock control end of the second D flip-flop is connected to an input end of the seventh selector to receive the sampling clock signal sampling _ clk.

A first input end of the twelfth selector is configured to receive the initial count value fliter _ cnt _ th of the third low-pass filter, the initial count value fliter _ cnt _ th is decoded according to the configuration bit etf of the register, a second input end of the twelfth selector is connected to a second comparison signal, the second comparison signal is a difference value between the signal filter _ cnt output by the Q output end of the third D flip-flop and the signal 4' b0001, a selection control end of the twelfth selector is connected to the first comparison signal, and an output end of the twelfth selector is connected to the first input end of the fifteenth selector.

A first input end of the thirteenth selector is configured to receive the initial count value fliter _ cnt _ th of the third low-pass filter, a second input end of the thirteenth selector is connected to the second comparison signal, a selection control end of the thirteenth selector is connected to the first comparison signal, an output end of the thirteenth selector is connected to a first input end of the fourteenth selector, and a second input end of the fourteenth selector is configured to receive the initial count value fliter _ cnt _ th of the third low-pass filter. The input end of the seventh inverter is connected with the output end of the fifth selector to receive the signal etrp, the output end of the seventh inverter is connected with the second input end of the fourth AND gate, the first input end of the fourth AND gate is connected with the Q output end of the second trigger, and the output end of the fourth AND gate is connected with the selection control end of the fourteenth selector.

A second input end of the fifteenth selector is connected with an output end of the fourteenth selector, an input end of the sixth inverter is connected with a Q output end of the second D flip-flop to receive a logic driving signal etrf, a first input end of the third and gate is connected with an output end of the fifth selector to receive a signal etrp, a second input end of the third and gate is connected with an output end of the sixth inverter, a selection control end of the fifteenth selector is connected with an output end of the third and gate, an output end of the fifteenth selector is connected with a D input end of the third D flip-flop, and a time control end of the third D flip-flop is connected with an input end of the seventh selector to receive the sampling clock signal sampling _ clk.

In this embodiment, a frequency division coefficient is selected according to a configuration bit etf of a register, counting of a sampling frequency division clock counter is performed, and a frequency-divided sampling clock signal sampling _ clk is generated according to a configuration value of the configuration bit etf of the register; the third low-pass filter performs sampling counting according to the sampling clock signal sampling _ clk and the signal etrp, until the signal etrp keeps the sampling level count value reduced to 0, and then a valid event level is considered. The signal etrp jumps by the number of counters that cannot keep the configuration value of the configuration bit etf of the register decoded, and the signal filter _ cnt output by the Q output of the third D flip-flop starts to count down from the configured filtered sample number again.

The signal etrp is the external trigger signal after polarity selection and pre-frequency division of the external trigger input signal etr. (1) In case the signal etrp is high and the logic drive signal etrf (i.e. the signal digitally filtered by the third low-pass filter) is low: when the count value of the third low-pass filter is 0, that is, the signal fliter _ cnt _ zero is 1, the signal fliter _ cnt is updated to the initial count value of the third low-pass filter, that is, the signal fliter _ cnt _ th, and the signal fliter _ cnt _ th is the initial count value decoded according to the configuration value of the configuration bit etf of the register; when the count value of the third low pass filter is not 0, i.e. the signal fliter _ cnt _ zero is 0, the signal fliter _ cnt will be self-decremented.

(2) In case the signal etrp is low and the logic drive signal etrf (i.e. the signal digitally filtered by the third low-pass filter) is high: if the count value of the third low pass filter is 0, i.e. the signal fliter _ cnt _ zero is 1, the signal fliter _ cnt is updated to the initial count value of the third low pass filter, i.e. the signal fliter _ cnt _ th, which is the initial count value decoded according to the configuration value of the configuration bit etf of the register; and when the count value of the third low-pass filter is not 0, i.e. the signal fliter _ cnt _ zero is 0, the signal fliter _ cnt will be self-reduced.

(3) Otherwise, the signal fliter _ cnt updates the counter initial value fliter _ cnt _ th of the third low-pass filter.

The above logic needs to be synchronized by the sampling clock signal sampling _ clk, that is, the sampling clock signal sampling _ clk is used as time precision to perform logic judgment on the change of the signal etrp.

The same holds for the logic for generating the logic drive signal etrf: (1) when the signal etrp is high and the logic drive signal etrf, i.e. the filtered signal, is low: when the count value of the third low-pass filter is 0, i.e. the signal fliter _ cnt _ zero is 1, the logic driving signal etrf will become a high signal 1' b1, and when the count value of the third low-pass filter is not 0, i.e. the signal fliter _ cnt _ zero is 0, the logic driving signal etrf will remain unchanged.

(2) When the signal etrp is low and the logic drive signal etrf, i.e. the filtered signal, is high: if the count value of the third low-pass filter is 0, i.e. the signal fliter _ cnt _ zero is 1, the logic driving signal etrf will become a low level signal of 1' b0, and if the count value of the third low-pass filter is not 0, the logic driving signal etrf will remain unchanged.

(3) In other cases, the logic drive signal etrf remains unchanged.

The first low-pass filter and the second low-pass filter in the present embodiment have the same structure as the third low-pass filter.

As shown in fig. 1, the third input trigger circuit generates a selection signal based on selecting an internal trigger input signal itr, which includes a first internal trigger input signal itr0 and a second internal trigger input signal itr2.

As shown in fig. 2, the third input trigger circuit includes a third selector, a first input terminal of the third selector is configured to receive the first internal trigger input signal itr0, a second input terminal of the third selector is configured to receive the second internal trigger input signal itr2, a third input terminal of the third selector is connected to the first edge detection circuit to receive the edge signal tilf _ ed of the signal tilf, a fourth input terminal of the third selector is connected to the low-level signal 1 ″ -b 0, a selection control terminal of the third selector is connected to the configuration bit ts of the register, and an output terminal of the third selector is connected to the fourth input terminal of the selector.

As shown in fig. 1, the selector selects the driving signals ti1fp1 and ti2fp2, the logic driving signal etrf and the selection signal to output the trigger signal trgi. The selection control terminal of the selector is connected to the configuration bit sms of the register, the first input terminal of the selector is configured to receive the first driving signal ti1fp1, the second input terminal of the selector is configured to receive the second driving signal ti2fp2, the third input terminal of the selector is configured to receive the logic driving signal etrf, the fourth input terminal of the selector is connected to the output terminal of the third selector to receive the selection signal, and the output terminal of the selector outputs the trigger signal trgi.

As shown in fig. 1, the trigger controller includes: the clock signal generating circuit includes an enable signal generating circuit, a gate signal generating circuit, a reset signal generating circuit, and a clock signal generating circuit.

The enable signal generation circuit generates a first enable signal cen for enabling the timer based on an edge signal of the trigger signal trgi in the trigger mode.

As shown in fig. 5, the enable signal generating circuit includes a fifth and gate, a fourth D flip-flop, a sixteenth selector, a seventeenth selector, an eighteenth selector, and a fifth D flip-flop.

The first input end of the fifth AND gate is connected with a configuration bit sms, and the configuration bit sms of the register is used for configuring the trigger mode. A second input terminal of the fifth and-gate is configured to receive a rising edge signal trgi _ rise of the trigger signal trgi, and a D input terminal of the fourth D flip-flop is connected to an output terminal of the fifth and-gate. The Q output end of the fourth D flip-flop is connected with the second input end of the sixteenth selector, the D input end of the fourth D flip-flop is connected with the first input end of the sixteenth selector, the selection control end of the sixteenth selector is connected with the configuration bit msm of the register, the first input end of the seventeenth selector is connected with a high-level signal 1'b1, the second input end of the seventeenth selector is connected with a low-level signal 1' b0, and the selection control end of the seventeenth selector is connected with the output end of the sixteenth selector.

A first input end of the eighteenth selector is a data write end, a second input end of the eighteenth selector is connected with an output end of the seventeenth selector, a selection control end of the eighteenth selector is a data write end, an output end of the eighteenth selector is connected with a D input end of the fifth D flip-flop, a clock control end of the fifth D flip-flop is used for receiving the internal clock signal clk _ per, and a Q output end of the fifth D flip-flop is used for outputting the first enable signal cen.

In this embodiment, the first enable signal cen enables enabling and disabling by writing a software write operation to the selection control terminal of the eighteenth selector; when the configuration bit sms of the register is configured in a trigger mode, and the second input end of the fifth and gate receives a rising edge signal trgi _ rise of the trigger signal trgi, the hardware triggers the first enable signal cen to set to 1 and keep; when the configuration bit msm of the register is set to 1, the first enable signal cen is set to 1 after the input of the control trigger signal trgi is delayed by one beat.

As shown in fig. 1, the gate signal generation circuit generates the second enable signal cnt _ en for enabling the timer based on the first enable signal cen or based on the trigger signal trgi in case the first enable signal cen is asserted.

As shown in fig. 6, the gate signal generating circuit includes a sixth and gate, a sixth D flip-flop, a nineteenth selector, a twentieth selector, a seventh D flip-flop, and an eighth D flip-flop.

A first input end of the sixth and gate is configured to receive the trigger signal trgi, a second input end of the sixth and gate is configured to receive the first enable signal cen, and a D input end of the sixth D flip-flop is connected to an output end of the sixth and gate. A clock control terminal of the sixth D flip-flop is configured to receive the internal clock signal clk _ per, a Q output terminal of the sixth D flip-flop is connected to the second input terminal of the nineteenth selector, a D input terminal of the sixth D flip-flop is connected to the first input terminal of the nineteenth selector, a selection control terminal of the nineteenth selector is connected to the configuration bit msm of the register, an output terminal of the nineteenth selector is connected to the first input terminal of the twentieth selector, the second input terminal of the twentieth selector is configured to receive the first enable signal cen, and a selection control terminal of the twentieth selector is connected to the configuration bit sms of the register.

A D input end of the seventh D flip-flop is connected to an output end of the twentieth selector, a Q output end of the seventh D flip-flop is connected to a D input end of the eighth D flip-flop, and a Q output end of the eighth D flip-flop is configured to output a second enable signal cnt _ en.

The timer is enabled by the selected input signal level. When the configuration bits sms of the register configure the gating mode, the second enable signal cnt _ en selects to output the trigger signal trgi, when the trigger signal trgi is high, the timer triggers the enable count, and when the trigger signal trgi is low, the second enable signal cnt _ en also becomes low; as can be seen from fig. 6, the gating trigger logic needs to enable the gating count by the trigger signal trgi when the first enable signal cen is active, i.e., the high-level logic of the second enable signal cnt _ en selects the active count by the trigger signal trgi. The configuration bit msm of the register is configured to be 1, and the trigger signal trgi is delayed by one beat to the second enable signal cnt _ en to control the counting in the gate control mode.

As shown in fig. 1, the reset signal generation circuit generates a reset signal reset for resetting the timer based on an edge signal of the trigger signal trgi.

As shown in fig. 7, the reset signal generating circuit includes a twenty-first selector, a ninth D flip-flop, a twenty-second selector, and a first or gate.

A first input terminal of the twenty-first selector is configured to receive the rising edge signal trgi _ rise of the trigger signal trgi, a second input terminal of the twenty-first selector is coupled to the low-level signal 1' b0, and a selection control terminal of the twenty-first selector is coupled to the configuration bit sms of the register. The D input end of the ninth D flip-flop is connected to the output end of the twenty-first selector, the clock control end of the ninth D flip-flop is connected to the internal clock signal clk _ per, the first input end of the twenty-second selector is connected to the output end of the twenty-first selector, the second input end of the twenty-second selector is connected to the Q output end of the ninth D flip-flop, and the selection control end of the twenty-second selector is connected to the configuration bit msm. The first input end of the first or gate is connected with the output end of the twenty-second selector, the second input end of the first or gate is a data writing end, and the output end of the first or gate is used for outputting a reset signal reset.

The second input end ug of the first or gate is operated by software, and the hardware is automatically cleared after 1 is written; in addition, the reset signal reset is controlled by a configuration mode of a configuration bit sms of the register, and when the configuration bit sms configures the reset mode, the reset signal reset is controlled by a rising edge signal trgi _ rise of the trigger signal trgi; that is, the rising edge signal trgi _ rise in the reset mode and the data writing at the second input terminal ug of the first or gate both output the reset signal reset, thereby initializing the internal timer.

As shown in fig. 1, the clock signal generation circuit generates a clock signal ck _ psc for the timer to operate based on the trigger signal trgi, the logic driving signal etrf, the count clock signal clk _ decoder output from the encoder, and the internal clock signal clk _ per.

As shown in fig. 8, the clock signal generating circuit includes a tenth D flip-flop, an eleventh D flip-flop, an eighth inverter, a seventh and gate, a twenty-third selector, and an eighth and gate.

A D input of the tenth D flip-flop is configured to receive the trigger signal trgi, a Q output of the tenth D flip-flop is connected to a D input of the eleventh D flip-flop, an input of the eighth inverter is connected to a Q output of the eleventh D flip-flop, a first input of the seventh and-gate is connected to a Q output of the tenth D flip-flop, a second input of the seventh and-gate is connected to an output of the eighth inverter, and an output of the seventh and-gate is configured to output a rising edge signal trgi _ rise of the trigger signal trgi.

A first input terminal of the twenty-third selector is configured to receive the logic driving signal etrf, a second input terminal of the twenty-third selector is coupled to an output terminal of the seventh and gate, a third input terminal of the twenty-third selector is coupled to the encoder to receive the count clock signal clk _ decoder, a fourth input terminal of the twenty-third selector is configured to receive the internal clock signal clk _ per, an output terminal of the twenty-third selector is coupled to a first input terminal of the eighth and gate, and an output terminal of the twenty-third selector is coupled to both clock control terminals of the seventh D flip-flop and the eighth D flip-flop. The selection control terminal of the twenty-third selector is controlled by a combination of a configuration bit ece and a configuration bit sms of the register, if the configuration bit ece is 111, the twenty-third selector selects a logic driving signal etrf to output, if the configuration bit ece is not 111 and the configuration bit sms is 000, the twenty-third selector selects an internal clock signal clk _ per to output, if the configuration bit ece is not 111 and the configuration bit sms is 111, the twenty-third selector selects a rising edge signal trgi _ rise of the trigger signal trgi to output, and if the configuration bit ece is not 111 and the configuration bit sms is 001, 011 or 100, the twenty-third selector selects a count clock signal clk _ decoder to output. A second input terminal of the eighth and gate is configured to receive the second enable signal cnt _ en, and an output terminal of the eighth and gate is configured to output the clock signal ck _ psc. The clock signal ck _ psc is used to provide the timer with work.

The logic driving signal etrf, the rising edge signal trgi _ rise of the trigger signal trgi, the count clock signal clk _ decoder, and the internal clock signal clk _ per correspond to four clock sources, and the signal ck _ psc _ w output from the output terminal of the twenty-third selector is derived from selection of the four clock sources. The clock signal ck _ psc is a clock signal which is generated effectively only when the second enable signal cnt _ en is turned on; to prevent clock glitch of the gated clock, as shown in fig. 6, the second enable signal cnt _ en needs to be synchronized with the signal ck _ psc _ w and then used as the gated clock enable signal.

As shown in fig. 1, the encoder generates a direction count signal dir _ decoder and a count clock signal clk _ decoder for the timer to operate based on the driving signals ti1fp1, ti2fp2 and the configuration bit sms.

As shown in fig. 9a, 9b and 9c, the encoder includes a fifteenth D flip-flop, a sixteenth D flip-flop, a seventeenth D flip-flop, an eighteenth D flip-flop, a seventeenth inverter, an eighteenth inverter, a nineteenth inverter, a twentieth inverter, a twenty-first and gate, a twenty-second and gate, a twenty-third and gate, a twenty-fourth and gate, a second or gate, a third or gate, a fourth or gate and a forty-first selector.

A D input terminal of the fifteenth D flip-flop is configured to receive the second driving signal ti2fp2, a D input terminal of the sixteenth D flip-flop is connected to a Q output terminal of the fifteenth D flip-flop, and clock control terminals of the fifteenth D flip-flop and the sixteenth D flip-flop are configured to receive the internal clock signal clk _ per. The input end of the seventeenth phase inverter is connected with the Q output end of the fifteenth D trigger, the first input end of the twenty-first AND gate is connected with the output end of the seventeenth phase inverter, the second input end of the twenty-first AND gate is connected with the Q output end of the sixteenth D trigger, the input end of the eighteenth phase inverter is connected with the Q output end of the sixteenth D trigger, the first input end of the twenty-second AND gate is connected with the Q output end of the fifteenth D trigger, the second input end of the twenty-second AND gate is connected with the output end of the eighteenth phase inverter, the first input end of the second OR gate is connected with the output end of the twenty-first AND gate, and the second input end of the second OR gate is connected with the output end of the twenty-second AND gate.

The D input terminal of the seventeenth D flip-flop is configured to receive the first driving signal ti1fp1, the D input terminal of the eighteenth D flip-flop is connected to the Q output terminal of the seventeenth D flip-flop, and the clock control terminals of the seventeenth D flip-flop and the eighteenth D flip-flop are configured to receive the internal clock signal clk _ per. The input end of the nineteenth inverter is connected with the Q output end of the seventeenth D trigger, the first input end of the twenty-third AND gate is connected with the output end of the nineteenth inverter, and the second input end of the twenty-third AND gate is connected with the Q output end of the eighteenth D trigger. The input end of the twentieth inverter is connected with the Q output end of the eighteenth D flip-flop, the first input end of the twenty-fourth AND gate is connected with the Q output end of the seventeenth D flip-flop, and the second input end of the twenty-fourth AND gate is connected with the output end of the twentieth inverter. The first input end of the third OR gate is connected with the output end of the twenty-third AND gate, and the second input end of the third OR gate is connected with the output end of the twenty-fourth AND gate.

A first input terminal of the fourth or gate is connected to an output terminal of the third or gate, a second input terminal of the fourth or gate is connected to an output terminal of the second or gate, a first input terminal of the forty-first selector is connected to an output terminal of the second or gate, a second input terminal of the forty-first selector is connected to an output terminal of the third or gate, a third input terminal of the forty-first selector is connected to an output terminal of the fourth or gate, a fourth input terminal of the forty-first selector is connected to a low level signal 1' b0, a selection control terminal of the forty-first selector is connected to a configuration bit sms of the register, and an output terminal of the forty-first selector is used for outputting a count clock signal clk _ decoder.

As shown in fig. 10 and fig. 9a and 9b, the input terminal of the ninth inverter is connected to the Q output terminal of the eighteenth D flip-flop, the first input terminal of the ninth and-gate is connected to the first driving signal ti1fp1, and the second input terminal of the ninth and-gate is connected to the output terminal of the ninth inverter. The input end of the tenth inverter is connected to the first driving signal ti1fp1, the first input end of the tenth and-gate is connected to the output end of the tenth inverter, and the second input end of the tenth and-gate is connected to the Q output end of the eighteenth D flip-flop. An input end of the eleventh inverter is connected to the Q output end of the sixteenth D flip-flop, a first input end of the eleventh and gate is connected to the second driving signal ti2fp2, and a second input end of the eleventh and gate is connected to an output end of the eleventh inverter. An input end of the twelfth inverter is connected to the second driving signal ti2fp2, a first input end of the twelfth and gate is connected to an output end of the twelfth inverter, and a second input end of the twelfth and gate is connected to the Q output end of the sixteenth D flip-flop.

As shown in fig. 11 and 10, a first input terminal of the thirteenth and-gate is connected to the output terminal of the tenth and-gate, and a second input terminal of the thirteenth and-gate is connected to the second driving signal ti2fp2. A first input terminal of the twenty-fourth selector is configured to receive the low-level signal 1' b0, a second input terminal of the twenty-fourth selector is connected to the Q output terminal of the twelfth flip-flop, and a selection control terminal of the twenty-fourth selector is connected to the output terminal of the thirteenth and gate.

The input end of the thirteenth inverter is connected to the second driving signal ti2fp2, the first input end of the fourteenth and gate is connected to the output end of the tenth and gate, and the selection control end of the twenty-fifth selector is connected to the output end of the fourteenth and gate. A first input terminal of the twenty-fifth selector is configured to receive the high signal 1' b1, and a second input terminal of the twenty-fifth selector is connected to the output terminal of the twenty-fourth selector.

An input end of the fourteenth inverter is connected to the second driving signal ti2fp2, a first input end of the fifteenth and gate is connected to an output end of the ninth and gate, a second input end of the fifteenth and gate is connected to an output end of the fourteenth inverter, a selection control end of the twenty-sixth selector is connected to an output end of the fifteenth and gate, a first input end of the twenty-sixth selector is connected to the low-level signal 1' b0, and a second input end of the twenty-sixth selector is connected to an output end of the twenty-sixth selector.

A first input terminal of the sixteenth and gate is connected to the output terminal of the ninth and gate, a second input terminal of the sixteenth and gate is connected to the second driving signal ti2fp2, a first input terminal of the twenty-seventh selector is configured to receive the high-level signal 1' b1, and a second input terminal of the twenty-seventh selector is connected to the output terminal of the twenty-sixth selector. A D input terminal of the twelfth D flip-flop is connected to the output terminal of the twenty-seventh selector, and a clock control terminal of the twelfth D flip-flop is configured to receive the internal clock signal clk _ per.

As shown in fig. 12 and 10, an input terminal of the fifteenth inverter is connected to the first driving signal ti1fp1, a first input terminal of the seventeenth and gate is connected to the output terminal of the twelfth and gate, a second input terminal of the seventeenth and gate is connected to the output terminal of the fifteenth inverter, a first input terminal of the twenty-eighth selector is connected to the low-level signal 1 ″ -b 0, a second input terminal of the twenty-eighth selector is connected to the Q output terminal of the thirteenth D flip-flop, and a selection control terminal of the twenty-eighth selector is connected to the output terminal of the seventeenth and gate.

A first input end of the eighteenth and gate is connected to the output end of the twelfth and gate, a second input end of the eighteenth and gate is connected to the first driving signal ti1fp1, a first input end of the twenty-ninth selector is connected to the high-level signal 1' b1, a second input end of the twenty-ninth selector is connected to the output end of the twenty-eighth selector, and a selection control end of the twenty-ninth selector is connected to the output end of the eighteenth and gate.

A first input terminal of the nineteenth and gate is connected to the output terminal of the eleventh and gate, a second input terminal of the nineteenth and gate is connected to the first driving signal ti1fp1, a first input terminal of the thirtieth selector is connected to the low-level signal 1' b0, and a second input terminal of the thirtieth selector is connected to the output terminal of the twenty-ninth selector.

A first input end of the twentieth and gate is connected to an output end of the eleventh and gate, an input end of the sixteenth inverter is connected to the first driving signal ti1fp1, a second input end of the twentieth and gate is connected to an output end of the sixteenth inverter, a first input end of the thirty-first selector is connected to the high-level signal 1' b1, and a second input end of the thirty-first selector is connected to an output end of the thirtieth selector. The D input terminal of the thirteenth D flip-flop is connected to the output terminal of the thirty-first selector, and the clock control terminal of the thirteenth D flip-flop is configured to receive the internal clock signal clk _ per.

As shown in fig. 13 and 10, an input terminal of the twenty-first inverter is connected to the first driving signal ti1fp1, a first input terminal of the twenty-fifth and gate is connected to an output terminal of the twelfth and gate, a second input terminal of the twenty-fifth and gate is connected to an output terminal of the twenty-first inverter, a first input terminal of the thirty-second selector is connected to the low-level signal 1' b0, a second input terminal of the thirty-second selector is connected to the Q output terminal of the fourteenth D flip-flop, and a selection control terminal of the thirty-second selector is connected to an output terminal of the twenty-fifth and gate.

A first input terminal of the twenty-sixth and gate is connected to the output terminal of the twelfth and gate, a second input terminal of the twenty-sixth and gate is connected to the first driving signal ti1fp1, a first input terminal of the thirty-third selector is connected to the high level signal 1' b1, a second input terminal of the thirty-third selector is connected to the output terminal of the thirty-second selector, and a selection control terminal of the thirty-third selector is connected to the output terminal of the twenty-sixth and gate.

A first input terminal of the twenty-seventh and gate is connected to the first driving signal ti1fp1, a second input terminal of the twenty-seventh and gate is connected to an output terminal of the eleventh and gate, a first input terminal of the thirty-fourth selector is connected to the low-level signal 1' b0, a second input terminal of the thirty-fourth selector is connected to an output terminal of the thirty-third selector, and a selection control terminal of the thirty-fourth selector is connected to an output terminal of the twenty-seventh and gate.

An input terminal of the twenty-second inverter is connected to the first driving signal ti1fp1, a first input terminal of the twenty-eighth and gate is connected to an output terminal of the eleventh and gate, a second input terminal of the twenty-eighth and gate is connected to an output terminal of the twenty-second inverter, a first input terminal of the thirty-fifth selector is connected to the high level signal 1' b1, a second input terminal of the thirty-fifth selector is connected to an output terminal of the thirty-fourth selector, and a selection control terminal of the thirty-fifth selector is connected to an output terminal of the twenty-eighth and gate.

A first input terminal of the twenty-ninth and gate is connected to the output terminal of the tenth and gate, a second input terminal of the twenty-ninth and gate is connected to the second driving signal ti2fp2, a first input terminal of the thirty-sixth selector is connected to the low-level signal 1' b0, a second input terminal of the thirty-sixth selector is connected to the output terminal of the thirty-fifth selector, and a selection control terminal of the thirty-sixth selector is connected to the output terminal of the twenty-ninth and gate.

An input end of the twenty-third inverter is connected with the second driving signal ti2fp2, a first input end of the thirty-third and gate is connected with an output end of the tenth and gate, a second input end of the thirty-third and gate is connected with an output end of the twenty-third inverter, a first input end of the thirty-seventh selector is connected with the high-level signal 1' b1, a second input end of the thirty-seventh selector is connected with an output end of the thirty-sixth selector, and a selection control end of the thirty-seventh selector is connected with an output end of the thirty-and gate.

An input terminal of the twenty-fourth inverter is connected to the second driving signal ti2fp2, a first input terminal of the thirty-first and gate is connected to an output terminal of the twenty-fourth inverter, a second input terminal of the thirty-first and gate is connected to an output terminal of the ninth and gate, a first input terminal of the thirty-eighth selector is connected to the low level signal 1' b0, a second input terminal of the thirty-eighth selector is connected to an output terminal of the thirty-seventh selector, and a selection control terminal of the thirty-eighth selector is connected to an output terminal of the thirty-first and gate.

A first input terminal of the thirty-second and gate is connected to the output terminal of the ninth and gate, a second input terminal of the thirty-second and gate is connected to the second driving signal ti2fp2, a first input terminal of the thirty-ninth selector is connected to the high level signal 1' b1, a second input terminal of the thirty-ninth selector is connected to the output terminal of the thirty-eighth selector, and a selection control terminal of the thirty-ninth selector is connected to the output terminal of the thirty-second and gate. A D input terminal of the fourteenth D flip-flop is connected to the output terminal of the thirty-ninth selector, and a clock control terminal of the fourteenth D flip-flop is configured to receive the internal clock signal clk _ per.

As shown in fig. 14, 11, 12 and 13, a first input terminal of a fortieth selector is connected to the Q output terminal of the thirteenth D flip-flop, a second input terminal of the fortieth selector is connected to the Q output terminal of the twelfth D flip-flop, a third input terminal of the fortieth selector is connected to the Q output terminal of the fourteenth D flip-flop, a fourth input terminal of the fortieth selector is connected to the low-level signal of 1 ″ -b 0, a selection control terminal of the fortieth selector is connected to the configuration bit sms, and an output terminal of the fortieth selector is used for outputting the direction count signal dir _ decoder.

In this embodiment, the encoder may be configured according to the configuration bit sms of the register and according to the relative relationship count of the first external clock input signal ti1 and the second external clock input signal ti 2: (1) the timer counts only the edges of the second external clock input signal ti 2; (2) the count is only at the edges of the first external clock input signal ti 1; (3) the timer counts the edges of the first and second external clock input signals ti1 and ti2 at the same time.

The first and second external clock input signals ti1 and ti2 and the external trigger input signal etr may select polarities of the first and second external clock input signals ti1 and ti2 by setting a register, and may perform programmable digital filtering on the input signals by a low pass filter. The encoder mode is typically used for motor control, and the first and second external clock input signals ti1 and ti2 are used to interface the incremental encoder. Referring to table 1 below, it is assumed that the first external clock input signal ti1 and the second external clock input signal ti2 do not transition at the same time.

TABLE 1 relationship of count direction to encoder signal

The encoder generates a count clock signal clk _ decoder and a direction count signal dir _ decoder mainly according to the relative relationship between the first external clock input signal ti1 and the second external clock input signal ti2, and the timer performs counting according to the generated count clock signal clk _ decoder and the direction count signal dir _ decoder. A timer in an encoder mode, which selects a direction for counting according to a rising edge of a count clock signal clk _ decoder in an encoder and a direction count signal dir _ decoder generated by the encoder, and in order to prevent misjudgment of a count direction and failure of meeting a corresponding time sequence logic relationship between a direction change edge and a clock edge, that is, signals in the count direction do not meet the time sequence relationship through clock edge synchronous sampling, so that the count direction and a count value are incorrect, as shown in fig. 9a and 9b, a designed direction bit judgment change logic obtains change edge signals corresponding to a first drive signal ti1fp1 and a second drive signal ti2fp2 input after synchronizing two beats with an internal clock signal clk _ per and passing through a corresponding logic relationship between the change edges of the first drive signal ti1fp1 and the second drive signal ti2fp2 (e.g., a signal ti1_ r _ dir, a signal fp1_ dir, a signal f _ dir, a signal fp2 and a signal dir 2_ dir in fig. 10); judging the change of the relative direction of the rising edge generated by the clock, and taking the rising edge signal that the first driving signal ti1fp1 and the second driving signal ti2fp2 are changed into clk _ per to synchronize for one beat; therefore, the rising edge of the clock and the change judgment of the direction bit are prevented from being in the change edge relation, and the condition that the direction bit dir and the clock are not satisfied with correspondingly establishing and maintaining the time sequence relation and the counting direction and the counting value are inaccurate is avoided.

As shown in fig. 9a, 9b, 9c, 10, 11, 12, 13 and 14, the direction count signal dir _ decoder of the encoder is a count direction bit in the encoder mode generated according to the relative relationship of the first and second drive signals ti1fp1 and ti2fp2 and according to the configuration bit sms.

When the configuration bit sms is configured as 2' bs001, the direction count signal dir _ decode selects the internal logic signal dir _ ti2_ sel, the clock signal clk _ decoder selects the clock signal ti2fp2_ ed, that is, the timer counts at the clock edge, that is, the edge of the second drive signal ti2fp2, the direction count signal generated by determining the level of the first drive signal ti1fp1 corresponds to the internal logic signal dir _ ti2_ sel, that is, at the edge of the second drive signal ti2fp2, the direction count signal generated by determining the level of the first drive signal ti1fp1, and the direction count signal generated by determining the level of the internal logic signal dir 2_ ti2_ tr (that is, the rising edge signal of the second drive signal ti2fp 2) 1, the first drive signal ti1 is high, and the level of the generated internal logic signal dir _ ti2_ sel is low; when the signal ti2fp2_ r _ dir (i.e., the rising edge signal of the second driving signal ti2fp 2) is 1, the first driving signal ti1fp1 is low, and the count is down, so that the level of the generated internal logic signal dir _ ti2_ sel is high; when the signal ti2fp2_ f _ dir (i.e., the falling edge signal of the second driving signal ti2fp 2) is 1, the first driving signal ti1fp1 is high, and then count down, and the level of the generated internal logic signal dir _ ti2_ sel is high, i.e., 1' b1; when the signal ti2fp2_ f _ dir (i.e., the falling edge signal of the second driving signal ti2fp 2) is 1, the first driving signal ti1fp1 is low, and the count-up is performed, and the level of the generated internal logic signal dir _ ti2_ sel is low, i.e., 1' b0; otherwise, the level of the internal logic signal dir _ ti2_ sel remains as it is.

When the configuration bit sms is configured as 2' b010, the direction counter signal dir _ decode selects the internal logic signal dir _ ti1_ sel, the clock signal clk _ decoder selects the signal ti1fp1_ ed, that is, the timer counts the clock edge of the encoder (that is, the edge of the first drive signal ti1fp 1), the count direction corresponds to the internal logic signal dir _ ti1_ sel (that is, the direction logic signal generated by determining the level of the second drive signal ti2fp2 at the edge of the first drive signal ti1fp 1), the signal ti1fp1_ r _ dir (that is, the rising edge signal of the first drive signal ti1fp 1) corresponding to the internal logic signal dir _ sel is 1, the second drive signal ti2fp2 is high, and the count down occurs, and the level of the generated internal logic signal dir _ 2_ ti is high, that is, 1 b010; when the signal ti1fp1_ r _ dir (i.e., the rising edge signal of the first driving signal ti1fp 1) is 1 and the second driving signal ti2fp2 is low, the count-up is performed, and the level of the generated internal logic signal dir _ ti1_ sel is low, i.e., 1' b0; when the signal ti1fp1_ f _ dir (i.e., the falling edge signal of the first driving signal ti1fp 1) is 1, the second driving signal ti2fp2 is high, and is counted up, and the level of the generated internal logic signal dir _ ti2_ sel is high, i.e., 1' b0; when the signal ti1fp1_ f _ dir (i.e., the falling edge signal of the first driving signal ti1fp 1) is 1, the second driving signal ti2fp2 is low, and is counted down, the logic level of the generated internal logic signal dir _ ti1_ sel is high, i.e., 1' b1. Otherwise, the level of the internal logic signal dir _ ti1_ sel is maintained as it is.

When the configuration bit sms is configured as 2' bs011, the direction count signal dir _ decode selects the logic of the internal logic signal dir _ ti1ti2_ sel, the count clock signal clk _ decoder selects the logic of the OR of the signal ti1fp1_ ed and the signal ti2fp2_ ed, that is, the timer counts at the encoder clock edge, that is, at the edges of the first driving signal ti1fp1 and the second driving signal ti2fp2, the count direction corresponds to the logic of the internal logic signal dir _ ti1ti2_ sel, that is, at the edge of the first driving signal ti1fp1, the level of the second driving signal ti2fp2 is judged, and at the edge of the second driving signal ti2, the direction logic signal generated by judging the level of the first driving signal 1fp1 is judged; when the signal ti1fp1_ r _ dir corresponding to the internal logic signal dir _ ti1ti2_ sel (i.e., the rising edge signal of the first driving signal ti1fp 1) is 1, the second driving signal ti2fp2 is high, and then count down, so that the level of the generated internal logic signal dir _ ti1ti2_ sel is high, i.e., 1' b1; when the signal ti1fp1_ r _ dir (i.e., the rising edge signal of the first driving signal ti1fp 1) is 1 and the second driving signal ti2fp2 is low, the count-up is performed, and the level of the generated internal logic signal dir _ ti1ti2_ sel is low, i.e., 1' b0; when the signal ti1fp1_ f _ dir (i.e., the falling edge signal of the first driving signal ti1fp 1) is 1, the second driving signal ti2fp2 is high, and the count-up is performed, so that the level of the generated internal logic signal dir _ ti1ti2_ sel is low, i.e., 1' b0; when the signal ti1fp1_ f _ dir (i.e., the falling edge signal of the first driving signal ti1fp 1) is 1, the second driving signal ti2fp2 is low, and the count-down is performed, and the level of the generated internal logic signal dir _ ti1ti2_ sel is high, i.e., 1' b1. When the signal ti2fp2_ r _ dir (i.e., the rising edge signal of the second driving signal ti2fp 2) is 1, the first driving signal ti1fp1 is high, and the count-up is performed, so that the level of the generated internal logic signal dir _ ti1ti2_ sel is low; when the signal ti2fp2_ r _ dir (i.e., the rising edge signal of the second driving signal ti2fp 2) is 1, the first driving signal ti1fp1 is low, and the count-down operation is performed, so that the level of the generated internal logic signal dir _ ti1ti2_ sel is high; when the signal ti2fp2_ f _ dir (i.e., the falling edge signal of the second driving signal ti2fp 2) is 1, the first driving signal ti1fp1 is high, and the count is down, so that the level of the generated internal logic signal dir _ ti1ti2_ sel is high, i.e., 1' b1; when the signal ti2fp2_ f _ dir (i.e., the falling edge signal of the second driving signal ti2fp 2) is 1, the first driving signal ti1fp1 is low, and the count-up is performed, and the level of the generated internal logic signal dir _ ti1ti2_ sel is low, i.e., 1' b0. Otherwise, the dir _ ti1ti2_ sel logic level remains at its original value.

Fig. 15a, 15b and 15c are waveform timing diagrams of internal logic signal changes generated according to the edge and relative level relationship of the first driving signal ti1fp1 and the second driving signal ti2fp2. The figure shows the change with respect to the internally generated count clock signal clk _ decoder in the encoder mode and the direction count signal dir _ decoder signal in the encoding mode.

The counter represents the increment and decrement of the timer, and the counter counts up the clock edge according to the dir count direction bit. The counter counts up at a rising edge of the count clock signal clk _ decoder and the direction count signal dir _ decoder is 0, and counts down at a rising edge of the count clock signal clk _ decoder and the direction count signal dir _ decoder is 1, the counter.

The encoding modes in fig. 15a, 15b, and 15c are the case when the configuration bits sms corresponding to the encoder mode are configured to 2' b001, the case when the configuration bits sms corresponding to the encoder mode are configured to 2' b010, and the case when the configuration bits sms corresponding to the encoder mode are configured to 2' b011.

The foregoing description of specific exemplary embodiments of the invention has been presented for the purposes of illustration and description. It is not intended to limit the invention to the precise form disclosed, and obviously many modifications and variations are possible in light of the above teaching. The exemplary embodiments were chosen and described in order to explain certain principles of the invention and its practical application to enable one skilled in the art to make and use various exemplary embodiments of the invention and various alternatives and modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims and their equivalents.

Claims

1. A signal generation control circuit for a timer, comprising:

a trigger controller, the trigger controller comprising:

2. The signal generation control circuit for a timer of claim 1, wherein the first input trigger circuit comprises a first low pass filter, a first edge detection circuit, a first inverter, a first selector, a second low pass filter, a second edge detection circuit, a second inverter, and a second selector;

3. The signal generation control circuit for a timer according to claim 1, wherein the second input trigger circuit includes a third inverter, a fourth selector, a frequency division counter, a fifth selector, a third low-pass filter, a sampling frequency division clock counter, a sixth selector, a first D flip-flop, and a seventh selector;

4. The signal generation control circuit for a timer of claim 3, wherein the third low pass filter comprises a fourth inverter, a first AND gate, an eighth selector, a fifth inverter, a second AND gate, a ninth selector, a tenth selector, an eleventh selector, a second D flip-flop, a sixth inverter, a third AND gate, a twelfth selector, a seventh inverter, a fourth AND gate, a thirteenth selector, a fourteenth selector, a fifteenth selector, and a third D flip-flop;

a first input end of the eighth selector is used for receiving a high level signal, a second input end of the eighth selector is connected with a Q output end of the second D flip-flop, the selection control end of the eighth selector is connected with the first comparison signal, the output end of the eighth selector is connected with the first input end of the eleventh selector, a first input end of the ninth selector is used for receiving a low level signal, a second input end of the ninth selector is connected with a Q output end of the second D flip-flop, the selection control end of the ninth selector is connected with the first comparison signal, the output end of the ninth selector is connected with the first input end of the tenth selector, a second input terminal of the tenth selector is connected to a Q output terminal of the second D flip-flop, an input terminal of the fifth inverter is connected to an output terminal of the fifth selector, the output end of the fifth inverter is connected with the second input end of the second AND gate, the first input end of the second AND gate is connected with the Q output end of the second D flip-flop, the output end of the second AND gate is connected with the selection control end of a tenth selector, the second input end of the eleventh selector is connected with the output end of the tenth selector, the input end of the fourth inverter is connected with the Q output end of the second D trigger, the first input end of the first AND gate is connected with the output end of the fifth selector, the second input end of the first AND gate is connected with the output end of the fourth inverter, the selection control end of the eleventh selector is connected with the output end of the first AND gate, the output end of the eleventh selector is connected with the D input end of the second D trigger, and the clock control end of the second D trigger is connected with the input end of the seventh selector;

5. The signal generation control circuit for a timer according to claim 2, wherein the third input flip-flop circuit comprises a third selector, a first input terminal of the third selector is configured to receive the first internal trigger input signal, a second input terminal of the third selector is configured to receive the second internal trigger input signal, a third input terminal of the third selector is connected to the first edge detection circuit, a selection control terminal of the third selector is connected to the configuration bit ts, and an output terminal of the third selector is connected to a fourth input terminal of the selector.

6. The signal generation control circuit for a timer according to claim 1, wherein the enable signal generation circuit comprises a fifth and gate, a fourth D flip-flop, a sixteenth selector, a seventeenth selector, an eighteenth selector, and a fifth D flip-flop;

7. The signal generation control circuit for a timer of claim 1, wherein the gating signal generation circuit comprises a sixth and gate, a sixth D flip-flop, a nineteenth selector, a twentieth selector, a seventh D flip-flop, and an eighth D flip-flop;

8. The signal generation control circuit for a timer according to claim 1, wherein the reset signal generation circuit comprises a twenty-first selector, a ninth D flip-flop, a twenty-second selector, and a first or gate;

9. The signal generation control circuit for the timer of claim 7, wherein the clock signal generation circuit comprises a tenth D flip-flop, an eleventh D flip-flop, an eighth inverter, a seventh and gate, a twenty-third selector, and an eighth and gate;

10. The signal generation control circuit for a timer according to claim 1, the encoder comprises a fifteenth D trigger, a sixteenth D trigger, a seventeenth D trigger, an eighteenth D trigger, a seventeenth inverter, an eighteenth inverter, a nineteenth inverter, a twentieth inverter, a twenty-first AND gate, a twenty-second AND gate, a twenty-third AND gate, a twenty-fourth AND gate, a second OR gate, a third OR gate, a fourth OR gate, a forty-first selector, a ninth inverter, a ninth AND gate, a tenth inverter, a tenth AND gate, an eleventh inverter, an eleventh AND gate, a twelfth inverter, a twelfth AND gate, a thirteenth inverter, a fourteenth inverter, a thirteenth AND gate, a fourteenth AND gate, a fifteenth AND gate, a sixteenth AND gate, a twenty-fourth selector, a twenty-fifth selector, a twenty-sixth selector, a twenty-seventh selector, a twelfth D trigger, a seventeenth AND gate, a fifteenth AND gate, a fourteenth selector, a twenty-fourth selector, a twenty-fifth selector, a twenty-sixth selector, a twenty-seventh selector, a twenty-fourth D trigger, a seventeenth inverter, a sixteenth and a sixteenth selector a fifteenth inverter, a sixteenth inverter, a seventeenth and, eighteenth and, nineteenth and, twentieth and, twenty-eighth selector, a twenty-ninth selector, a thirtieth selector, a thirty-eleventh selector, a thirteenth flip-flop, a twenty-first inverter, a twenty-second inverter, a twenty-third inverter, a twenty-fourth inverter, a twenty-fifth and, a twenty-sixth and, a twenty-seventh and, a twenty-eighth and, a twenty-ninth and, a thirty-eighth and, a thirty-eleventh and, a thirty-second selector, a thirty-third selector, a thirty-fourth selector, a thirty-fifth selector, a thirty-sixth selector, a thirty-seventh selector, a thirty-eighth selector, a thirty-ninth selector, a fourteenth and a forty selector;

the first input end of the thirteenth and gate is connected with the output end of the tenth and gate, the second input end of the thirteenth and gate is connected with the second driving signal, the first input end of the twenty-fourth selector is used for receiving a low level signal, the second input end of the twenty-fourth selector is connected with the Q output end of the twelfth D flip-flop, the selection control end of the twenty-fourth selector is connected with the output end of the thirteenth and gate, the input end of the thirteenth inverter is connected with the second driving signal, the first input end of the fourteenth and gate is connected with the output end of the tenth and gate, the selection control end of the twenty-fifth selector is connected with the output end of the fourteenth and gate, the first input end of the twenty-fifth selector is used for receiving a high level signal, the second input end of the twenty-fifth selector is connected with the output end of the twenty-fourth selector, the input end of the fourteenth inverter is connected with the second driving signal, the first input end of the fifteenth and-gate is connected with the output end of the ninth and-gate, the second input end of the fifteenth and-gate is connected with the output end of the fourteenth inverter, the selection control end of the twenty-sixth selector is connected with the output end of the fifteenth and-gate, the first input end of the twenty-sixth selector is connected with the low level signal, the second input end of the twenty-sixth selector is connected with the output end of the twenty-sixth selector, the first input end of the sixteenth and-gate is connected with the output end of the ninth and-gate, the second input end of the sixteenth and-gate is connected with the second driving signal, the first input end of the twenty-seventh selector is used for receiving the high level signal, and the second input end of the twenty-seventh selector is connected with the output end of the twenty-sixth selector, a D input end of the twelfth D trigger is connected with an output end of the twenty-seventh selector, and a clock control end of the twelfth D trigger is used for receiving an internal clock signal;

the input end of the fifteenth inverter is connected with a first driving signal, the first input end of the seventeenth and gate is connected with the output end of the twelfth and gate, the second input end of the seventeenth and gate is connected with the output end of the fifteenth inverter, the first input end of the twenty-eighth selector is connected with a low level signal, the second input end of the twenty-eighth selector is connected with the Q output end of the thirteenth D trigger, the selection control end of the twenty-eighth selector is connected with the output end of the seventeenth and gate, the first input end of the eighteenth and gate is connected with the output end of the twelfth and gate, the second input end of the eighteenth and gate is connected with the first driving signal, the first input end of the twenty-ninth selector is connected with a high level signal, and the second input end of the twenty-ninth selector is connected with the output end of the twenty-eighth selector, the selection control end of the twenty-ninth selector is connected with the output end of an eighteenth AND gate, the first input end of the nineteenth AND gate is connected with the output end of an eleventh AND gate, the second input end of the nineteenth AND gate is connected with a first driving signal, the first input end of the thirtieth selector is connected with a low level signal, the second input end of the thirtieth selector is connected with the output end of the twenty-ninth selector, the first input end of the twentieth AND gate is connected with the output end of the eleventh AND gate, the input end of the sixteenth inverter is connected with a first driving signal, the second input end of the twentieth AND gate is connected with the output end of the sixteenth inverter, the first input end of the thirty-eleventh selector is connected with a high level signal, and the second input end of the thirty-eighth selector is connected with the output end of the thirtieth selector, a D input end of the thirteenth D flip-flop is connected to an output end of the thirty-first selector, and a clock control end of the thirteenth D flip-flop is configured to receive an internal clock signal;