CN115359826A - Split-gate memory array and operation method thereof - Google Patents
Split-gate memory array and operation method thereof Download PDFInfo
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- CN115359826A CN115359826A CN202211058615.0A CN202211058615A CN115359826A CN 115359826 A CN115359826 A CN 115359826A CN 202211058615 A CN202211058615 A CN 202211058615A CN 115359826 A CN115359826 A CN 115359826A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/18—Bit line organisation; Bit line lay-out
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- G—PHYSICS
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- G11C8/14—Word line organisation; Word line lay-out
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Abstract
The invention provides a split gate memory array and an operation method thereof, which are applied to the technical field of semiconductors. The memory cell comprises a plurality of memory cells with the same structure, and memory arrays which are distributed in the X direction and the Y direction and are arranged in a well, wherein each memory cell comprises a selection tube formed in a split gate structure and two memory tubes symmetrically distributed on two sides of the selection tube, and the gates of the two memory tubes in each memory cell are interconnected, so that each memory cell is used as one memory bit. In the storage array provided by the invention, every two adjacent columns of storage units on the left and right are connected by adopting a common source, namely all the storage units in the two adjacent columns share one source line SL in a source electrode sharing mode, so that the structure of the storage units is more compact, the whole storage array is simplified, and the area is saved compared with the structure that one SL and one BL are arranged in each storage unit, thereby effectively reducing the area of the storage units and simplifying the operation of the storage units.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a split gate memory array and an operation method thereof.
Background
With the rapid popularization of electronic products, flash memories are rapidly popularized as current mainstream storage carriers, and the technology of flash memories is rapidly developed. The non-volatile memory (NVM) technology mainly comprises floating gate (floating gate) technology and SONOS (Silicon-Oxide-nitride-Oxide-Silicon) technology from the storage medium, and mainly comprises single gate (1-Transistor), split gate (split gate), double gate (2-Transistor) and other technologies from the structure. Flash has been widely applied to various embedded electronic products such as financial IC cards, automotive electronics, etc. due to its advantages of long life, non-volatility, low price, and easy programming and erasing. The memory integration density is improved, so that the chip area is saved, and the manufacturing cost is reduced.
At present, with the development of mainstream process technology and urgent requirements of people on Flash devices, split gate Flash based on a split gate structure is widely concerned by people, compared with the traditional Flash, the split gate Flash memory is used as one of Flash memories, and has high programming speed and capability of completely avoiding over-erasing, so that the split gate Flash memory is more concerned by people in both single and embedded products, and at present, the split gate Flash memory is widely applied to products such as personal computers, digital equipment, mobile terminals, smart cards and the like. The novel split-gate Flash is excellent in reliability, no over-erasure and the like, and has a better optimization effect on the improvement of capacity due to the compact structure and the integration of more storage units in the same chip area. However, due to the rapid increase of data volume in the information age at present, the further optimization of the memory structure to achieve higher capacity is always the pursuit of the industry.
Disclosure of Invention
The invention aims to provide a split-gate memory array structure and an operation method thereof, and provides a novel split-gate structure type memory array which is compact in structure and simple to operate.
In a first aspect, to solve the above technical problem, the present invention provides a split gate memory array structure, including:
the storage cell array comprises a plurality of storage cells with the same structure, wherein the storage cells are distributed in the X direction and the Y direction to form a storage array arranged in a well, each storage cell comprises a selection tube formed in a split-gate structure and two storage tubes symmetrically distributed on two sides of the selection tube, and gates of the two storage tubes in each storage cell are interconnected, so that each storage cell is used as one storage bit;
in the Y direction of the memory array, the memory cells in each two adjacent columns are connected by adopting a common source, so that all the memory cells in the two adjacent columns share one source line SLn in a mode of sharing a source electrode, and in each column of the memory array, the drains of a plurality of memory cells in the same column are all connected with the bit line BLn in the Y direction of the corresponding column; in the X direction in the memory array, two storage tubes in the plurality of memory cells in each row are connected with the gates of the storage tubes at the same row position in the adjacent memory cells, the gates of two storage tubes in the two memory cells at the head and the tail of each row are respectively connected together to be connected as a storage gate word line WLSn, and the gates of the selection tubes in the plurality of memory cells in the same row are connected to be connected as a selection gate word line WLn.
Further, in the Y direction of the memory array, the sources of every two adjacent memory cells in each column thereof may be shorted.
Furthermore, a channel is shared by a selection tube and a storage tube formed by the split-gate structure in the storage unit, so that a source electrode and a drain electrode of the selection tube positioned in the middle and contact holes led out outwards and corresponding to the source electrode and the drain electrode are omitted.
Further, the storage tube may be a SONOS storage tube.
Further, the select transistor may be an MOS transistor device including a stacked gate oxide layer and a polysilicon gate layer.
In a second aspect, based on the split-gate memory array structure, the invention further provides an operating method of the split-gate memory array structure, which specifically includes that a row operation mode is adopted when data is read, erased and written in the memory array, that is, data is erased, read and written in memory cells included in the same row at the same time.
Further, when erasing, programming or reading data in the memory array, different voltage values are applied to the wells.
Further, when data of the memory array is erased, a negative voltage Vneg is applied to the memory gate word line WLSn corresponding to the row where the selected target memory cell is located, while positive voltages Vpos are applied to the memory gate word lines WLSn of the row where the current unselected memory cell in the memory array is located, all the selection gate word lines WLn in the memory array are grounded, and the bit line BLn connected to the drain of all the memory cells in the memory array and the source line SLn connected to the source thereof are set to be in a floating state.
Further, when data is written into the memory array, the memory cell in each memory cell close to the common source line SLn in two adjacent columns of the left and right common sources always maintains a data "0" state, and the other memory cell in each memory cell far from the common source line SLn can be written with data "1" or data "0".
Further, when data writing is performed on the memory array, a positive voltage Vpos is applied to the memory gate word line WLSn corresponding to the row where the selected target memory cell is located, a positive voltage Vp0 is applied to the common source line SLn corresponding to the memory gate word line WLSn, a negative voltage Vneg is applied to the memory gate word lines WLSn of the row where the current non-selected memory cell in the memory array is located, and a negative voltage Vneg is applied to all the selection gate word lines WLn in the memory array; and applying a negative voltage Vneg to the bit line BLn connected to the drain of the selected target memory cell when data "1" is written to the memory cell far from the common source line SLn in the selected target memory cell, or applying a positive voltage Vp0 to the bit line BLn connected to the drain of the selected target memory cell when data "0" is written to the memory cell far from the common source line SLn in the selected target memory cell.
Further, when data is read from the memory array, a positive voltage Vlim is applied to the bit line BLn connected to the drain of the selected target memory cell, a positive voltage Vpwr greater than the device turn-on voltage is applied to the select gate word line WLn of the row in which the selected target memory cell is located, and the remaining terminals of the target memory cell are grounded, so that the state of the data stored in the selected memory cell can be obtained by reading the current of the bit line BLn connected to the drain of the selected target memory cell.
Further, when the selected target memory cell is subjected to an erase operation, the voltage applied to the well is a positive voltage Vpos; when the selected target memory cell is subjected to the writing operation, the voltage applied to the trap is a negative voltage Vneg; when a read operation is performed on the selected target memory cell, the well is directly grounded Vgnd.
Further, the Vpos < Vgnd < Vlim < Vp0< Vpos, where Vgnd =0V.
Further, the Vneg = -4V, vlim = -0.8v, the Vp0=1.6V, the Vpwr =2v, vpos the Vpos =7V.
Compared with the prior art, the technical scheme of the invention has at least one of the following beneficial effects:
in the split-gate memory array structure provided by the invention, a plurality of memory cells with the same structure are distributed in the X direction and the Y direction to form a memory array arranged in a well, each memory cell comprises a selection tube formed in a split-gate structure and two memory tubes symmetrically distributed on two sides of the selection tube, and the grids of the two memory tubes in each memory cell are interconnected, so that each memory cell is used as one memory bit. In the storage array provided by the invention, every two adjacent columns of storage units on the left and right are connected by common sources, namely all the storage units in the two adjacent columns share one source line SL in a source electrode sharing mode, so that the structure of the storage units is more compact, the whole storage array is simplified, and compared with a structure that each storage unit is provided with one SL and one BL, the area of the storage units is saved, the area of the storage units is effectively reduced, and the operation of the storage units is simplified.
Drawings
Fig. 1 is a schematic structural diagram of a split-gate memory array structure according to an embodiment of the invention;
FIG. 2 is a schematic structural diagram of any memory cell in a split-gate memory array structure according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of local voltages during an erase operation of a split-gate memory array structure according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of local voltages during a write operation of the split-gate memory array structure according to an embodiment of the present invention;
fig. 5 is a schematic diagram of local voltages during a read operation of the split-gate memory array structure according to an embodiment of the invention.
Detailed Description
The structure and operation method of the split-gate memory array according to the present invention will be described in detail with reference to the accompanying drawings. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than those specifically described herein, and thus the present invention is not limited to the specific embodiments disclosed below.
As used in this application and the appended claims, the terms "a," "an," "the," and/or "the" are not intended to be inclusive in the singular, but rather are intended to be inclusive in the plural unless the context clearly dictates otherwise. In general, the terms "comprises" and "comprising" merely indicate that steps and elements are included which are explicitly identified, that the steps and elements do not form an exclusive list, and that a method or apparatus may include other steps or elements. In describing the embodiments of the present invention in detail, the cross-sectional views illustrating the structure of the device are not enlarged partially in a general scale for convenience of illustration, and the schematic drawings are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
As described in the background art, at present, with the development of mainstream process technology and urgent requirements of people on Flash devices, split-gate Flash based on a split-gate structure is widely concerned by people, compared with the traditional Flash, the split-gate Flash memory is used as one of Flash memories, and has high programming speed and capability of completely avoiding over-erasing, so that people pay more attention to the split-gate Flash memory in both single and embedded products, and at present, the split-gate Flash memory is widely applied to products such as personal computers, digital equipment, mobile terminals, smart cards and the like. The novel split-gate Flash is excellent in reliability, no over-erasure and the like, and has a better optimization effect on the improvement of capacity due to the compact structure and the integration of more storage units in the same chip area. However, due to the rapid increase of data volume in the information age at present, the further optimization of the memory structure to achieve higher capacity is always the pursuit of the industry.
Therefore, the invention provides a split-gate memory array structure and an operation method thereof, and provides a novel split-gate structure type memory array which is compact in structure and simple to operate.
First, the structure of a split-gate memory array according to the present invention will be described in detail.
Referring to fig. 1 in detail, and with reference to fig. 2, fig. 1 is a schematic structural diagram of a split-gate memory array structure provided in an embodiment of the invention, and fig. 2 is a schematic structural diagram of any memory cell in the split-gate memory array structure provided in an embodiment of the invention.
Specifically, as shown in fig. 1 and fig. 2, the split-gate memory array structure provided by the present invention may specifically include:
a plurality of memory cells a with the same structure (or alternatively, the memory cells B, C and D in fig. 1) are distributed in the X direction and the Y direction to form a memory array disposed in a well, and each of the memory cells a may include a selection transistor 11 formed in a split gate structure and two memory transistors 12 symmetrically disposed on two sides of the selection transistor, and gates of the two memory transistors 12 in each of the memory cells a are interconnected to make each of the memory cells serve as a storage bit.
In the Y direction of the memory array, the memory cells in each adjacent left and right two columns are connected by common sources, so that all the memory cells in the left and right adjacent two columns share one source line SLn in a manner of sharing a source, such as SL1 in fig. 1, and in each column of the memory array, the drains of the memory cells in the same column are connected to the bit line BLn in the Y direction of the corresponding column, such as BL1 in fig. 1; in the X direction in the memory array, two storage tubes in a plurality of memory cells in each row are connected with the gates of the storage tubes at the same row position in the adjacent memory cells, the gates of two storage tubes in the two memory cells at the head and the tail of each row are respectively connected together to be connected as a memory gate word line WLSn, and the gates of the selection tubes in a plurality of memory cells in the same row are connected to be connected as a selection gate word line WLn; in the Y direction in the memory array, the sources of a plurality of memory cells in the same column are all connected to the bit line BLn in the Y direction of the corresponding column.
In this embodiment, each row or each column in the memory array may include a plurality of memory cells, and all the memory cells included in two adjacent left and right columns share one source line SLn arranged in the vertical direction in a source sharing manner, such as SL1 in fig. 1; in the Y direction of the memory array, the source of each two adjacent memory cells in each column of the memory array is shorted and then connected to the shared source line SLn, as shown in fig. 1, the memory cell a and the memory cell C or the memory cell B and the memory cell D are both shorted and then connected to the shared source line SL1; each memory cell a stores only one data state, such as a data "1" state or a data "0" state, that is, one of the memory cells located on the side of the select gate 11 away from the common source line SLn among the memory cells a may write data "1" or data "0", while the other memory cell located close to the common source line SLn always maintains the data "0" state. And the selection tube 11 and the storage tube 12 formed by the split-gate structure in the memory cell a share a channel, so as to omit the source and drain of the selection tube 11 located in the middle and the contact holes led out respectively and correspondingly. Specifically, the storage tube 12 may be a SONOS storage tube, and the selection tube 11 is an MOS device including a stacked gate oxide layer and a polysilicon gate layer.
In each storage unit of the split-gate memory array structure provided by the invention, the left storage tube and the right storage tube are symmetrically distributed on two sides of the selection tube, and the two storage tubes are interconnected together through the grid electrode and only do one storage bit; however, because the split-gate structure is adopted between the selection tube and the storage tube, a source/drain and an external hole (the source/drain and the external hole of the selection tube are omitted) are not needed, and under the same process node, the mirror-symmetric split-gate SONOS memory still saves more than 20% of area compared with the traditional two-tube SONOS memory. Furthermore, in the storage array provided by the invention, each two adjacent columns of storage units on the left and right are connected by adopting a common source, namely all the storage units in the two adjacent columns share one source line SL in a source electrode sharing mode, so that the structure of the storage units is more compact, the whole storage array is simplified, and compared with the structure that each storage unit is provided with one SL and one BL, the area of the storage units is saved, the area of the storage units is effectively reduced, and the operation on the storage units is simplified.
In addition, based on the split-gate memory array structure shown in fig. 1 and fig. 2, the present invention also provides an operation method of the split-gate memory array structure, and the following first describes in detail an operation method of the split-gate memory array structure provided by the present invention.
Specifically, in this embodiment, the memory array employs a row operation manner when reading, erasing, and writing data, that is, the memory cells included in the same row perform data erasing, reading, and writing simultaneously; as is known in the art, when reading, erasing, and writing data to a memory cell, a corresponding voltage is applied to each of the corresponding memory cells, and in particular, in an embodiment of the present invention, a table of voltages applied to the memory array according to the present invention for reading, erasing, and writing data is specifically shown in table 1 below.
TABLE 1
As can be seen from table 1, in table 1, "Erase" indicates an Erase operation of data to the memory Cell, "Program" indicates a write operation of data to the memory Cell, and "Read" indicates a Read operation of data to the memory Cell; "Vwl" represents a voltage value applied to the selection gate word line WLn of the memory Cell, "Vwls" represents a voltage value applied to the memory gate word line WLSn of the memory Cell, and similarly, "Vbl", "Vsl", and "Vbulk" represent a voltage value applied to the bit line of the memory Cell, a voltage value applied to the source line, and a voltage value applied to the well bulk, respectively.
As shown in fig. 3, fig. 3 is a schematic diagram of local potentials during an erase operation of the split-gate memory array structure according to an embodiment of the invention.
In this embodiment, when erasing data of a memory cell in the memory array, it may apply a negative voltage Vneg, such as-4V, to the memory gate word line WLS1 corresponding to the row where the selected target memory cell a or B is located, and apply a positive voltage Vpos, such as 7V, to the memory gate word line WLS2 of the row where the current non-selected memory cell in the memory array, such as memory cell C or memory cell D is located, and ground all the select gate word lines WL in the memory array (with a voltage of 0V), and set the bit lines BLn (identified by floating in the figure) to which the drains of all the memory cells in the memory array are connected and the source lines SLn to which the sources of all the memory cells in the memory array are connected to a floating state, that is, to say, to no voltage, such as BL1, BL2, and SL1. And, when the erase operation is performed on the selected target memory cell, the voltage applied to the well bulk is a positive voltage Vpos, for example, 7V.
Further, as shown in fig. 4, fig. 4 is a schematic diagram of local potentials of the split-gate memory array structure during a write operation according to an embodiment of the invention.
In this embodiment, when data is written into the memory array, the memory cell in each memory cell close to the common source line SLn in two adjacent columns of the left and right common sources always maintains a data "0" state, and the other memory cell in each memory cell far from the common source line SLn can be written with data "1" or data "0".
Specifically, a positive voltage Vpos is applied to a memory gate word line WLS1 corresponding to a row where a selected target memory cell a or B is located, for example, 7V, and a positive voltage Vp0 is applied to a common source line SL1 corresponding to the selected target memory cell a or B, for example, 1.6V, a negative voltage Vneg is applied to a memory gate word line WLS2 of a row where a current non-selected memory cell C or D in the memory array is located, for example, -4V, and a negative voltage Vneg is applied to all the select gate word lines WL1 and WL2 in the memory array, for example, -4V; and a negative voltage Vneg, such as-4V, is applied to the bit line BL1 to which the drain of the target memory cell is connected when writing data "1" to the selected target memory cell, for example, the memory cell far from the common source line SL1 in the memory cell a, or a positive voltage Vp0, such as 1.6V, is applied to the bit line BL2 to which the drain of the target memory cell B is connected when writing data "0" to the selected target memory cell, for example, the memory cell far from the common source line SL1 in the memory cell B. And, in the write operation to the selected target memory cell, the voltage applied to the well bulk is a negative voltage Vneg, such as-4V.
In the data writing operation for the memory cell a or B, data "1" or data "0" is written into the memory cell of each memory cell distant from the source line SL1 connected to the shared source of the adjacent left and right two columns, and the memory cell of each memory cell close to the source line SL1 connected to the shared source of the two columns always maintains the data "0" state.
Further, as shown in fig. 5, fig. 5 is a schematic diagram of local potentials of the split-gate memory array structure provided in an embodiment of the invention during a read operation.
In this embodiment, when reading data from the memory array, a positive voltage Vlim, such as 0.8V, is applied to the bit line BL1 of a selected target memory cell, for example, a memory cell a or a memory cell B, a positive voltage Vpwr, such as 2V, greater than a device turn-on voltage is applied to the select gate word line WL1 of the row of the selected target memory cell, for example, the memory cell a or the memory cell B, and the remaining terminals of the target memory cell, for example, the memory cell a or the memory cell B, are grounded, i.e., have a ground voltage of 0, so that the state of the data stored in the selected memory cell can be obtained by reading the current of the bit line BL of the selected target memory cell. And, when a read operation is performed on the selected target memory cell, the well bulk is directly grounded to Vgnd, i.e., the voltage value of the ground is 0V.
It should be noted that, in this embodiment, the relationship between the voltages Vneg, vlim, vp0, vpwr, and Vpos may be Vneg < Vgnd < Vlim < Vp0< Vpos, where Vgnd =0V. Specifically, what the voltage values of the voltages Vneg, vlim, vp0, vpwr, and Vpos are is, for example, shown in the present invention, that is, vneg = -4V, vlim =0.8V, vp0=1.6V, vpwr =2V, and Vpos =7V, but in other cases, different voltage values may be set according to actual situations, and the present invention is not limited in particular.
Therefore, the above is only a preferred embodiment of the present invention, and is not intended to limit the present invention. Various modifications and alterations to this invention will become apparent to those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
In summary, the split-gate memory array structure provided by the present invention specifically includes a plurality of memory cells with the same structure, so as to form a memory array disposed in a well in an X direction and a Y direction in a distributed manner, each of the memory cells includes a selection transistor formed in a split-gate structure and two memory transistors symmetrically disposed on two sides of the selection transistor, and gates of the two memory transistors in each of the memory cells are interconnected, so that each of the memory cells serves as a storage bit. In the storage array provided by the invention, every two adjacent columns of storage units on the left and right are connected by common sources, namely all the storage units in the two adjacent columns share one source line SL in a source electrode sharing mode, so that the structure of the storage units is more compact, the whole storage array is simplified, and compared with a structure that each storage unit is provided with one SL and one BL, the area of the storage units is saved, the area of the storage units is effectively reduced, and the operation of the storage units is simplified.
It should be noted that, although the present invention has been described with reference to the preferred embodiments, the present invention is not limited to the embodiments. It will be apparent to those skilled in the art from this disclosure that many changes and modifications can be made, or equivalents modified, in the embodiments of the invention without departing from the scope of the invention. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the protection scope of the technical solution of the present invention, unless the content of the technical solution of the present invention is departed from.
It should be further understood that the terms "first," "second," "third," and the like in the description are used for distinguishing between various components, elements, steps, and the like, and are not intended to imply a logical or sequential relationship between various components, elements, steps, or the like, unless otherwise indicated or indicated.
It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to limit the scope of the present invention. It must be noted that, as used herein and in the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. For example, reference to "a step" or "an apparatus" means a reference to one or more steps or apparatuses and may include sub-steps as well as sub-apparatuses. All conjunctions used should be understood in the broadest sense. And, the word "or" should be understood to have the definition of a logical "or" rather than the definition of a logical "exclusive or" unless the context clearly dictates otherwise. Further, implementation of the methods and/or apparatus of embodiments of the present invention may include performing the selected task manually, automatically, or in combination.
Claims (14)
1. A split gate memory array structure, comprising:
the storage cell array comprises a plurality of storage cells with the same structure, wherein the storage cells are distributed in the X direction and the Y direction to form a storage array arranged in a well, each storage cell comprises a selection tube formed in a split-gate structure and two storage tubes symmetrically distributed on two sides of the selection tube, and gates of the two storage tubes in each storage cell are interconnected, so that each storage cell is used as one storage bit;
in the Y direction of the memory array, the memory cells in every two adjacent columns are connected by adopting a common source, so that all the memory cells in the left and right adjacent columns share one source line SLn in a mode of sharing a source electrode, and in each column of the memory array, the drains of a plurality of memory cells in the same column are all connected with the bit line BLn in the Y direction of the corresponding column; in the X direction of the memory array, two storage tubes in a plurality of memory cells in each row are connected with the gates of the storage tubes at the same row position in the adjacent memory cells, the gates of two storage tubes in the two memory cells at the head and the tail of each row are respectively connected together to be connected as a storage gate word line WLSn, and the gates of the selection tubes in a plurality of memory cells in the same row are connected to be connected as a selection gate word line WLn.
2. The split-gate memory array structure of claim 1, wherein in the Y-direction of the memory array, the sources of every two adjacent memory cells in each column thereof are shorted.
3. The split-gate memory array structure of claim 1, wherein the select transistors and the storage transistors formed in the split-gate structure of the memory cells share a channel to omit the source and drain electrodes of the select transistors in the middle and their corresponding contact holes leading out.
4. The split-gate memory array structure of claim 1, wherein said memory transistor is a SONOS memory transistor.
5. The split-gate memory array structure of claim 3, wherein the select transistors are MOS transistor devices comprising stacked gate oxide layers and polysilicon gate layers.
6. An operation method of the split gate memory array structure according to any one of claims 1 to 5, wherein the memory array employs a row operation manner when reading, erasing and writing data, that is, data erasing, reading and writing are simultaneously performed on memory cells included in the same row.
7. The method of claim 6, wherein different voltages are applied to the wells during erasing, programming or reading data from the memory array.
8. The method for operating the split-gate memory array structure of claim 7, wherein when erasing data in the memory array, a negative voltage Vneg is applied to the memory gate word line WLSn corresponding to the row in which the selected target memory cell is located, a positive voltage Vpos is applied to the memory gate word lines WLSn of the row in which the current non-selected memory cell in the memory array is located, all the selection gate word lines WLn in the memory array are grounded, and the bit line BLn to which the drains of all the memory cells in the memory array are connected and the source line SLn to which the sources thereof are connected are set to be in a floating state.
9. The method of operating the split gate memory array structure as claimed in claim 8, wherein when data writing is performed to the memory array, the memory cell in each memory cell close to the common source line SLn in two adjacent columns of the left and right common source always maintains the data "0" state, and the other memory cell in each memory cell far from the common source line SLn can be written with data "1" or data "0".
10. The method of operating the split-gate memory array structure of claim 9, wherein when data is written into the memory array, a positive voltage Vpos is applied to a memory gate word line WLSn corresponding to a row where a selected target memory cell is located, a positive voltage Vp0 is applied to a common source line SLn corresponding to the memory gate word line WLSn, a negative voltage Vneg is applied to memory gate word lines WLSn of rows where non-selected memory cells are located this time in the memory array, and a negative voltage Vneg is applied to all select gate word lines WLn in the memory array; and applying a negative voltage Vneg to the bit line BLn connected to the drain of the selected target memory cell when data "1" is written to the memory cell far from the common source line SLn in the selected target memory cell, or applying a positive voltage Vp0 to the bit line BLn connected to the drain of the selected target memory cell when data "0" is written to the memory cell far from the common source line SLn in the selected target memory cell.
11. The method of claim 10, wherein when reading data from the memory array, applying a positive voltage Vlim to the bit line BLn connected to the drain of a selected target memory cell, applying a positive voltage Vpwr greater than a device turn-on voltage to the select gate word line WLn of the row in which the selected target memory cell is located, and grounding the remaining terminals of the target memory cell, so as to obtain the state of the data stored in the selected memory cell by reading the current of the bit line BLn connected to the drain of the selected target memory cell.
12. The method of claim 11, wherein when performing an erase operation on said selected target memory cell, the voltage applied to the well is a positive voltage Vpos; when the selected target storage unit is subjected to writing operation, the voltage applied to the trap is a negative voltage Vneg; when a read operation is performed on the selected target memory cell, the well is directly grounded Vgnd.
13. The method of operating a split gate memory array architecture of claim 12, wherein Vneg < Vgnd < Vlim < Vp0< Vpos, where Vgnd =0V.
14. The method of operating a split gate memory array structure as recited in claim 13, wherein Vneg = -4V, wherein Vlim =0.8V, wherein Vp0=1.6V, wherein Vpwr =2V, and wherein Vpos =7V.
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