CN115357544A - Method, system, equipment and storage medium for improving reliability of nor flash controller - Google Patents

Method, system, equipment and storage medium for improving reliability of nor flash controller Download PDF

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Publication number
CN115357544A
CN115357544A CN202211038506.2A CN202211038506A CN115357544A CN 115357544 A CN115357544 A CN 115357544A CN 202211038506 A CN202211038506 A CN 202211038506A CN 115357544 A CN115357544 A CN 115357544A
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China
Prior art keywords
flash
flash controller
wdt
instruction
read instruction
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CN202211038506.2A
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Chinese (zh)
Inventor
刘刚
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Shandong Yunhai Guochuang Cloud Computing Equipment Industry Innovation Center Co Ltd
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Shandong Yunhai Guochuang Cloud Computing Equipment Industry Innovation Center Co Ltd
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Priority to CN202211038506.2A priority Critical patent/CN115357544A/en
Publication of CN115357544A publication Critical patent/CN115357544A/en
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
    • G06F15/781—On-chip cache; Off-chip memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F2015/761—Indexing scheme relating to architectures of general purpose stored programme computers
    • G06F2015/766—Flash EPROM

Abstract

The invention relates to the technical field of computers, in particular to a method, a system, equipment and a storage medium for improving the reliability of a nor flash controller. The method comprises the following steps: acquiring a first read instruction, and reading a flash by a flash controller in a 3byte mode according to the acquired first read instruction to start; if the starting is successful, controlling wdt to shut down, and stopping the wdt for timing; if the starting cannot be successfully carried out, the wdt cannot be turned off, and when the wdt reaches the timing time, the flash controller is switched to read from the 3byte mode to the 4byte mode, and the cpu is reset; and the flash controller acquires a second read instruction, and reads the flash in a 4byte mode according to the acquired second read instruction to start for the second time. The method adds wdt and wdt in the flash controller to be in an on state by default, is used for switching the reading mode at fixed time when the start fails, and simultaneously resets the CPU for restarting.

Description

Method, system, equipment and storage medium for improving reliability of nor flash controller
Technical Field
The invention relates to the technical field of computers, in particular to a method, a system, equipment and a storage medium for improving the reliability of a nor flash controller.
Background
In the soc system, the system can directly read data from the nor flash to start up, and therefore, the reliable reading of the nor flash is more and more concerned.
In the existing soc system, a flash is divided into a 3-byte mode and a 4-byte mode and is used for expanding the address space of a nor flash, a nor flash controller and the nor flash default to the 3-byte mode when the system is powered on, the 4-byte mode can be adjusted through software configuration, and the flash controller and a hardware reset flash are configured through software or the flash controller and the flash are configured through software during reset so as to ensure that the flash controller and the flash mode are kept consistent.
The existing nor flash controller has the defects that the normal restart can be realized only by resetting the flash through a software configuration controller and hardware when a system is reset or an external reset is carried out, and the complexity of software and hardware is increased.
Disclosure of Invention
In order to solve the technical problems in the prior art, the invention provides a method, a system, equipment and a storage medium for improving the reliability of a nor flash controller, and the complexity of software and hardware when a soc system accesses a nor flash is simplified mainly by optimizing the flash controller.
In order to achieve the above purpose, the embodiment of the present invention provides the following technical solutions:
in a first aspect, in an embodiment provided by the present invention, a method for improving reliability of a nor flash controller is provided, the method including the steps of:
acquiring a first read instruction, and reading a flash by a flash controller in a 3byte mode according to the acquired first read instruction to start;
if the starting is successful, controlling wdt to shut down, and stopping the wdt for timing;
if the starting cannot be successfully carried out, the wdt cannot be shut down, and when the wdt reaches the timing, the flash controller is switched to read from a 3byte mode to a 4byte mode and reset the cpu; and the flash controller acquires a second read instruction, and reads the flash in a 4byte mode according to the acquired second read instruction to start for the second time.
As a further scheme of the present invention, if the secondary start includes unsuccessful secondary start, wdt does not read the flash after the timing is up, and identifies the start failure.
As a further scheme of the invention, the flash controller reads the flash in a 3byte mode according to the obtained first read instruction to start, including that the flash controller reads the flash according to the obtained first read instruction to obtain the first read instruction;
the flash controller transmits the acquired first reading instruction to the cpu, judges whether the reading instruction is correct, if so, the cpu executes correctly, turns off wdt, and stops wdt to time.
As a further scheme of the present invention, the flash controller reads the flash in a 3byte mode according to the acquired first read instruction to start up, including that the flash controller reads the flash according to the acquired first read instruction to obtain the first read instruction;
and the flash controller transmits the acquired reading instruction to the cpu, judges whether the reading instruction is correct, if not, does not turn off wdt, and switches the flash controller from 3 bytes to 4 bytes when wdt reaches the timing, and simultaneously resets the cpu.
As a further scheme of the present invention, the flash controller reads the flash in a 4byte mode according to the obtained second read instruction to start up, including that the flash controller reads the flash according to the obtained second read instruction to obtain the second read instruction;
and the flash controller transmits the acquired second reading instruction to the cpu, judges whether the second reading instruction is correct, if so, the cpu executes correctly, turns off wdt, stops timing wdt, and starts successfully.
As a further scheme of the present invention, the flash controller reads the flash in a 4byte mode according to the obtained second read instruction to start up, including that the flash controller reads the flash according to the obtained second read instruction to obtain the second read instruction;
and the flash controller transmits the acquired second reading instruction to the cpu, judges whether the second reading instruction is correct or not, and if the second reading instruction is incorrect, the wdt does not read the flash after the time is counted, and marks the start failure.
As a further scheme of the invention, a rebot command is acquired, and the operations of resetting the cpu and starting wdt of the flash controller are completed according to the rebot command.
In a second aspect, in another embodiment provided by the present invention, there is provided a system for improving the reliability of a nor flash controller, the system including:
the system comprises Flash, a Flash controller, a WDT and a CPU;
the Flash is used for storing data;
the flash controller is used for receiving a reading instruction, acquiring flash data according to the reading instruction and acquiring the reading instruction;
the WDT is arranged in the flash controller and used for switching a 3-byte reading mode of the flash controller into a 4-byte reading mode at fixed time when the starting fails;
the CPU is used for sending a reading instruction to the flash controller, judging whether the returned reading instruction is correct or not according to the reading instruction returned by the flash controller, and if the returned reading instruction is correct, executing to finish starting; if not, resetting and carrying out secondary starting.
In a third aspect, in a further embodiment provided by the present invention, there is provided an apparatus comprising a memory and a processor, the memory storing a computer program, the processor implementing the steps of the method for improving reliability of a nor flash controller when the computer program is loaded and executed.
In a fourth aspect, in a further embodiment provided by the present invention, there is provided a storage medium storing a computer program which is loaded by a processor and which, when executed, performs the steps of the method for improving reliability of a nor flash controller.
The technical scheme provided by the invention has the following beneficial effects:
the invention provides a method, a system, equipment and a storage medium for improving the reliability of a nor flash controller, wherein wdt and wdt are added in the flash controller and are acquiedly determined to be in an open state, the method is used for switching a reading mode at fixed time when the start fails, and simultaneously resetting a cpu for restarting, and the complexity of software and hardware when a soc system accesses the nor flash is simplified mainly by optimizing the flash controller.
These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter. It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other embodiments can be obtained by using the drawings without creative efforts.
FIG. 1 is a flow chart of improving the reliability of a nor flash controller according to an embodiment of the present invention;
fig. 2 is a first structural block diagram of a system for improving the reliability of a nor flash controller according to an embodiment of the present invention;
fig. 3 is a block diagram of a second structure of the system for improving the reliability of the nor flash controller according to an embodiment of the present invention.
In the figure: flash-100, flash controller-200, WDT-300, CPU-400 and input device-500.
Detailed Description
The following describes various embodiments and/or aspects with reference to the drawings. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of one or more aspects. However, it will be understood by those skilled in the art that these aspects may be practiced without the specific details. Specific examples of one or more aspects will be described in detail in the following description and the accompanying drawings. However, these aspects are merely illustrative, and some of the various methods in the principles that can utilize various aspects are possible, and the description set forth is intended to include all aspects and their equivalents. In particular, the terms "embodiment," "example," "modality," "exemplary" and the like used in this specification may be construed as any modality or design described may be better or have an advantage over other modalities or designs.
In addition, various aspects and features may be embodied in a system including one or more devices, terminals, servers, equipment, components, and/or modules. It is to be understood and appreciated that the various systems may include additional pluralities of devices, terminals, servers, equipment, components, and/or modules, and/or may not include all of the pluralities of devices, terminals, servers, equipment, components, modules, etc. shown in the figures.
As used in this specification, the terms "computer program," "component," "module," "system," and the like are used interchangeably and refer to a computer-related entity, either hardware, firmware, software, a combination of software and hardware, or software in execution. For example, a component may be, but is not limited to being, a process executing on a processor, an object, a thread of execution, a program, and/or a computer. For example, it may be an application program executed on the computer device and/or all components of the computer device. More than one component may be located within a processor and/or thread of execution. A component may be localized in a computer. A component may also be distributed between more than two computers.
Also, these components can execute from various computer readable media having various data constructs stored therein. These components may communicate by way of local and/or remote processes such as in accordance with a signal having more than one data packet (e.g., data transmitted by one component interacting with another component in a local system, distributed system, and so forth over a network such as the internet with other systems by way of the signal).
Hereinafter, the same or similar components are denoted by the same reference numerals regardless of the reference numerals in the drawings, and redundant description thereof will be omitted. In describing the embodiments disclosed in the present specification, detailed descriptions of known techniques will be omitted if it is determined that the detailed descriptions thereof will obscure the gist of the present invention. The drawings are only for easier understanding of the embodiments disclosed in the present specification, and the technical ideas disclosed in the present specification are not limited to the drawings.
The terminology used in the description is for the purpose of describing the embodiments and is not intended to be limiting of the invention. The singular expressions in this specification include plural expressions unless specifically mentioned. The use of "comprising" and/or "comprising" in the specification does not exclude the presence or addition of one or more other elements or components other than the stated elements.
The terms first, second, etc. may be used to describe various elements or components, but the elements or components are not limited by the terms. The term is used to distinguish one element or constituent element from another element or constituent element. Therefore, the first element or component mentioned below may be the 2 nd element or component within the technical idea of the present invention.
Unless defined otherwise, all terms (including technical and scientific terms) used herein may be used in the same sense as commonly understood by one of ordinary skill in the art to which this invention belongs. In addition, terms defined in a general dictionary should not be interpreted in an ideal or excessive manner unless they are explicitly defined.
In addition, the term "or" is not meant to be an exclusive "or" but rather an inclusive "or". That is, "X employs A or B" means one of the alternatives of natural connotations unless there is any other specificity or context is ambiguous. That is, X utilizes A or; when X uses B or X uses A and B, "X uses A or B" may be any of the above. Also, it should be understood that the term "and/or" as used in this specification refers to all possible combinations of more than one of the associated items included in the list.
In addition, the terms "information" and "data" used in the present specification are generally used interchangeably.
The suffixes "module" and "section" used for the constituent elements in the following description are given or mixed for convenience of writing the description, and do not have mutually different meanings or functions.
The existing nor flash controller has the defects that the normal restart can be realized only by resetting the flash through a software configuration controller and hardware when a system is reset or an external reset is carried out, and the complexity of software and hardware is increased.
The invention simplifies the complexity of software and hardware when the soc system accesses the nor flash mainly by optimizing the flash controller.
Specifically, the embodiments of the present invention will be further explained below with reference to the drawings.
Referring to fig. 1, fig. 1 is a flowchart of a method for improving the reliability of a nor flash controller according to an embodiment of the present invention, and as shown in fig. 1, the method for improving the reliability of a nor flash controller includes steps S10 to S20.
S10, acquiring a first read instruction, and reading the flash to start by the flash controller in a 3byte mode according to the acquired first read instruction;
s20, if the starting is successful, controlling wdt to shut down, and stopping wdt to time;
if the starting cannot be successfully carried out, the method does not shut down wdt, and switches the flash controller to read from the 3byte mode to the 4byte mode and reset the cpu when wdt reaches the timing; and then the flash controller acquires a second read instruction, the flash controller reads the flash in a 4byte mode according to the acquired second read instruction to start for the second time, if the flash controller cannot start again successfully, the flash controller does not read the flash after timing of wdt is up, and starting failure is identified.
The start-up mode of the present invention can be automatically started in two modes.
And the flash controller reads the flash in a 4byte mode according to the acquired second read instruction to start the same CPU.
In the embodiment of the invention, the flash controller acquires the first read instruction, and the first read instruction is transmitted by the CPU.
In the embodiment of the invention, the flash controller reads the flash in a 3byte mode according to the acquired first read instruction to start, and the method comprises the following steps that the flash controller reads the flash according to the acquired first read instruction to acquire the first read instruction;
and the flash controller transmits the acquired first reading instruction to the cpu, judges whether the reading instruction is correct or not, if so, the cpu executes correctly, turns off wdt, and stops the timing of wdt.
In the embodiment of the invention, the flash controller reads the flash in a 3byte mode according to the acquired first read instruction to start, and the method comprises the steps that the flash controller reads the flash according to the acquired first read instruction to acquire the first read instruction;
and the flash controller transmits the acquired reading instruction to the cpu, judges whether the reading instruction is correct, if not, does not turn off wdt, and switches the flash controller from 3byte to 4byte when wdt reaches timing, and simultaneously resets the cpu.
In the embodiment of the invention, the flash controller reads the flash in a 4byte mode according to the acquired second read instruction to start, and the method comprises the following steps that the flash controller reads the flash according to the acquired second read instruction to obtain the second read instruction;
and the flash controller transmits the acquired second reading instruction to the cpu, judges whether the second reading instruction is correct, if so, the cpu executes correctly, turns off wdt, stops timing wdt, and then starts successfully.
In the embodiment of the invention, the flash controller reads the flash in a 4byte mode according to the acquired second read instruction to start, and the method comprises the following steps that the flash controller reads the flash according to the acquired second read instruction to obtain the second read instruction;
and the flash controller transmits the acquired second reading instruction to the cpu, judges whether the second reading instruction is correct, and if the second reading instruction is incorrect, the wdt does not read the flash after the timing is up and identifies the start failure.
In the embodiment of the invention, a reboot command is acquired, and the operations of resetting the cpu and starting the wdt of the flash controller are completed according to the reboot command.
Specifically, a rebot command is obtained, a flash controller obtains a first read instruction according to the rebot command, and the flash controller reads the flash in a 3byte mode according to the obtained first read instruction to start.
Specifically, when the system rebot is performed, the cpu sends out a first read instruction, the flash controller reads a flash return instruction after obtaining the first read instruction, and the flash controller sends the first read instruction to the cpu to execute the first read instruction, and then the flash controller is started to complete the operations of resetting the cpu and starting the wdt of the flash controller.
The invention simplifies the complexity of software and hardware when the soc system accesses the nor flash mainly by optimizing the flash controller.
It should be understood that although the steps are described above in a certain order, the steps are not necessarily performed in the order described. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, some steps of the present embodiment may include multiple steps or multiple stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of performing the steps or stages is not necessarily sequential, but may be performed alternately or in turns with other steps or at least a part of the steps or stages in other steps.
In one embodiment, referring to fig. 2, a system for improving the reliability of a nor Flash controller is further provided in an embodiment of the present invention, and the system includes a Flash100, a Flash controller 200, a WDT300, and a CPU400.
The Flash100 is used for storing data.
The flash controller 200 is configured to receive a read instruction, obtain flash data according to the read instruction, and obtain the read instruction.
And the WDT300 is arranged in the flash controller 200 and is used for switching the 3-byte reading mode of the flash controller to the 4-byte reading mode at a timing of a start failure. By setting the WDT300 to optimize the flash controller, the complexity of software and hardware when the soc system accesses the nor flash is simplified.
The CPU400 is configured to send a read instruction to the flash controller 200, determine whether the returned read instruction is correct according to the read instruction returned by the flash controller 200, and if the read instruction is correct, execute the start; if not, resetting, and carrying out secondary starting, wherein the secondary starting is final starting. That is, if the second boot fails, the next boot is not performed, indicating that the boot has failed.
Referring to fig. 3, in an embodiment of the present invention, the system further includes an input device 500.
The input device 500 is used for inputting a rebot command.
Specifically, when the system rebot is performed, the cpu sends out a first read instruction, the flash controller reads a flash return instruction after obtaining the first read instruction, and the flash controller sends the first read instruction to the cpu to execute the first read instruction, and then the flash controller is started to complete the operations of resetting the cpu and starting the wdt of the flash controller.
The invention simplifies the complexity of software and hardware when the soc system accesses the nor flash mainly by optimizing the flash controller.
In an embodiment, there is also provided an apparatus including at least one processor, and a memory communicatively connected to the at least one processor, the memory storing instructions executable by the at least one processor, the instructions being executable by the at least one processor to cause the at least one processor to perform the method for improving the reliability of a nor flash controller, the processor implementing the steps in the method embodiments when executing the instructions:
s10, acquiring a first read instruction, and reading a flash in a 3byte mode by a flash controller according to the acquired first read instruction to start;
s20, if the starting is successful, controlling wdt to shut down, and stopping wdt to time;
if the starting cannot be successfully carried out, the controller cannot be shut down wdt, and the flash controller is switched from 3byte to 4byte and reset the cpu when the wdt reaches the timing; and then the flash controller acquires a second reading instruction, the flash controller reads the flash in a 4byte mode according to the acquired second reading instruction to start, and if the flash controller cannot be started again successfully, the flash controller does not read the flash after the timing of wdt is up, and the starting failure is identified.
The start-up mode of the present invention can be automatically started in two modes.
And the flash controller reads the flash in a 4byte mode according to the acquired second reading instruction to start the same CPU.
In the embodiment of the present invention, the obtaining, by the flash controller, the first read instruction includes obtaining, by the flash controller, the first read instruction sent by the cpu.
In the embodiment of the invention, the flash controller reads the flash in a 3byte mode according to the acquired first read instruction to start, and the method comprises the following steps that the flash controller reads the flash according to the acquired first read instruction to acquire the first read instruction;
the flash controller transmits the obtained reading instruction to the cpu, judges whether the reading instruction is correct, if so, the cpu executes correctly, turns off wdt, and stops timing wdt.
In the embodiment of the invention, the flash controller reads the flash in a 3byte mode according to the acquired first read instruction to start, and the method comprises the following steps that the flash controller reads the flash according to the acquired first read instruction to acquire the first read instruction;
and the flash controller transmits the acquired reading instruction to the cpu, judges whether the reading instruction is correct, if not, does not turn off wdt, and switches the flash controller from 3byte to 4byte when wdt reaches timing, and simultaneously resets the cpu.
In the embodiment of the invention, the flash controller reads the flash in a 4byte mode according to the acquired second read instruction to start, and the method comprises the following steps that the flash controller reads the flash according to the acquired second read instruction to obtain the second read instruction;
and the flash controller transmits the acquired second reading instruction to the cpu, judges whether the second reading instruction is correct, if so, the cpu executes correctly, turns off wdt, stops timing wdt, and then starts successfully.
In the embodiment of the invention, the flash controller reads the flash in a 4byte mode according to the acquired second read instruction to start, and the method comprises the following steps that the flash controller reads the flash according to the acquired second read instruction to obtain the second read instruction;
and the flash controller transmits the acquired second reading instruction to the cpu, judges whether the second reading instruction is correct, and if the second reading instruction is incorrect, the wdt does not read the flash after the timing is up and identifies the start failure.
In the embodiment of the invention, a reboot command is acquired, and the operations of resetting the cpu and starting the wdt of the flash controller are completed according to the reboot command.
Specifically, a rebot command is obtained, a flash controller obtains a first read instruction according to the rebot command, and the flash controller reads the flash in a 3byte mode according to the obtained first read instruction to start.
Specifically, when the system rebot is performed, the cpu sends out a first read instruction, the flash controller reads a flash return instruction after obtaining the first read instruction, and the flash controller sends the first read instruction to the cpu to execute the first read instruction, and then the flash controller is started to complete the operations of resetting the cpu and starting the wdt of the flash controller.
The method mainly simplifies the complexity of software and hardware when the soc system accesses the nor flash by optimizing the flash controller.
The device comprises user equipment and network equipment. Wherein the user equipment includes but is not limited to computers, smart phones, PDAs, etc.; the network device includes, but is not limited to, a single network server, a server group consisting of a plurality of network servers, or a Cloud Computing (Cloud Computing) based Cloud consisting of a large number of computers or network servers, wherein the Cloud Computing is one of distributed Computing, a super virtual computer consisting of a collection of loosely coupled computers. Wherein the devices may operate alone to implement the invention, or may access a network and implement the invention through interoperation with other devices in the network. The network where the device is located includes, but is not limited to, the internet, a wide area network, a metropolitan area network, a local area network, a VPN network, and the like.
It should also be understood that the term "and/or" as used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.
In an embodiment of the present invention, there is also provided a storage medium having stored thereon a computer program which, when executed by a processor, implements the steps in the above-described method embodiment:
s10, acquiring a first read instruction, and reading the flash to start by the flash controller in a 3byte mode according to the acquired first read instruction;
s20, if the starting is successful, controlling wdt to shut down, and stopping wdt to time;
if the starting cannot be successfully carried out, the controller cannot be shut down wdt, and the flash controller is switched from 3byte to 4byte and reset the cpu when the wdt reaches the timing; and then the flash controller acquires a second reading instruction, the flash controller reads the flash in a 4byte mode according to the acquired second reading instruction to start, and if the flash controller cannot be started again successfully, the flash controller does not read the flash after the timing of wdt is up, and the starting failure is identified.
The start-up mode of the present invention can be automatically started in two modes.
And the flash controller reads the flash in a 4byte mode according to the acquired second read instruction to start the same CPU.
In the embodiment of the present invention, the obtaining, by the flash controller, the first read instruction includes obtaining, by the flash controller, the first read instruction sent by the cpu.
In the embodiment of the invention, the flash controller reads the flash in a 3byte mode according to the acquired first read instruction to start, and the method comprises the following steps that the flash controller reads the flash according to the acquired first read instruction to acquire the first read instruction;
and the flash controller transmits the acquired reading instruction to the cpu, judges whether the reading instruction is correct or not, if so, the cpu executes correctly, turns off wdt, and stops wdt to time.
In the embodiment of the invention, the flash controller reads the flash in a 3byte mode according to the acquired first read instruction to start, and the method comprises the steps that the flash controller reads the flash according to the acquired first read instruction to acquire the first read instruction;
and the flash controller transmits the acquired reading instruction to the cpu, judges whether the reading instruction is correct, if not, does not turn off wdt, and switches the flash controller from 3byte to 4byte when wdt reaches timing, and simultaneously resets the cpu.
In the embodiment of the invention, the flash controller reads the flash in a 4byte mode according to the obtained second read instruction to start, and the method comprises the steps that the flash controller reads the flash according to the obtained second read instruction to obtain the second read instruction;
and the flash controller transmits the acquired second reading instruction to the cpu, judges whether the second reading instruction is correct, if so, the cpu executes correctly, turns off wdt, stops timing wdt, and then starts successfully.
In the embodiment of the invention, the flash controller reads the flash in a 4byte mode according to the obtained second read instruction to start, and the method comprises the steps that the flash controller reads the flash according to the obtained second read instruction to obtain the second read instruction;
and the flash controller transmits the acquired second reading instruction to the cpu, judges whether the second reading instruction is correct, and if the second reading instruction is incorrect, the wdt does not read the flash after the timing is up and identifies the start failure.
In the embodiment of the invention, a reboot command is acquired, and the operations of resetting the cpu and starting the wdt of the flash controller are completed according to the reboot command.
Specifically, a rebot command is obtained, a flash controller obtains a first read instruction according to the rebot command, and the flash controller reads the flash in a 3byte mode according to the obtained first read instruction to start.
Specifically, when the system rebot is performed, the cpu sends out a first read instruction, the flash controller reads a flash return instruction after obtaining the first read instruction, and the flash controller sends the first read instruction to the cpu to execute the first read instruction, and then the flash controller is started to complete the operations of resetting the cpu and starting the wdt of the flash controller.
The invention simplifies the complexity of software and hardware when the soc system accesses the nor flash mainly by optimizing the flash controller.
It will be understood by those skilled in the art that all or part of the processes of the methods of the above embodiments may be implemented by hardware instructions of a computer program, which may be stored in a non-volatile computer-readable storage medium, and when executed, may include processes of the embodiments of the methods described above. Any reference to memory, storage, database or other medium used in embodiments provided herein may include at least one of non-volatile and volatile memory.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.
The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the present disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. Furthermore, although elements of the disclosed embodiments of the invention may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.
It should be understood that, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items. The numbers of the embodiments disclosed in the embodiments of the present invention are merely for description, and do not represent the merits of the embodiments.
Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, of embodiments of the invention is limited to these examples; within the idea of an embodiment of the invention, also technical features in the above embodiment or in different embodiments may be combined and there are many other variations of the different aspects of the embodiments of the invention as described above, which are not provided in detail for the sake of brevity. Therefore, any omissions, modifications, substitutions, improvements, and the like that may be made without departing from the spirit and principles of the embodiments of the present invention are intended to be included within the scope of the embodiments of the present invention.

Claims (10)

1. A method for improving the reliability of a nor flash controller is applied to a system for improving the reliability of the nor flash controller, and the system comprises the following steps: flash, a Flash controller, WDT and CPU, characterized in that, the method comprises: acquiring a first read instruction, and reading a flash by a flash controller in a 3byte mode according to the acquired first read instruction to start;
if the starting is successful, controlling wdt to shut down, and stopping the wdt for timing;
if the starting cannot be successfully carried out, the wdt cannot be turned off, and when the wdt reaches the timing time, the flash controller is switched to read from the 3byte mode to the 4byte mode, and the cpu is reset; and the flash controller acquires a second read instruction, and reads the flash in a 4byte mode according to the acquired second read instruction to start for the second time.
2. The method as claimed in claim 1, wherein the secondary start-up comprises unsuccessful secondary start-up, and wdt is no longer reading flash after timing up, and identifying the failure of start-up.
3. The method for improving the reliability of a nor flash controller of claim 1, wherein the flash controller reads a flash in a 3byte mode according to the obtained first read instruction to start up, and the method comprises the steps that the flash controller reads the flash according to the obtained first read instruction to obtain a first read instruction;
and the flash controller transmits the acquired first reading instruction to the cpu, judges whether the reading instruction is correct or not, if so, the cpu executes correctly, turns off wdt, and stops the timing of wdt.
4. The method for improving the reliability of a nor flash controller of claim 3, wherein the flash controller reads the flash in a 3byte mode according to the obtained first read instruction to start up, and the method comprises the steps that the flash controller reads the flash according to the obtained first read instruction to obtain a first read instruction;
and the flash controller transmits the acquired reading instruction to the cpu, judges whether the reading instruction is correct, if not, does not turn off wdt, and switches the flash controller from 3byte to 4byte when wdt reaches timing, and simultaneously resets the cpu.
5. The method for improving the reliability of a nor flash controller of claim 1, wherein the flash controller reads the flash in a 4byte mode according to the obtained second read instruction to start up, and the method comprises the steps that the flash controller reads the flash according to the obtained second read instruction to obtain the second read instruction;
and the flash controller transmits the acquired second reading instruction to the cpu, judges whether the second reading instruction is correct, if so, the cpu executes correctly, turns off wdt, stops timing wdt, and starts successfully.
6. The method for improving the reliability of a nor flash controller according to claim 5, wherein the flash controller reads the flash in a 4byte mode according to the obtained second read instruction to start, and comprises the steps of reading the flash by the flash controller according to the obtained second read instruction to obtain a second read instruction;
and the flash controller transmits the acquired second reading instruction to the cpu, judges whether the second reading instruction is correct, and if the second reading instruction is incorrect, the wdt does not read the flash after the timing is up and identifies the start failure.
7. The method for improving the reliability of a nor flash controller of any one of claims 1 to 6, wherein a reboot command is obtained, and the operations of resetting the cpu and starting the wdt of the flash controller are completed according to the reboot command.
8. A system for improving the reliability of a nor flash controller, the system comprising: the system comprises Flash, a Flash controller, a WDT and a CPU;
the Flash is used for storing data;
the flash controller is used for receiving a reading instruction, acquiring flash data according to the reading instruction and acquiring the reading instruction;
the WDT is arranged in the flash controller and used for switching a 3-byte reading mode of the flash controller into a 4-byte reading mode at fixed time when the starting fails;
the CPU is used for sending a reading instruction to the flash controller, judging whether the returned reading instruction is correct or not according to the reading instruction returned by the flash controller, and if the returned reading instruction is correct, executing to finish starting; if not, resetting and carrying out secondary starting.
9. An apparatus comprising a memory and a processor, the memory storing a computer program which when loaded and executed implements the steps of the method of improving reliability of a nor flash controller as claimed in any of claims 1 to 7.
10. A storage medium storing a computer program which, when loaded and executed by a processor, carries out the steps of the method of improving reliability of a nor flash controller as claimed in any one of claims 1 to 7.
CN202211038506.2A 2022-08-29 2022-08-29 Method, system, equipment and storage medium for improving reliability of nor flash controller Pending CN115357544A (en)

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CN202211038506.2A CN115357544A (en) 2022-08-29 2022-08-29 Method, system, equipment and storage medium for improving reliability of nor flash controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202211038506.2A CN115357544A (en) 2022-08-29 2022-08-29 Method, system, equipment and storage medium for improving reliability of nor flash controller

Publications (1)

Publication Number Publication Date
CN115357544A true CN115357544A (en) 2022-11-18

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