CN115357416A

CN115357416A - Method and device for performing data processing across systems

Info

Publication number: CN115357416A
Application number: CN202211276472.0A
Authority: CN
Inventors: 吴斌
Original assignee: Nanjing Semidrive Technology Co Ltd
Current assignee: Nanjing Semidrive Technology Co Ltd
Priority date: 2022-10-19
Filing date: 2022-10-19
Publication date: 2022-11-18
Anticipated expiration: 2042-10-19
Also published as: CN115357416B

Abstract

The application discloses a method, a device, a chip, a semiconductor integrated panel, an electronic component and a vehicle for cross-system data processing. The method is mainly applied to a first system and a second system which are interconnected through a system interconnection bus, wherein the first system acquires a physical memory address space which is allocated by the second system for second data processing equipment through the system interconnection bus and maps the physical memory address space into a virtual memory address space of the first system; and then, the physical memory address space allocated by the second system for the second processing device can be accessed through the virtual memory address space of the first system, and the second data processing device is controlled to process the local data of the first system. Therefore, the processor in the first system can directly access and control the second data processing equipment in the second system, and the speed and the efficiency of data processing across the systems are greatly improved.

Description

Method and device for performing data processing across systems

Technical Field

The present application relates to the field of computing data processing technologies, and in particular, to a method, an apparatus, a chip, a semiconductor integrated panel, an electronic component, and a vehicle for data processing across systems.

Background

In a peer-to-peer system interconnected by a bus, when a certain device (e.g., a camera) of a certain system needs to process data using a data processing device (e.g., a digital signal processing device), and the processing capability of the data processing device in the system is insufficient, an attempt is made to control the data processing device using another system to perform a coordinated process.

At present, the common technical scheme is as follows: the two systems respectively control and use the data processing equipment in the system, when the data processing equipment of the other system needs to be called, the other system is informed through remote call (RPC), and the other system controls the data processing equipment to realize the control. However, the above method requires multiple communications and precise synchronization through software, and is complex to implement and prone to errors.

Disclosure of Invention

The applicant inventively provides a method, apparatus, chip, semiconductor integrated panel, electronic component and vehicle for data processing across a system.

According to a first aspect of embodiments of the present application, there is provided a method for performing data processing across systems, which is applied to a first system, where the first system is provided with a first data processing device, and the method includes: acquiring a physical memory address space allocated by a second system for second data processing equipment through a system interconnection bus to obtain a first memory address space, wherein the second system and the first system are interconnected peer-to-peer systems, and a drive of the first data processing equipment is suitable for the second data processing equipment; allocating a virtual memory address space for the second data processing equipment to obtain a second memory address space, and establishing a mapping relation between the first memory address space and the second memory address space; and controlling the second data processing equipment to process the local data of the first system through the second memory address space.

According to an embodiment of the present application, establishing a mapping relationship between a first memory address space and a second memory address space includes: establishing a forward address mapping table from the second memory address to the first memory address; and establishing a reverse address mapping table from the first memory address to the second memory address.

According to an embodiment of the present application, establishing a forward address mapping table from a second memory address space to a first memory address space includes: and establishing a forward address mapping table from the second memory address space to the first memory address space in a manner of increasing the memory address progressively.

According to an embodiment of the present application, before controlling the second data processing apparatus to process the local data of the first system through the second memory address space, the method further includes: loading the firmware to a second memory address space; the second data processing device is enabled.

According to an embodiment of the present application, loading firmware into a second memory address space includes: acquiring a first memory address of firmware to be loaded in a first memory address space; acquiring a second memory address of the first memory address mapped in a second memory address space; and loading the firmware to be loaded to the second memory address.

According to an embodiment of the present application, the second data processing device is provided with a shared memory in a first memory address space, and accordingly, the second data processing device is controlled to process the local data of the first system through a second memory address space, including: the processor of the first system writes the command and the input data into the shared memory based on the virtual memory address mapped in the second memory address space in the shared memory; the second data processing equipment reads a command and input data from the shared memory based on a physical memory address in the first memory address space in the shared memory, executes a corresponding command according to the command and the input data, and writes an execution result of the corresponding command into the shared memory; and the processor of the first system reads the execution result of the corresponding command from the shared memory based on the virtual memory address mapped in the second memory address space in the shared memory.

According to an embodiment of the present application, writing a command and input data to a shared memory based on a virtual memory address mapped in a second memory address space existing in the shared memory, includes: allocating a first buffer address for writing commands and input data based on the virtual memory address mapped in the second memory address space existing in the share; the command and the input data are written to the first buffer address.

According to an embodiment of the application, the processing device is a digital signal processing device.

According to a second aspect of the embodiments of the present application, there is provided an apparatus for performing data processing across systems, which is applied to a first system, where the first system is provided with a first data processing device, and the apparatus includes: a first memory address space obtaining module, configured to obtain, through a system interconnection bus, a physical memory address space allocated by a second system to a second data processing device, to obtain a first memory address space, where the second system and the first system are interconnected peer-to-peer systems, and a drive of the first data processing device is applicable to the second data processing device; the address space mapping module is used for allocating a virtual memory address space for the second data processing equipment to obtain a second memory address space and establishing a mapping relation between the first memory address space and the second memory address space; and the second data processing equipment using module is used for controlling the second data processing equipment to process the local data of the first system through the second memory address space.

According to a third aspect of the embodiments of the present application, there is provided a chip for performing any one of the above methods for data processing across systems.

According to a fourth aspect of the embodiments of the present application, there is provided a semiconductor integrated panel provided with the above chip.

According to a fifth aspect of embodiments of the present application, there is provided an electronic component provided with the above-described semiconductor integrated panel.

According to a sixth aspect of the embodiments of the present application, there is provided a vehicle provided with the electronic component described above.

The embodiment of the application provides a method, a device, a chip, a semiconductor integrated panel, an electronic component and a vehicle for data processing across systems. The method is mainly applied to a first system and a second system which are interconnected through a system interconnection bus, wherein the first system acquires a physical memory address space distributed by the second system for second data processing equipment through the system interconnection bus and maps the physical memory address space into a virtual memory address space of the first system; and then, the physical memory address space allocated by the second system for the second processing device can be accessed through the virtual memory address space of the first system, and the second data processing device is controlled to process the local data of the first system. Therefore, the processor in the first system can directly access and control the second data processing equipment in the second system without transferring commands or transmitting data through the processor in the second system, and the speed and the efficiency of data processing across the systems are greatly improved.

It is to be understood that not all of the above advantages need to be achieved in the present application, but that a specific technical solution may achieve a specific technical effect, and that other embodiments of the present application may also achieve advantages not mentioned above.

Drawings

The above and other objects, features and advantages of exemplary embodiments of the present application will become readily apparent from the following detailed description, which proceeds with reference to the accompanying drawings. Several embodiments of the present application are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which:

in the drawings, like or corresponding reference characters designate like or corresponding parts.

FIG. 1 is a schematic diagram of a dual system architecture for implementing a cross-system data processing method according to an embodiment of the present application;

FIG. 2 is a schematic flowchart illustrating a method for implementing data processing across systems according to the embodiment shown in FIG. 1;

FIG. 3 is a diagram illustrating a conventional system architecture before applying a method for cross-system data processing according to another embodiment of the present application;

FIG. 4 is a schematic diagram of a system architecture of an improved system for implementing a method for data processing across systems according to the embodiment of the present application shown in FIG. 3;

FIG. 5 is a flowchart illustrating a method for implementing data processing across systems according to the embodiment shown in FIG. 3;

FIG. 6 is a diagram illustrating a forward address mapping table established in the embodiment of FIG. 3;

FIG. 7 is a diagram illustrating a reverse address mapping table established in the embodiment of FIG. 3 of the present application;

FIG. 8 is a flowchart illustrating loading firmware according to the embodiment of FIG. 3;

FIG. 9 is a data diagram of a program header table used in the embodiment of FIG. 3 of the present application;

FIG. 10 is a diagram illustrating a buffer allocation table used in the embodiment of FIG. 3;

FIG. 11 is a diagram illustrating a shared memory used in the embodiment of FIG. 3;

FIG. 12 is a diagram of a second embodiment of a shared memory used in the present application shown in FIG. 3;

fig. 13 is a schematic structural diagram of an apparatus for performing data processing across systems according to an embodiment of the present application.

Detailed Description

In order to make the objects, features and advantages of the present application more obvious and understandable, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all the embodiments. All other embodiments obtained by a person skilled in the art based on the embodiments in the present application without making any creative effort belong to the protection scope of the present application.

In the description herein, reference to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Moreover, various embodiments or examples and features of various embodiments or examples described in this specification can be combined and combined by one skilled in the art without being mutually inconsistent.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or to implicitly indicate the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.

Fig. 1 illustrates a dual system architecture to which a method of data processing across systems is applied according to an embodiment of the present application. As shown in fig. 1, in a scenario to which this embodiment is applied, a peer-to-peer dual system is provided: a first system 11 and a second system 12.

On the one hand, the first system 11 and the second system 12 may each operate independently; on the other hand, the first system 11 and the second system 12 may communicate with each other via a system interconnection bus 13, and communication and data transmission may be performed between the first system 11 and the second system 12 to cooperatively perform a specific task.

In addition, other devices are also provided in the first system 11 and the second system 12, respectively, for example, a first data processing device 1102 is provided in the first system 11, and a second data processing device 1202 is provided in the second system 12.

Typically, these devices are managed and controlled by the processors of the respective systems through the memory address spaces allocated to the respective devices by the respective systems.

For example, in the second system 12, the first memory address space 1203 is allocated to the second data processing apparatus 1202 to access the control register of the second data processing apparatus 1202, to create a shared memory for exchanging data with the second data processing apparatus 1202, and the like; the second processor 1201 accesses the control register of the second data processing apparatus 1202 through the first memory address space 1203, and exchanges data or the like with the second data processing apparatus 1202 through the shared memory in the first memory address space 1203 to control the second data processing apparatus 1202 to perform a specified operation.

Similarly, in the first system 11, a third memory address space 1103 is allocated to the first data processing apparatus 1102 to access a control register of the first data processing apparatus 1102, create a shared memory for exchanging data with the first data processing apparatus 1102, and the like; the first processor 1101 accesses the control register of the first data processing apparatus 1102 through the third memory address space 1103, and exchanges data and the like with the first data processing apparatus 1102 through the shared memory in the third memory address space 1103 to control the first data processing apparatus 1102 to perform a specified operation.

In general, in a peer-to-peer system, each system still maintains its own independent memory address space, which is only used by the system, is invisible to other systems, and is not available.

Therefore, if the first processor 1101 of the first system 11 needs to access and control the second data processing apparatus 1202 in the second system 12, it is often necessary to communicate with the second processor 1201 and transmit a command and data to be processed to the second processor 1201, and the second processor 1201 accesses and controls the second data processing apparatus 1202 to process the data to be processed transmitted by the first processor 1101. After that, the second processor 1201 acquires the processing result, and returns the processing result to the first processor 1101 of the first system 11. Therefore, the process of data processing across the system is extremely complicated, and errors are easy to occur.

To this end, the inventor of the present application has creatively provided a method for data processing across systems, which enables the first system 11 to process local data using the second data processing apparatus 1202 in the second system 12, as with the local apparatus, directly through the second memory address space 1104 within the first system 11, without synchronization of communication with the second processor 1201. Referring to fig. 2, the method includes:

in operation S210, a physical memory address space allocated by the second system 12 to the second data processing apparatus 1202 is obtained through the system interconnection bus 13, so as to obtain a first memory address space 1203, where the second system 12 and the first system 11 are interconnected peer systems, and a driver of the first data processing apparatus 1102 is applicable to the second data processing apparatus 1202.

The system interconnection bus generally refers to a bus that connects the bus of the first system 11 and the bus of the second system 12 through a bus interface to form a bus that can access the system resource of the other system, for example, a Peripheral Component Interconnect Express (PCIe) bus, a CXL (computer Express Link) bus, and the like.

A physical memory address refers to the actual address of a physical memory that actually exists (e.g., a DDR memory), and is also the address used to address the physical memory on the bus, and is also referred to as an absolute address.

The physical memory address space is an address space consisting of physical memory addresses.

The bus of the first system 11 may communicate with the bus of the second system 12 through the system interconnection bus 13, and obtain the physical memory address of the first memory address space 1203 in the second system 12 through the bus of the second system 12.

A peer system refers to another system or systems functionally equivalent and equivalent to the present system connected to the present system through a system interconnection bus.

A data processing device refers to a device for processing data, in particular a programmable data processing device. For example, a Digital Signal Processing (DSP) device, a Graphic Processing Unit (GPU), a Microcontroller (MCU), or the like.

In the present embodiment, the driving of the first data processing apparatus 1102 in the first system 11 is also applied to the second data processing apparatus 1202. As such, within the first system 11, the second data processing apparatus 1202 can be accessed and controlled directly using the driver of the first data processing apparatus 1102.

In operation S220, a virtual memory address space is allocated to the second data processing apparatus 1202 to obtain a second memory address space 1104, and a mapping relationship is established between the first memory address space 1203 and the second memory address space 1104.

The virtual memory address space refers to a memory area allocated with a local memory address space accessible by the first processor 1101, but not actually occupying or corresponding to the local physical memory of the first system.

The virtual memory address space may be mapped to physical memory regions of other systems by a mapping means (e.g., PCIe address mapping).

The second memory address space 1104 of the first system 11 is mapped to the first memory address space 1203 allocated by the second system 12 to the second data processing apparatus 1202, and a mapping relationship between the memory address in the second memory address space 1104 and the memory address in the first memory address space 1203 may be stored by establishing an address mapping table.

However, for the first processor 1101, the second memory address space 1104 and the third memory address space 1103 are available local memory address spaces regardless of whether the physical memory address space of the background mapping is local, and are not differentiated in use.

In operation S230, the second data processing apparatus 1202 is controlled to process the local data of the first system 11 through the second memory address space 1104.

As mentioned above, the processors in each system access and control each device through local memory addresses. Therefore, after mapping the physical memory address space, i.e. the first memory address space 1203, allocated by the second system 12 to the second data processing apparatus 1202 to the virtual memory address space, i.e. the second memory address space 1104 of the first system 11, the second data processing apparatus 1202 can be accessed and controlled to process the local data of the first system 11 through the first processor 1101 and the second memory address space 1104 in the first system 11, and it is not necessary to relay a command or transmit data through the second processor 1201 in the second system 12, which greatly improves the speed and efficiency of data processing across systems.

Fig. 3 shows a system framework of a first system 31 and a second system 32 to which another embodiment of the present application implements a method of data processing across systems.

As shown in fig. 3, the first system 31 is provided with a first processor CPU311 and a first data processing device DSP312. When using the DSP312, it is necessary to include at least the following in the memory address space 313: the DSP controls the register mapping space; the DSP firmware runs the memory space; a shared memory space "shared memory-command queue" for placing command queues and a shared memory space "shared memory-data buffer" for placing input-output data buffers (buffers).

The memory address space 313 is a physical memory address space on the first system 31.

The DSP control register maps space for accessing the physical addresses of the control registers, such as reset/clock, of the DSP312. The CPU311 accesses the DSP control register by reading and writing an address in the DSP control register map to control the DSP312 to enable (enable) or disable (disable), or the like.

DSP firmware operating memory space is memory space allocated exclusively to DSP312, the function code of DSP312 operates in this section of memory, and CPU311 loads the firmware from the file system into this section of memory before DSP312 begins to process commands.

The "shared memory-command queue" is a shared memory space for placing a command queue, which is a memory space that can be read and written by both the DSP312 and the CPU311, for transferring commands between the DSP312 and the CPU311.

The "shared memory-data buffer" is a shared memory for storing input/output data buffers, which is a memory that can be read and written by both the DSP312 and the CPU311, and is used for storing input data to be processed by the DSP311 and returned output result data.

The second system 32 is provided with a second processor CPU321 and a second data processing device DSP322. When using the DSP322, it is also necessary to include at least the following in the memory address space 323: the DSP controls the register mapping space; the DSP firmware runs the memory space; the shared memory space "shared memory-command queue" for placing command queues and the shared memory space "shared memory-data buffer" for placing input and output data buffers.

The purpose of each memory space is the same as that of the corresponding memory space in the memory address space 313 in the first system 31, and will not be described herein again.

When the first system 31 and the second system 32 each independently use the DSP of the present system, each system accesses the memory address space in the respective system through the respective CPU to access and control the DSP in the respective system.

Taking the first system 31 as an example, after the memory address space 313 establishes each memory space and allocates an address for each memory space, the following steps may be performed to process local data using the DSP 312:

1) Loading the firmware of the DSP312 from the file system into a DSP firmware operating memory space;

2) Enable (enable) DSP312;

3) Setting a shared memory for buffering data as an input-output data buffer, and sending a command to be executed to the shared memory for placing a command queue;

4) DSP312 then obtains the command from the shared memory for placing the command queue, reads the input data from the shared memory for buffering the data, executes the command to process the input data, and places the processed result back into the shared memory for buffering the data.

Thus, the process of processing the local data using the DSP312 is completed once.

Fig. 4 shows a system architecture of the embodiment shown in fig. 3 after the first system 31 is modified to implement the method for data processing across systems of the present application.

As shown in fig. 4, in order to enable the CPU311 of the first system 31 to directly use the DSP322 in the second system 32 to process local data, buses of the first system 31 and the second system 32 are connected through the system interconnect bus PCIe33, and a part of the memory address space is allocated as the PCIe map address space 314 within a virtual memory address space (for example, 8G memory address space of x9_0000 to 0xa 0000) allocated by the CPU311 to the system interconnect bus PCIe33 on the first system 31. The virtual memory addresses in the PCIe mapping address space 314 may be configured to map to physical memory addresses (e.g., DDR memory addresses) in the memory address space 323 of the second system 32. The physical memory addresses in the memory address space 323 of the second system 32 are typically physical memory addresses that are physically accessible to the PCIe root device connected to the system interconnect bus PCIe 33.

The CPU311 can then access and control the DSP322 on the second system 32 via the virtual memory address in the PCIe mapped address space 314.

Specifically, the first system 31 is modified to make the first system 31 use the DSP322 in the second system 32 to process the local data, as shown in fig. 5:

operation S510 establishes a PCIe map.

Specifically, the method comprises the following steps:

1) Acquiring a physical memory address space of a memory address space 323 in the second system 32, which can be actually accessed by PCIe root equipment, by using an interconnection bus PCIe 33;

2) In the virtual memory address space allocated by the first system 31 for the PCIe33 as the interconnect bus, a part of the virtual memory address is allocated to map to the physical memory address of the DSP322 in the memory address space 32, so as to form a PCIe mapping address space 314.

In the embodiment of the present application, after the PCIe mapping is established, the CPU321 of the second system 32 will not control and use the DSP322. The first system 31 logically becomes a system with 2 DSP devices. The 2 DSP devices are controlled and used in the same manner for the drivers running on the CPU311 in the first system 31, but with different memory address spaces.

For the firmware running on the DSP322 in the second system 32, the address spaces are consistent with the addresses in the previous stage, so that the firmware can be executed as usual without modification.

In operation S520, a forward and reverse address mapping table is established.

In the embodiment of the present application, the forward address mapping table is an address mapping table formed by mapping virtual memory addresses of the first system 31 to physical memory addresses of the DSP322 in the memory address space 323 of the second system 32, as shown in fig. 6.

The forward address mapping table 60 includes: the number of address mapping entries and a plurality of address mapping entries (e.g., address mapping entry 601 and address mapping entry 602, etc.).

Each address mapping entry, taking the address mapping entry 601 as an example, includes: source CPU address, destination DSP address and mapping space size. The source CPU address refers to a virtual memory address allocated to the DSP322 for use by the first processor 311 in the first system 31, and may be mapped to a physical memory address allocated to the DSP322 in the memory address space 323 for the second system 32 after PCIe mapping; the destination DSP address refers to a memory address for use by the DSP322 and is a physical memory address allocated by the second system 32 for the DSP322 in the memory address space 323.

In the embodiment of the present application, for example, to facilitate querying, the address mapping entries are arranged in the order of increasing addresses. Other sorting methods can be adopted by the implementer according to specific implementation conditions.

In the embodiment of the present application, the reverse address mapping table is an address mapping table formed by mapping the physical memory address in the memory address space 323 of the second system 32 to the virtual memory address in the PCIe mapping address space 314 of the first system 31, as shown in fig. 7.

The reverse address mapping table 70 includes: the number of address mapping entries and a plurality of address mapping entries (e.g., address mapping entry 701 and address mapping entry 702, etc.).

Each address mapping entry, taking address mapping entry 701 as an example, includes: source DSP address, destination CPU address, and mapping space size. Wherein, the source DSP address refers to a memory address used by the DSP322, which is a physical memory address allocated by the second system 32 for the DSP322 in the memory address space 323; the destination CPU address refers to a virtual memory address allocated to the DSP322 for use by the first processor 311 in the first system 31, and is mapped to a physical memory address allocated in the memory address space 323 for the DSP322 by the second system 32 after PCIe mapping.

In the embodiment of the present application, the reverse address mapping table 70 is obtained by exchanging the CPU address and the DSP address of each address mapping entry in the reverse address mapping table 60 and arranging the addresses in the increasing order of the DSP addresses. Other sorting methods can be adopted by the implementer according to specific implementation conditions.

In the embodiment of the present application, the number of the memory segments mapped by the forward address mapping table 60 and the reverse address mapping table 70 is not large and will not be dynamically adjusted, and a binary tree lookup algorithm may be used to perform data lookup.

In operation S530, the firmware is loaded to the 2 DSPs.

Fig. 8 shows a main flow of loading firmware according to an embodiment of the present application, which includes:

step S810, reading the ELF format DSP firmware.

In step S820, the physical address (PhycAddr) to be loaded in each segment is read from the Program Header (Program Header) table of the firmware.

The program header table in the ELF file is shown in fig. 9.

Step S830, the physical address is used as the source DSP address in the reverse address mapping table to obtain the destination CPU address.

Taking the program header table shown in fig. 9 as an example, the physad entry is a memory address of the DSP during actual operation, and the source DSP address of the reverse address mapping table of DSP- > CPU is used as the entry, so that the destination CPU address is found.

Step S840 loads the content of the segment to the destination CPU address.

Step S850, determining that all segments are loaded, if yes, continuing step S860, otherwise, returning to step S820.

Step S860, operating register enable DSPs according to the respective control register mapping of the 2 DSPs.

In operation S540, the input and output data buffers are allocated by the CPU311 in the first system 31, and a command is sent to cause the DSP322 in the second system 32 to process the local data.

The CPU311 in the first system 31 interacts with each DSP through the shared memory, and sends commands and stores input/output data through the shared memory. The device driver of the DSP322 dynamically allocates and retrieves an input data buffer (buffer) to be processed by the DSP and an output buffer (buffer) processed by the DSP from the shared memory using the DSP address (physical address mapped in the memory address space 323 in the second system 32), and maps the input data buffer and the output data buffer to the CPU address (logical address in the PCIe mapped address space 314 in the first system 31) for the CPU311 to access.

For each buffer, the CPU311 maintains a buffer allocation table in memory as shown in fig. 10. The buffer allocation table includes a plurality of buffer allocation table entries, such as a buffer allocation table entry 101 and a buffer allocation table entry 102. Each buffer allocation table entry records the size of the allocation buffer, the DSP address and the CPU address corresponding to the DSP address.

The CPU311 uses the "shared memory-data buffer" in the PCIe mapping address space 314, as shown in fig. 11.

The CPU311 in the first system 31 dynamically allocates and reclaims the input buffer (e.g., "input buffer 0") that needs to be processed by the DSP and the output buffer (e.g., "output buffer 0") that is processed by the DSP from the "shared memory-data buffer" through the CPU address; the DSP322, through firmware running on the DSP, uses the DSP address to access a "shared memory-data buffer" (e.g., "input buffer0 DSP address", "input buffer 1 DSP address", "output buffer0 DSP address", and "output buffer 1 DSP address") in the PCIe mapped address space 314 and translates the buffer DSP address into a CPU address (e.g., "input buffer0" and "output buffer 0") for access by the CPU311.

The command sent by the CPU311 in the first system 31 includes a command type, the number of buffers for input and output, and the addresses of the input and output buffers.

The command is placed into a "shared memory-command queue" in the PCIe mapped address space 314, as shown in FIG. 12.

After the CPU311 places the command into the command queue, when the DSP device driver running on the CPU311 copies the data in the CPU running memory to the command queue of the "shared memory-command queue", the values of the input buffer address table pointer and the output buffer address table pointer are converted into DSP addresses according to the forward address mapping table of the source CPU- > destination DSP, so that the DSP can access normally.

After that, the CPU311 notifies the corresponding DSP to perform processing by an interrupt or other means.

In operation S550, the DSP322 in the second system 32 executes the command and returns the processing result.

The DSP322 in the second system 32 reads a command from the command queue in the "shared memory-command queue" shown in fig. 12, acquires input data from the "shared memory-data buffer" shown in fig. 12, and puts a processing result into the output buffer after the processing is completed.

After that, the CPU311 in the first system 31 is notified by an interrupt or other means. The CPU311 searches the buffer allocation table by outputting the DSP address of the buffer, obtains the CPU address, and obtains the processing result.

In the embodiment of the present application, by mapping the physical memory address of the DSP322 in the second system 32 to the virtual memory address in the first system 31, the application on the first system 31 can use 2 DSP devices on the first system 31 at the same time without going through the CPU321 in the second system 32, which reduces the complexity of application development.

In addition, the same or different firmware can be used on 2 DSP devices according to requirements, and the use is more flexible. If the same firmware is to be used, the boot addresses of the 2 DSP devices may be set to the same physical memory address in both systems.

In this way, the device driver on the first system 31 can manage 2 DSP devices simultaneously by adding only the address mapping table.

Further, the embodiment of the application also provides a device for performing data processing across systems, which is applied to a first system, and the first system is provided with a first data processing device. As shown in fig. 13, the apparatus 130 includes: a first memory address space obtaining module 1301, configured to obtain, through a system interconnection bus, a physical memory address space allocated by a second system to a second data processing apparatus, to obtain a first memory address space, where the second system and the first system are interconnected peer-to-peer systems, and a drive of the first data processing apparatus is applicable to the second data processing apparatus; an address space mapping module 1302, configured to allocate a virtual memory address space for a second data processing apparatus, to obtain a second memory address space, and establish a mapping relationship between the first memory address space and the second memory address space; the second data processing device using module 1303 is configured to control the second data processing device to process the local data of the first system through the second memory address space.

According to an embodiment of the present application, the address space mapping module 1302 includes: the forward address mapping table establishing submodule is used for establishing a forward address mapping table from the second memory address to the first memory address; and the reverse address mapping table establishing submodule is used for establishing a reverse address mapping table from the first memory address to the second memory address.

According to an embodiment of the present application, the forward address mapping table establishing submodule is specifically configured to establish a forward address mapping table from the second memory address space to the first memory address space in a manner of increasing memory addresses incrementally.

According to an embodiment of the present application, the apparatus 130 further includes: the firmware loading module is used for loading the firmware to the second memory address space; a second data processing apparatus enabling module for enabling the second data processing apparatus.

According to an embodiment of the application, the firmware loading module includes: the first memory address acquisition submodule is used for acquiring a first memory address of the firmware to be loaded in a first memory address space; the second memory address acquisition submodule is used for acquiring a second memory address of the first memory address mapped in a second memory address space; and the firmware loading submodule is used for loading the firmware to be loaded to the second memory address.

According to an embodiment of the present application, the second data processing device is provided with a shared memory in the first memory address space, and accordingly, the second data processing device using module 1303 includes: the command writing sub-module is used for writing a command and input data into the shared memory by the processor of the first system based on the virtual memory address mapped in the second memory address space in the shared memory; the command execution sub-module is used for reading a command and input data from the shared memory by the second data processing equipment based on the physical memory address in the first memory address space in the shared memory, executing a corresponding command according to the command and the input data, and writing an execution result of the corresponding command into the shared memory; and the command execution result acquisition submodule is used for reading the execution result of the corresponding command from the shared memory by the processor of the first system based on the virtual memory address mapped in the second memory address space in the shared memory.

According to an embodiment of the present application, the second data processing device using module 1303 includes: the physical address allocation submodule is used for allocating a first buffer address for writing a command and input data based on a virtual memory address mapped in a second memory address space in the shared memory; and the command writing submodule is used for writing the command and the input data into the first buffer address.

The embodiment of the present application further provides a computer-readable storage medium storing computer instructions, where the computer instructions are used to make a computer execute any one of the above methods for data processing across systems.

The embodiment of the present application further provides a chip, where the chip runs with a heterogeneous integrated system on chip, the heterogeneous integrated system on chip includes at least two hardware domains, the hardware domains run with independent operating systems on mutually isolated hardware resources, and the chip is configured to execute any one of the above methods for performing data processing across systems.

The embodiment of the application also provides a semiconductor integrated panel, and the semiconductor integrated panel is provided with the chip.

The embodiment of the application also provides an electronic component which is provided with the semiconductor integrated panel.

The embodiment of the application also provides a vehicle, and the vehicle is provided with the electronic component.

It is to be noted here that: the above description of the apparatus for performing data processing across a system, the above description of the embodiment of the computer storage medium, the above description of the embodiment of the chip, the above description of the embodiment of the semiconductor integrated panel, the above description of the embodiment of the electronic component, and the above description of the embodiment of the vehicle are similar to the description of the foregoing method embodiments, and have similar beneficial effects to the foregoing method embodiments, and therefore, the description is not repeated. For the descriptions of the device for data processing across systems, the above descriptions of the embodiments of the computer storage medium, the above descriptions of the embodiments of the chip, the above descriptions of the embodiments of the semiconductor integrated panel, the above descriptions of the embodiments of the electronic component, and the above descriptions of the embodiments of the vehicle, which have not been disclosed yet, please refer to the descriptions of the foregoing method embodiments of the present application for understanding, and therefore will not be described again for brevity.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one of 8230, and" comprising 8230does not exclude the presence of additional like elements in a process, method, article, or apparatus comprising the element.

In the several embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above-described device embodiments are merely illustrative, for example, the division of a unit is only one logical function division, and there may be other division ways in actual implementation, such as: multiple units or components may be combined, or may be integrated into another device, or some features may be omitted, or not implemented. In addition, the coupling, direct coupling or communication connection between the components shown or discussed may be through some interfaces, and the indirect coupling or communication connection between the devices or units may be electrical, mechanical or in other forms.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units; can be located in one place or distributed on a plurality of network units; some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, all functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may be separately regarded as one unit, or two or more units may be integrated into one unit; the integrated unit can be realized in a form of hardware, or in a form of hardware plus a software functional unit.

Those of ordinary skill in the art will understand that: all or part of the steps of implementing the method embodiments may be implemented by hardware related to program instructions, and the program may be stored in a computer-readable storage medium, and when executed, executes the steps including the method embodiments; and the aforementioned storage medium includes: various media capable of storing program codes, such as a removable storage medium, a Read Only Memory (ROM), a magnetic disk, or an optical disk.

Alternatively, the integrated units described above in the present application may be stored in a computer-readable storage medium if they are implemented in the form of software functional modules and sold or used as independent products. Based on such understanding, the technical solutions of the embodiments of the present application may be essentially implemented or portions thereof that contribute to the prior art may be embodied in the form of a software product stored in a storage medium, and including several instructions for enabling a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the methods of the embodiments of the present application. And the aforementioned storage medium includes: a removable storage medium, a ROM, a magnetic disk, an optical disk, or the like, which can store the program code.

The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A method for data processing across systems, which is applied to a first system provided with a first data processing device, and comprises the following steps:

acquiring a physical memory address space allocated by a second system to second data processing equipment through a system interconnection bus to obtain a first memory address space, wherein the second system and the first system are interconnected peer-to-peer systems, and a drive of the first data processing equipment is suitable for the second data processing equipment;

allocating a virtual memory address space for the second data processing device to obtain a second memory address space, and establishing a mapping relation between the first memory address space and the second memory address space;

and controlling the second data processing equipment to process the local data of the first system through the second memory address space.

2. The method of claim 1, the establishing a mapping between the first memory address space and the second memory address space, comprising:

establishing a forward address mapping table from the second memory address to the first memory address;

and establishing a reverse address mapping table from the first memory address to the second memory address.

3. The method of claim 2, wherein establishing a forward address mapping table from the second memory address space to the first memory address space comprises:

and establishing a forward address mapping table from the second memory address space to the first memory address space in a memory address increasing mode.

4. The method of claim 1, prior to said controlling said second data processing device to process local data of said first system via said second memory address space, further comprising:

loading firmware to the second memory address space;

enabling the second data processing device.

5. The method of claim 4, the loading firmware into the second memory address space, comprising:

acquiring a first memory address of firmware to be loaded in a first memory address space;

acquiring a second memory address mapped by the first memory address in the second memory address space;

and loading the firmware to be loaded to the second memory address.

6. The method of claim 1, the second data processing device having a shared memory disposed in the first memory address space,

correspondingly, the controlling the second data processing device to process the local data of the first system through the second memory address space includes:

the processor of the first system writes commands and input data into the shared memory based on the virtual memory address mapped in the second memory address space existing in the shared memory;

the second data processing device reads the command and the input data from the shared memory based on the physical memory address of the shared memory in the first memory address space, executes the corresponding command according to the command and the input data, and writes the execution result of the corresponding command into the shared memory;

and the processor of the first system reads the execution result of the corresponding command from the shared memory based on the virtual memory address mapped in the second memory address space in the shared memory.

7. The method of claim 6, the writing commands and input data to the shared memory based on the presence within the shared memory of virtual memory addresses mapped in the second memory address space, comprising:

allocating a first buffer address for writing commands and input data based on the virtual memory address mapped in the second memory address space existing in the share;

the command and input data are written to the first buffer address.

8. The method of any one of claims 1 to 7, the data processing device being a digital signal processing device.

9. An apparatus for performing data processing across systems, applied to a first system provided with a first data processing device, the apparatus comprising:

a first memory address space obtaining module, configured to obtain, through a system interconnection bus, a physical memory address space allocated by a second system to a second data processing apparatus, to obtain a first memory address space, where the second system and the first system are interconnected peer-to-peer systems, and a drive of the first data processing apparatus is applicable to the second data processing apparatus;

an address space mapping module, configured to allocate a virtual memory address space to the second data processing apparatus, to obtain a second memory address space, and establish a mapping relationship between the first memory address space and the second memory address space;

and the second data processing equipment using module is used for controlling the second data processing equipment to process the local data of the first system through the second memory address space.

10. A chip for performing the method of data processing across systems of any of claims 1-8.

11. A semiconductor integrated panel provided with the chip of claim 10.

12. An electronic component provided with the semiconductor integrated panel claimed in claim 11.

13. A vehicle provided with the electronic component of claim 12.