CN115332179A - Memory structure and manufacturing method thereof - Google Patents

Abstract

The present disclosure relates to a memory structure and a method of manufacturing the same, the method comprising: providing a substrate, and forming a plurality of discrete active regions arranged in an array on the substrate; forming a plurality of embedded word lines in the substrate, wherein each active region is intersected with only one word line, the word lines extend along a first direction, and the first direction is oblique to the extending direction of the active regions; forming a bit line contact on a first end of each of the active regions and forming a plurality of bit lines extending in a second direction perpendicular to the first direction, the first end of each of the active regions being connected to one of the bit line contacts and to one of the bit lines on which the bit line contact is located; forming a plurality of capacitors, the second end of each of the active regions being connected to one of the capacitors. The memory structure and the manufacturing method can reduce leakage current between word lines, increase data retention time and improve the row hammer effect.

Description

Memory structure and manufacturing method thereof

Technical Field

The present disclosure relates to the field of semiconductor technologies, and in particular, to a memory structure and a method for manufacturing the same.

Background

A Dynamic Random Access Memory (DRAM) is a semiconductor Memory, which has a simple structure and a high capacity per unit volume, and thus has a low cost. The information of the DRAM is stored in the capacitor, and the charge in the capacitor is gradually leaked due to the existence of the leakage current, so that the DRAM needs to be refreshed continuously, which is also called a dynamic reason.

The conduction of adjacent transistors in the DRAM may cause a leakage current phenomenon, thereby causing a decrease in the reliability of the DRAM. Thus, leakage current has become a critical consideration in DRAM device design.

In addition, current DRAM device designs make DRAM susceptible to the row hammer (Rowhammer) effect. The column hammer effect is, for example, to change the value of a cell from 1 to 0 after a sufficient number of accesses by the interaction of electrons between adjacent memory cells. The Rowhammer effect is thus one of the major issues affecting DRAM reliability and security.

Disclosure of Invention

To overcome the problems in the related art, the present disclosure provides a memory structure and a method of manufacturing the same.

According to a first aspect of the embodiments of the present disclosure, there is provided a method for manufacturing a memory structure, including:

providing a substrate, and forming a plurality of discrete active regions arranged in an array on the substrate;

forming a plurality of embedded word lines in the substrate, wherein each active region is intersected with only one word line, the word lines extend along a first direction, and the first direction is oblique to the extending direction of the active regions;

forming a bit line contact on a first end of each of the active regions and forming a plurality of bit lines extending in a second direction perpendicular to the first direction, the first end of each of the active regions being connected to one of the bit line contacts and to one of the bit lines on which the bit line contact is located;

forming a plurality of capacitors, the second end of each of the active regions being connected to one of the capacitors.

In an alternative embodiment, the forming a plurality of discrete active regions arranged in an array on the substrate includes:

forming a plurality of discrete active regions arranged in an array on the substrate, so that the plurality of active regions in the same column are parallel to each other; and/or the presence of a gas in the gas,

the active regions positioned in two adjacent columns are mutually parallel or are arranged in an inclined way;

wherein the first direction is taken as a direction in which the columns extend.

In an alternative embodiment, when the active regions in two adjacent columns are arranged obliquely with respect to each other, the included angle between the extending directions of the active regions in two adjacent columns is 90 ° to 130 °.

In an alternative embodiment, the forming a plurality of discrete active regions arranged in an array on the substrate includes:

forming a pattern mask on the substrate, wherein the pattern mask exposes a part of the substrate, and the projection pattern of the pattern mask on the substrate is a plurality of discrete columnar patterns or wavy patterns arranged in an array;

partially removing the exposed substrate to form an isolation trench;

filling an insulating material in the isolation groove to form a shallow groove isolation structure;

and removing the pattern mask.

In an alternative embodiment, the wavy pattern comprises a first meandering portion, a second meandering portion, and a third meandering portion connected in series; the first and third meandering portions extend in the second direction, and the first direction is oblique to an extending direction of the second meandering portion; each of the active regions includes a first end portion corresponding to the first meandering portion, a channel portion corresponding to the second meandering portion, and a second end portion corresponding to the third meandering portion, the channel portion of the active region intersecting one of the word lines.

In an alternative embodiment, forming the plurality of capacitors comprises:

forming a plurality of spacing structures between adjacent bit lines, wherein the spacing structures are arranged along the second direction, and a groove is formed by the spacing structures and the bit lines in a surrounding mode;

forming a capacitor contact in the groove;

a capacitor is formed on the capacitor contact.

In an alternative embodiment, the plurality of capacitors are hexagonally close-packed.

According to a second aspect of the embodiments of the present disclosure, there is provided a memory structure, including:

the device comprises a substrate, a first electrode and a second electrode, wherein a plurality of discrete active regions arranged in an array are formed on the substrate;

a plurality of word lines extending in a first direction oblique to an extending direction of the active regions, each of the active regions intersecting with only one of the word lines;

a plurality of bit lines extending in a second direction perpendicular to the first direction;

a plurality of bit line contacts, each of the bit line contacts being located at a first end of each of the active regions, each of the active regions being connected to one of the bit lines at which the bit line contact is located by the bit line contact located at the first end thereof;

a plurality of capacitors, a second end of each of the active regions being connected to one of the plurality of capacitors.

In an alternative embodiment, the memory structure further includes an isolation structure formed on the substrate, the isolation structure enclosing the active region;

the shape enclosed by the projection of the isolation structure on the substrate is set to be a plurality of discrete columnar patterns or wavy patterns arranged in an array.

In an alternative embodiment, the wavy pattern comprises a first meandering portion, a second meandering portion, and a third meandering portion connected in series;

the first and third meandering portions extend in the second direction, and the first direction is oblique to an extending direction of the second meandering portion;

each of the active regions includes a first end portion corresponding to the first meandering portion, a channel portion corresponding to the second meandering portion, and a second end portion corresponding to the third meandering portion, the channel portion of the active region intersecting one of the word lines.

In an alternative embodiment, the first direction is taken as the direction in which the columns extend,

a plurality of active regions in the same column are parallel to each other; and/or the presence of a gas in the atmosphere,

the active regions in two adjacent columns are parallel to each other or are obliquely arranged relative to each other.

In an alternative embodiment, when the active regions in two adjacent columns are arranged obliquely with respect to each other, the included angle between the extending directions of the active regions in two adjacent columns is 90 ° to 130 °.

In an alternative embodiment, the storage structure further comprises:

the spacer structures are formed between adjacent bit lines, the spacer structures are arranged along the second direction, and the spacer structures and the bit lines surround to form grooves;

a capacitor contact formed in the recess and connected to the capacitor.

In an alternative embodiment, the plurality of capacitors are hexagonally close-packed.

By adopting the technical scheme, the embodiment of the disclosure has the following advantages: one word line is only connected with one bit line and one capacitor, and adjacent word lines are isolated, so that leakage current between the word lines is reduced. That is, in the above-described embodiment, the capacitor and the bit line are connected using a single transistor, and both sides of the single transistor are blocked by the shallow trench isolation insulating layer, thereby preventing conduction of adjacent transistors or leakage between adjacent transistors. By adopting the design, the data retention time can be increased, and the line hammer effect can be improved.

The foregoing summary is provided for the purpose of illustration only and is not intended to be in any way limiting. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features of the present invention will be readily apparent by reference to the drawings and following detailed description.

Drawings

In the drawings, the same reference numerals refer to the same or similar parts or elements throughout the several figures unless otherwise specified. The figures are not necessarily to scale. It is appreciated that these drawings depict only some embodiments in accordance with the disclosure and are therefore not to be considered limiting of its scope.

FIG. 1 is a flow chart illustrating a method of fabricating a memory structure according to an exemplary embodiment;

FIG. 2 is a top view of the substrate surface after step S101 is completed in the manufacturing method shown in FIG. 1;

FIG. 3 is a cross-sectional view of the manufacturing method shown in FIG. 1 taken along line B-B' after step S101 is completed;

FIG. 4 is a top view of the substrate surface after step S102 is completed in the manufacturing method shown in FIG. 1;

FIG. 5 is a cross-sectional view of the method of manufacture shown in FIG. 1 taken along line B-B' after step S102 is completed;

FIG. 6 is a top view of the substrate surface after step S103 of the fabrication method shown in FIG. 1 is completed;

FIG. 7 is a cross-sectional view of the method of manufacture shown in FIG. 1 taken along line B-B' after step S103 has been completed;

FIG. 8 is a top view of the substrate surface after step S104 is completed in the manufacturing method shown in FIG. 1;

FIG. 9 is a cross-sectional view of the method of manufacture shown in FIG. 1 taken along line B-B' after completion of step S104;

FIG. 10 is a top view of the substrate surface after step S104 is completed in the method of manufacturing shown in FIG. 1;

fig. 11 is a top view of the substrate surface after completion of step S104 of the manufacturing method shown in fig. 1;

FIG. 12 is a cross-sectional view taken along line B-B' of the method of manufacture shown in FIG. 1 after completion of step S104;

fig. 13 is a top view of the substrate surface after step S104 is completed in the manufacturing method shown in fig. 1.

The reference numbers illustrate:

110: a substrate;

111: a shallow trench isolation structure;

120: an active region;

121: a first meandering section;

122: a second meandering section;

123: a third meandering section;

130: a word line;

140: a bit line;

150: a bit line contact;

160: a capacitor;

161: a capacitive contact;

170: a spacer structure.

Detailed Description

In the following, only certain exemplary embodiments are briefly described. As those skilled in the art can appreciate, the described embodiments can be modified in various different ways, without departing from the spirit or scope of the present disclosure. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.

The memory structure and the method for manufacturing the memory structure provided by the present disclosure are described in detail below with reference to fig. 1 to 13.

The method for manufacturing the memory structure, as shown in fig. 1, includes the following steps.

Step S101, providing a substrate 110, and forming a plurality of discrete active regions 120 arranged in an array on the substrate 110, as shown in fig. 2. Specifically, a substrate 110 is provided, in one embodiment, the substrate 110 is P-type or N-type; a photoresist is coated on the surface of the substrate 110 and a photoresist pattern (not shown) is formed to expose regions of the substrate 110 for forming the active regions 120, and a dopant having a reverse type to that of the dopant in the substrate 110 is implanted into the exposed regions of the substrate 110 to form a plurality of active regions 120. In one embodiment, when the substrate 110 is P-type, the implanted dopant is N-type (e.g., phosphorus, arsenic, antimony, etc.); when the substrate 110 is N-type, the implanted dopant is P-type (e.g., boron, gallium, etc.). The active regions 120 are spaced apart from each other and arranged in an array to form an active region array. Fig. 3 is a cross-sectional view taken along line B-B' of fig. 2, showing that the active regions 120 are formed on the surface of the substrate 110 and do not penetrate the substrate 110, and the two active regions 120 are spaced apart from each other. Specifically, the active region 120 is blocked by a Shallow Trench Isolation (STI) insulating layer 111 around it. In each of the active regions 120, a diffusion region is formed, for example, by an ion implantation technique.

Step S102 is to form a plurality of embedded word lines 130 in the substrate 110, wherein each of the active regions 120 intersects with only one of the word lines 130, and the word lines 130 extend along a first direction, which is oblique to the extending direction of the active regions, as shown in fig. 4. The direction indicated by the arrow D1 is a first direction, and the direction indicated by the arrow D2 is an extending direction of the active region 120. Specifically, etching a plurality of grooves in the substrate 110 forms the buried word lines 130, as shown in fig. 5. Fig. 5 is a sectional view taken along line B-B' in fig. 4. In one embodiment, the grooves are formed in the substrate 110 in a linearly extending manner, and the grooves are parallel to each other and intersect the active region 120 at an angle. As shown in fig. 4, word lines 130 extend in the direction of the columns in the active area array and intersect the active areas 120, wherein each active area 120 intersects only one word line. In one embodiment, the distance between any two adjacent columns of word lines 130 is equal.

Step S103, forming a bit line contact 150 at a first end of each active region, and forming a plurality of bit lines 140, wherein the plurality of bit lines 140 extend along a second direction perpendicular to the first direction, and the first end of each active region is connected to one bit line contact and to one bit line on which the bit line contact is located, as shown in fig. 6. The direction indicated by the arrow D1 is a first direction, the direction indicated by the arrow D2 is an extending direction of the active region 120, and the direction indicated by the arrow D3 is a second direction. Specifically, a bit line contact 150 is formed at a first end of the active region 120 (e.g., the end where the drain is formed), a bit line material is deposited on the surface of the substrate 110, and a plurality of bit lines 140 are formed. And bit line 140 is connected to a plurality of bit line contacts 150 as shown in fig. 7. Fig. 7 is a sectional view taken along line B-B' of fig. 6. As further shown in fig. 6, the bit lines 140 extend in a direction perpendicular to the direction in which the word lines 130 extend. Thus, the bit lines 140 extend in the direction of the rows in the array of active regions 120 and intersect the active regions. Each bitline 140 is connected to a plurality of bitline contacts 150 arranged at intervals. Each active region 120 is connected by its first end to one bitline contact 150 and, in turn, to the bitline 140 on which the bitline contact 150 is located. In one embodiment, the distances between any two adjacent rows of bit lines 140 are all equal. Also, the distance between any two adjacent bitline contacts 150 on the same bitline 140 is equal.

In step S104, a plurality of capacitors 160 are formed, and the second end of each active region 120 is connected to one capacitor 160. As shown in fig. 8 and 9, a capacitor 160 is formed at a second end of the active region 120 (e.g., the end where the source is formed). Fig. 9 is a sectional view taken along line B-B' in fig. 8.

The manufacturing method of the memory structure provided by the above embodiments of the present disclosure may be used for manufacturing a semiconductor memory device, particularly a memory device such as a DRAM. In the above embodiments of the present disclosure, one word line is connected to only one bit line and one capacitor, and adjacent word lines are isolated, thereby reducing leakage current between word lines. That is, in the above-described embodiment, the capacitor and the bit line are connected using a single transistor, and both sides of the single transistor are blocked by the shallow trench isolation insulating layer, thereby preventing conduction of adjacent transistors or leakage between adjacent transistors. By adopting the design, the data retention time can be increased, and the Rawhammer effect (Rawhammer) can be improved.

In an alternative embodiment, the forming of the plurality of discrete active regions 120 arranged in an array on the substrate 110 in step S101 includes: forming a plurality of discrete active regions 120 arranged in an array on the substrate 110 such that a plurality of the active regions 120 located in a same column are parallel to each other; and/or the active regions 120 located in two adjacent columns are arranged parallel or obliquely with respect to each other, wherein the first direction is taken as the direction in which the columns extend. As shown in fig. 6, the active regions 120 of two adjacent columns are parallel to each other. As shown in fig. 10 and fig. 11, two adjacent rows of active regions 120 are disposed in an opposite inclined manner, that is, the two adjacent rows of active regions 120 form an included angle, which can be designed according to specific situations.

In this embodiment, different capacitive stacking patterns can be achieved by using different arrangements of the active regions 120.

In an alternative embodiment, when the active regions in two adjacent columns are arranged obliquely with respect to each other, the included angle between the extending directions of the active regions in two adjacent columns is 90 ° to 130 °. As shown in fig. 10, the extending direction of the active regions 120 of two adjacent columns forms an included angle of 130 °. As shown in fig. 11, the extending direction of the active regions 120 of two adjacent columns forms an angle of 90 °. In one embodiment, the included angle may be 120 °. By adopting the included angle design, high-density accumulation of the capacitor columns on the substrate can be realized.

In an alternative embodiment, the forming a plurality of discrete active regions 120 arranged in an array on the substrate 110 includes:

forming a pattern mask on the substrate 110, wherein the pattern mask exposes a part of the substrate 110, and a projection pattern of the pattern mask on the substrate 110 is a plurality of discrete columnar patterns or wavy patterns arranged in an array;

partially removing the exposed substrate 110 to form an isolation trench;

filling an insulating material in the isolation trench to form a shallow trench isolation structure 111;

and removing the pattern mask.

Fig. 3 shows a shallow trench isolation structure, i.e., the aforementioned shallow trench isolation insulating layer 111, formed after filling an insulating material in the isolation trench. The area surrounded by the shallow trench isolation structure 111 is a plurality of discrete active regions 120, that is, the shape of the active regions 120 is a columnar pattern or a wavy pattern when the substrate is viewed from the top view.

As shown in fig. 10, each active region 120 is a pillar pattern when the substrate is viewed from the top view, and the pillar pattern has a simple structure and is easy to implement. As shown in fig. 11, each active region 120 has a wavy pattern when viewed from the top of the substrate, and such wavy structure can increase the length of the channel, thereby improving the performance of the memory structure.

In an alternative embodiment, the wavy pattern comprises a first zigzag portion 121, a second zigzag portion 122 and a third zigzag portion 123 connected in sequence; the first meandering portion 121 and the third meandering portion 123 extend in the second direction, and the first direction is oblique to the extending direction of the second meandering portion 122; each of the active regions includes a first end portion corresponding to the first meandering portion 121, a channel portion corresponding to the second meandering portion 122, and a second end portion corresponding to the third meandering portion 123, the channel portion of the active region intersecting one of the word lines 130.

As shown in fig. 11, the first and third meandering portions 121 and 123 extend in the second direction in which the bit lines 140 extend, and the second meandering portion 122 extends in a direction oblique to the first direction in which the word lines 130 extend. The extending directions of the first and third meandering portions 121 and 123 and the extending direction of the second meandering portion 122 are different, so that three portions constitute a wavy pattern. Neither the first meandering portions 121 nor the third meandering portions 123 of the wavy pattern intersect with the word line 130, but only the second meandering portions 122 intersect with the word line 130. In one embodiment, the first end of the active region 120 corresponding to the first meandering portion 121 is connected to a bit line through a bit line contact, and the second end of the active region 120 corresponding to the third meandering portion 123 is connected to a capacitor.

Note that the aforementioned extending direction of the active region 120 refers to the extending direction of the second meandering portion 122.

In an alternative embodiment, forming the plurality of capacitors comprises:

forming a plurality of spacer structures 170 between adjacent bit lines, wherein each spacer structure 170 is arranged along the second direction, and a groove is formed by the spacer structures 170 and each bit line;

forming a capacitive contact 161 within the recess;

a capacitor 160 is formed on the capacitor contact 161.

A spacer structure 170 is formed between adjacent bit lines 140. Specifically, as shown in fig. 8, a spacer structure 170 is formed between a pair of adjacent bit lines 140, and the spacer structure 170 is formed on an upper layer of the embedded word line 130 and is arranged along the second direction in which the bit lines 140 extend. Thus, two adjacent spacers 170 and two adjacent bitlines 140 enclose a recess. A capacitor contact 161 is formed in the recess and a capacitor 160 is formed on the capacitor contact 161, as shown in fig. 9.

In an alternative embodiment, the plurality of capacitors are hexagonally close-packed.

Fig. 9 and 12 show a schematic diagram of forming a capacitor 160 on a capacitor contact 161. In fig. 9, the capacitor 160 is formed vertically on top of the capacitor contact 161, in which case a square stacking pattern of capacitors is formed as viewed from the top view of the substrate. In fig. 12, when the capacitor 160 is formed on top of the capacitor contact 161, the capacitor 160 is slightly displaced from the capacitor contact 161, and in this case, a hexagonal closest-packing pattern of the capacitor is formed as viewed from the top of the substrate, and high-density packing of the capacitor is realized.

The embodiment of the disclosure also provides a memory structure manufactured by the manufacturing method of the memory structure provided by the disclosure. As shown in fig. 8, the memory structure includes:

a substrate 110 having a plurality of discrete active regions 120 formed thereon in an array arrangement;

a plurality of word lines 130, the plurality of word lines 130 extending along a first direction, the first direction being oblique to the extending direction of the active regions 120, each of the active regions 120 intersecting with only one of the word lines 130;

a plurality of bit lines 140, the plurality of bit lines 140 extending in a second direction perpendicular to the first direction;

a plurality of bit line contacts 150, each of the bit line contacts 150 being located at a first end of each of the active regions 120, each of the active regions 120 being connected to one of the bit lines 140 at which the bit line contact 150 is located through the bit line contact 150 located at the first end thereof;

a plurality of capacitors 160, a second end of each of the active regions 120 being connected to one of the plurality of capacitors 160.

The memory structure provided by the embodiment of the disclosure is a semiconductor memory device. In the memory structure, one word line is only connected with one bit line and one capacitor, and adjacent word lines are isolated, so that leakage current between the word lines is reduced, and conduction of adjacent transistors or leakage current between the adjacent transistors is avoided.

In an alternative embodiment, as shown in fig. 3, the memory structure further includes an isolation structure 111 formed on the substrate, where the isolation structure 111 encloses the active region;

the shape defined by the projection of the isolation structures 111 on the substrate is configured as a plurality of discrete pillar patterns or wave patterns arranged in an array.

The isolation structure 111 is the aforementioned shallow trench isolation structure 111. Forming a pattern mask in the substrate 110, removing a portion of the substrate not covered by the pattern mask to form an isolation trench, and filling an insulating material in the isolation trench to form a shallow trench isolation structure 111. The active region 120 is blocked by the shallow trench isolation structure 111, which prevents conduction of adjacent transistors or leakage between adjacent transistors.

In an alternative embodiment, as shown in fig. 11, the wavy pattern comprises a first zigzag portion 121, a second zigzag portion 122 and a third zigzag portion 123 connected in sequence;

the first meandering portion 121 and the third meandering portion 123 extend in the second direction, and the first direction is oblique to the extending direction of the second meandering portion 122;

each of the active regions includes a first end portion corresponding to the first meandering portion 121, a channel portion corresponding to the second meandering portion 122, and a second end portion corresponding to the third meandering portion 123, the channel portion of the active region intersecting one of the word lines.

In an alternative embodiment, the first direction is taken as the direction in which the columns extend,

a plurality of the active regions 120 located in the same column are parallel to each other; and/or the presence of a gas in the gas,

the active regions 120 located in two adjacent columns are arranged parallel to each other or inclined with respect to each other.

As shown in fig. 8, the active regions 120 located in two adjacent columns are parallel to each other; as shown in fig. 10, the active regions 120 located in two adjacent columns are disposed at an angle with respect to each other.

In an alternative embodiment, when the active regions 120 in two adjacent columns are disposed obliquely with respect to each other, an included angle between extending directions of the active regions 120 in two adjacent columns is 90 ° to 130 °.

In an alternative embodiment, the storage structure further comprises:

a plurality of spacer structures 170, wherein the spacer structures 170 are formed between adjacent bit lines 140, each spacer structure 170 is arranged along the second direction, and a groove is formed by the spacer structures and each bit line 140;

a capacitor contact 161, wherein the capacitor contact 161 is formed in the groove, and the capacitor contact 161 is connected to the capacitor 160.

As shown in fig. 8, a plurality of spacer structures 170 are formed between adjacent bit lines 140, and the spacer structures 170 may be formed on an upper layer of the position of the buried word line 130. In one embodiment, the distance between two adjacent spacers 170 is the same. Two adjacent spacers 170 and the bit lines 140 on the upper and lower sides enclose a groove. A capacitor contact 161 is formed in the recess in connection with the capacitor 160 as shown in fig. 9.

In an alternative embodiment, the plurality of capacitors are hexagonally close-packed.

The following are several specific embodiments of the memory structure provided by the present disclosure.

Detailed description of the preferred embodiment

A memory structure, as shown in fig. 8, comprising:

the active region 120 is defined by a shallow trench isolation structure 111, and a projection of the shallow trench isolation structure 111 on the substrate defines a columnar pattern. The extension directions of the active regions 120 in the same column are the same (parallel), and the extension directions of the active regions 120 in each column are the same;

a plurality of word lines 130, the word lines 130 extending along a first direction, the first direction being oblique to the extending direction of the active regions 120, each active region 120 intersecting with only one word line 130;

a plurality of bit lines 140, the bit lines 140 extending in a second direction perpendicular to the first direction;

a plurality of bit line contacts 150, each bit line contact located at a first end of the active region 120, one bit line 140 connected to the plurality of bit line contacts 150;

a plurality of capacitors 170, the capacitors 170 being formed on the capacitor contacts 161.

In this embodiment, a first end of each active region 120 is connected to one of the bit line contacts 150 and to the bit line 140 through the bit line contact 150, and a second end of each active region 120 is connected to a capacitor contact 161 and to a capacitor 170 through the capacitor contact 161.

Detailed description of the invention

A memory structure, as shown in fig. 10, comprising:

the active region 120 is defined by a shallow trench isolation structure 111, and a projection of the shallow trench isolation structure 111 on the substrate defines a shape of a pillar pattern. The extending directions of the active regions 120 in the same row are the same (parallel), and the extending directions of the active regions 120 in two adjacent rows are inclined to each other;

a plurality of word lines 130, the word lines 130 extending along a first direction, the first direction being oblique to the extending direction of the active regions 120, each active region 120 intersecting with only one word line 130;

a plurality of bit lines 140, the bit lines 140 extending in a second direction perpendicular to the first direction;

a plurality of bit line contacts 150, each bit line contact located at a first end of the active region 120, one bit line 140 connected to the plurality of bit line contacts 150;

a plurality of capacitors 170, the capacitors 170 being formed on the capacitor contacts 161.

In this embodiment, a first end of each active region 120 is connected to one bit line contact 150 and to the bit line 140 through the bit line contact 150, and a second end of each active region 120 is connected to a capacitor contact 161 and to a capacitor 170 through the capacitor contact 161.

Detailed description of the preferred embodiment

A memory structure, as shown in fig. 13, comprising:

the active region 120 is defined by a shallow trench isolation structure 111, and a shape defined by a projection of the shallow trench isolation structure 111 on the substrate is a wavy pattern. The extension directions of the active regions 120 in the same column are the same (parallel), and the extension directions of the active regions 120 in each column are the same;

a plurality of word lines 130, the word lines 130 extending along a first direction, the first direction being oblique to the extending direction of the active regions 120, each active region 120 intersecting with only one word line 130;

a plurality of bit lines 140, the bit lines 140 extending in a second direction perpendicular to the first direction;

a plurality of bit line contacts 150, each bit line contact located at a first end of the active region 120, one bit line 140 connected to the plurality of bit line contacts 150;

a plurality of capacitors 170, the capacitors 170 being formed on the capacitor contacts 161.

In this embodiment, a first end of each active region 120 is connected to one of the bit line contacts 150 and to the bit line 140 through the bit line contact 150, and a second end of each active region 120 is connected to a capacitor contact 161 and to a capacitor 170 through the capacitor contact 161.

Detailed description of the invention

A memory structure, as shown in fig. 12, comprising:

the active region 120 is defined by a shallow trench isolation structure 111, and a shape defined by a projection of the shallow trench isolation structure 111 on the substrate is a wavy pattern. The extending directions of the active regions 120 in the same row are the same (parallel), and the extending directions of the active regions 120 in two adjacent rows are inclined to each other;

a plurality of word lines 130, the word lines 130 extending along a first direction, the first direction being oblique to the extending direction of the active regions 120, each active region 120 intersecting with only one word line 130;

a plurality of bit lines 140, the bit lines 140 extending in a second direction perpendicular to the first direction;

a plurality of bit line contacts 150, each bit line contact located at a first end of the active region 120, one bit line 140 connected to the plurality of bit line contacts 150;

a plurality of capacitors 170, the capacitors 170 being formed on the capacitor contacts 161.

In this embodiment, a first end of each active region 120 is connected to one bit line contact 150 and to the bit line 140 through the bit line contact 150, and a second end of each active region 120 is connected to a capacitor contact 161 and to a capacitor 170 through the capacitor contact 161.

In the memory structure provided in the above embodiment, since one word line is connected to only one bit line and one capacitor, and adjacent word lines are isolated, leakage current between word lines is reduced, thereby preventing conduction of adjacent transistors or leakage current between adjacent transistors.

In the description herein, references to the terms "example," "embodiment," or the like, mean that a particular feature, structure, material, or characteristic described in connection with the example or embodiment is included in at least one example or embodiment of the invention. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or implementations. Furthermore, the various embodiments or implementations described in this specification, as well as features of the various embodiments or implementations, may be combined and combined by those skilled in the art without contradiction.

The terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.

The above disclosure provides different embodiments or examples to implement different structures of the present invention. The components and arrangements of the specific examples are described above to simplify the present disclosure. Of course, they are merely examples and are not intended to limit the present invention. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, the present invention provides examples of various specific processes and materials, but one of ordinary skill in the art may contemplate the use of other processes and/or the use of other materials.

The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can think of other changes or substitutions within the technical scope of the present invention, and these changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.

Claims (14)

1. A method of fabricating a memory structure, comprising:

providing a substrate, and forming a plurality of discrete active regions arranged in an array on the substrate;

forming a plurality of embedded word lines in the substrate, wherein each active region is intersected with only one word line, the word lines extend along a first direction, and the first direction is oblique to the extending direction of the active regions;

forming a bit line contact on a first end of each of the active regions and forming a plurality of bit lines extending in a second direction perpendicular to the first direction, the first end of each of the active regions being connected to one of the bit line contacts and to one of the bit lines on which the bit line contact is located;

forming a plurality of capacitors, the second end of each of the active regions being connected to one of the capacitors.

2. The method of fabricating a memory structure according to claim 1, wherein forming a plurality of discrete active regions arranged in an array on the substrate comprises:

forming a plurality of discrete active regions arranged in an array on the substrate, so that the plurality of active regions in the same column are parallel to each other; and/or the presence of a gas in the atmosphere,

the active regions positioned in two adjacent columns are mutually parallel or are arranged in an inclined way;

wherein the first direction is taken as a direction in which the columns extend.

3. The method of manufacturing a memory structure according to claim 2, wherein when the active regions in two adjacent columns are disposed to be inclined with respect to each other, the extending direction of the active regions in two adjacent columns has an angle of 90 ° to 130 °.

4. The method of fabricating a memory structure according to claim 1, wherein forming a plurality of discrete active regions arranged in an array on the substrate comprises:

forming a pattern mask on the substrate, wherein the pattern mask exposes part of the substrate, and the projection pattern of the pattern mask on the substrate is a plurality of discrete columnar patterns or wavy patterns arranged in an array;

partially removing the exposed substrate to form an isolation trench;

filling an insulating material in the isolation groove to form a shallow groove isolation structure;

and removing the pattern mask.

5. The method of manufacturing a storage structure according to claim 4, wherein the wavy pattern includes a first meandering portion, a second meandering portion, and a third meandering portion connected in series; the first and third meandering portions extend in the second direction, and the first direction is oblique to an extending direction of the second meandering portion; each of the active regions includes a first end portion corresponding to the first meander portion, a channel portion corresponding to the second meander portion, and a second end portion corresponding to the third meander portion, the channel portion of the active region intersecting one of the word lines.

6. The method of manufacturing a memory structure of claim 1, wherein forming a plurality of capacitors comprises:

forming a plurality of spacing structures between adjacent bit lines, wherein the spacing structures are arranged along the second direction, and the spacing structures and the bit lines surround to form grooves;

forming a capacitor contact in the groove;

forming a capacitor on the capacitor contact.

7. The method of fabricating a memory structure according to claim 1, wherein the plurality of capacitors are hexagonally close-packed.

8. A memory structure, comprising:

the device comprises a substrate, a first electrode and a second electrode, wherein a plurality of discrete active regions arranged in an array are formed on the substrate;

a plurality of word lines extending in a first direction oblique to an extending direction of the active regions, each of the active regions intersecting with only one of the word lines;

a plurality of bit lines extending in a second direction perpendicular to the first direction;

a plurality of bit line contacts, each of the bit line contacts being located at a first end of each of the active regions, each of the active regions being connected to one of the bit lines at which the bit line contact is located by the bit line contact located at the first end thereof;

a plurality of capacitors, a second end of each of the active regions being connected to one of the plurality of capacitors.

9. The memory structure of claim 8, further comprising an isolation structure formed in the substrate, the isolation structure enclosing the active region;

the shape enclosed by the projection of the isolation structure on the substrate is set to be a plurality of discrete columnar patterns or wavy patterns arranged in an array.

10. The storage structure of claim 9, wherein the wavy pattern comprises a first meandering portion, a second meandering portion, and a third meandering portion connected in series;

the first and third meandering portions extend in the second direction, and the first direction is oblique to the extending direction of the second meandering portion;

each of the active regions includes a first end portion corresponding to the first meandering portion, a channel portion corresponding to the second meandering portion, and a second end portion corresponding to the third meandering portion, the channel portion of the active region intersecting one of the word lines.

11. The memory structure according to claim 8, wherein the first direction is a direction extending as a column,

a plurality of active regions in the same column are parallel to each other; and/or the presence of a gas in the gas,

the active regions in two adjacent columns are parallel to each other or are obliquely arranged relative to each other.

12. The memory structure according to claim 11, wherein when the active regions in two adjacent columns are disposed obliquely, the extending direction of the active regions in two adjacent columns has an included angle of 90 ° to 130 °.

13. The memory structure of claim 8, further comprising:

the spacer structures are formed between adjacent bit lines, the spacer structures are arranged along the second direction, and the spacer structures and the bit lines surround to form grooves;

a capacitor contact formed in the recess and connected to the capacitor.

14. The memory structure of claim 8, wherein the plurality of capacitors are hexagonally close-packed.

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